enable_mask        33 arch/arm/mach-ep93xx/clock.c 	u32		enable_mask;
enable_mask        54 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_DEVCFG_U1EN,
enable_mask        61 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_DEVCFG_U2EN,
enable_mask        68 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_DEVCFG_U3EN,
enable_mask        89 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_PWRCNT_USH_EN,
enable_mask        95 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
enable_mask       102 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_KEYTCHCLKDIV_TSEN,
enable_mask       117 arch/arm/mach-ep93xx/clock.c 	.enable_mask    = EP93XX_SYSCON_CLKDIV_ENABLE,
enable_mask       124 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_CLKDIV_ENABLE,
enable_mask       132 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_I2SCLKDIV_SENA,
enable_mask       140 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_I2SCLKDIV_SENA,
enable_mask       148 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P0,
enable_mask       153 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P1,
enable_mask       158 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P2,
enable_mask       163 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P3,
enable_mask       168 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P4,
enable_mask       173 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P5,
enable_mask       178 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P6,
enable_mask       183 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P7,
enable_mask       188 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P8,
enable_mask       193 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P9,
enable_mask       198 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2M0,
enable_mask       203 arch/arm/mach-ep93xx/clock.c 	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2M1,
enable_mask       254 arch/arm/mach-ep93xx/clock.c 			v |= clk->enable_mask;
enable_mask       285 arch/arm/mach-ep93xx/clock.c 			v &= ~clk->enable_mask;
enable_mask       345 arch/arm/mach-ep93xx/clock.c 	div_bit = clk->enable_mask >> 15;
enable_mask        83 arch/arm/mach-omap2/display.c 	u32 enable_mask, enable_shift;
enable_mask        89 arch/arm/mach-omap2/display.c 		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
enable_mask        94 arch/arm/mach-omap2/display.c 		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
enable_mask       108 arch/arm/mach-omap2/display.c 	reg &= ~enable_mask;
enable_mask       111 arch/arm/mach-omap2/display.c 	reg |= (lanes << enable_shift) & enable_mask;
enable_mask        59 arch/mips/kernel/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_DUMP,
enable_mask        87 arch/x86/events/amd/ibs.c 	u64				enable_mask;
enable_mask       366 arch/x86/events/amd/ibs.c 	wrmsrl(hwc->config_base, hwc->config | config | perf_ibs->enable_mask);
enable_mask       382 arch/x86/events/amd/ibs.c 	config &= ~perf_ibs->enable_mask;
enable_mask       534 arch/x86/events/amd/ibs.c 	.enable_mask		= IBS_FETCH_ENABLE,
enable_mask       559 arch/x86/events/amd/ibs.c 	.enable_mask		= IBS_OP_ENABLE,
enable_mask       836 arch/x86/events/perf_event.h 					  u64 enable_mask)
enable_mask       842 arch/x86/events/perf_event.h 	wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
enable_mask       466 drivers/acpi/acpica/aclocal.h 	u8 enable_mask;		/* Current mask of enabled GPEs */
enable_mask        62 drivers/acpi/acpica/evgpe.c 	gpe_register_info->enable_mask = gpe_register_info->enable_for_run;
enable_mask        24 drivers/acpi/acpica/hwgpe.c acpi_hw_gpe_enable_write(u8 enable_mask,
enable_mask        68 drivers/acpi/acpica/hwgpe.c 	u64 enable_mask;
enable_mask        82 drivers/acpi/acpica/hwgpe.c 	status = acpi_hw_read(&enable_mask, &gpe_register_info->enable_address);
enable_mask        95 drivers/acpi/acpica/hwgpe.c 		if (!(register_bit & gpe_register_info->enable_mask)) {
enable_mask       103 drivers/acpi/acpica/hwgpe.c 		ACPI_SET_BIT(enable_mask, register_bit);
enable_mask       108 drivers/acpi/acpica/hwgpe.c 		ACPI_CLEAR_BIT(enable_mask, register_bit);
enable_mask       122 drivers/acpi/acpica/hwgpe.c 		    acpi_hw_write(enable_mask,
enable_mask       270 drivers/acpi/acpica/hwgpe.c acpi_hw_gpe_enable_write(u8 enable_mask,
enable_mask       275 drivers/acpi/acpica/hwgpe.c 	gpe_register_info->enable_mask = enable_mask;
enable_mask       277 drivers/acpi/acpica/hwgpe.c 	status = acpi_hw_write(enable_mask, &gpe_register_info->enable_address);
enable_mask       377 drivers/acpi/acpica/hwgpe.c 	u8 enable_mask;
enable_mask       391 drivers/acpi/acpica/hwgpe.c 		enable_mask = gpe_register_info->enable_for_run &
enable_mask       394 drivers/acpi/acpica/hwgpe.c 		    acpi_hw_gpe_enable_write(enable_mask, gpe_register_info);
enable_mask       109 drivers/bus/qcom-ebi2.c 	u32 enable_mask;
enable_mask       117 drivers/bus/qcom-ebi2.c 		.enable_mask = EBI2_CS0_ENABLE_MASK,
enable_mask       123 drivers/bus/qcom-ebi2.c 		.enable_mask = EBI2_CS1_ENABLE_MASK,
enable_mask       129 drivers/bus/qcom-ebi2.c 		.enable_mask = EBI2_CS2_ENABLE_MASK,
enable_mask       135 drivers/bus/qcom-ebi2.c 		.enable_mask = EBI2_CS3_ENABLE_MASK,
enable_mask       141 drivers/bus/qcom-ebi2.c 		.enable_mask = EBI2_CS4_ENABLE_MASK,
enable_mask       147 drivers/bus/qcom-ebi2.c 		.enable_mask = EBI2_CS5_ENABLE_MASK,
enable_mask       240 drivers/bus/qcom-ebi2.c 	val |= csd->enable_mask;
enable_mask        36 drivers/clk/clk-palmas.c 	unsigned int enable_mask;
enable_mask        68 drivers/clk/clk-palmas.c 				 cinfo->clk_desc->enable_mask,
enable_mask        69 drivers/clk/clk-palmas.c 				 cinfo->clk_desc->enable_mask);
enable_mask        93 drivers/clk/clk-palmas.c 				 cinfo->clk_desc->enable_mask, 0);
enable_mask       115 drivers/clk/clk-palmas.c 	return !!(val & cinfo->clk_desc->enable_mask);
enable_mask       139 drivers/clk/clk-palmas.c 		.enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
enable_mask       155 drivers/clk/clk-palmas.c 		.enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
enable_mask       952 drivers/clk/microchip/clk-core.c 	u32 enable_mask;
enable_mask       966 drivers/clk/microchip/clk-core.c 	writel(sosc->enable_mask, PIC32_SET(sosc->enable_reg));
enable_mask       978 drivers/clk/microchip/clk-core.c 	writel(sosc->enable_mask, PIC32_CLR(sosc->enable_reg));
enable_mask       987 drivers/clk/microchip/clk-core.c 	enabled = readl(sosc->enable_reg) & sosc->enable_mask;
enable_mask      1018 drivers/clk/microchip/clk-core.c 	sosc->enable_mask = data->enable_mask;
enable_mask        53 drivers/clk/microchip/clk-core.h 	const u32 enable_mask;
enable_mask       112 drivers/clk/microchip/clk-pic32mzda.c 	.enable_mask = BIT(1),
enable_mask        25 drivers/clk/mmp/clk-apmu.c 	u32		enable_mask;
enable_mask        38 drivers/clk/mmp/clk-apmu.c 	data = readl_relaxed(apmu->base) | apmu->enable_mask;
enable_mask        56 drivers/clk/mmp/clk-apmu.c 	data = readl_relaxed(apmu->base) & ~apmu->enable_mask;
enable_mask        69 drivers/clk/mmp/clk-apmu.c 		void __iomem *base, u32 enable_mask, spinlock_t *lock)
enable_mask        86 drivers/clk/mmp/clk-apmu.c 	apmu->enable_mask = enable_mask;
enable_mask       134 drivers/clk/mmp/clk.h 		const char *parent_name, void __iomem *base, u32 enable_mask,
enable_mask        84 drivers/clk/mvebu/clk-corediv.c 	u32 enable_mask = BIT(desc->fieldbit) << soc_desc->enable_bit_offset;
enable_mask        86 drivers/clk/mvebu/clk-corediv.c 	return !!(readl(corediv->reg) & enable_mask);
enable_mask       306 drivers/clk/nxp/clk-lpc32xx.c 	u32 enable_mask;
enable_mask       399 drivers/clk/nxp/clk-lpc32xx.c 				  clk->enable_mask, clk->enable);
enable_mask       417 drivers/clk/nxp/clk-lpc32xx.c 	return ((val & clk->enable_mask) == clk->enable);
enable_mask       719 drivers/clk/nxp/clk-lpc32xx.c 	val &= clk->enable_mask | clk->busy_mask;
enable_mask       742 drivers/clk/nxp/clk-lpc32xx.c 				  clk->enable_mask, hclk_div << 7);
enable_mask       755 drivers/clk/nxp/clk-lpc32xx.c 	val &= clk->enable_mask;
enable_mask      1176 drivers/clk/nxp/clk-lpc32xx.c 					.enable_mask = (_em),		\
enable_mask       661 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       679 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       697 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       710 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       728 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       741 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       754 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       772 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       790 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       808 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       826 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       844 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       862 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       880 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       898 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       916 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       934 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       952 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       969 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       982 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       995 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1013 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1026 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1039 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1052 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1070 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1088 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1106 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1123 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1136 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1154 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1172 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1190 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1207 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1225 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1243 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1261 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1279 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1297 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1310 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1328 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1346 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1364 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1377 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1395 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1413 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1431 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1449 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1467 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1485 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1503 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask      1516 drivers/clk/qcom/camcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       147 drivers/clk/qcom/clk-pll.c 	u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
enable_mask       154 drivers/clk/qcom/clk-pll.c 	enabled = (mode & enable_mask) == enable_mask;
enable_mask       307 drivers/clk/qcom/clk-pll.c 	u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
enable_mask       314 drivers/clk/qcom/clk-pll.c 	enabled = (mode & enable_mask) == enable_mask;
enable_mask        33 drivers/clk/qcom/clk-regmap.c 		return (val & rclk->enable_mask) == 0;
enable_mask        35 drivers/clk/qcom/clk-regmap.c 		return (val & rclk->enable_mask) != 0;
enable_mask        56 drivers/clk/qcom/clk-regmap.c 		val = rclk->enable_mask;
enable_mask        59 drivers/clk/qcom/clk-regmap.c 				  rclk->enable_mask, val);
enable_mask        78 drivers/clk/qcom/clk-regmap.c 		val = rclk->enable_mask;
enable_mask        82 drivers/clk/qcom/clk-regmap.c 	regmap_update_bits(rclk->regmap, rclk->enable_reg, rclk->enable_mask,
enable_mask        24 drivers/clk/qcom/clk-regmap.h 	unsigned int enable_mask;
enable_mask       263 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       276 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       290 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       326 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       345 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       381 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       399 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       417 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       435 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       453 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       471 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       490 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       508 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       526 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       539 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       557 drivers/clk/qcom/dispcc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       119 drivers/clk/qcom/gcc-apq8084.c 	.enable_mask = BIT(0),
enable_mask       182 drivers/clk/qcom/gcc-apq8084.c 	.enable_mask = BIT(1),
enable_mask       209 drivers/clk/qcom/gcc-apq8084.c 	.enable_mask = BIT(4),
enable_mask       281 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask       298 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1324 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1378 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(12),
enable_mask      1395 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(17),
enable_mask      1411 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1428 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1445 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1462 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1479 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1496 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1513 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1530 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1547 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1564 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1581 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1598 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1615 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1632 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1649 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1666 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1683 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1700 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1718 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(15),
enable_mask      1734 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1751 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1768 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1785 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1802 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1819 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1836 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1853 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1870 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1887 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1904 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1921 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1938 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1955 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1972 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1989 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2006 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2023 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2041 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(10),
enable_mask      2058 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(3),
enable_mask      2075 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(4),
enable_mask      2092 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(5),
enable_mask      2110 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2127 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(1),
enable_mask      2144 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(2),
enable_mask      2162 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2179 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2196 drivers/clk/qcom/gcc-apq8084.c 		.enable_mask = BIT(0),
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enable_mask      1591 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1608 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1625 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1642 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1659 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1676 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1693 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1710 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1727 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1744 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1761 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1777 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1793 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1810 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1827 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1844 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1861 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1877 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1894 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1911 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1928 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1945 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1962 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1979 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      1996 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2013 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2030 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2047 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2064 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2081 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2098 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2115 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2132 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2149 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2166 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2183 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2200 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2217 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2234 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2251 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2268 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2285 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2302 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2319 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2336 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2353 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2370 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2387 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2404 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2421 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2438 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2455 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2472 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2489 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2506 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2523 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2540 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2557 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2574 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2591 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2608 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2626 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2643 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2660 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2677 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2694 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2711 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2728 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2745 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2762 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2779 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2796 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2813 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2830 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2847 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2864 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2881 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2898 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2915 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2932 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2949 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2966 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2981 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      2998 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask      3015 drivers/clk/qcom/mmcc-apq8084.c 		.enable_mask = BIT(0),
enable_mask       192 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask       207 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask       241 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask       256 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask       290 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask       305 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask       345 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask       360 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask       376 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(8),
enable_mask       409 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask       424 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask       440 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(8),
enable_mask       473 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask       488 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask       504 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(8),
enable_mask       618 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(26),
enable_mask       635 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(10),
enable_mask       652 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(13),
enable_mask       669 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask       686 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(6),
enable_mask       725 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
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enable_mask       758 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(9),
enable_mask       774 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(11),
enable_mask       835 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask       850 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask       895 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask       910 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask       996 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      1018 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      1074 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      1089 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      1105 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(13),
enable_mask      1153 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
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enable_mask      1201 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      1216 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      1281 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      1296 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      1312 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      1328 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(6),
enable_mask      1380 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      1395 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      1443 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
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enable_mask      1493 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      1509 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(12),
enable_mask      1525 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(14),
enable_mask      1541 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(16),
enable_mask      1557 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(11),
enable_mask      1614 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      1629 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      1665 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      1680 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      1733 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      1748 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      1764 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(12),
enable_mask      1780 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(24),
enable_mask      1795 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(21),
enable_mask      1810 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(22),
enable_mask      1823 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(25),
enable_mask      1838 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(23),
enable_mask      1853 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(25),
enable_mask      1868 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(19),
enable_mask      1881 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(18),
enable_mask      1896 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(23),
enable_mask      1911 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(24),
enable_mask      1926 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(12),
enable_mask      1941 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(26),
enable_mask      1956 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(25),
enable_mask      1969 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(24),
enable_mask      1982 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(7),
enable_mask      1995 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(9),
enable_mask      2010 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(18),
enable_mask      2023 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(17),
enable_mask      2038 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(22),
enable_mask      2067 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      2083 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      2115 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      2131 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      2154 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      2170 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      2193 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      2209 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      2232 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      2247 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      2270 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      2285 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      2317 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      2332 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      2364 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
enable_mask      2379 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(0),
enable_mask      2397 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(19),
enable_mask      2412 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(2),
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enable_mask      2442 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(14),
enable_mask      2457 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(4),
enable_mask      2470 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(5),
enable_mask      2485 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(6),
enable_mask      2498 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(21),
enable_mask      2511 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(10),
enable_mask      2524 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(12),
enable_mask      2539 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(15),
enable_mask      2552 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(25),
enable_mask      2565 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(1),
enable_mask      2580 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(11),
enable_mask      2593 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(13),
enable_mask      2606 drivers/clk/qcom/mmcc-msm8960.c 		.enable_mask = BIT(16),
enable_mask       197 drivers/clk/qcom/mmcc-msm8974.c 	.enable_mask = BIT(0),
enable_mask       224 drivers/clk/qcom/mmcc-msm8974.c 	.enable_mask = BIT(1),
enable_mask       938 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask       954 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask       971 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask       987 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1004 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1021 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1038 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1055 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1071 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1088 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1105 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1122 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1139 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1155 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1172 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1189 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1206 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1223 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1239 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1256 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1273 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1290 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1307 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1324 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1341 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1358 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1375 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1391 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1408 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1425 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1442 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1458 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1474 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1491 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1508 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1525 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1542 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1559 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1575 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1592 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1609 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1626 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1642 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1658 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1675 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1692 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1709 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1725 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1741 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1758 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1774 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1791 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1808 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1825 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1842 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1859 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1876 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1893 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1910 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1927 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1943 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1960 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1977 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      1994 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2011 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2028 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2045 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2061 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2078 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2095 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2112 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2129 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2145 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2162 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2179 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2196 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2213 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2229 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2245 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2261 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2277 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask      2294 drivers/clk/qcom/mmcc-msm8974.c 		.enable_mask = BIT(0),
enable_mask       265 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask       295 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(1),
enable_mask      1233 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1248 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1263 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1278 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1292 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1307 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1322 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1337 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1352 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1367 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1382 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1397 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1412 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1427 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1442 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1457 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1472 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1487 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1502 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1517 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1532 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1547 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1562 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1577 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1592 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1607 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1622 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1637 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1652 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1667 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1682 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1697 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1712 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1727 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1742 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1757 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1772 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1787 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1802 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1817 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1832 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1847 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1862 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1877 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1892 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1907 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1922 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1937 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1952 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1967 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1982 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      1997 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2012 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2027 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2042 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2057 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2072 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2087 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2102 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2117 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2132 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2147 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2162 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2177 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2192 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2207 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2222 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2237 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2252 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2267 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2282 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2297 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2312 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2327 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2342 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2357 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2372 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2387 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2402 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2417 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2432 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2447 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2462 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2477 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2492 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2507 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2522 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2537 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2552 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2567 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2582 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2597 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2612 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2627 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2642 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2657 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2672 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2687 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2702 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2717 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2732 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2747 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2762 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2777 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2792 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2807 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2822 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2837 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2852 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2867 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask      2882 drivers/clk/qcom/mmcc-msm8996.c 		.enable_mask = BIT(0),
enable_mask        27 drivers/clk/qcom/turingcc-qcs404.c 		.enable_mask = BIT(0),
enable_mask        40 drivers/clk/qcom/turingcc-qcs404.c 		.enable_mask = BIT(0),
enable_mask        53 drivers/clk/qcom/turingcc-qcs404.c 		.enable_mask = BIT(0),
enable_mask        66 drivers/clk/qcom/turingcc-qcs404.c 		.enable_mask = BIT(0),
enable_mask        79 drivers/clk/qcom/turingcc-qcs404.c 		.enable_mask = BIT(0),
enable_mask        93 drivers/clk/qcom/videocc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       106 drivers/clk/qcom/videocc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       119 drivers/clk/qcom/videocc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       132 drivers/clk/qcom/videocc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       145 drivers/clk/qcom/videocc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       158 drivers/clk/qcom/videocc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       176 drivers/clk/qcom/videocc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       189 drivers/clk/qcom/videocc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       207 drivers/clk/qcom/videocc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       220 drivers/clk/qcom/videocc-sdm845.c 		.enable_mask = BIT(0),
enable_mask       233 drivers/clk/qcom/videocc-sdm845.c 		.enable_mask = BIT(0),
enable_mask        24 drivers/clk/sprd/gate.c 		reg |= sg->enable_mask;
enable_mask        26 drivers/clk/sprd/gate.c 		reg &= ~sg->enable_mask;
enable_mask        48 drivers/clk/sprd/gate.c 			  sg->enable_mask);
enable_mask        91 drivers/clk/sprd/gate.c 		reg ^= sg->enable_mask;
enable_mask        93 drivers/clk/sprd/gate.c 	reg &= sg->enable_mask;
enable_mask        14 drivers/clk/sprd/gate.h 	u32			enable_mask;
enable_mask        24 drivers/clk/sprd/gate.h 		.enable_mask	= _enable_mask,				\
enable_mask        64 drivers/clk/ti/apll.c 	v &= ~ad->enable_mask;
enable_mask        65 drivers/clk/ti/apll.c 	v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
enable_mask       103 drivers/clk/ti/apll.c 	v &= ~ad->enable_mask;
enable_mask       104 drivers/clk/ti/apll.c 	v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
enable_mask       117 drivers/clk/ti/apll.c 	v &= ad->enable_mask;
enable_mask       119 drivers/clk/ti/apll.c 	v >>= __ffs(ad->enable_mask);
enable_mask       225 drivers/clk/ti/apll.c 	ad->enable_mask = 0x3;
enable_mask       248 drivers/clk/ti/apll.c 	v &= ad->enable_mask;
enable_mask       250 drivers/clk/ti/apll.c 	v >>= __ffs(ad->enable_mask);
enable_mask       274 drivers/clk/ti/apll.c 	v &= ~ad->enable_mask;
enable_mask       275 drivers/clk/ti/apll.c 	v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);
enable_mask       304 drivers/clk/ti/apll.c 	v &= ~ad->enable_mask;
enable_mask       305 drivers/clk/ti/apll.c 	v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);
enable_mask       389 drivers/clk/ti/apll.c 	ad->enable_mask = 0x3 << val;
enable_mask       214 drivers/clk/ti/clkt_dpll.c 	v &= dd->enable_mask;
enable_mask       215 drivers/clk/ti/clkt_dpll.c 	v >>= __ffs(dd->enable_mask);
enable_mask       250 drivers/clk/ti/clkt_dpll.c 	v &= dd->enable_mask;
enable_mask       251 drivers/clk/ti/clkt_dpll.c 	v >>= __ffs(dd->enable_mask);
enable_mask       396 drivers/clk/ti/dpll.c 		.enable_mask = 0x7,
enable_mask       421 drivers/clk/ti/dpll.c 		.enable_mask = 0x7,
enable_mask       440 drivers/clk/ti/dpll.c 		.enable_mask = 0x7 << 16,
enable_mask       460 drivers/clk/ti/dpll.c 		.enable_mask = 0x7 << 16,
enable_mask       483 drivers/clk/ti/dpll.c 		.enable_mask = 0x7,
enable_mask       502 drivers/clk/ti/dpll.c 		.enable_mask = 0x7,
enable_mask       523 drivers/clk/ti/dpll.c 		.enable_mask = 0x7,
enable_mask       544 drivers/clk/ti/dpll.c 		.enable_mask = 0x7,
enable_mask       565 drivers/clk/ti/dpll.c 		.enable_mask = 0x7,
enable_mask       587 drivers/clk/ti/dpll.c 		.enable_mask = 0x7,
enable_mask       606 drivers/clk/ti/dpll.c 		.enable_mask = 0x7,
enable_mask       626 drivers/clk/ti/dpll.c 		.enable_mask = 0x7,
enable_mask       647 drivers/clk/ti/dpll.c 		.enable_mask = 0x7,
enable_mask       665 drivers/clk/ti/dpll.c 		.enable_mask = 0x7,
enable_mask       683 drivers/clk/ti/dpll.c 		.enable_mask = 0x3,
enable_mask        55 drivers/clk/ti/dpll3xxx.c 	v &= ~dd->enable_mask;
enable_mask        56 drivers/clk/ti/dpll3xxx.c 	v |= clken_bits << __ffs(dd->enable_mask);
enable_mask       771 drivers/clk/ti/dpll3xxx.c 	WARN_ON(!dd->enable_mask);
enable_mask       773 drivers/clk/ti/dpll3xxx.c 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;
enable_mask       774 drivers/clk/ti/dpll3xxx.c 	v >>= __ffs(dd->enable_mask);
enable_mask       798 drivers/clk/ti/dpll3xxx.c 	clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
enable_mask       859 drivers/clk/ti/dpll3xxx.c 	clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
enable_mask       890 drivers/clk/ti/dpll3xxx.c 	if (clk->context == ((ctrl & dd->enable_mask) >>
enable_mask       891 drivers/clk/ti/dpll3xxx.c 			     __ffs(dd->enable_mask)) &&
enable_mask        82 drivers/clocksource/timer-armada-370-xp.c static u32 enable_mask;
enable_mask       122 drivers/clocksource/timer-armada-370-xp.c 	local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
enable_mask       151 drivers/clocksource/timer-armada-370-xp.c 	local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
enable_mask       262 drivers/clocksource/timer-armada-370-xp.c 		enable_mask = TIMER0_EN;
enable_mask       265 drivers/clocksource/timer-armada-370-xp.c 		enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
enable_mask       286 drivers/clocksource/timer-armada-370-xp.c 		TIMER0_RELOAD_EN | enable_mask,
enable_mask       287 drivers/clocksource/timer-armada-370-xp.c 		TIMER0_RELOAD_EN | enable_mask);
enable_mask       402 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 				 local_cac_reg->enable_mask);
enable_mask      2110 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	u32 enable_mask, i;
enable_mask      2112 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
enable_mask      2117 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		if (enable_mask & (1 << i))
enable_mask      2130 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	u32 enable_mask, i;
enable_mask      2132 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
enable_mask      2137 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		if (enable_mask & (1 << i))
enable_mask        92 drivers/gpu/drm/amd/amdgpu/kv_dpm.h 	u32 enable_mask;
enable_mask       218 drivers/gpu/drm/amd/amdgpu/kv_dpm.h int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask);
enable_mask        56 drivers/gpu/drm/amd/amdgpu/kv_smc.c int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask)
enable_mask        63 drivers/gpu/drm/amd/amdgpu/kv_smc.c 		*enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0);
enable_mask        94 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 		.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
enable_mask       109 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 		.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
enable_mask       122 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 		.enable_mask =\
enable_mask       137 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 		.enable_mask =\
enable_mask       153 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 		.enable_mask =\
enable_mask       107 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c 	.enable_mask = \
enable_mask        97 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c 		.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
enable_mask       112 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c 		.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
enable_mask       126 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c 		.enable_mask =\
enable_mask       141 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c 		.enable_mask =\
enable_mask       157 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c 		.enable_mask =\
enable_mask       188 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c 	.enable_mask = \
enable_mask       190 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c 	.enable_mask = \
enable_mask       186 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c 	.enable_mask = \
enable_mask        97 drivers/gpu/drm/amd/display/dc/irq/irq_service.c 	value = (value & ~info->enable_mask) |
enable_mask        98 drivers/gpu/drm/amd/display/dc/irq/irq_service.c 		(info->enable_value[enable ? 0 : 1] & info->enable_mask);
enable_mask        50 drivers/gpu/drm/amd/display/dc/irq/irq_service.h 	uint32_t enable_mask;
enable_mask        94 drivers/gpu/drm/i915/display/intel_fifo_underrun.c 	u32 enable_mask;
enable_mask       101 drivers/gpu/drm/i915/display/intel_fifo_underrun.c 	enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
enable_mask       102 drivers/gpu/drm/i915/display/intel_fifo_underrun.c 	I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
enable_mask       119 drivers/gpu/drm/i915/display/intel_fifo_underrun.c 		u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
enable_mask       121 drivers/gpu/drm/i915/display/intel_fifo_underrun.c 		I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
enable_mask        93 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask)
enable_mask        97 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c 	gt->pm_ier |= enable_mask;
enable_mask        99 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c 	gen6_gt_pm_unmask_irq(gt, enable_mask);
enable_mask        17 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask);
enable_mask       597 drivers/gpu/drm/i915/i915_irq.c 	u32 enable_mask = status_mask << 16;
enable_mask       617 drivers/gpu/drm/i915/i915_irq.c 	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
enable_mask       621 drivers/gpu/drm/i915/i915_irq.c 		enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
enable_mask       623 drivers/gpu/drm/i915/i915_irq.c 		enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
enable_mask       626 drivers/gpu/drm/i915/i915_irq.c 	WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
enable_mask       629 drivers/gpu/drm/i915/i915_irq.c 		  pipe_name(pipe), enable_mask, status_mask);
enable_mask       631 drivers/gpu/drm/i915/i915_irq.c 	return enable_mask;
enable_mask       638 drivers/gpu/drm/i915/i915_irq.c 	u32 enable_mask;
enable_mask       651 drivers/gpu/drm/i915/i915_irq.c 	enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
enable_mask       653 drivers/gpu/drm/i915/i915_irq.c 	I915_WRITE(reg, enable_mask | status_mask);
enable_mask       661 drivers/gpu/drm/i915/i915_irq.c 	u32 enable_mask;
enable_mask       674 drivers/gpu/drm/i915/i915_irq.c 	enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
enable_mask       676 drivers/gpu/drm/i915/i915_irq.c 	I915_WRITE(reg, enable_mask | status_mask);
enable_mask      1730 drivers/gpu/drm/i915/i915_irq.c 		u32 status_mask, enable_mask, iir_bit = 0;
enable_mask      1762 drivers/gpu/drm/i915/i915_irq.c 		enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
enable_mask      1775 drivers/gpu/drm/i915/i915_irq.c 			I915_WRITE(reg, enable_mask);
enable_mask      3187 drivers/gpu/drm/i915/i915_irq.c 	u32 enable_mask;
enable_mask      3196 drivers/gpu/drm/i915/i915_irq.c 	enable_mask = I915_DISPLAY_PORT_INTERRUPT |
enable_mask      3203 drivers/gpu/drm/i915/i915_irq.c 		enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
enable_mask      3208 drivers/gpu/drm/i915/i915_irq.c 	dev_priv->irq_mask = ~enable_mask;
enable_mask      3210 drivers/gpu/drm/i915/i915_irq.c 	GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
enable_mask      3907 drivers/gpu/drm/i915/i915_irq.c 	u16 enable_mask;
enable_mask      3920 drivers/gpu/drm/i915/i915_irq.c 	enable_mask =
enable_mask      3926 drivers/gpu/drm/i915/i915_irq.c 	GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
enable_mask      4074 drivers/gpu/drm/i915/i915_irq.c 	u32 enable_mask;
enable_mask      4086 drivers/gpu/drm/i915/i915_irq.c 	enable_mask =
enable_mask      4095 drivers/gpu/drm/i915/i915_irq.c 		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
enable_mask      4100 drivers/gpu/drm/i915/i915_irq.c 	GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
enable_mask      4180 drivers/gpu/drm/i915/i915_irq.c 	u32 enable_mask;
enable_mask      4206 drivers/gpu/drm/i915/i915_irq.c 	enable_mask =
enable_mask      4215 drivers/gpu/drm/i915/i915_irq.c 		enable_mask |= I915_BSD_USER_INTERRUPT;
enable_mask      4217 drivers/gpu/drm/i915/i915_irq.c 	GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
enable_mask       986 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	u32 enable_mask;
enable_mask       999 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off);
enable_mask      1007 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		intr->save_irq_status[i] &= enable_mask;
enable_mask      1945 drivers/gpu/drm/omapdrm/dss/dsi.c 	u32 enable_mask, enable_shift;
enable_mask      1949 drivers/gpu/drm/omapdrm/dss/dsi.c 		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
enable_mask      1954 drivers/gpu/drm/omapdrm/dss/dsi.c 		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
enable_mask      1963 drivers/gpu/drm/omapdrm/dss/dsi.c 		enable_mask | pipd_mask,
enable_mask       259 drivers/gpu/drm/radeon/dce6_afmt.c 		       u8 enable_mask)
enable_mask       265 drivers/gpu/drm/radeon/dce6_afmt.c 			enable_mask ? AUDIO_ENABLED : 0);
enable_mask        39 drivers/gpu/drm/radeon/evergreen_hdmi.c 			      u8 enable_mask)
enable_mask        46 drivers/gpu/drm/radeon/evergreen_hdmi.c 	if (enable_mask) {
enable_mask        48 drivers/gpu/drm/radeon/evergreen_hdmi.c 		if (enable_mask & 1)
enable_mask        50 drivers/gpu/drm/radeon/evergreen_hdmi.c 		if (enable_mask & 2)
enable_mask        52 drivers/gpu/drm/radeon/evergreen_hdmi.c 		if (enable_mask & 4)
enable_mask        54 drivers/gpu/drm/radeon/evergreen_hdmi.c 		if (enable_mask & 8)
enable_mask       276 drivers/gpu/drm/radeon/kv_dpm.c 				 local_cac_reg->enable_mask);
enable_mask      2044 drivers/gpu/drm/radeon/kv_dpm.c 	u32 enable_mask, i;
enable_mask      2046 drivers/gpu/drm/radeon/kv_dpm.c 	ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
enable_mask      2051 drivers/gpu/drm/radeon/kv_dpm.c 		if (enable_mask & (1 << i))
enable_mask      2064 drivers/gpu/drm/radeon/kv_dpm.c 	u32 enable_mask, i;
enable_mask      2066 drivers/gpu/drm/radeon/kv_dpm.c 	ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
enable_mask      2071 drivers/gpu/drm/radeon/kv_dpm.c 		if (enable_mask & (1 << i))
enable_mask        66 drivers/gpu/drm/radeon/kv_dpm.h 	u32 enable_mask;
enable_mask       189 drivers/gpu/drm/radeon/kv_dpm.h int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);
enable_mask        53 drivers/gpu/drm/radeon/kv_smc.c int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask)
enable_mask        60 drivers/gpu/drm/radeon/kv_smc.c 		*enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0);
enable_mask       143 drivers/gpu/drm/radeon/r600_hdmi.c 		       u8 enable_mask)
enable_mask       150 drivers/gpu/drm/radeon/r600_hdmi.c 	if (enable_mask) {
enable_mask       152 drivers/gpu/drm/radeon/r600_hdmi.c 		if (enable_mask & 1)
enable_mask       154 drivers/gpu/drm/radeon/r600_hdmi.c 		if (enable_mask & 2)
enable_mask       156 drivers/gpu/drm/radeon/r600_hdmi.c 		if (enable_mask & 4)
enable_mask       158 drivers/gpu/drm/radeon/r600_hdmi.c 		if (enable_mask & 8)
enable_mask      2875 drivers/gpu/drm/radeon/radeon.h 		       u8 enable_mask);
enable_mask      2878 drivers/gpu/drm/radeon/radeon.h 		       u8 enable_mask);
enable_mask        33 drivers/gpu/drm/radeon/radeon_audio.c 		u8 enable_mask);
enable_mask        35 drivers/gpu/drm/radeon/radeon_audio.c 		u8 enable_mask);
enable_mask        37 drivers/gpu/drm/radeon/radeon_audio.c 		u8 enable_mask);
enable_mask       246 drivers/gpu/drm/radeon/radeon_audio.c 				struct r600_audio_pin *pin, u8 enable_mask)
enable_mask       266 drivers/gpu/drm/radeon/radeon_audio.c 		if ((pin_count > 1) && (enable_mask == 0))
enable_mask       271 drivers/gpu/drm/radeon/radeon_audio.c 		rdev->audio.funcs->enable(rdev, pin, enable_mask);
enable_mask        41 drivers/gpu/drm/radeon/radeon_audio.h 		struct r600_audio_pin *pin, u8 enable_mask);
enable_mask        66 drivers/gpu/drm/via/via_drv.h 	uint32_t enable_mask;
enable_mask       284 drivers/gpu/drm/via/via_irq.c 			cur_irq->enable_mask = dev_priv->irq_masks[i][0];
enable_mask       287 drivers/gpu/drm/via/via_irq.c 			dev_priv->irq_enable_mask |= cur_irq->enable_mask;
enable_mask       916 drivers/iio/adc/meson_saradc.c 	u32 enable_mask;
enable_mask       919 drivers/iio/adc/meson_saradc.c 		enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;
enable_mask       921 drivers/iio/adc/meson_saradc.c 		enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;
enable_mask       923 drivers/iio/adc/meson_saradc.c 	regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask,
enable_mask       924 drivers/iio/adc/meson_saradc.c 			   on_off ? enable_mask : 0);
enable_mask       534 drivers/iio/imu/adis16480.c 	unsigned int enable_mask, offset, reg;
enable_mask       540 drivers/iio/imu/adis16480.c 	enable_mask = BIT(offset + 2);
enable_mask       546 drivers/iio/imu/adis16480.c 	if (!(val & enable_mask))
enable_mask       558 drivers/iio/imu/adis16480.c 	unsigned int enable_mask, offset, reg;
enable_mask       566 drivers/iio/imu/adis16480.c 	enable_mask = BIT(offset + 2);
enable_mask       573 drivers/iio/imu/adis16480.c 		val &= ~enable_mask;
enable_mask       589 drivers/iio/imu/adis16480.c 		val |= enable_mask;
enable_mask       321 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h 	u8 enable_mask;
enable_mask       113 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c 		if (!(hw->enable_mask & BIT(sensor->id)))
enable_mask       139 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c 		if (hw->enable_mask & BIT(sensor->id)) {
enable_mask       223 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c 		data = hw->enable_mask ? ST_LSM6DSX_MAX_FIFO_ODR_VAL : 0;
enable_mask       249 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c 		if (!(hw->enable_mask & BIT(cur_sensor->id)))
enable_mask       480 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c 		if (hw->enable_mask & BIT(ST_LSM6DSX_ID_EXT0))
enable_mask       482 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c 		else if (hw->enable_mask & BIT(ST_LSM6DSX_ID_EXT1))
enable_mask       488 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c 		if ((hw->enable_mask & BIT(ST_LSM6DSX_ID_EXT0)) &&
enable_mask       489 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c 		    (hw->enable_mask & BIT(ST_LSM6DSX_ID_EXT1)))
enable_mask       642 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c 	if (hw->enable_mask) {
enable_mask       999 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 		if (hw->enable_mask & BIT(id))
enable_mask      1004 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 		return (hw->enable_mask & BIT(id)) ? ref->odr : 0;
enable_mask      1070 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 		hw->enable_mask |= BIT(sensor->id);
enable_mask      1072 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 		hw->enable_mask &= ~BIT(sensor->id);
enable_mask      1559 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 		if (!(hw->enable_mask & BIT(sensor->id)))
enable_mask      1606 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 	if (hw->enable_mask)
enable_mask        99 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c 	odr = (hw->enable_mask & BIT(ST_LSM6DSX_ID_ACC)) ? sensor->odr : 13;
enable_mask       362 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c 	u8 config[9] = {}, enable_mask, slv_addr;
enable_mask       369 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c 		enable_mask = hw->enable_mask | BIT(sensor->id);
enable_mask       371 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c 		enable_mask = hw->enable_mask & ~BIT(sensor->id);
enable_mask       378 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c 		if (!(enable_mask & BIT(cur_sensor->id)))
enable_mask       544 drivers/iio/light/tcs3472.c 	u8 enable_mask = TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON;
enable_mask       549 drivers/iio/light/tcs3472.c 		data->enable & ~enable_mask);
enable_mask       551 drivers/iio/light/tcs3472.c 		data->enable &= ~enable_mask;
enable_mask       583 drivers/iio/light/tcs3472.c 	u8 enable_mask = TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON;
enable_mask       588 drivers/iio/light/tcs3472.c 		data->enable | enable_mask);
enable_mask       590 drivers/iio/light/tcs3472.c 		data->enable |= enable_mask;
enable_mask        23 drivers/input/misc/pm8xxx-vibrator.c 	unsigned int enable_mask;
enable_mask        40 drivers/input/misc/pm8xxx-vibrator.c 	.enable_mask = BIT(7),
enable_mask        91 drivers/input/misc/pm8xxx-vibrator.c 	if (regs->enable_mask)
enable_mask        93 drivers/input/misc/pm8xxx-vibrator.c 					regs->enable_mask, on ? ~0 : 0);
enable_mask       938 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c 		    NPC_AF_KPUX_ENTRY_DISX(kpu, 0), enable_mask(num_entries));
enable_mask       942 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c 			    enable_mask(num_entries - 64));
enable_mask      3870 drivers/net/ethernet/qlogic/qed/qed_debug.c 				u8 enable_mask,
enable_mask      3877 drivers/net/ethernet/qlogic/qed/qed_debug.c 	qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, enable_mask);
enable_mask       827 drivers/net/ethernet/via/via-rhine.c 	u16 enable_mask = RHINE_EVENT & 0xffff;
enable_mask       858 drivers/net/ethernet/via/via-rhine.c 		enable_mask &= ~RHINE_EVENT_SLOW;
enable_mask       864 drivers/net/ethernet/via/via-rhine.c 		iowrite16(enable_mask, ioaddr + IntrEnable);
enable_mask        88 drivers/perf/xgene_pmu.c 	u32 enable_mask;
enable_mask      1145 drivers/perf/xgene_pmu.c 		if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask))
enable_mask      1163 drivers/perf/xgene_pmu.c 		if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask))
enable_mask      1171 drivers/perf/xgene_pmu.c 		if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask))
enable_mask      1522 drivers/perf/xgene_pmu.c 	inf->enable_mask = 1 << enable_bit;
enable_mask      1671 drivers/perf/xgene_pmu.c 	inf->enable_mask = 1 << enable_bit;
enable_mask       485 drivers/power/supply/ucs1002_power.c 	.enable_mask	= F_PWR_EN_SET,
enable_mask        31 drivers/pwm/pwm-mtk-disp.c 	u32 enable_mask;
enable_mask       148 drivers/pwm/pwm-mtk-disp.c 	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
enable_mask       149 drivers/pwm/pwm-mtk-disp.c 				 mdp->data->enable_mask);
enable_mask       158 drivers/pwm/pwm-mtk-disp.c 	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
enable_mask       253 drivers/pwm/pwm-mtk-disp.c 	.enable_mask = BIT(16),
enable_mask       263 drivers/pwm/pwm-mtk-disp.c 	.enable_mask = BIT(0),
enable_mask       273 drivers/pwm/pwm-mtk-disp.c 	.enable_mask = BIT(0),
enable_mask       102 drivers/regulator/88pm800-regulator.c 		.enable_mask		= 1 << (ebit),			\
enable_mask       130 drivers/regulator/88pm800-regulator.c 		.enable_mask		= 1 << (ebit),			\
enable_mask       242 drivers/regulator/88pm8607.c 		.enable_mask = (ebit),					\
enable_mask       264 drivers/regulator/88pm8607.c 		.enable_mask = 1 << (ebit),				\
enable_mask       285 drivers/regulator/88pm8607.c 		.enable_mask = 1 << (ebit),				\
enable_mask        25 drivers/regulator/aat2870-regulator.c 	u8 enable_mask;
enable_mask        61 drivers/regulator/aat2870-regulator.c 	return aat2870->update(aat2870, ri->enable_addr, ri->enable_mask,
enable_mask        62 drivers/regulator/aat2870-regulator.c 			       ri->enable_mask);
enable_mask        70 drivers/regulator/aat2870-regulator.c 	return aat2870->update(aat2870, ri->enable_addr, ri->enable_mask, 0);
enable_mask        84 drivers/regulator/aat2870-regulator.c 	return val & ri->enable_mask ? 1 : 0;
enable_mask       140 drivers/regulator/aat2870-regulator.c 	ri->enable_mask = 0x1 << ri->enable_shift;
enable_mask       453 drivers/regulator/act8865-regulator.c 		.enable_mask		= ACT8865_ENA,			\
enable_mask       482 drivers/regulator/act8865-regulator.c 		.enable_mask = ACT8865_ENA,
enable_mask       499 drivers/regulator/act8865-regulator.c 		.enable_mask = ACT8865_ENA,
enable_mask       512 drivers/regulator/act8865-regulator.c 		.enable_mask = ACT8600_LDO10_ENA,
enable_mask       250 drivers/regulator/act8945a-regulator.c 		.enable_mask		= ACT8945A_ENA,			\
enable_mask       301 drivers/regulator/anatop-regulator.c 			rdesc->enable_mask = BIT(enable_bit);
enable_mask       143 drivers/regulator/arizona-micsupp.c 	.enable_mask = ARIZONA_CPMIC_ENA,
enable_mask       170 drivers/regulator/arizona-micsupp.c 	.enable_mask = ARIZONA_CPMIC_ENA,
enable_mask       216 drivers/regulator/arizona-micsupp.c 	.enable_mask = MADERA_CPMIC_ENA,
enable_mask        30 drivers/regulator/as3711-regulator.c 	unsigned int fast_bit = rdev->desc->enable_mask,
enable_mask        54 drivers/regulator/as3711-regulator.c 	unsigned int fast_bit = rdev->desc->enable_mask,
enable_mask       133 drivers/regulator/as3711-regulator.c 		.enable_mask = BIT(_en_bit),				   \
enable_mask        54 drivers/regulator/as3722-regulator.c 	u8 enable_mask;
enable_mask        82 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_SDn_CTRL(0),
enable_mask        94 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_SDn_CTRL(1),
enable_mask       107 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_SDn_CTRL(2),
enable_mask       121 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_SDn_CTRL(3),
enable_mask       135 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_SDn_CTRL(4),
enable_mask       149 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_SDn_CTRL(5),
enable_mask       162 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_SDn_CTRL(6),
enable_mask       175 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_LDO0_CTRL,
enable_mask       187 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_LDO1_CTRL,
enable_mask       199 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_LDO2_CTRL,
enable_mask       211 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_LDO3_CTRL,
enable_mask       223 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_LDO4_CTRL,
enable_mask       235 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_LDO5_CTRL,
enable_mask       247 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_LDO6_CTRL,
enable_mask       259 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_LDO7_CTRL,
enable_mask       271 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_LDO9_CTRL,
enable_mask       283 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_LDO10_CTRL,
enable_mask       295 drivers/regulator/as3722-regulator.c 		.enable_mask = AS3722_LDO11_CTRL,
enable_mask       675 drivers/regulator/as3722-regulator.c 		desc->enable_mask = as3722_reg_lookup[id].enable_mask;
enable_mask       288 drivers/regulator/axp20x-regulator.c 		.enable_mask	= (_emask),					\
enable_mask       310 drivers/regulator/axp20x-regulator.c 		.enable_mask	= (_emask),					\
enable_mask       324 drivers/regulator/axp20x-regulator.c 		.enable_mask	= (_emask),					\
enable_mask       356 drivers/regulator/axp20x-regulator.c 		.enable_mask	= (_emask),					\
enable_mask       638 drivers/regulator/axp20x-regulator.c 	.enable_mask	= AXP20X_VBUS_IPSOUT_MGMT_MASK,
enable_mask       324 drivers/regulator/bcm590xx-regulator.c 			pmu->desc[i].enable_mask = BCM590XX_VBUS_ENABLE;
enable_mask       328 drivers/regulator/bcm590xx-regulator.c 			pmu->desc[i].enable_mask = BCM590XX_REG_ENABLE;
enable_mask       127 drivers/regulator/bd70528-regulator.c 		.enable_mask = BD70528_MASK_RUN_EN,
enable_mask       143 drivers/regulator/bd70528-regulator.c 		.enable_mask = BD70528_MASK_RUN_EN,
enable_mask       159 drivers/regulator/bd70528-regulator.c 		.enable_mask = BD70528_MASK_RUN_EN,
enable_mask       175 drivers/regulator/bd70528-regulator.c 		.enable_mask = BD70528_MASK_RUN_EN,
enable_mask       191 drivers/regulator/bd70528-regulator.c 		.enable_mask = BD70528_MASK_RUN_EN,
enable_mask       207 drivers/regulator/bd70528-regulator.c 		.enable_mask = BD70528_MASK_RUN_EN,
enable_mask       222 drivers/regulator/bd70528-regulator.c 		.enable_mask = BD70528_MASK_LED1_EN,
enable_mask       237 drivers/regulator/bd70528-regulator.c 		.enable_mask = BD70528_MASK_LED2_EN,
enable_mask       497 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       521 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       549 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       576 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       598 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       622 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       648 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_LDO_EN,
enable_mask       670 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_LDO_EN,
enable_mask       693 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_LDO_EN,
enable_mask       716 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_LDO_EN,
enable_mask       742 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_LDO_EN,
enable_mask       767 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_LDO_EN,
enable_mask       793 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       817 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       841 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       865 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       893 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       917 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       939 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       963 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_BUCK_EN,
enable_mask       989 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_LDO_EN,
enable_mask      1011 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_LDO_EN,
enable_mask      1034 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_LDO_EN,
enable_mask      1057 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_LDO_EN,
enable_mask      1082 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_LDO_EN,
enable_mask      1109 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_LDO_EN,
enable_mask      1134 drivers/regulator/bd718x7-regulator.c 			.enable_mask = BD718XX_LDO_EN,
enable_mask       121 drivers/regulator/cpcap-regulator.c 		.enable_mask = (mode_mask),				\
enable_mask       299 drivers/regulator/da9052-regulator.c 		.enable_mask = 1 << (ebits),\
enable_mask       321 drivers/regulator/da9052-regulator.c 		.enable_mask = 1 << (ebits),\
enable_mask       342 drivers/regulator/da9055-regulator.c 		.enable_mask = 1, \
enable_mask       372 drivers/regulator/da9055-regulator.c 		.enable_mask = 1,\
enable_mask       370 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_BUCK1_EN_MASK,
enable_mask       406 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_BUCK3_EN_MASK,
enable_mask       442 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_BUCK4_EN_MASK,
enable_mask       475 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_LDO1_EN_MASK,
enable_mask       508 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_LDO2_EN_MASK,
enable_mask       541 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_LDO3_EN_MASK,
enable_mask       574 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_LDO4_EN_MASK,
enable_mask       614 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_BUCK1_EN_MASK,
enable_mask       650 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_BUCK2_EN_MASK,
enable_mask       686 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_BUCK3_EN_MASK,
enable_mask       722 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_BUCK4_EN_MASK,
enable_mask       755 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_LDO1_EN_MASK,
enable_mask       788 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_LDO2_EN_MASK,
enable_mask       821 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_LDO3_EN_MASK,
enable_mask       854 drivers/regulator/da9062-regulator.c 		.desc.enable_mask = DA9062AA_LDO4_EN_MASK,
enable_mask        98 drivers/regulator/da9063-regulator.c 	.desc.enable_mask = DA9063_LDO_EN, \
enable_mask       122 drivers/regulator/da9063-regulator.c 	.desc.enable_mask = DA9063_BUCK_EN, \
enable_mask        62 drivers/regulator/da9210-regulator.c 	.enable_mask = DA9210_BUCK_EN,
enable_mask       235 drivers/regulator/da9211-regulator.c 	.enable_mask = DA9211_BUCKA_EN,\
enable_mask       399 drivers/regulator/fan53555.c 	rdesc->enable_mask = VSEL_BUCK_EN;
enable_mask        36 drivers/regulator/helpers.c 	val &= rdev->desc->enable_mask;
enable_mask        68 drivers/regulator/helpers.c 			val = rdev->desc->enable_mask;
enable_mask        72 drivers/regulator/helpers.c 				  rdev->desc->enable_mask, val);
enable_mask        92 drivers/regulator/helpers.c 			val = rdev->desc->enable_mask;
enable_mask        98 drivers/regulator/helpers.c 				  rdev->desc->enable_mask, val);
enable_mask       145 drivers/regulator/hi6421-regulator.c 			.enable_mask	= emask,			\
enable_mask       185 drivers/regulator/hi6421-regulator.c 			.enable_mask	= emask,			\
enable_mask       225 drivers/regulator/hi6421-regulator.c 			.enable_mask	= emask,			\
enable_mask       262 drivers/regulator/hi6421-regulator.c 			.enable_mask	= emask,			\
enable_mask       298 drivers/regulator/hi6421-regulator.c 			.enable_mask	= emask,			\
enable_mask        88 drivers/regulator/hi6421v530-regulator.c 		.enable_mask	 = emask,				\
enable_mask        78 drivers/regulator/hi655x-regulator.c 	return (value & rdev->desc->enable_mask);
enable_mask        86 drivers/regulator/hi655x-regulator.c 			    rdev->desc->enable_mask);
enable_mask       122 drivers/regulator/hi655x-regulator.c 		.enable_mask     = BIT(cmask),                   \
enable_mask       144 drivers/regulator/hi655x-regulator.c 		.enable_mask     = BIT(cmask),                   \
enable_mask        80 drivers/regulator/isl9305.c 		.enable_mask =	ISL9305_DCD1_EN,
enable_mask        95 drivers/regulator/isl9305.c 		.enable_mask =	ISL9305_DCD2_EN,
enable_mask       110 drivers/regulator/isl9305.c 		.enable_mask =	ISL9305_LDO1_EN,
enable_mask       125 drivers/regulator/isl9305.c 		.enable_mask =	ISL9305_LDO2_EN,
enable_mask       131 drivers/regulator/lm363x-regulator.c 		.enable_mask    = LM3631_EN_CONT_MASK,
enable_mask       146 drivers/regulator/lm363x-regulator.c 		.enable_mask    = LM3631_EN_OREF_MASK,
enable_mask       161 drivers/regulator/lm363x-regulator.c 		.enable_mask    = LM3631_EN_VPOS_MASK,
enable_mask       176 drivers/regulator/lm363x-regulator.c 		.enable_mask    = LM3631_EN_VNEG_MASK,
enable_mask       205 drivers/regulator/lm363x-regulator.c 		.enable_mask    = LM3632_EN_VPOS_MASK,
enable_mask       220 drivers/regulator/lm363x-regulator.c 		.enable_mask    = LM3632_EN_VNEG_MASK,
enable_mask       250 drivers/regulator/lm363x-regulator.c 		.enable_mask    = LM36274_EN_VPOS_MASK,
enable_mask       265 drivers/regulator/lm363x-regulator.c 		.enable_mask    = LM36274_EN_VNEG_MASK,
enable_mask       151 drivers/regulator/lochnagar-regulator.c 		.enable_mask = LOCHNAGAR2_MICVDD_REG_ENA_MASK,
enable_mask       174 drivers/regulator/lochnagar-regulator.c 		.enable_mask = LOCHNAGAR2_P1_INPUT_BIAS_ENA_MASK,
enable_mask       189 drivers/regulator/lochnagar-regulator.c 		.enable_mask = LOCHNAGAR2_P2_INPUT_BIAS_ENA_MASK,
enable_mask       204 drivers/regulator/lochnagar-regulator.c 		.enable_mask = LOCHNAGAR2_VDDCORE_CDC_REG_ENA_MASK,
enable_mask       471 drivers/regulator/lp872x.c 		.enable_mask = LP872X_EN_LDO1_M,
enable_mask       485 drivers/regulator/lp872x.c 		.enable_mask = LP872X_EN_LDO2_M,
enable_mask       499 drivers/regulator/lp872x.c 		.enable_mask = LP872X_EN_LDO3_M,
enable_mask       513 drivers/regulator/lp872x.c 		.enable_mask = LP872X_EN_LDO4_M,
enable_mask       527 drivers/regulator/lp872x.c 		.enable_mask = LP872X_EN_LDO5_M,
enable_mask       539 drivers/regulator/lp872x.c 		.enable_mask = LP8720_EN_BUCK_M,
enable_mask       556 drivers/regulator/lp872x.c 		.enable_mask = LP872X_EN_LDO1_M,
enable_mask       570 drivers/regulator/lp872x.c 		.enable_mask = LP872X_EN_LDO2_M,
enable_mask       584 drivers/regulator/lp872x.c 		.enable_mask = LP872X_EN_LDO3_M,
enable_mask       598 drivers/regulator/lp872x.c 		.enable_mask = LP872X_EN_LDO4_M,
enable_mask       612 drivers/regulator/lp872x.c 		.enable_mask = LP872X_EN_LDO5_M,
enable_mask       626 drivers/regulator/lp872x.c 		.enable_mask = LP8725_EN_LILO1_M,
enable_mask       640 drivers/regulator/lp872x.c 		.enable_mask = LP8725_EN_LILO2_M,
enable_mask       652 drivers/regulator/lp872x.c 		.enable_mask = LP8725_BUCK1_EN_M,
enable_mask       668 drivers/regulator/lp872x.c 		.enable_mask = LP8725_BUCK2_EN_M,
enable_mask        38 drivers/regulator/lp873x-regulator.c 			.enable_mask		= _em,			\
enable_mask       309 drivers/regulator/lp8755.c 	.enable_mask = LP8755_BUCK_EN_M,\
enable_mask        30 drivers/regulator/lp87565-regulator.c 			.enable_mask		= _em,			\
enable_mask       378 drivers/regulator/lp8788-buck.c 		.enable_mask = LP8788_EN_BUCK1_M,
enable_mask       390 drivers/regulator/lp8788-buck.c 		.enable_mask = LP8788_EN_BUCK2_M,
enable_mask       404 drivers/regulator/lp8788-buck.c 		.enable_mask = LP8788_EN_BUCK3_M,
enable_mask       418 drivers/regulator/lp8788-buck.c 		.enable_mask = LP8788_EN_BUCK4_M,
enable_mask       197 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_DLDO1_M,
enable_mask       210 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_DLDO2_M,
enable_mask       223 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_DLDO3_M,
enable_mask       236 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_DLDO4_M,
enable_mask       249 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_DLDO5_M,
enable_mask       262 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_DLDO6_M,
enable_mask       275 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_DLDO7_M,
enable_mask       288 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_DLDO8_M,
enable_mask       301 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_DLDO9_M,
enable_mask       314 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_DLDO10_M,
enable_mask       327 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_DLDO11_M,
enable_mask       337 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_DLDO12_M,
enable_mask       354 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_ALDO1_M,
enable_mask       364 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_ALDO2_M,
enable_mask       375 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_ALDO3_M,
enable_mask       386 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_ALDO4_M,
enable_mask       397 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_ALDO5_M,
enable_mask       411 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_ALDO6_M,
enable_mask       424 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_ALDO7_M,
enable_mask       434 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_ALDO8_M,
enable_mask       445 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_ALDO9_M,
enable_mask       456 drivers/regulator/lp8788-ldo.c 		.enable_mask = LP8788_EN_ALDO10_M,
enable_mask       241 drivers/regulator/ltc3589.c 		.enable_mask = (en_bit),				\
enable_mask       213 drivers/regulator/ltc3676.c 		.enable_mask = (1 << en_bit),                  \
enable_mask       104 drivers/regulator/max14577-regulator.c 	.enable_mask	= CTRL2_SFOUTORD_MASK, \
enable_mask       115 drivers/regulator/max14577-regulator.c 	.enable_mask	= CHGCTRL2_MBCHOSTEN_MASK, \
enable_mask       146 drivers/regulator/max14577-regulator.c 	.enable_mask	= MAX77836_CNFG1_LDO_PWRMD_MASK, \
enable_mask       130 drivers/regulator/max77686-regulator.c 				 rdev->desc->enable_mask, val << shift);
enable_mask       164 drivers/regulator/max77686-regulator.c 				  rdev->desc->enable_mask,
enable_mask       198 drivers/regulator/max77686-regulator.c 				 rdev->desc->enable_mask,
enable_mask       219 drivers/regulator/max77686-regulator.c 				  rdev->desc->enable_mask,
enable_mask       275 drivers/regulator/max77686-regulator.c 					 desc->enable_mask,
enable_mask       352 drivers/regulator/max77686-regulator.c 	.enable_mask	= MAX77686_OPMODE_MASK				\
enable_mask       370 drivers/regulator/max77686-regulator.c 	.enable_mask	= MAX77686_OPMODE_MASK				\
enable_mask       388 drivers/regulator/max77686-regulator.c 	.enable_mask	= MAX77686_OPMODE_MASK				\
enable_mask       406 drivers/regulator/max77686-regulator.c 	.enable_mask	= MAX77686_OPMODE_MASK				\
enable_mask       426 drivers/regulator/max77686-regulator.c 	.enable_mask	= MAX77686_OPMODE_MASK,				\
enable_mask       444 drivers/regulator/max77686-regulator.c 	.enable_mask	= MAX77686_OPMODE_MASK,				\
enable_mask       462 drivers/regulator/max77686-regulator.c 	.enable_mask	= MAX77686_OPMODE_MASK				\
enable_mask       160 drivers/regulator/max77693-regulator.c 	.enable_mask	= SAFEOUT_CTRL_ENSAFEOUT##_num##_MASK ,	\
enable_mask       175 drivers/regulator/max77693-regulator.c 		.enable_mask = CHG_CNFG_00_CHG_MASK |
enable_mask       199 drivers/regulator/max77693-regulator.c 	.enable_mask	= MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT ## num,	\
enable_mask       216 drivers/regulator/max77693-regulator.c 		.enable_mask	= MAX77843_CHG_MASK,
enable_mask       103 drivers/regulator/max77802-regulator.c 				  rdev->desc->enable_mask, val << shift);
enable_mask       133 drivers/regulator/max77802-regulator.c 				  rdev->desc->enable_mask, val << shift);
enable_mask       207 drivers/regulator/max77802-regulator.c 				  rdev->desc->enable_mask, val << shift);
enable_mask       220 drivers/regulator/max77802-regulator.c 				  rdev->desc->enable_mask,
enable_mask       369 drivers/regulator/max77802-regulator.c 	.enable_mask	= MAX77802_OPMODE_MASK << MAX77802_OPMODE_SHIFT_LDO, \
enable_mask       390 drivers/regulator/max77802-regulator.c 	.enable_mask	= MAX77802_OPMODE_MASK << MAX77802_OPMODE_SHIFT_LDO, \
enable_mask       411 drivers/regulator/max77802-regulator.c 	.enable_mask	= MAX77802_OPMODE_MASK,				\
enable_mask       432 drivers/regulator/max77802-regulator.c 	.enable_mask	= MAX77802_OPMODE_MASK <<			\
enable_mask       454 drivers/regulator/max77802-regulator.c 	.enable_mask	= MAX77802_OPMODE_MASK,				\
enable_mask       475 drivers/regulator/max77802-regulator.c 	.enable_mask	= MAX77802_OPMODE_MASK,				\
enable_mask       139 drivers/regulator/max8649.c 	.enable_mask	= MAX8649_EN_PD,
enable_mask        60 drivers/regulator/max8907-regulator.c 		.enable_mask = MAX8907_MASK_LDO_EN, \
enable_mask        86 drivers/regulator/max8907-regulator.c 		.enable_mask = MAX8907_MASK_OUT5V_EN, \
enable_mask       749 drivers/regulator/max8973-regulator.c 			max->desc.enable_mask = MAX8973_VOUT_ENABLE;
enable_mask       788 drivers/regulator/max8973-regulator.c 		max->desc.enable_mask = MAX8973_VOUT_ENABLE;
enable_mask       102 drivers/regulator/mcp16502.c 		.enable_mask		= MCP16502_EN,			\
enable_mask        62 drivers/regulator/mt6311-regulator.c 	.enable_mask = MT6311_PMIC_VDVFS11_EN_MASK,\
enable_mask        77 drivers/regulator/mt6311-regulator.c 	.enable_mask = MT6311_PMIC_RG_VBIASN_EN_MASK,\
enable_mask        55 drivers/regulator/mt6323-regulator.c 		.enable_mask = BIT(0),					\
enable_mask        78 drivers/regulator/mt6323-regulator.c 		.enable_mask = BIT(enbit),				\
enable_mask        97 drivers/regulator/mt6323-regulator.c 		.enable_mask = BIT(enbit),				\
enable_mask        57 drivers/regulator/mt6358-regulator.c 		.enable_mask = BIT(0),	\
enable_mask        86 drivers/regulator/mt6358-regulator.c 		.enable_mask = BIT(enbit),	\
enable_mask       112 drivers/regulator/mt6358-regulator.c 		.enable_mask = BIT(0),	\
enable_mask       133 drivers/regulator/mt6358-regulator.c 		.enable_mask = BIT(enbit),	\
enable_mask       108 drivers/regulator/mt6380-regulator.c 		.enable_mask = BIT(enbit),				\
enable_mask       130 drivers/regulator/mt6380-regulator.c 		.enable_mask = BIT(enbit),				\
enable_mask       148 drivers/regulator/mt6380-regulator.c 		.enable_mask = BIT(enbit),				\
enable_mask        57 drivers/regulator/mt6397-regulator.c 		.enable_mask = BIT(0),					\
enable_mask        83 drivers/regulator/mt6397-regulator.c 		.enable_mask = BIT(enbit),				\
enable_mask        99 drivers/regulator/mt6397-regulator.c 		.enable_mask = BIT(enbit),				\
enable_mask       935 drivers/regulator/palmas-regulator.c 			desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
enable_mask       970 drivers/regulator/palmas-regulator.c 			desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
enable_mask      1053 drivers/regulator/palmas-regulator.c 			desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
enable_mask      1077 drivers/regulator/palmas-regulator.c 			desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
enable_mask      1208 drivers/regulator/palmas-regulator.c 				desc->enable_mask = SMPS10_SWITCH_EN;
enable_mask      1210 drivers/regulator/palmas-regulator.c 				desc->enable_mask = SMPS10_BOOST_EN;
enable_mask      1257 drivers/regulator/palmas-regulator.c 			desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
enable_mask      1362 drivers/regulator/palmas-regulator.c 		desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
enable_mask        32 drivers/regulator/pbias-regulator.c 	u32 enable_mask;
enable_mask        75 drivers/regulator/pbias-regulator.c 	.enable_mask = BIT(1),
enable_mask        86 drivers/regulator/pbias-regulator.c 	.enable_mask = BIT(9),
enable_mask        96 drivers/regulator/pbias-regulator.c 	.enable_mask = BIT(26) | BIT(25) | BIT(22),
enable_mask       107 drivers/regulator/pbias-regulator.c 	.enable_mask = BIT(27) | BIT(25) | BIT(26),
enable_mask       224 drivers/regulator/pbias-regulator.c 		drvdata[data_idx].desc.enable_mask = info->enable_mask;
enable_mask        36 drivers/regulator/pcf50633-regulator.c 		.enable_mask = PCF50633_REGULATOR_ON,		\
enable_mask       223 drivers/regulator/pfuze100-regulator.c 			.enable_mask = 0x10,	\
enable_mask       241 drivers/regulator/pfuze100-regulator.c 			.enable_mask = 0xf,	\
enable_mask       261 drivers/regulator/pfuze100-regulator.c 			.enable_mask = 0x48,	\
enable_mask       279 drivers/regulator/pfuze100-regulator.c 			.enable_mask = 0x10,	\
enable_mask       298 drivers/regulator/pfuze100-regulator.c 			.enable_mask = 0x8,	\
enable_mask       315 drivers/regulator/pfuze100-regulator.c 		.enable_mask = 0x10,	\
enable_mask       159 drivers/regulator/pv88060-regulator.c 		.enable_mask = PV88060_BUCK_EN, \
enable_mask       184 drivers/regulator/pv88060-regulator.c 		.enable_mask = PV88060_LDO_EN, \
enable_mask       203 drivers/regulator/pv88060-regulator.c 		.enable_mask = PV88060_SW_EN,\
enable_mask       491 drivers/regulator/pv88080-regulator.c 		pv88080_regulator_info[i].desc.enable_mask
enable_mask       533 drivers/regulator/pv88080-regulator.c 	pv88080_regulator_info[PV88080_ID_HVBUCK].desc.enable_mask
enable_mask       175 drivers/regulator/pv88090-regulator.c 		.enable_mask = PV88090_##regl_name##_EN, \
enable_mask       201 drivers/regulator/pv88090-regulator.c 		.enable_mask = PV88090_##regl_name##_EN, \
enable_mask      2023 drivers/regulator/qcom_spmi-regulator.c 		vreg->desc.enable_mask = SPMI_COMMON_ENABLE_MASK;
enable_mask        76 drivers/regulator/rc5t583-regulator.c 		.enable_mask = BIT(_en_bit),			\
enable_mask        85 drivers/regulator/rk808-regulator.c 		.enable_mask	= (_emask),				\
enable_mask       109 drivers/regulator/rk808-regulator.c 		.enable_mask	= (_emask),				\
enable_mask       141 drivers/regulator/rk808-regulator.c 		.enable_mask	= (_emask),				\
enable_mask       451 drivers/regulator/rk808-regulator.c 				  rdev->desc->enable_mask,
enable_mask       452 drivers/regulator/rk808-regulator.c 				  rdev->desc->enable_mask);
enable_mask       462 drivers/regulator/rk808-regulator.c 				  rdev->desc->enable_mask,
enable_mask       473 drivers/regulator/rk808-regulator.c 				  rdev->desc->enable_mask,
enable_mask       484 drivers/regulator/rk808-regulator.c 				  rdev->desc->enable_mask,
enable_mask       485 drivers/regulator/rk808-regulator.c 				  rdev->desc->enable_mask);
enable_mask       588 drivers/regulator/rk808-regulator.c 	val |= (rdev->desc->enable_mask & 0xf0);
enable_mask       589 drivers/regulator/rk808-regulator.c 	val &= rdev->desc->enable_mask;
enable_mask       769 drivers/regulator/rk808-regulator.c 		.enable_mask = BIT(0),
enable_mask       785 drivers/regulator/rk808-regulator.c 		.enable_mask = BIT(1),
enable_mask       797 drivers/regulator/rk808-regulator.c 		.enable_mask = BIT(2),
enable_mask       831 drivers/regulator/rk808-regulator.c 		.enable_mask = BIT(0),
enable_mask       847 drivers/regulator/rk808-regulator.c 		.enable_mask = BIT(1),
enable_mask       859 drivers/regulator/rk808-regulator.c 		.enable_mask = BIT(2),
enable_mask       885 drivers/regulator/rk808-regulator.c 		.enable_mask = BIT(2),
enable_mask       925 drivers/regulator/rk808-regulator.c 		.enable_mask = ENABLE_MASK(RK817_ID_DCDC1),
enable_mask       944 drivers/regulator/rk808-regulator.c 		.enable_mask = ENABLE_MASK(RK817_ID_DCDC2),
enable_mask       963 drivers/regulator/rk808-regulator.c 		.enable_mask = ENABLE_MASK(RK817_ID_DCDC3),
enable_mask       982 drivers/regulator/rk808-regulator.c 		.enable_mask = ENABLE_MASK(RK817_ID_DCDC4),
enable_mask      1002 drivers/regulator/rk808-regulator.c 		.enable_mask = ENABLE_MASK(1),
enable_mask      1067 drivers/regulator/rk808-regulator.c 		.enable_mask = ENABLE_MASK(RK817_ID_DCDC1),
enable_mask      1086 drivers/regulator/rk808-regulator.c 		.enable_mask = ENABLE_MASK(RK817_ID_DCDC2),
enable_mask      1105 drivers/regulator/rk808-regulator.c 		.enable_mask = ENABLE_MASK(RK817_ID_DCDC3),
enable_mask      1124 drivers/regulator/rk808-regulator.c 		.enable_mask = ENABLE_MASK(RK817_ID_DCDC4),
enable_mask      1190 drivers/regulator/rk808-regulator.c 		.enable_mask = BIT(0),
enable_mask      1206 drivers/regulator/rk808-regulator.c 		.enable_mask = BIT(1),
enable_mask      1218 drivers/regulator/rk808-regulator.c 		.enable_mask = BIT(2),
enable_mask      1247 drivers/regulator/rk808-regulator.c 		.enable_mask = BIT(2),
enable_mask        38 drivers/regulator/rn5t618-regulator.c 		.enable_mask	= (emask),				\
enable_mask        46 drivers/regulator/rt5033-regulator.c 		.enable_mask	= RT5033_CTRL_EN_BUCK_MASK,
enable_mask        62 drivers/regulator/rt5033-regulator.c 		.enable_mask	= RT5033_CTRL_EN_LDO_MASK,
enable_mask        77 drivers/regulator/rt5033-regulator.c 		.enable_mask	= RT5033_CTRL_EN_SAFE_LDO_MASK,
enable_mask       244 drivers/regulator/s2mpa01.c 	.enable_mask	= S2MPA01_ENABLE_MASK		\
enable_mask       262 drivers/regulator/s2mpa01.c 	.enable_mask	= S2MPA01_ENABLE_MASK			\
enable_mask       280 drivers/regulator/s2mpa01.c 	.enable_mask	= S2MPA01_ENABLE_MASK			\
enable_mask       298 drivers/regulator/s2mpa01.c 	.enable_mask	= S2MPA01_ENABLE_MASK			\
enable_mask       239 drivers/regulator/s2mps11.c 			val = rdev->desc->enable_mask;
enable_mask       248 drivers/regulator/s2mps11.c 			val = rdev->desc->enable_mask;
enable_mask       254 drivers/regulator/s2mps11.c 			val = rdev->desc->enable_mask;
enable_mask       261 drivers/regulator/s2mps11.c 			rdev->desc->enable_mask, val);
enable_mask       325 drivers/regulator/s2mps11.c 	if (!(val & rdev->desc->enable_mask))
enable_mask       329 drivers/regulator/s2mps11.c 				  rdev->desc->enable_mask, state);
enable_mask       370 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPS11_ENABLE_MASK		\
enable_mask       387 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPS11_ENABLE_MASK			\
enable_mask       404 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPS11_ENABLE_MASK			\
enable_mask       421 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPS11_ENABLE_MASK			\
enable_mask       437 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPS11_ENABLE_MASK			\
enable_mask       510 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPS14_ENABLE_MASK			\
enable_mask       527 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPS14_ENABLE_MASK			\
enable_mask       544 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPS14_ENABLE_MASK			\
enable_mask       561 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPS14_ENABLE_MASK			\
enable_mask       641 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPS14_ENABLE_MASK		\
enable_mask       658 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPS14_ENABLE_MASK			\
enable_mask       732 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPS15_ENABLE_MASK		\
enable_mask       748 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPS15_ENABLE_MASK				\
enable_mask       830 drivers/regulator/s2mps11.c 			rdev->desc->enable_mask, S2MPS14_ENABLE_EXT_CONTROL);
enable_mask       955 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPU02_ENABLE_MASK		\
enable_mask       970 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPU02_ENABLE_MASK		\
enable_mask       985 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPU02_ENABLE_MASK		\
enable_mask      1000 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPU02_ENABLE_MASK		\
enable_mask      1015 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPU02_ENABLE_MASK		\
enable_mask      1032 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPU02_ENABLE_MASK			\
enable_mask      1048 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPU02_ENABLE_MASK			\
enable_mask      1064 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPU02_ENABLE_MASK			\
enable_mask      1080 drivers/regulator/s2mps11.c 	.enable_mask	= S2MPU02_ENABLE_MASK			\
enable_mask       947 drivers/regulator/s5m8767.c 			regulators[id].enable_mask = S5M8767_ENCTRL_MASK;
enable_mask       144 drivers/regulator/sc2731-regulator.c 	.enable_mask		= en_mask,			\
enable_mask        53 drivers/regulator/sky81452-regulator.c 	.enable_mask = SKY81452_LEN,
enable_mask       232 drivers/regulator/slg51000-regulator.c 		.enable_mask = BIT(SLG51000_REGULATOR_##_id),      \
enable_mask        37 drivers/regulator/stm32-booster.c 	.enable_mask = STM32H7_SYSCFG_BOOSTE_MASK,
enable_mask        68 drivers/regulator/stm32-booster.c 	.enable_mask = STM32MP1_SYSCFG_EN_BOOSTER_MASK,
enable_mask        63 drivers/regulator/stm32-pwr.c 	return (val & rdev->desc->enable_mask);
enable_mask        73 drivers/regulator/stm32-pwr.c 	val |= rdev->desc->enable_mask;
enable_mask        92 drivers/regulator/stm32-pwr.c 	val &= ~rdev->desc->enable_mask;
enable_mask       119 drivers/regulator/stm32-pwr.c 		.enable_mask = _en, \
enable_mask       207 drivers/regulator/stpmic1_regulator.c 	.enable_mask = LDO_ENABLE_MASK, \
enable_mask       226 drivers/regulator/stpmic1_regulator.c 	.enable_mask = LDO_ENABLE_MASK, \
enable_mask       247 drivers/regulator/stpmic1_regulator.c 	.enable_mask = LDO_ENABLE_MASK, \
enable_mask       266 drivers/regulator/stpmic1_regulator.c 	.enable_mask = BUCK_ENABLE_MASK, \
enable_mask       286 drivers/regulator/stpmic1_regulator.c 	.enable_mask = BUCK_ENABLE_MASK, \
enable_mask       303 drivers/regulator/stpmic1_regulator.c 	.enable_mask = BOOST_ENABLED, \
enable_mask       320 drivers/regulator/stpmic1_regulator.c 	.enable_mask = USBSW_OTG_SWITCH_ENABLED, \
enable_mask       340 drivers/regulator/stpmic1_regulator.c 	.enable_mask = SWIN_SWOUT_ENABLED, \
enable_mask        49 drivers/regulator/stw481x-vmmc.c 	.enable_mask = STW_CONF1_PDN_VMMC | STW_CONF1_MMC_LS_STATUS,
enable_mask        99 drivers/regulator/sy8824x.c 	rdesc->enable_mask = SY8824C_BUCK_EN;
enable_mask        49 drivers/regulator/tps6105x-regulator.c 	.enable_mask	= TPS6105X_REG0_MODE_MASK,
enable_mask       102 drivers/regulator/tps65023-regulator.c 		.enable_mask	= _em,				\
enable_mask       121 drivers/regulator/tps65023-regulator.c 		.enable_mask	= 1 << (_num),			\
enable_mask        43 drivers/regulator/tps65086-regulator.c 			.enable_mask		= _em,			\
enable_mask        64 drivers/regulator/tps65086-regulator.c 			.enable_mask		= _em,			\
enable_mask        94 drivers/regulator/tps65090-regulator.c 				 rdev->desc->enable_mask,
enable_mask        95 drivers/regulator/tps65090-regulator.c 				 rdev->desc->enable_mask);
enable_mask       151 drivers/regulator/tps65090-regulator.c 					 rdev->desc->enable_mask, 0);
enable_mask       195 drivers/regulator/tps65090-regulator.c 	.enable_mask = _en_bits,			\
enable_mask        44 drivers/regulator/tps65217-regulator.c 		.enable_mask	= _em,			\
enable_mask        82 drivers/regulator/tps65217-regulator.c 				 dev->desc->enable_mask, dev->desc->enable_mask,
enable_mask        96 drivers/regulator/tps65217-regulator.c 				   dev->desc->enable_mask, TPS65217_PROTECT_L1);
enable_mask        49 drivers/regulator/tps65218-regulator.c 		.enable_mask		= _em,			\
enable_mask       109 drivers/regulator/tps65218-regulator.c 				 dev->desc->enable_mask, dev->desc->enable_mask,
enable_mask       123 drivers/regulator/tps65218-regulator.c 				   dev->desc->enable_mask, TPS65218_PROTECT_L1);
enable_mask       121 drivers/regulator/tps6586x-regulator.c 		.enable_mask = 1 << (ebit0),				\
enable_mask       146 drivers/regulator/tps6586x-regulator.c 		.enable_mask = 1 << (ebit0),				\
enable_mask      1201 drivers/regulator/tps65910-regulator.c 		pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED;
enable_mask        43 drivers/regulator/tps65912-regulator.c 		.enable_mask		= BIT(7),			\
enable_mask       144 drivers/regulator/uniphier-regulator.c 	.enable_mask = USB3VBUS_REG_EN | USB3VBUS_REG,
enable_mask       439 drivers/regulator/wm831x-dcdc.c 	dcdc->desc.enable_mask = 1 << id;
enable_mask       597 drivers/regulator/wm831x-dcdc.c 	dcdc->desc.enable_mask = 1 << id;
enable_mask       716 drivers/regulator/wm831x-dcdc.c 	dcdc->desc.enable_mask = 1 << id;
enable_mask       800 drivers/regulator/wm831x-dcdc.c 	dcdc->desc.enable_mask = 1 << dcdc->desc.id;
enable_mask       263 drivers/regulator/wm831x-ldo.c 	ldo->desc.enable_mask = 1 << id;
enable_mask       475 drivers/regulator/wm831x-ldo.c 	ldo->desc.enable_mask = 1 << id;
enable_mask       618 drivers/regulator/wm831x-ldo.c 	ldo->desc.enable_mask = 1 << id;
enable_mask       934 drivers/regulator/wm8350-regulator.c 		.enable_mask = WM8350_DC1_ENA,
enable_mask       944 drivers/regulator/wm8350-regulator.c 		.enable_mask = WM8350_DC2_ENA,
enable_mask       959 drivers/regulator/wm8350-regulator.c 		.enable_mask = WM8350_DC3_ENA,
enable_mask       974 drivers/regulator/wm8350-regulator.c 		.enable_mask = WM8350_DC4_ENA,
enable_mask       984 drivers/regulator/wm8350-regulator.c 		.enable_mask = WM8350_DC5_ENA,
enable_mask       999 drivers/regulator/wm8350-regulator.c 		.enable_mask = WM8350_DC6_ENA,
enable_mask      1014 drivers/regulator/wm8350-regulator.c 		.enable_mask = WM8350_LDO1_ENA,
enable_mask      1029 drivers/regulator/wm8350-regulator.c 		.enable_mask = WM8350_LDO2_ENA,
enable_mask      1044 drivers/regulator/wm8350-regulator.c 		.enable_mask = WM8350_LDO3_ENA,
enable_mask      1059 drivers/regulator/wm8350-regulator.c 		.enable_mask = WM8350_LDO4_ENA,
enable_mask       121 drivers/regulator/wm8400-regulator.c 		.enable_mask = WM8400_LDO1_ENA,
enable_mask       135 drivers/regulator/wm8400-regulator.c 		.enable_mask = WM8400_LDO2_ENA,
enable_mask       149 drivers/regulator/wm8400-regulator.c 		.enable_mask = WM8400_LDO3_ENA,
enable_mask       163 drivers/regulator/wm8400-regulator.c 		.enable_mask = WM8400_LDO4_ENA,
enable_mask       177 drivers/regulator/wm8400-regulator.c 		.enable_mask = WM8400_DC1_ENA_MASK,
enable_mask       191 drivers/regulator/wm8400-regulator.c 		.enable_mask = WM8400_DC2_ENA_MASK,
enable_mask        70 drivers/thermal/broadcom/brcmstb_thermal.c 	u32 enable_mask;
enable_mask        82 drivers/thermal/broadcom/brcmstb_thermal.c 		.enable_mask	= AVS_TMON_EN_TEMP_INT_SRCS_low,
enable_mask        90 drivers/thermal/broadcom/brcmstb_thermal.c 		.enable_mask	= AVS_TMON_EN_TEMP_INT_SRCS_high,
enable_mask        98 drivers/thermal/broadcom/brcmstb_thermal.c 		.enable_mask	= AVS_TMON_EN_OVERTEMP_RESET_msk,
enable_mask       175 drivers/thermal/broadcom/brcmstb_thermal.c 		val |= trip->enable_mask;
enable_mask       177 drivers/thermal/broadcom/brcmstb_thermal.c 		val &= ~trip->enable_mask;
enable_mask       100 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_LOG,
enable_mask       113 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_KEYBOARD,
enable_mask       129 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_KEYBOARD,
enable_mask       146 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_DUMP,
enable_mask       159 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_BOOT,
enable_mask       170 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_SYNC,
enable_mask       192 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_REMOUNT,
enable_mask       258 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_DUMP,
enable_mask       276 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_DUMP,
enable_mask       288 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_DUMP,
enable_mask       299 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_DUMP,
enable_mask       313 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_DUMP,
enable_mask       327 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_DUMP,
enable_mask       358 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_SIGNAL,
enable_mask       388 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_SIGNAL,
enable_mask       400 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_SIGNAL,
enable_mask       413 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_SIGNAL,
enable_mask       424 drivers/tty/sysrq.c 	.enable_mask	= SYSRQ_ENABLE_RTNICE,
enable_mask       553 drivers/tty/sysrq.c 		if (!check_mask || sysrq_on_mask(op_p->enable_mask)) {
enable_mask      1041 drivers/tty/sysrq.c int sysrq_toggle_support(int enable_mask)
enable_mask      1045 drivers/tty/sysrq.c 	sysrq_enabled = enable_mask;
enable_mask        27 drivers/usb/dwc3/drd.c static void dwc3_otg_enable_events(struct dwc3 *dwc, u32 enable_mask)
enable_mask        31 drivers/usb/dwc3/drd.c 	reg |= (enable_mask);
enable_mask        38 drivers/watchdog/st_lpc_wdt.c 	unsigned int enable_mask;
enable_mask        53 drivers/watchdog/st_lpc_wdt.c 	.enable_mask		= BIT(19),
enable_mask        77 drivers/watchdog/st_lpc_wdt.c 			   st_wdog->syscfg->enable_mask,
enable_mask        78 drivers/watchdog/st_lpc_wdt.c 			   enable ? 0 : st_wdog->syscfg->enable_mask);
enable_mask        88 include/linux/clk/ti.h 	u32			enable_mask;
enable_mask       369 include/linux/regulator/driver.h 	unsigned int enable_mask;
enable_mask        36 include/linux/sysrq.h 	int enable_mask;
enable_mask        52 include/linux/sysrq.h int sysrq_toggle_support(int enable_mask);
enable_mask        45 include/sound/sof/pm.h 	uint32_t enable_mask;
enable_mask        36 kernel/power/poweroff.c 	.enable_mask	= SYSRQ_ENABLE_BOOT,
enable_mask       711 kernel/rcu/tree_stall.h 	.enable_mask = SYSRQ_ENABLE_DUMP,
enable_mask      5054 sound/soc/codecs/rt5677.c 	unsigned int enable_mask;
enable_mask      5061 sound/soc/codecs/rt5677.c 		.enable_mask = RT5677_EN_IRQ_GPIO_JD1,
enable_mask      5066 sound/soc/codecs/rt5677.c 		.enable_mask = RT5677_EN_IRQ_GPIO_JD2,
enable_mask      5071 sound/soc/codecs/rt5677.c 		.enable_mask = RT5677_EN_IRQ_GPIO_JD3,
enable_mask      5162 sound/soc/codecs/rt5677.c 	rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask;
enable_mask      5169 sound/soc/codecs/rt5677.c 	rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask;
enable_mask      1393 sound/soc/sof/topology.c 	pm_core_config.enable_mask = sdev->enabled_cores_mask;