eeh_ops           237 arch/powerpc/include/asm/eeh.h extern struct eeh_ops *eeh_ops;
eeh_ops           299 arch/powerpc/include/asm/eeh.h int __init eeh_ops_register(struct eeh_ops *ops);
eeh_ops           109 arch/powerpc/kernel/eeh.c struct eeh_ops *eeh_ops = NULL;
eeh_ops           188 arch/powerpc/kernel/eeh.c 	eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg);
eeh_ops           192 arch/powerpc/kernel/eeh.c 	eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg);
eeh_ops           198 arch/powerpc/kernel/eeh.c 		eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg);
eeh_ops           202 arch/powerpc/kernel/eeh.c 		eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);
eeh_ops           210 arch/powerpc/kernel/eeh.c 		eeh_ops->read_config(pdn, cap, 4, &cfg);
eeh_ops           214 arch/powerpc/kernel/eeh.c 		eeh_ops->read_config(pdn, cap+4, 4, &cfg);
eeh_ops           226 arch/powerpc/kernel/eeh.c 			eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
eeh_ops           253 arch/powerpc/kernel/eeh.c 			eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
eeh_ops           334 arch/powerpc/kernel/eeh.c 		eeh_ops->configure_bridge(pe);
eeh_ops           343 arch/powerpc/kernel/eeh.c 	eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
eeh_ops           412 arch/powerpc/kernel/eeh.c 	ret = eeh_ops->get_state(phb_pe, NULL);
eeh_ops           529 arch/powerpc/kernel/eeh.c 	ret = eeh_ops->get_state(pe, NULL);
eeh_ops           557 arch/powerpc/kernel/eeh.c 		ret = eeh_ops->get_state(parent_pe, NULL);
eeh_ops           664 arch/powerpc/kernel/eeh.c 		rc = eeh_ops->get_state(pe, NULL);
eeh_ops           679 arch/powerpc/kernel/eeh.c 	rc = eeh_ops->set_option(pe, function);
eeh_ops           737 arch/powerpc/kernel/eeh.c 	if (pdn && eeh_ops->restore_config)
eeh_ops           738 arch/powerpc/kernel/eeh.c 		eeh_ops->restore_config(pdn);
eeh_ops           754 arch/powerpc/kernel/eeh.c 		eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
eeh_ops           758 arch/powerpc/kernel/eeh.c 		eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
eeh_ops           762 arch/powerpc/kernel/eeh.c 		eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2,
eeh_ops           765 arch/powerpc/kernel/eeh.c 			eeh_ops->read_config(pdn,
eeh_ops           769 arch/powerpc/kernel/eeh.c 			eeh_ops->write_config(pdn,
eeh_ops           776 arch/powerpc/kernel/eeh.c 	eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd);
eeh_ops           778 arch/powerpc/kernel/eeh.c 	eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd);
eeh_ops           782 arch/powerpc/kernel/eeh.c 		eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
eeh_ops           788 arch/powerpc/kernel/eeh.c 		eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
eeh_ops           794 arch/powerpc/kernel/eeh.c 		eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP,
eeh_ops           797 arch/powerpc/kernel/eeh.c 		eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP,
eeh_ops           825 arch/powerpc/kernel/eeh.c 		eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
eeh_ops           835 arch/powerpc/kernel/eeh.c 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
eeh_ops           839 arch/powerpc/kernel/eeh.c 		eeh_ops->reset(pe, EEH_RESET_HOT);
eeh_ops           844 arch/powerpc/kernel/eeh.c 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
eeh_ops           848 arch/powerpc/kernel/eeh.c 		eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
eeh_ops           885 arch/powerpc/kernel/eeh.c 			state = eeh_ops->get_state(pe, NULL);
eeh_ops           988 arch/powerpc/kernel/eeh.c 		eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]);
eeh_ops          1008 arch/powerpc/kernel/eeh.c int __init eeh_ops_register(struct eeh_ops *ops)
eeh_ops          1016 arch/powerpc/kernel/eeh.c 	if (eeh_ops && eeh_ops != ops) {
eeh_ops          1018 arch/powerpc/kernel/eeh.c 			__func__, eeh_ops->name, ops->name);
eeh_ops          1022 arch/powerpc/kernel/eeh.c 	eeh_ops = ops;
eeh_ops          1042 arch/powerpc/kernel/eeh.c 	if (eeh_ops && !strcmp(eeh_ops->name, name)) {
eeh_ops          1043 arch/powerpc/kernel/eeh.c 		eeh_ops = NULL;
eeh_ops          1090 arch/powerpc/kernel/eeh.c 	if (!eeh_ops) {
eeh_ops          1094 arch/powerpc/kernel/eeh.c 	} else if ((ret = eeh_ops->init()))
eeh_ops          1137 arch/powerpc/kernel/eeh.c 	eeh_ops->probe(pdn, NULL);
eeh_ops          1208 arch/powerpc/kernel/eeh.c 		eeh_ops->probe(pdn, NULL);
eeh_ops          1361 arch/powerpc/kernel/eeh.c 	ret = eeh_ops->get_state(pe, NULL);
eeh_ops          1559 arch/powerpc/kernel/eeh.c 		if (!eeh_ops || !eeh_ops->set_option) {
eeh_ops          1592 arch/powerpc/kernel/eeh.c 	if (!eeh_ops || !eeh_ops->get_state)
eeh_ops          1606 arch/powerpc/kernel/eeh.c 	result = eeh_ops->get_state(pe, NULL);
eeh_ops          1680 arch/powerpc/kernel/eeh.c 	if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)
eeh_ops          1685 arch/powerpc/kernel/eeh.c 		ret = eeh_ops->reset(pe, option);
eeh_ops          1699 arch/powerpc/kernel/eeh.c 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
eeh_ops          1702 arch/powerpc/kernel/eeh.c 		ret = eeh_ops->reset(pe, option);
eeh_ops          1754 arch/powerpc/kernel/eeh.c 	if (!eeh_ops || !eeh_ops->err_inject)
eeh_ops          1765 arch/powerpc/kernel/eeh.c 	return eeh_ops->err_inject(pe, type, func, addr, mask);
eeh_ops           444 arch/powerpc/kernel/eeh_driver.c 	if (eeh_ops->notify_resume && eeh_dev_to_pdn(edev))
eeh_ops           445 arch/powerpc/kernel/eeh_driver.c 		eeh_ops->notify_resume(eeh_dev_to_pdn(edev));
eeh_ops           690 arch/powerpc/kernel/eeh_driver.c 	eeh_ops->configure_bridge(pe);
eeh_ops          1149 arch/powerpc/kernel/eeh_driver.c 		rc = eeh_ops->next_error(&pe);
eeh_ops           123 arch/powerpc/kernel/eeh_pe.c 		ret = eeh_ops->get_state(pe, &mwait);
eeh_ops           717 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val);
eeh_ops           724 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val);
eeh_ops           726 arch/powerpc/kernel/eeh_pe.c 		eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val);
eeh_ops           731 arch/powerpc/kernel/eeh_pe.c 			eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val);
eeh_ops           737 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val);
eeh_ops           739 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val);
eeh_ops           742 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val);
eeh_ops           755 arch/powerpc/kernel/eeh_pe.c 		eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val);
eeh_ops           780 arch/powerpc/kernel/eeh_pe.c 		eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
eeh_ops           782 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->write_config(pdn, 14*4, 4, edev->config_space[14]);
eeh_ops           785 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
eeh_ops           787 arch/powerpc/kernel/eeh_pe.c         eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
eeh_ops           790 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
eeh_ops           793 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1] |
eeh_ops           807 arch/powerpc/kernel/eeh_pe.c 		eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
eeh_ops           809 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->write_config(pdn, 12*4, 4, edev->config_space[12]);
eeh_ops           811 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
eeh_ops           813 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
eeh_ops           817 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
eeh_ops           823 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cmd);
eeh_ops           832 arch/powerpc/kernel/eeh_pe.c 	eeh_ops->write_config(pdn, PCI_COMMAND, 4, cmd);
eeh_ops           854 arch/powerpc/kernel/eeh_pe.c 	if (eeh_ops->restore_config && pdn)
eeh_ops           855 arch/powerpc/kernel/eeh_pe.c 		eeh_ops->restore_config(pdn);
eeh_ops            66 arch/powerpc/kernel/eeh_sysfs.c 	state = eeh_ops->get_state(edev->pe, NULL);
eeh_ops           116 arch/powerpc/kernel/eeh_sysfs.c 	if (!edev || !edev->pe || !eeh_ops->notify_resume)
eeh_ops           119 arch/powerpc/kernel/eeh_sysfs.c 	if (eeh_ops->notify_resume(pci_get_pdn(pdev)))
eeh_ops           130 arch/powerpc/platforms/powernv/eeh-powernv.c 	if (!eeh_ops || !eeh_ops->err_inject)
eeh_ops           150 arch/powerpc/platforms/powernv/eeh-powernv.c 	ret = eeh_ops->err_inject(pe, type, func, addr, mask);
eeh_ops           862 arch/powerpc/platforms/powernv/eeh-powernv.c 			eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
eeh_ops           865 arch/powerpc/platforms/powernv/eeh-powernv.c 			eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
eeh_ops           869 arch/powerpc/platforms/powernv/eeh-powernv.c 		eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
eeh_ops           871 arch/powerpc/platforms/powernv/eeh-powernv.c 		eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
eeh_ops           876 arch/powerpc/platforms/powernv/eeh-powernv.c 		eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
eeh_ops           878 arch/powerpc/platforms/powernv/eeh-powernv.c 		eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
eeh_ops           884 arch/powerpc/platforms/powernv/eeh-powernv.c 			eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
eeh_ops           887 arch/powerpc/platforms/powernv/eeh-powernv.c 			eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
eeh_ops           960 arch/powerpc/platforms/powernv/eeh-powernv.c 		eeh_ops->read_config(pdn, pos, 2, &status);
eeh_ops           981 arch/powerpc/platforms/powernv/eeh-powernv.c 	eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, &reg);
eeh_ops           991 arch/powerpc/platforms/powernv/eeh-powernv.c 		eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
eeh_ops           994 arch/powerpc/platforms/powernv/eeh-powernv.c 		eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
eeh_ops           999 arch/powerpc/platforms/powernv/eeh-powernv.c 		eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
eeh_ops          1002 arch/powerpc/platforms/powernv/eeh-powernv.c 		eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
eeh_ops          1019 arch/powerpc/platforms/powernv/eeh-powernv.c 	eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap);
eeh_ops          1034 arch/powerpc/platforms/powernv/eeh-powernv.c 		eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL,
eeh_ops          1039 arch/powerpc/platforms/powernv/eeh-powernv.c 		eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0);
eeh_ops          1418 arch/powerpc/platforms/powernv/eeh-powernv.c 		ret = eeh_ops->get_state(dev_pe, NULL);
eeh_ops          1614 arch/powerpc/platforms/powernv/eeh-powernv.c 				state = eeh_ops->get_state(parent_pe, NULL);
eeh_ops          1677 arch/powerpc/platforms/powernv/eeh-powernv.c static struct eeh_ops pnv_eeh_ops = {
eeh_ops          3617 arch/powerpc/platforms/powernv/pci-ioda.c 	if (eehpe && eeh_ops && eeh_ops->reset)
eeh_ops          3618 arch/powerpc/platforms/powernv/pci-ioda.c 		eeh_ops->reset(eehpe, EEH_RESET_HOT);
eeh_ops           286 arch/powerpc/platforms/pseries/eeh_pseries.c 	ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE);
eeh_ops           291 arch/powerpc/platforms/pseries/eeh_pseries.c 		edev->pe_config_addr = eeh_ops->get_pe_addr(&pe);
eeh_ops           298 arch/powerpc/platforms/pseries/eeh_pseries.c 		ret = eeh_ops->get_state(&pe, NULL);
eeh_ops           776 arch/powerpc/platforms/pseries/eeh_pseries.c static struct eeh_ops pseries_eeh_ops = {