dwbc              377 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	struct dwbc *dwb;
dwbc              396 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dwbc              422 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dwbc               47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
dwbc               66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
dwbc               68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
dwbc               71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	dwbc->funcs->disable(dwbc);
dwbc               83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c static bool dwb1_disable(struct dwbc *dwbc)
dwbc               85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
dwbc              256 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	struct dwbc base;
dwbc               50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
dwbc               52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc               72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params)
dwbc               74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc               99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
dwbc              101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc              121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwb2_config_dwb_cnv(dwbc, params);
dwbc              124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwb2_set_scaler(dwbc, params);
dwbc              135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c bool dwb2_disable(struct dwbc *dwbc)
dwbc              137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc              158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c static bool dwb2_update(struct dwbc *dwbc, struct dc_dwb_params *params)
dwbc              160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc              185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwb2_config_dwb_cnv(dwbc, params);
dwbc              188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwb2_set_scaler(dwbc, params);
dwbc              198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c bool dwb2_is_enabled(struct dwbc *dwbc)
dwbc              200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc              210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c void dwb2_set_stereo(struct dwbc *dwbc,
dwbc              213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc              226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c void dwb2_set_new_content(struct dwbc *dwbc,
dwbc              229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc              235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c static void dwb2_set_warmup(struct dwbc *dwbc,
dwbc              238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc              250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params)
dwbc              252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc              416 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	struct dwbc base;
dwbc              429 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h bool dwb2_disable(struct dwbc *dwbc);
dwbc              431 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h bool dwb2_is_enabled(struct dwbc *dwbc);
dwbc              433 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h void dwb2_set_stereo(struct dwbc *dwbc,
dwbc              436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h void dwb2_set_new_content(struct dwbc *dwbc,
dwbc              439 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h void dwb2_config_dwb_cnv(struct dwbc *dwbc,
dwbc              442 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);
dwbc             1361 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dwbc *dwb;
dwbc             1367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dwbc             1388 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dwbc *dwb;
dwbc             1392 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb = dc->res_pool->dwbc[dwb_pipe_inst];
dwbc             2084 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
dwbc             1373 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (pool->base.dwbc[i] != NULL) {
dwbc             1374 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
dwbc             1375 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pool->base.dwbc[i] = NULL;
dwbc             3037 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pool->dwbc[i] = &dwbc20->base;
dwbc              901 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		if (pool->base.dwbc[i] != NULL) {
dwbc              902 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
dwbc              903 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			pool->base.dwbc[i] = NULL;
dwbc              182 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dwbc *dwbc[MAX_DWB_PIPES];
dwbc              314 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dwbc *dwbc;
dwbc              129 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 		struct dwbc *dwbc,
dwbc              133 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 		struct dwbc *dwbc,
dwbc              136 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 	bool (*disable)(struct dwbc *dwbc);
dwbc              139 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 		struct dwbc *dwbc,
dwbc              143 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 		struct dwbc *dwbc);
dwbc              146 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 		struct dwbc *dwbc,
dwbc              150 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 		struct dwbc *dwbc,
dwbc              156 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 		struct dwbc *dwbc,
dwbc              162 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 		struct dwbc *dwbc);
dwbc              164 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 		struct dwbc *dwbc,