dw_update_bits    350 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 	dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time);
dw_update_bits    351 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 	dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time);
dw_update_bits    352 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 	dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10),
dw_update_bits    354 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 	dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10),
dw_update_bits    356 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 	dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8),
dw_update_bits    358 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 	dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8),