dw_pcie_wr_own_conf  160 drivers/pci/controller/dwc/pcie-designware-host.c 	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
dw_pcie_wr_own_conf  179 drivers/pci/controller/dwc/pcie-designware-host.c 	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
dw_pcie_wr_own_conf  194 drivers/pci/controller/dwc/pcie-designware-host.c 	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit));
dw_pcie_wr_own_conf  310 drivers/pci/controller/dwc/pcie-designware-host.c 	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
dw_pcie_wr_own_conf  312 drivers/pci/controller/dwc/pcie-designware-host.c 	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
dw_pcie_wr_own_conf  633 drivers/pci/controller/dwc/pcie-designware-host.c 		return dw_pcie_wr_own_conf(pp, where, size, val);
dw_pcie_wr_own_conf  662 drivers/pci/controller/dwc/pcie-designware-host.c 			dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +
dw_pcie_wr_own_conf  665 drivers/pci/controller/dwc/pcie-designware-host.c 			dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
dw_pcie_wr_own_conf  709 drivers/pci/controller/dwc/pcie-designware-host.c 	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
dw_pcie_wr_own_conf  712 drivers/pci/controller/dwc/pcie-designware-host.c 	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
dw_pcie_wr_own_conf  716 drivers/pci/controller/dwc/pcie-designware-host.c 	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);