dsi_phy_write 381 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c dsi_phy_write(phy->base + reg, val | bit_mask); dsi_phy_write 383 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c dsi_phy_write(phy->base + reg, val & (~bit_mask)); dsi_phy_write 32 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + dsi_phy_write 35 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + dsi_phy_write 50 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i), dsi_phy_write 57 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(i), 0); dsi_phy_write 58 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_PIN_SWAP(i), 0x0); dsi_phy_write 59 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(i), dsi_phy_write 67 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG0(i), 0x0); dsi_phy_write 68 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG1(i), 0x0); dsi_phy_write 69 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG2(i), 0x0); dsi_phy_write 70 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG3(i), dsi_phy_write 72 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + dsi_phy_write 74 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + dsi_phy_write 76 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(i), dsi_phy_write 82 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05); dsi_phy_write 83 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04); dsi_phy_write 120 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data); dsi_phy_write 123 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0x00); dsi_phy_write 126 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x00); dsi_phy_write 129 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_GLBL_CTRL, 0x10); dsi_phy_write 132 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_VREG_CTRL, 0x59); dsi_phy_write 135 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CFG0, 0x21); dsi_phy_write 136 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CFG1, 0x84); dsi_phy_write 139 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0, dsi_phy_write 141 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1, dsi_phy_write 143 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2, dsi_phy_write 145 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3, dsi_phy_write 147 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4, dsi_phy_write 149 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5, dsi_phy_write 151 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6, dsi_phy_write 153 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7, dsi_phy_write 155 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8, dsi_phy_write 157 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9, dsi_phy_write 159 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10, dsi_phy_write 161 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11, dsi_phy_write 165 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, 0x7f); dsi_phy_write 172 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data); dsi_phy_write 173 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0, 0x1F); dsi_phy_write 176 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40); dsi_phy_write 27 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx), dsi_phy_write 29 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx), dsi_phy_write 31 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx), dsi_phy_write 33 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx), dsi_phy_write 35 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx), dsi_phy_write 37 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx), dsi_phy_write 39 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx), dsi_phy_write 41 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx), dsi_phy_write 44 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx), dsi_phy_write 46 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx), dsi_phy_write 69 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data); dsi_phy_write 71 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0x1); dsi_phy_write 75 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i), dsi_phy_write 78 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + dsi_phy_write 80 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + dsi_phy_write 84 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG3(i), dsi_phy_write 86 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG2(i), 0x10); dsi_phy_write 87 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i), dsi_phy_write 89 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i), dsi_phy_write 96 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0x00); dsi_phy_write 101 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x80); dsi_phy_write 104 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00); dsi_phy_write 118 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0xff); dsi_phy_write 125 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0); dsi_phy_write 126 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0); dsi_phy_write 14 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, dsi_phy_write 16 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, dsi_phy_write 18 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, dsi_phy_write 21 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, dsi_phy_write 23 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, dsi_phy_write 25 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, dsi_phy_write 27 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, dsi_phy_write 29 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7, dsi_phy_write 31 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8, dsi_phy_write 33 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9, dsi_phy_write 36 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_10, dsi_phy_write 38 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_11, dsi_phy_write 47 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0); dsi_phy_write 52 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d); dsi_phy_write 57 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03); dsi_phy_write 58 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03); dsi_phy_write 59 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00); dsi_phy_write 60 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20); dsi_phy_write 61 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01); dsi_phy_write 62 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00); dsi_phy_write 63 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03); dsi_phy_write 84 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff); dsi_phy_write 91 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i), dsi_phy_write 93 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i), 0x01); dsi_phy_write 94 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i), 0x46); dsi_phy_write 95 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_0(i), 0x02); dsi_phy_write 96 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_1(i), 0xa0); dsi_phy_write 97 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]); dsi_phy_write 100 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_3, 0x80); dsi_phy_write 101 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR0, 0x01); dsi_phy_write 102 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR1, 0x46); dsi_phy_write 103 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_0, 0x00); dsi_phy_write 104 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_1, 0xa0); dsi_phy_write 105 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_2, 0x00); dsi_phy_write 106 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_4, 0x00); dsi_phy_write 110 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_1, 0x00); dsi_phy_write 112 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_1, 0x06); dsi_phy_write 116 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_0, 0x7f); dsi_phy_write 123 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0); dsi_phy_write 14 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0, dsi_phy_write 16 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1, dsi_phy_write 18 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2, dsi_phy_write 21 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3, dsi_phy_write 23 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4, dsi_phy_write 25 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5, dsi_phy_write 27 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6, dsi_phy_write 29 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7, dsi_phy_write 31 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8, dsi_phy_write 33 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_9, dsi_phy_write 36 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_10, dsi_phy_write 38 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_11, dsi_phy_write 47 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0); dsi_phy_write 51 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); dsi_phy_write 52 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1); dsi_phy_write 53 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0); dsi_phy_write 54 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0); dsi_phy_write 55 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x3); dsi_phy_write 56 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9); dsi_phy_write 57 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7); dsi_phy_write 58 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); dsi_phy_write 76 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_0, 0xff); dsi_phy_write 80 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00); dsi_phy_write 84 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_1, 0x00); dsi_phy_write 85 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); dsi_phy_write 87 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_1, 0x6); dsi_phy_write 90 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_0(i), 0); dsi_phy_write 91 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0); dsi_phy_write 92 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0); dsi_phy_write 93 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0); dsi_phy_write 94 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0); dsi_phy_write 95 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0); dsi_phy_write 96 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0); dsi_phy_write 97 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1); dsi_phy_write 98 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97); dsi_phy_write 101 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0); dsi_phy_write 102 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0); dsi_phy_write 103 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1); dsi_phy_write 104 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb); dsi_phy_write 106 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); dsi_phy_write 117 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0); dsi_phy_write 16 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0, dsi_phy_write 18 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1, dsi_phy_write 20 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2, dsi_phy_write 22 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3, 0x0); dsi_phy_write 23 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4, dsi_phy_write 25 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5, dsi_phy_write 27 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6, dsi_phy_write 29 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_7, dsi_phy_write 31 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_8, dsi_phy_write 33 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_9, dsi_phy_write 36 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_10, dsi_phy_write 38 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_11, dsi_phy_write 46 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0, 0x3); dsi_phy_write 47 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1, 1); dsi_phy_write 48 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2, 1); dsi_phy_write 49 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3, 0); dsi_phy_write 50 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4, dsi_phy_write 58 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0, 0x3); dsi_phy_write 59 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1, 0xa); dsi_phy_write 60 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2, 0x4); dsi_phy_write 61 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3, 0x0); dsi_phy_write 62 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4, 0x20); dsi_phy_write 71 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG, dsi_phy_write 74 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2, 0x0); dsi_phy_write 75 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1, 0x5a); dsi_phy_write 76 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3, 0x10); dsi_phy_write 77 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4, 0x1); dsi_phy_write 78 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0, 0x1); dsi_phy_write 80 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER, 0x1); dsi_phy_write 82 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER, 0x0); dsi_phy_write 101 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_0(i), 0x80); dsi_phy_write 102 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_1(i), 0x45); dsi_phy_write 103 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_2(i), 0x00); dsi_phy_write 104 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(i), dsi_phy_write 106 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(i), dsi_phy_write 108 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(i), dsi_phy_write 112 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_0, 0x40); dsi_phy_write 113 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_1, 0x67); dsi_phy_write 114 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_2, 0x0); dsi_phy_write 115 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH, 0x0); dsi_phy_write 116 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0, 0x1); dsi_phy_write 117 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1, 0x88); dsi_phy_write 136 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LDO_CTRL, 0x04); dsi_phy_write 139 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_0, 0xff); dsi_phy_write 140 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_1, 0x00); dsi_phy_write 141 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_2, 0x06); dsi_phy_write 144 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_0, 0x5f); dsi_phy_write 145 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_1, 0x00); dsi_phy_write 146 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_2, 0x00); dsi_phy_write 147 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_3, 0x10); dsi_phy_write 155 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4, 0x0f); dsi_phy_write 156 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_1, 0x03); dsi_phy_write 157 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_0, 0x03); dsi_phy_write 158 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4, 0x0); dsi_phy_write 167 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(phy->base + REG_DSI_28nm_8960_PHY_CTRL_0, 0x0);