dsc_enc_caps       41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
dsc_enc_caps      107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)
dsc_enc_caps      109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */
dsc_enc_caps      111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;
dsc_enc_caps      112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;
dsc_enc_caps      113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;
dsc_enc_caps      114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;
dsc_enc_caps      116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->lb_bit_depth = 13;
dsc_enc_caps      117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->is_block_pred_supported = true;
dsc_enc_caps      119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->color_formats.bits.RGB = 1;
dsc_enc_caps      120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
dsc_enc_caps      121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 0;
dsc_enc_caps      122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
dsc_enc_caps      123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
dsc_enc_caps      125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
dsc_enc_caps      126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;
dsc_enc_caps      127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;
dsc_enc_caps      134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz;
dsc_enc_caps      140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0;
dsc_enc_caps      141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;
dsc_enc_caps      142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2;
dsc_enc_caps      146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */
dsc_enc_caps      147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
dsc_enc_caps      182 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	struct dsc_enc_caps *dsc_enc_caps,
dsc_enc_caps      188 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	memset(dsc_enc_caps, 0, sizeof(struct dsc_enc_caps));
dsc_enc_caps      190 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);
dsc_enc_caps      198 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	const struct dsc_enc_caps *dsc_enc_caps,
dsc_enc_caps      200 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	struct dsc_enc_caps *dsc_common_caps)
dsc_enc_caps      205 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	memset(dsc_common_caps, 0, sizeof(struct dsc_enc_caps));
dsc_enc_caps      207 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->dsc_version = min(dsc_sink_caps->dsc_version, dsc_enc_caps->dsc_version);
dsc_enc_caps      211 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->slice_caps.bits.NUM_SLICES_1 = dsc_sink_caps->slice_caps1.bits.NUM_SLICES_1 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_1;
dsc_enc_caps      212 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->slice_caps.bits.NUM_SLICES_2 = dsc_sink_caps->slice_caps1.bits.NUM_SLICES_2 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_2;
dsc_enc_caps      213 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->slice_caps.bits.NUM_SLICES_4 = dsc_sink_caps->slice_caps1.bits.NUM_SLICES_4 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;
dsc_enc_caps      214 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->slice_caps.bits.NUM_SLICES_8 = dsc_sink_caps->slice_caps1.bits.NUM_SLICES_8 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_8;
dsc_enc_caps      218 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->lb_bit_depth = min(dsc_sink_caps->lb_bit_depth, dsc_enc_caps->lb_bit_depth);
dsc_enc_caps      222 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->is_block_pred_supported = dsc_sink_caps->is_block_pred_supported && dsc_enc_caps->is_block_pred_supported;
dsc_enc_caps      224 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->color_formats.raw = dsc_sink_caps->color_formats.raw & dsc_enc_caps->color_formats.raw;
dsc_enc_caps      228 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->color_depth.raw = dsc_sink_caps->color_depth.raw & dsc_enc_caps->color_depth.raw;
dsc_enc_caps      246 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->max_total_throughput_mps = min(total_sink_throughput, dsc_enc_caps->max_total_throughput_mps);
dsc_enc_caps      248 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->max_slice_width = min(dsc_sink_caps->max_slice_width, dsc_enc_caps->max_slice_width);
dsc_enc_caps      252 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->bpp_increment_div = min(dsc_sink_caps->bpp_increment_div, dsc_enc_caps->bpp_increment_div);
dsc_enc_caps      288 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		const struct dsc_enc_caps *dsc_caps,
dsc_enc_caps      324 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		const struct dsc_enc_caps *dsc_common_caps,
dsc_enc_caps      512 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		const struct dsc_enc_caps *dsc_enc_caps,
dsc_enc_caps      517 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	struct dsc_enc_caps dsc_common_caps;
dsc_enc_caps      542 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, dsc_enc_caps, timing->pixel_encoding, &dsc_common_caps);
dsc_enc_caps      813 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	struct dsc_enc_caps dsc_enc_caps;
dsc_enc_caps      814 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	struct dsc_enc_caps dsc_common_caps;
dsc_enc_caps      817 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	get_dsc_enc_caps(dc, &dsc_enc_caps, timing->pix_clk_100hz);
dsc_enc_caps      819 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, &dsc_enc_caps,
dsc_enc_caps      824 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 				&dsc_enc_caps,
dsc_enc_caps      842 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	struct dsc_enc_caps dsc_enc_caps;
dsc_enc_caps      844 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	get_dsc_enc_caps(dc, &dsc_enc_caps, timing->pix_clk_100hz);
dsc_enc_caps      846 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 			&dsc_enc_caps,
dsc_enc_caps       91 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h 	void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);