drm_mode_set_crtcinfo 632 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 174 drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 292 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c drm_mode_set_crtcinfo(adjusted_mode, 0); drm_mode_set_crtcinfo 2059 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 3622 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_mode_set_crtcinfo(&mode, 0); drm_mode_set_crtcinfo 405 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c drm_mode_set_crtcinfo(adjusted_mode, 0); drm_mode_set_crtcinfo 210 drivers/gpu/drm/armada/armada_crtc.c drm_mode_set_crtcinfo(adj, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 822 drivers/gpu/drm/drm_modes.c drm_mode_set_crtcinfo(&adjusted, CRTC_STEREO_DOUBLE_ONLY); drm_mode_set_crtcinfo 905 drivers/gpu/drm/drm_modes.c EXPORT_SYMBOL(drm_mode_set_crtcinfo); drm_mode_set_crtcinfo 1915 drivers/gpu/drm/drm_modes.c drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 2051 drivers/gpu/drm/drm_modes.c drm_mode_set_crtcinfo(out, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 541 drivers/gpu/drm/drm_probe_helper.c drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 987 drivers/gpu/drm/exynos/exynos_hdmi.c drm_mode_set_crtcinfo(adjusted_mode, 0); drm_mode_set_crtcinfo 960 drivers/gpu/drm/gma500/cdv_intel_display.c drm_mode_set_crtcinfo(mode, 0); drm_mode_set_crtcinfo 891 drivers/gpu/drm/gma500/cdv_intel_dp.c drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 295 drivers/gpu/drm/gma500/cdv_intel_lvds.c drm_mode_set_crtcinfo(adjusted_mode, drm_mode_set_crtcinfo 707 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 89 drivers/gpu/drm/gma500/mdfld_tmd_vid.c drm_mode_set_crtcinfo(mode, 0); drm_mode_set_crtcinfo 49 drivers/gpu/drm/gma500/mdfld_tpo_vid.c drm_mode_set_crtcinfo(mode, 0); drm_mode_set_crtcinfo 276 drivers/gpu/drm/gma500/oaktrail_lvds.c drm_mode_set_crtcinfo(mode_dev->panel_fixed_mode, 0); drm_mode_set_crtcinfo 415 drivers/gpu/drm/gma500/psb_intel_display.c drm_mode_set_crtcinfo(mode, 0); drm_mode_set_crtcinfo 411 drivers/gpu/drm/gma500/psb_intel_lvds.c drm_mode_set_crtcinfo(adjusted_mode, drm_mode_set_crtcinfo 952 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_mode_set_crtcinfo(adjusted_mode, 0); drm_mode_set_crtcinfo 1617 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_mode_set_crtcinfo(psb_intel_sdvo->sdvo_lvds_fixed_mode, drm_mode_set_crtcinfo 612 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c drm_mode_set_crtcinfo(mode, 0); drm_mode_set_crtcinfo 12353 drivers/gpu/drm/i915/display/intel_display.c drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, drm_mode_set_crtcinfo 51 drivers/gpu/drm/i915/display/intel_panel.c drm_mode_set_crtcinfo(adjusted_mode, 0); drm_mode_set_crtcinfo 920 drivers/gpu/drm/i915/display/intel_sdvo.c drm_mode_set_crtcinfo(&mode, 0); drm_mode_set_crtcinfo 1210 drivers/gpu/drm/i915/display/intel_tv.c drm_mode_set_crtcinfo(adjusted_mode, 0); drm_mode_set_crtcinfo 1326 drivers/gpu/drm/i915/display/intel_tv.c drm_mode_set_crtcinfo(adjusted_mode, 0); drm_mode_set_crtcinfo 250 drivers/gpu/drm/nouveau/dispnv50/head.c drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE); drm_mode_set_crtcinfo 594 drivers/gpu/drm/omapdrm/dss/venc.c drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 313 drivers/gpu/drm/radeon/atombios_encoders.c drm_mode_set_crtcinfo(adjusted_mode, 0); drm_mode_set_crtcinfo 1691 drivers/gpu/drm/radeon/radeon_atombios.c drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 1282 drivers/gpu/drm/radeon/radeon_combios.c drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 794 drivers/gpu/drm/radeon/radeon_connectors.c drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 525 drivers/gpu/drm/radeon/radeon_dp_mst.c drm_mode_set_crtcinfo(adjusted_mode, 0); drm_mode_set_crtcinfo 352 drivers/gpu/drm/radeon/radeon_encoders.c drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); drm_mode_set_crtcinfo 261 drivers/gpu/drm/radeon/radeon_legacy_encoders.c drm_mode_set_crtcinfo(adjusted_mode, 0); drm_mode_set_crtcinfo 508 include/drm/drm_modes.h void drm_mode_set_crtcinfo(struct drm_display_mode *p,