drm_dp_dpcd_write 501 drivers/gpu/drm/amd/amdgpu/atombios_dp.c drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, drm_dp_dpcd_write 1556 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c wret = drm_dp_dpcd_write( drm_dp_dpcd_write 501 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, drm_dp_dpcd_write 277 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2); drm_dp_dpcd_write 318 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, drm_dp_dpcd_write 529 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, drm_dp_dpcd_write 603 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, drm_dp_dpcd_write 985 drivers/gpu/drm/bridge/tc358767.c ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2); drm_dp_dpcd_write 992 drivers/gpu/drm/bridge/tc358767.c ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2); drm_dp_dpcd_write 222 drivers/gpu/drm/drm_dp_aux_dev.c res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo); drm_dp_dpcd_write 110 drivers/gpu/drm/drm_dp_cec.c err = drm_dp_dpcd_write(aux, DP_CEC_LOGICAL_ADDRESS_MASK, mask, 2); drm_dp_dpcd_write 121 drivers/gpu/drm/drm_dp_cec.c err = drm_dp_dpcd_write(aux, DP_CEC_TX_MESSAGE_BUFFER, drm_dp_dpcd_write 321 drivers/gpu/drm/drm_dp_helper.c EXPORT_SYMBOL(drm_dp_dpcd_write); drm_dp_dpcd_write 459 drivers/gpu/drm/drm_dp_helper.c err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); drm_dp_dpcd_write 1553 drivers/gpu/drm/drm_dp_mst_topology.c ret = drm_dp_dpcd_write( drm_dp_dpcd_write 1938 drivers/gpu/drm/drm_dp_mst_topology.c ret = drm_dp_dpcd_write(mgr->aux, regbase + offset, drm_dp_dpcd_write 3473 drivers/gpu/drm/drm_dp_mst_topology.c ret = drm_dp_dpcd_write(mgr->aux, DP_PAYLOAD_ALLOCATE_SET, payload_alloc, 3); drm_dp_dpcd_write 4732 drivers/gpu/drm/i915/display/intel_dp.c wret = drm_dp_dpcd_write(&intel_dp->aux, drm_dp_dpcd_write 5617 drivers/gpu/drm/i915/display/intel_dp.c dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, drm_dp_dpcd_write 6004 drivers/gpu/drm/i915/display/intel_dp.c ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, drm_dp_dpcd_write 95 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, drm_dp_dpcd_write 89 drivers/gpu/drm/i915/display/intel_dp_link_training.c ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, drm_dp_dpcd_write 111 drivers/gpu/drm/i915/display/intel_dp_link_training.c ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, drm_dp_dpcd_write 155 drivers/gpu/drm/i915/display/intel_dp_link_training.c drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); drm_dp_dpcd_write 159 drivers/gpu/drm/i915/display/intel_dp_link_training.c drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, drm_dp_dpcd_write 164 drivers/gpu/drm/i915/display/intel_dp_link_training.c drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); drm_dp_dpcd_write 312 drivers/gpu/drm/i915/display/intel_lspcon.c ret = drm_dp_dpcd_write(aux, reg, data, 8); drm_dp_dpcd_write 327 drivers/gpu/drm/i915/display/intel_lspcon.c ret = drm_dp_dpcd_write(aux, reg, &avi_if_ctrl, 1); drm_dp_dpcd_write 386 drivers/gpu/drm/i915/display/intel_lspcon.c ret = drm_dp_dpcd_write(aux, reg, (void *)data, 1); drm_dp_dpcd_write 412 drivers/gpu/drm/i915/display/intel_lspcon.c ret = drm_dp_dpcd_write(aux, reg, &val, 1); drm_dp_dpcd_write 485 drivers/gpu/drm/msm/edp/edp_ctrl.c if (drm_dp_dpcd_write(ctrl->drm_aux, 0x103, buf, 4) < 4) { drm_dp_dpcd_write 498 drivers/gpu/drm/msm/edp/edp_ctrl.c if (drm_dp_dpcd_write(ctrl->drm_aux, drm_dp_dpcd_write 1223 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3); drm_dp_dpcd_write 563 drivers/gpu/drm/radeon/atombios_dp.c drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, drm_dp_dpcd_write 720 drivers/gpu/drm/radeon/radeon_dp_mst.c wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux, drm_dp_dpcd_write 801 drivers/gpu/drm/tegra/dpaux.c err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values, drm_dp_dpcd_write 1320 include/drm/drm_dp_helper.h ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, drm_dp_dpcd_write 1350 include/drm/drm_dp_helper.h return drm_dp_dpcd_write(aux, offset, &value, 1);