drm_dp_dpcd_readb  376 drivers/gpu/drm/amd/amdgpu/atombios_dp.c 		if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
drm_dp_dpcd_readb  388 drivers/gpu/drm/amd/amdgpu/atombios_dp.c 		if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
drm_dp_dpcd_readb  735 drivers/gpu/drm/amd/amdgpu/atombios_dp.c 	if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
drm_dp_dpcd_readb  756 drivers/gpu/drm/bridge/analogix-anx78xx.c 	err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);
drm_dp_dpcd_readb  925 drivers/gpu/drm/bridge/analogix-anx78xx.c 	err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);
drm_dp_dpcd_readb  110 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
drm_dp_dpcd_readb  126 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
drm_dp_dpcd_readb  173 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
drm_dp_dpcd_readb  194 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
drm_dp_dpcd_readb  561 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
drm_dp_dpcd_readb  622 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
drm_dp_dpcd_readb  635 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
drm_dp_dpcd_readb  752 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 		ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
drm_dp_dpcd_readb  867 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 		ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
drm_dp_dpcd_readb  876 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 		ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
drm_dp_dpcd_readb  927 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
drm_dp_dpcd_readb  996 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
drm_dp_dpcd_readb 1032 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
drm_dp_dpcd_readb 1031 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c 	val = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &status);
drm_dp_dpcd_readb  682 drivers/gpu/drm/bridge/tc358767.c 	ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, &reg);
drm_dp_dpcd_readb  687 drivers/gpu/drm/bridge/tc358767.c 	ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, &reg);
drm_dp_dpcd_readb  693 drivers/gpu/drm/bridge/tc358767.c 	ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, &reg);
drm_dp_dpcd_readb  964 drivers/gpu/drm/bridge/tc358767.c 		ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
drm_dp_dpcd_readb  142 drivers/gpu/drm/drm_dp_cec.c 	err = drm_dp_dpcd_readb(aux, DP_CEC_TUNNELING_CONTROL, &val);
drm_dp_dpcd_readb  192 drivers/gpu/drm/drm_dp_cec.c 	err = drm_dp_dpcd_readb(aux, DP_CEC_RX_MESSAGE_INFO, &rx_msg_info);
drm_dp_dpcd_readb  213 drivers/gpu/drm/drm_dp_cec.c 	if (drm_dp_dpcd_readb(aux, DP_CEC_TUNNELING_IRQ_FLAGS, &flags) < 0)
drm_dp_dpcd_readb  251 drivers/gpu/drm/drm_dp_cec.c 	ret = drm_dp_dpcd_readb(aux, DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1,
drm_dp_dpcd_readb  267 drivers/gpu/drm/drm_dp_cec.c 	if (drm_dp_dpcd_readb(aux, DP_CEC_TUNNELING_CAPABILITY, &cap) != 1 ||
drm_dp_dpcd_readb  388 drivers/gpu/drm/drm_dp_helper.c 	err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
drm_dp_dpcd_readb  426 drivers/gpu/drm/drm_dp_helper.c 	err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
drm_dp_dpcd_readb 1017 drivers/gpu/drm/drm_dp_helper.c 	ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
drm_dp_dpcd_readb 1023 drivers/gpu/drm/drm_dp_helper.c 	ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
drm_dp_dpcd_readb 1199 drivers/gpu/drm/drm_dp_helper.c 	ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
drm_dp_dpcd_readb 1226 drivers/gpu/drm/drm_dp_helper.c 	ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
drm_dp_dpcd_readb 3480 drivers/gpu/drm/drm_dp_mst_topology.c 	ret = drm_dp_dpcd_readb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status);
drm_dp_dpcd_readb 3515 drivers/gpu/drm/drm_dp_mst_topology.c 		ret = drm_dp_dpcd_readb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status);
drm_dp_dpcd_readb 4187 drivers/gpu/drm/i915/display/intel_dp.c 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
drm_dp_dpcd_readb 4219 drivers/gpu/drm/i915/display/intel_dp.c 		    drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
drm_dp_dpcd_readb 4334 drivers/gpu/drm/i915/display/intel_dp.c 		r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
drm_dp_dpcd_readb 4378 drivers/gpu/drm/i915/display/intel_dp.c 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
drm_dp_dpcd_readb 4520 drivers/gpu/drm/i915/display/intel_dp.c 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
drm_dp_dpcd_readb 4529 drivers/gpu/drm/i915/display/intel_dp.c 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
drm_dp_dpcd_readb 4556 drivers/gpu/drm/i915/display/intel_dp.c 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
drm_dp_dpcd_readb 4579 drivers/gpu/drm/i915/display/intel_dp.c 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
drm_dp_dpcd_readb 4665 drivers/gpu/drm/i915/display/intel_dp.c 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
drm_dp_dpcd_readb 4915 drivers/gpu/drm/i915/display/intel_dp.c 	if (drm_dp_dpcd_readb(&intel_dp->aux,
drm_dp_dpcd_readb   36 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
drm_dp_dpcd_readb  137 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 	if (drm_dp_dpcd_readb(&intel_dp->aux,
drm_dp_dpcd_readb  142 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 	if (drm_dp_dpcd_readb(&intel_dp->aux,
drm_dp_dpcd_readb  184 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 	if (drm_dp_dpcd_readb(&intel_dp->aux,
drm_dp_dpcd_readb  175 drivers/gpu/drm/i915/display/intel_lspcon.c 	if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV,
drm_dp_dpcd_readb  237 drivers/gpu/drm/i915/display/intel_psr.c 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
drm_dp_dpcd_readb  247 drivers/gpu/drm/i915/display/intel_psr.c 	if (drm_dp_dpcd_readb(&intel_dp->aux,
drm_dp_dpcd_readb 1270 drivers/gpu/drm/i915/display/intel_psr.c 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) {
drm_dp_dpcd_readb 1281 drivers/gpu/drm/i915/display/intel_psr.c 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
drm_dp_dpcd_readb 2099 drivers/gpu/drm/i915/i915_debugfs.c 	ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
drm_dp_dpcd_readb 1292 drivers/gpu/drm/nouveau/dispnv50/disp.c 		ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
drm_dp_dpcd_readb 1298 drivers/gpu/drm/nouveau/dispnv50/disp.c 		ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
drm_dp_dpcd_readb 1379 drivers/gpu/drm/nouveau/dispnv50/disp.c 	ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
drm_dp_dpcd_readb  430 drivers/gpu/drm/radeon/atombios_dp.c 		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
drm_dp_dpcd_readb  442 drivers/gpu/drm/radeon/atombios_dp.c 		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
drm_dp_dpcd_readb  834 drivers/gpu/drm/radeon/atombios_dp.c 	if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)