dpu_hw_ctl 124 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c struct dpu_hw_ctl *ctl = mixer->lm_ctl; dpu_hw_ctl 193 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c struct dpu_hw_ctl *ctl; dpu_hw_ctl 81 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h struct dpu_hw_ctl *lm_ctl; dpu_hw_ctl 210 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS]; dpu_hw_ctl 957 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL }; dpu_hw_ctl 1015 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c hw_ctl[i] = (struct dpu_hw_ctl *)hw_iter.hw; dpu_hw_ctl 1428 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_hw_ctl *ctl; dpu_hw_ctl 1480 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_hw_ctl *ctl; dpu_hw_ctl 1522 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_hw_ctl *ctl; dpu_hw_ctl 1556 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_hw_ctl *ctl; dpu_hw_ctl 1609 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_hw_ctl *ctl; dpu_hw_ctl 221 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h struct dpu_hw_ctl *hw_ctl; dpu_hw_ctl 58 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_hw_ctl *ctl; dpu_hw_ctl 470 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_hw_ctl *ctl; dpu_hw_ctl 291 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_hw_ctl *hw_ctl; dpu_hw_ctl 436 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_hw_ctl *ctl; dpu_hw_ctl 523 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; dpu_hw_ctl 543 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_hw_ctl *ctl; dpu_hw_ctl 67 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx) dpu_hw_ctl 74 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx) dpu_hw_ctl 81 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx) dpu_hw_ctl 88 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx) dpu_hw_ctl 95 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx, dpu_hw_ctl 103 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) dpu_hw_ctl 108 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx) dpu_hw_ctl 115 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl *ctx, dpu_hw_ctl 170 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static uint32_t dpu_hw_ctl_get_bitmask_mixer(struct dpu_hw_ctl *ctx, dpu_hw_ctl 203 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static int dpu_hw_ctl_get_bitmask_intf(struct dpu_hw_ctl *ctx, dpu_hw_ctl 225 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us) dpu_hw_ctl 247 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static int dpu_hw_ctl_reset_control(struct dpu_hw_ctl *ctx) dpu_hw_ctl 259 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static int dpu_hw_ctl_wait_reset_status(struct dpu_hw_ctl *ctx) dpu_hw_ctl 278 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static void dpu_hw_ctl_clear_all_blendstages(struct dpu_hw_ctl *ctx) dpu_hw_ctl 291 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx, dpu_hw_ctl 425 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, dpu_hw_ctl 477 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, dpu_hw_ctl 481 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c struct dpu_hw_ctl *c; dpu_hw_ctl 506 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx) dpu_hw_ctl 24 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h struct dpu_hw_ctl; dpu_hw_ctl 60 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h void (*trigger_start)(struct dpu_hw_ctl *ctx); dpu_hw_ctl 68 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h void (*trigger_pending)(struct dpu_hw_ctl *ctx); dpu_hw_ctl 75 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h void (*clear_pending_flush)(struct dpu_hw_ctl *ctx); dpu_hw_ctl 82 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx); dpu_hw_ctl 90 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h void (*update_pending_flush)(struct dpu_hw_ctl *ctx, dpu_hw_ctl 97 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h void (*trigger_flush)(struct dpu_hw_ctl *ctx); dpu_hw_ctl 104 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h u32 (*get_flush_register)(struct dpu_hw_ctl *ctx); dpu_hw_ctl 111 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx, dpu_hw_ctl 114 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h int (*reset)(struct dpu_hw_ctl *c); dpu_hw_ctl 125 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h int (*wait_reset_status)(struct dpu_hw_ctl *ctx); dpu_hw_ctl 127 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h uint32_t (*get_bitmask_sspp)(struct dpu_hw_ctl *ctx, dpu_hw_ctl 130 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx, dpu_hw_ctl 133 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h int (*get_bitmask_intf)(struct dpu_hw_ctl *ctx, dpu_hw_ctl 141 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx); dpu_hw_ctl 149 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h void (*setup_blendstage)(struct dpu_hw_ctl *ctx, dpu_hw_ctl 184 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw) dpu_hw_ctl 186 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h return container_of(hw, struct dpu_hw_ctl, base); dpu_hw_ctl 196 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, dpu_hw_ctl 204 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx); dpu_hw_ctl 756 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl, dpu_hw_ctl 78 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl, dpu_hw_ctl 448 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter.blk->hw);