dpu_encoder_helper_register_irq  376 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
dpu_encoder_helper_register_irq  300 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_RDPTR);
dpu_encoder_helper_register_irq  331 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_PINGPONG);
dpu_encoder_helper_register_irq  332 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
dpu_encoder_helper_register_irq  336 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 			dpu_encoder_helper_register_irq(phys_enc,
dpu_encoder_helper_register_irq  419 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 		ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC);
dpu_encoder_helper_register_irq  658 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 		dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);