dpp 67 arch/ia64/kernel/unwind_decoder.c unw_decode_uleb128 (unsigned char **dpp) dpp 71 arch/ia64/kernel/unwind_decoder.c unsigned char *bp = *dpp; dpp 81 arch/ia64/kernel/unwind_decoder.c *dpp = bp; dpp 250 arch/sparc/vdso/vma.c struct page *dp, **dpp = NULL; dpp 290 arch/sparc/vdso/vma.c dpp = kcalloc(dnpages, sizeof(struct page *), GFP_KERNEL); dpp 291 arch/sparc/vdso/vma.c vvar_mapping.pages = dpp; dpp 293 arch/sparc/vdso/vma.c if (!dpp) dpp 300 arch/sparc/vdso/vma.c dpp[0] = dp; dpp 318 arch/sparc/vdso/vma.c if (dpp != NULL) { dpp 320 arch/sparc/vdso/vma.c if (dpp[i] != NULL) dpp 321 arch/sparc/vdso/vma.c __free_page(dpp[i]); dpp 323 arch/sparc/vdso/vma.c kfree(dpp); dpp 313 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { dpp 328 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> dpp 527 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; dpp 107 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( dpp 108 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pipe_ctx->plane_res.dpp, dpp 113 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; dpp 287 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; dpp 304 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; dpp 1001 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.dpp != NULL) dpp 1002 drivers/gpu/drm/amd/display/dc/core/dc_resource.c res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( dpp 1003 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); dpp 1023 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.dpp != NULL) dpp 1024 drivers/gpu/drm/amd/display/dc/core/dc_resource.c res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( dpp 1025 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.dpp, dpp 1217 drivers/gpu/drm/amd/display/dc/core/dc_resource.c split_pipe->plane_res.dpp = pool->dpps[i]; dpp 1621 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.dpp = pool->dpps[i]; dpp 1891 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.dpp = pool->dpps[tg_inst]; dpp 350 drivers/gpu/drm/amd/display/dc/core/dc_stream.c (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || dpp 351 drivers/gpu/drm/amd/display/dc/core/dc_stream.c (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) dpp 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->tf_regs->reg dpp 45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->base.ctx dpp 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->tf_shift->field_name, dpp->tf_mask->field_name dpp 94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c void dpp_read_state(struct dpp *dpp_base, dpp 97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp) dpp 133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp, dpp 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && dpp 152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->ctx->dc->debug.max_downscale_src_width != 0 && dpp 153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) dpp 189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (!dpp->ctx->dc->debug.always_scale) { dpp 203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c void dpp_reset(struct dpp *dpp_base) dpp 205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->filter_h_c = NULL; dpp 208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->filter_v_c = NULL; dpp 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->filter_h = NULL; dpp 210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->filter_v = NULL; dpp 212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c memset(&dpp->scl_data, 0, sizeof(dpp->scl_data)); dpp 213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data)); dpp 219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) dpp 221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3; dpp 236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0) dpp 240 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); dpp 242 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (dpp->is_write_to_ram_a_safe) dpp 249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->pwl_data = *params; dpp 251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4; dpp 252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe; dpp 274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, dpp 277 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, dpp 306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 428 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, dpp 432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 449 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, dpp 455 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 491 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, dpp 494 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 503 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, dpp 507 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 510 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (dpp->tf_mask->DPPCLK_RATE_CONTROL) dpp 562 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp, dpp 569 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->base.ctx = ctx; dpp 571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->base.inst = inst; dpp 572 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->base.funcs = &dcn10_dpp_funcs; dpp 573 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->base.caps = &dcn10_dpp_cap; dpp 575 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->tf_regs = tf_regs; dpp 576 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->tf_shift = tf_shift; dpp 577 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->tf_mask = tf_mask; dpp 579 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->lb_pixel_depth_supported = dpp 584 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; dpp 585 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ dpp 30 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h #define TO_DCN10_DPP(dpp)\ dpp 31 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h container_of(dpp, struct dcn10_dpp, base) dpp 1345 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp base; dpp 1370 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1374 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1400 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1404 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1408 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1414 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1428 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1431 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h void dpp1_full_bypass(struct dpp *dpp_base); dpp 1434 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1437 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h void dpp1_set_degamma_pwl(struct dpp *dpp_base, dpp 1441 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h void dpp_read_state(struct dpp *dpp_base, dpp 1444 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h void dpp_reset(struct dpp *dpp_base); dpp 1447 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1452 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1456 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1461 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1466 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1469 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1473 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1477 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp, dpp 1481 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1485 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1496 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h void dpp1_full_bypass(struct dpp *dpp_base); dpp 1499 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 1504 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->tf_regs->reg dpp 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->base.ctx dpp 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->tf_shift->field_name, dpp->tf_mask->field_name dpp 112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp, dpp 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; dpp 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; dpp 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; dpp 141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; dpp 149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->base.ctx, dpp 159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->base.ctx, dpp 169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->base.ctx, dpp 181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 184 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS); dpp 200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c program_gamut_remap(dpp, arr_reg_val, GAMUT_REMAP_COEFF); dpp 205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp, dpp 233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11; dpp 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; dpp 235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12; dpp 236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; dpp 251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->base.ctx, dpp 260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_cm_program_color_matrix(dpp, regval); dpp 277 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp, dpp 280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; dpp 281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; dpp 282 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; dpp 283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; dpp 284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; dpp 285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; dpp 286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; dpp 287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; dpp 289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; dpp 290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; dpp 291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; dpp 292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; dpp 293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; dpp 294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; dpp 295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; dpp 296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; dpp 297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B; dpp 298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B; dpp 299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; dpp 300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; dpp 304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp, dpp 307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; dpp 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; dpp 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; dpp 310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; dpp 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; dpp 312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; dpp 313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; dpp 314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; dpp 316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B; dpp 317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B; dpp 318 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; dpp 319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; dpp 320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end_base = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_BASE_B; dpp 321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end_base = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_BASE_B; dpp 322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; dpp 323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_linear_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; dpp 324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B; dpp 325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region_start = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_B; dpp 326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; dpp 327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; dpp 330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 333 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_cm_program_color_matrix(dpp, regval); dpp 338 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, dpp 341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c void dpp1_cm_program_regamma_lut(struct dpp *dpp_base, dpp 353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 369 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 383 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 386 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_cm_get_reg_field(dpp, &gam_regs); dpp 406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); dpp 412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_cm_get_reg_field(dpp, &gam_regs); dpp 435 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); dpp 439 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 444 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 487 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; dpp 488 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; dpp 489 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; dpp 490 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; dpp 505 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->base.ctx, dpp 515 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 518 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 536 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 539 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 542 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_cm_get_degamma_reg_field(dpp, &gam_regs); dpp 560 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); dpp 565 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 568 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_cm_get_degamma_reg_field(dpp, &gam_regs); dpp 588 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); dpp 592 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 595 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 603 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base) dpp 605 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 612 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 615 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 636 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 639 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 649 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 654 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 670 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 677 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 699 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c void dpp1_set_degamma_pwl(struct dpp *dpp_base, dpp 717 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c void dpp1_full_bypass(struct dpp *dpp_base) dpp 719 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 732 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c if (dpp->tf_mask->CM_BYPASS_EN) dpp 743 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c static bool dpp1_ingamma_ram_inuse(struct dpp *dpp_base, dpp 748 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 775 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 779 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 824 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp 827 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->tf_regs->reg dpp 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->base.ctx dpp 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->tf_shift->field_name, dpp->tf_mask->field_name dpp 89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dcn10_dpp *dpp, dpp 117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dcn10_dpp *dpp, const struct scaler_data *data) dpp 168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dpp *dpp_base, dpp 202 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dcn10_dpp *dpp, dpp 207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { dpp 261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dcn10_dpp *dpp, dpp 299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dcn10_dpp *dpp, dpp 341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c filter_updated = (filter_h && (filter_h != dpp->filter_h)) dpp 342 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c || (filter_v && (filter_v != dpp->filter_v)); dpp 349 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c)) dpp 350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c || (filter_v_c && (filter_v_c != dpp->filter_v_c)); dpp 358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp, scl_data->taps.h_taps, dpp 361 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->filter_h = filter_h; dpp 364 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp, scl_data->taps.v_taps, dpp 367 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->filter_v = filter_v; dpp 371 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp, scl_data->taps.h_taps_c, dpp 376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp, scl_data->taps.v_taps_c, dpp 380 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->filter_h_c = filter_h_c; dpp 381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->filter_v_c = filter_v_c; dpp 384 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT, dpp 385 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT); dpp 479 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp, dpp 489 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (dpp->base.ctx->dc->debug.use_max_lb) dpp 492 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->base.caps->dscl_calc_lb_num_partitions( dpp 499 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->base.caps->dscl_calc_lb_num_partitions( dpp 508 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->base.caps->dscl_calc_lb_num_partitions( dpp 516 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->base.caps->dscl_calc_lb_num_partitions( dpp 527 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dpp *dpp_base, dpp 531 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 537 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_overscan(dpp, scl_data); dpp 539 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_otg_blank(dpp, scl_data); dpp 546 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data); dpp 547 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config); dpp 575 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr); dpp 580 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dcn10_dpp *dpp, const struct scaler_data *data) dpp 644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dcn10_dpp *dpp, const struct rect *recout) dpp 647 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) dpp 661 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c - visual_confirm_on * 4 * (dpp->base.inst + 1)); dpp 666 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dpp *dpp_base, dpp 670 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp 676 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) dpp 681 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->scl_data = *scl_data; dpp 690 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_recout(dpp, &scl_data->recout); dpp 706 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data); dpp 707 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config); dpp 726 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_manual_ratio_init(dpp, scl_data); dpp 735 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr); dpp 258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp = pool->dpps[i]; dpp 261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->funcs->dpp_read_state(dpp, &s); dpp 268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->inst, dpp 980 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c int dpp_id = pipe_ctx->plane_res.dpp->inst; dpp 1007 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp, dpp 1016 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.dpp_pg_control(hws, dpp->inst, false); dpp 1018 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->funcs->dpp_reset(dpp); dpp 1032 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp = pipe_ctx->plane_res.dpp; dpp 1039 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->funcs->dpp_dppclk_control(dpp, false, false); dpp 1050 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp, dpp 1128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp = dc->res_pool->dpps[i]; dpp 1144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->funcs->dpp_reset(dpp); dpp 1150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp = dpp; dpp 1151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.mpcc_inst = dpp->inst; dpp 1152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->mpcc_id = dpp->inst; dpp 1392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp_base = pipe_ctx->plane_res.dpp; dpp 1471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp = pipe_ctx->plane_res.dpp; dpp 1473 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (dpp == NULL) dpp 1476 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; dpp 1481 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB); dpp 1488 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &dpp->regamma_params, false)) { dpp 1489 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->funcs->dpp_program_regamma_pwl( dpp 1490 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp, dpp 1491 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &dpp->regamma_params, OPP_REGAMMA_USER); dpp 1493 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS); dpp 1499 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->regamma_params.hw_points_num); dpp 1909 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust); dpp 1936 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix); dpp 1949 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) { dpp 1965 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix); dpp 1969 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL) dpp 1970 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace); dpp 2161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) dpp 2166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->funcs->dpp_setup(dpp, dpp 2179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (dpp->funcs->dpp_program_bias_and_scale) dpp 2180 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); dpp 2275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( dpp 2276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); dpp 2285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp = pipe_ctx->plane_res.dpp; dpp 2298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->funcs->dpp_dppclk_control( dpp 2299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp, dpp 2306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->inst, dpp 2338 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c update_dpp(dpp, plane_state); dpp 2466 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier( dpp 2467 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp, hw_mult); dpp 2958 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp = pipe_ctx->plane_res.dpp; dpp 3017 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width, hubp->curs_attr.height); dpp 3026 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes( dpp 3027 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp, attributes); dpp 3038 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes) dpp 3053 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes( dpp 3054 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp, &opt_attr); dpp 342 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c struct dpp *dpp = pool->dpps[i]; dpp 345 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dpp->funcs->dpp_read_state(dpp, &s); dpp 352 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dpp->inst, s.igam_input_format, dpp 579 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static void dcn10_dpp_destroy(struct dpp **dpp) dpp 581 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c kfree(TO_DCN10_DPP(*dpp)); dpp 582 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c *dpp = NULL; dpp 585 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static struct dpp *dcn10_dpp_create( dpp 589 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c struct dcn10_dpp *dpp = dpp 592 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (!dpp) dpp 595 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dpp1_construct(dpp, ctx, inst, dpp 597 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &dpp->base; dpp 1112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; dpp 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->tf_regs->reg dpp 45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->base.ctx dpp 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->tf_shift->field_name, dpp->tf_mask->field_name dpp 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c void dpp20_read_state(struct dpp *dpp_base, dpp 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp_base, dpp 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp_base, dpp 96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp_base, dpp 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp_base, dpp 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 321 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp_base, dpp 324 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 344 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp_base, dpp 348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 375 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp, dpp 389 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && dpp 394 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->ctx->dc->debug.max_downscale_src_width != 0 && dpp 395 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) dpp 443 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (!dpp->ctx->dc->debug.always_scale) { dpp 458 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp, dpp 495 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dcn20_dpp *dpp, dpp 502 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->base.ctx = ctx; dpp 504 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->base.inst = inst; dpp 505 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->base.funcs = &dcn20_dpp_funcs; dpp 506 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->base.caps = &dcn20_dpp_cap; dpp 508 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->tf_regs = tf_regs; dpp 509 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->tf_shift = tf_shift; dpp 510 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->tf_mask = tf_mask; dpp 512 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->lb_pixel_depth_supported = dpp 517 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; dpp 518 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ dpp 30 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h #define TO_DCN20_DPP(dpp)\ dpp 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h container_of(dpp, struct dcn20_dpp, base) dpp 627 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp base; dpp 645 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h void dpp20_read_state(struct dpp *dpp_base, dpp 649 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp 653 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp 657 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, const struct pwl_params *params); dpp 660 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp 664 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp 668 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp 678 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp 682 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp 686 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp, dpp 691 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp 695 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp, dpp 707 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp->tf_regs->reg dpp 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp->base.ctx dpp 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp->tf_shift->field_name, dpp->tf_mask->field_name dpp 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base) dpp 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp, dpp 210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; dpp 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; dpp 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; dpp 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; dpp 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; dpp 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; dpp 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; dpp 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; dpp 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; dpp 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; dpp 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; dpp 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; dpp 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; dpp 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; dpp 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; dpp 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; dpp 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; dpp 228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; dpp 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; dpp 230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; dpp 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dcn20_dpp_cm_get_reg_field(dpp, &gam_regs); dpp 258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); dpp 263 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 269 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dcn20_dpp_cm_get_reg_field(dpp, &gam_regs); dpp 286 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); dpp 289 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c static enum dc_lut_mode dpp20_get_blndgam_current(struct dpp *dpp_base) dpp 293 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, const struct pwl_params *params) dpp 320 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 351 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 382 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c static enum dc_lut_mode dpp20_get_shaper_current(struct dpp *dpp_base) dpp 386 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 409 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 412 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 424 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 428 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 574 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 578 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 725 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 731 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 761 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 767 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 807 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 813 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 828 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 832 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 843 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 848 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 877 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 882 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 898 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 901 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 909 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 989 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp 992 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp 479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dpp *dpp = pipe_ctx->plane_res.dpp; dpp 493 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dpp->funcs->dpp_dppclk_control(dpp, false, false); dpp 498 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.dpp, dpp 693 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dpp *dpp_base = pipe_ctx->plane_res.dpp; dpp 715 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dpp *dpp_base = pipe_ctx->plane_res.dpp; dpp 752 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dpp *dpp_base = pipe_ctx->plane_res.dpp; dpp 916 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); dpp 2039 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dpp *dpp = res_pool->dpps[i]; dpp 2041 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dpp->funcs->dpp_reset(dpp); dpp 2059 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dpp *dpp = dc->res_pool->dpps[i]; dpp 2065 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.dpp = dpp; dpp 2066 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.mpcc_inst = dpp->inst; dpp 2067 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->mpcc_id = dpp->inst; dpp 966 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c void dcn20_dpp_destroy(struct dpp **dpp) dpp 968 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(TO_DCN20_DPP(*dpp)); dpp 969 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c *dpp = NULL; dpp 972 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dpp *dcn20_dpp_create( dpp 976 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dcn20_dpp *dpp = dpp 979 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!dpp) dpp 982 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (dpp2_construct(dpp, ctx, inst, dpp 984 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &dpp->base; dpp 987 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(dpp); dpp 1737 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; dpp 1817 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; dpp 2955 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; dpp 72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h void dcn20_dpp_destroy(struct dpp **dpp); dpp 74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h struct dpp *dcn20_dpp_create( dpp 656 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static struct dpp *dcn21_dpp_create( dpp 660 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct dcn20_dpp *dpp = dpp 663 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (!dpp) dpp 666 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (dpp2_construct(dpp, ctx, inst, dpp 668 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &dpp->base; dpp 671 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kfree(dpp); dpp 169 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct dpp *dpps[MAX_PIPES]; dpp 263 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct dpp *dpp; dpp 111 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h void (*dpp_program_cm_dealpha)(struct dpp *dpp_base, dpp 115 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp 118 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s); dpp 120 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h void (*dpp_reset)(struct dpp *dpp); dpp 122 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h void (*dpp_set_scaler)(struct dpp *dpp, dpp 126 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 131 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 136 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 140 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 144 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 148 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 152 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 157 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 161 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 165 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 169 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 174 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 178 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp 182 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp 185 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h void (*dpp_program_degamma_pwl)(struct dpp *dpp_base, dpp 189 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp 200 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h void (*dpp_full_bypass)(struct dpp *dpp_base); dpp 203 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp 207 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp 215 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp 219 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp 223 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp 229 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 232 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 235 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp, dpp 238 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp 200 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h int dpp[MAX_PIPES]; dpp 83 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct dpp; dpp 290 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct dpp *dpp, dpp 59 fs/nfsd/vfs.c nfsd_cross_mnt(struct svc_rqst *rqstp, struct dentry **dpp, dpp 63 fs/nfsd/vfs.c struct dentry *dentry = *dpp; dpp 102 fs/nfsd/vfs.c *dpp = path.dentry; dpp 43 fs/nfsd/vfs.h int nfsd_cross_mnt(struct svc_rqst *rqstp, struct dentry **dpp,