dpll 980 drivers/ata/pata_hpt37x.c int dpll, adjust; dpll 983 drivers/ata/pata_hpt37x.c dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; dpll 985 drivers/ata/pata_hpt37x.c f_low = (MHz[clock_slot] * 48) / MHz[dpll]; dpll 1013 drivers/ata/pata_hpt37x.c if (dpll == 3) dpll 1019 drivers/ata/pata_hpt37x.c MHz[clock_slot], MHz[dpll]); dpll 317 drivers/ata/pata_hpt3x2n.c int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); dpll 324 drivers/ata/pata_hpt3x2n.c if ((flags & USE_DPLL) != dpll && alt->qc_active) dpll 333 drivers/ata/pata_hpt3x2n.c int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); dpll 335 drivers/ata/pata_hpt3x2n.c if ((flags & USE_DPLL) != dpll) { dpll 337 drivers/ata/pata_hpt3x2n.c flags |= dpll; dpll 340 drivers/ata/pata_hpt3x2n.c hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); dpll 183 drivers/clk/rockchip/clk-px30.c [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, dpll 137 drivers/clk/rockchip/clk-rk3036.c [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), dpll 160 drivers/clk/rockchip/clk-rk3128.c [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), dpll 216 drivers/clk/rockchip/clk-rk3188.c [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), dpll 227 drivers/clk/rockchip/clk-rk3188.c [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), dpll 170 drivers/clk/rockchip/clk-rk3228.c [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), dpll 222 drivers/clk/rockchip/clk-rk3288.c [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4), dpll 183 drivers/clk/rockchip/clk-rk3308.c [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, dpll 217 drivers/clk/rockchip/clk-rk3328.c [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, dpll 134 drivers/clk/rockchip/clk-rk3368.c [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8), dpll 221 drivers/clk/rockchip/clk-rk3399.c [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16), dpll 155 drivers/clk/rockchip/clk-rv1108.c [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8), dpll 1448 drivers/clk/samsung/clk-exynos5420.c [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, dpll 522 drivers/gpu/drm/gma500/cdv_device.c .dpll = DPLL_A, dpll 547 drivers/gpu/drm/gma500/cdv_device.c .dpll = DPLL_B, dpll 581 drivers/gpu/drm/gma500/cdv_intel_display.c u32 dpll = 0, dspcntr, pipeconf; dpll 663 drivers/gpu/drm/gma500/cdv_intel_display.c dpll = DPLL_VGA_MODE_DIS; dpll 667 drivers/gpu/drm/gma500/cdv_intel_display.c dpll |= 3; dpll 680 drivers/gpu/drm/gma500/cdv_intel_display.c dpll |= DPLL_SYNCLOCK_ENABLE; dpll 726 drivers/gpu/drm/gma500/cdv_intel_display.c REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); dpll 727 drivers/gpu/drm/gma500/cdv_intel_display.c REG_READ(map->dpll); dpll 762 drivers/gpu/drm/gma500/cdv_intel_display.c dpll |= DPLL_VCO_ENABLE; dpll 771 drivers/gpu/drm/gma500/cdv_intel_display.c REG_WRITE(map->dpll, dpll 772 drivers/gpu/drm/gma500/cdv_intel_display.c (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); dpll 773 drivers/gpu/drm/gma500/cdv_intel_display.c REG_READ(map->dpll); dpll 777 drivers/gpu/drm/gma500/cdv_intel_display.c if (!(REG_READ(map->dpll) & DPLL_LOCK)) { dpll 846 drivers/gpu/drm/gma500/cdv_intel_display.c u32 dpll; dpll 853 drivers/gpu/drm/gma500/cdv_intel_display.c dpll = REG_READ(map->dpll); dpll 854 drivers/gpu/drm/gma500/cdv_intel_display.c if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) dpll 861 drivers/gpu/drm/gma500/cdv_intel_display.c dpll = p->dpll; dpll 862 drivers/gpu/drm/gma500/cdv_intel_display.c if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) dpll 877 drivers/gpu/drm/gma500/cdv_intel_display.c ffs((dpll & dpll 882 drivers/gpu/drm/gma500/cdv_intel_display.c dev_err(dev->dev, "PLL %d\n", dpll); dpll 886 drivers/gpu/drm/gma500/cdv_intel_display.c if ((dpll & PLL_REF_INPUT_MASK) == dpll 893 drivers/gpu/drm/gma500/cdv_intel_display.c if (dpll & PLL_P1_DIVIDE_BY_TWO) dpll 897 drivers/gpu/drm/gma500/cdv_intel_display.c ((dpll & dpll 901 drivers/gpu/drm/gma500/cdv_intel_display.c if (dpll & PLL_P2_DIVIDE_BY_4) dpll 215 drivers/gpu/drm/gma500/gma_display.c temp = REG_READ(map->dpll); dpll 217 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->dpll, temp); dpll 218 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->dpll); dpll 221 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); dpll 222 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->dpll); dpll 225 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); dpll 226 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->dpll); dpll 301 drivers/gpu/drm/gma500/gma_display.c temp = REG_READ(map->dpll); dpll 303 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); dpll 304 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->dpll); dpll 544 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDPLL = REG_READ(map->dpll); dpll 583 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->dpll, dpll 585 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->dpll); dpll 595 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->dpll, crtc_state->saveDPLL); dpll 596 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->dpll); dpll 187 drivers/gpu/drm/gma500/mdfld_device.c pipe->dpll = PSB_RVDC32(map->dpll); dpll 241 drivers/gpu/drm/gma500/mdfld_device.c u32 dpll; dpll 248 drivers/gpu/drm/gma500/mdfld_device.c u32 dpll_val = pipe->dpll; dpll 273 drivers/gpu/drm/gma500/mdfld_device.c PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); dpll 274 drivers/gpu/drm/gma500/mdfld_device.c PSB_RVDC32(map->dpll); dpll 279 drivers/gpu/drm/gma500/mdfld_device.c dpll = PSB_RVDC32(map->dpll); dpll 281 drivers/gpu/drm/gma500/mdfld_device.c if (!(dpll & DPLL_VCO_ENABLE)) { dpll 285 drivers/gpu/drm/gma500/mdfld_device.c if (dpll & MDFLD_PWR_GATE_EN) { dpll 286 drivers/gpu/drm/gma500/mdfld_device.c dpll &= ~MDFLD_PWR_GATE_EN; dpll 287 drivers/gpu/drm/gma500/mdfld_device.c PSB_WVDC32(dpll, map->dpll); dpll 293 drivers/gpu/drm/gma500/mdfld_device.c PSB_WVDC32(dpll_val, map->dpll); dpll 298 drivers/gpu/drm/gma500/mdfld_device.c PSB_WVDC32(dpll_val, map->dpll); dpll 299 drivers/gpu/drm/gma500/mdfld_device.c PSB_RVDC32(map->dpll); dpll 444 drivers/gpu/drm/gma500/mdfld_device.c .dpll = MRST_DPLL_A, dpll 466 drivers/gpu/drm/gma500/mdfld_device.c .dpll = MDFLD_DPLL_B, dpll 489 drivers/gpu/drm/gma500/mdfld_device.c .dpll = MRST_DPLL_A, dpll 629 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c pkg_sender->dpll_reg = map->dpll; dpll 266 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->dpll); dpll 272 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->dpll, temp); dpll 273 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->dpll); dpll 280 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); dpll 322 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->dpll); dpll 329 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->dpll, temp); dpll 334 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->dpll, temp); dpll 335 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->dpll); dpll 339 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); dpll 340 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->dpll); dpll 452 drivers/gpu/drm/gma500/mdfld_intel_display.c temp = REG_READ(map->dpll); dpll 458 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->dpll, temp); dpll 459 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->dpll); dpll 672 drivers/gpu/drm/gma500/mdfld_intel_display.c u32 dpll = 0, fp = 0; dpll 915 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll = REG_READ(map->dpll); dpll 917 drivers/gpu/drm/gma500/mdfld_intel_display.c if (dpll & DPLL_VCO_ENABLE) { dpll 918 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll &= ~DPLL_VCO_ENABLE; dpll 919 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->dpll, dpll); dpll 920 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->dpll); dpll 928 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll &= ~MDFLD_P1_MASK; dpll 929 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->dpll, dpll); dpll 936 drivers/gpu/drm/gma500/mdfld_intel_display.c if (dpll & MDFLD_PWR_GATE_EN) { dpll 937 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll &= ~MDFLD_PWR_GATE_EN; dpll 938 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->dpll, dpll); dpll 942 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll = 0; dpll 947 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll &= ~MDFLD_INPUT_REF_SEL; dpll 949 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll |= MDFLD_INPUT_REF_SEL; dpll 953 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll |= MDFLD_VCO_SEL; dpll 959 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll |= (1 << (clock.p1 - 2)) << 17; dpll 962 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll = 0x00050000; dpll 966 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll = 0x02010000; dpll 971 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll = 0x00020000; dpll 975 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll = 0x00800000; dpll 980 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->dpll, dpll); dpll 984 drivers/gpu/drm/gma500/mdfld_intel_display.c dpll |= DPLL_VCO_ENABLE; dpll 985 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->dpll, dpll); dpll 986 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->dpll); dpll 242 drivers/gpu/drm/gma500/oaktrail_crtc.c temp = REG_READ_WITH_AUX(map->dpll, i); dpll 244 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_WRITE_WITH_AUX(map->dpll, temp, i); dpll 245 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ_WITH_AUX(map->dpll, i); dpll 248 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_WRITE_WITH_AUX(map->dpll, dpll 250 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ_WITH_AUX(map->dpll, i); dpll 253 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_WRITE_WITH_AUX(map->dpll, dpll 255 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ_WITH_AUX(map->dpll, i); dpll 314 drivers/gpu/drm/gma500/oaktrail_crtc.c temp = REG_READ_WITH_AUX(map->dpll, i); dpll 316 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_WRITE_WITH_AUX(map->dpll, dpll 318 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ_WITH_AUX(map->dpll, i); dpll 370 drivers/gpu/drm/gma500/oaktrail_crtc.c u32 dpll = 0, fp = 0, dspcntr, pipeconf; dpll 499 drivers/gpu/drm/gma500/oaktrail_crtc.c dpll = 0; /*BIT16 = 0 for 100MHz reference */ dpll 523 drivers/gpu/drm/gma500/oaktrail_crtc.c dpll |= DPLL_VGA_MODE_DIS; dpll 526 drivers/gpu/drm/gma500/oaktrail_crtc.c dpll |= DPLL_VCO_ENABLE; dpll 529 drivers/gpu/drm/gma500/oaktrail_crtc.c dpll |= DPLLA_MODE_LVDS; dpll 531 drivers/gpu/drm/gma500/oaktrail_crtc.c dpll |= DPLLB_MODE_DAC_SERIAL; dpll 537 drivers/gpu/drm/gma500/oaktrail_crtc.c dpll |= DPLL_DVO_HIGH_SPEED; dpll 538 drivers/gpu/drm/gma500/oaktrail_crtc.c dpll |= dpll 546 drivers/gpu/drm/gma500/oaktrail_crtc.c dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16; dpll 548 drivers/gpu/drm/gma500/oaktrail_crtc.c dpll |= (1 << (clock.p1 - 2)) << 17; dpll 550 drivers/gpu/drm/gma500/oaktrail_crtc.c dpll |= DPLL_VCO_ENABLE; dpll 552 drivers/gpu/drm/gma500/oaktrail_crtc.c if (dpll & DPLL_VCO_ENABLE) { dpll 555 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); dpll 556 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ_WITH_AUX(map->dpll, i); dpll 564 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_WRITE_WITH_AUX(map->dpll, dpll, i); dpll 565 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ_WITH_AUX(map->dpll, i); dpll 570 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_WRITE_WITH_AUX(map->dpll, dpll, i); dpll 571 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ_WITH_AUX(map->dpll, i); dpll 202 drivers/gpu/drm/gma500/oaktrail_device.c p->dpll = PSB_RVDC32(MRST_DPLL_A); dpll 319 drivers/gpu/drm/gma500/oaktrail_device.c PSB_WVDC32(p->dpll, MRST_DPLL_A); dpll 460 drivers/gpu/drm/gma500/oaktrail_device.c .dpll = MRST_DPLL_A, dpll 484 drivers/gpu/drm/gma500/oaktrail_device.c .dpll = DPLL_B, dpll 283 drivers/gpu/drm/gma500/oaktrail_hdmi.c u32 dspcntr, pipeconf, dpll, temp; dpll 293 drivers/gpu/drm/gma500/oaktrail_hdmi.c dpll = REG_READ(DPLL_CTRL); dpll 294 drivers/gpu/drm/gma500/oaktrail_hdmi.c if ((dpll & DPLL_PWRDN) == 0) { dpll 295 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); dpll 309 drivers/gpu/drm/gma500/oaktrail_hdmi.c dpll = REG_READ(DPLL_CTRL); dpll 310 drivers/gpu/drm/gma500/oaktrail_hdmi.c dpll &= ~DPLL_PDIV_MASK; dpll 311 drivers/gpu/drm/gma500/oaktrail_hdmi.c dpll &= ~(DPLL_PWRDN | DPLL_RESET); dpll 315 drivers/gpu/drm/gma500/oaktrail_hdmi.c REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); dpll 257 drivers/gpu/drm/gma500/psb_device.c .dpll = DPLL_A, dpll 281 drivers/gpu/drm/gma500/psb_device.c .dpll = DPLL_B, dpll 270 drivers/gpu/drm/gma500/psb_drv.h u32 dpll; dpll 304 drivers/gpu/drm/gma500/psb_drv.h u32 dpll; dpll 105 drivers/gpu/drm/gma500/psb_intel_display.c u32 dpll = 0, fp = 0, dspcntr, pipeconf; dpll 152 drivers/gpu/drm/gma500/psb_intel_display.c dpll = DPLL_VGA_MODE_DIS; dpll 154 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= DPLLB_MODE_LVDS; dpll 155 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= DPLL_DVO_HIGH_SPEED; dpll 157 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= DPLLB_MODE_DAC_SERIAL; dpll 161 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= DPLL_DVO_HIGH_SPEED; dpll 162 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= dpll 167 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= (1 << (clock.p1 - 1)) << 16; dpll 170 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; dpll 173 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; dpll 176 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; dpll 179 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; dpll 186 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= 3; dpll 188 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= PLL_REF_INPUT_DREFCLK; dpll 203 drivers/gpu/drm/gma500/psb_intel_display.c dpll |= DPLL_VCO_ENABLE; dpll 212 drivers/gpu/drm/gma500/psb_intel_display.c if (dpll & DPLL_VCO_ENABLE) { dpll 214 drivers/gpu/drm/gma500/psb_intel_display.c REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); dpll 215 drivers/gpu/drm/gma500/psb_intel_display.c REG_READ(map->dpll); dpll 249 drivers/gpu/drm/gma500/psb_intel_display.c REG_WRITE(map->dpll, dpll); dpll 250 drivers/gpu/drm/gma500/psb_intel_display.c REG_READ(map->dpll); dpll 255 drivers/gpu/drm/gma500/psb_intel_display.c REG_WRITE(map->dpll, dpll); dpll 257 drivers/gpu/drm/gma500/psb_intel_display.c REG_READ(map->dpll); dpll 304 drivers/gpu/drm/gma500/psb_intel_display.c u32 dpll; dpll 311 drivers/gpu/drm/gma500/psb_intel_display.c dpll = REG_READ(map->dpll); dpll 312 drivers/gpu/drm/gma500/psb_intel_display.c if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) dpll 319 drivers/gpu/drm/gma500/psb_intel_display.c dpll = p->dpll; dpll 321 drivers/gpu/drm/gma500/psb_intel_display.c if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) dpll 336 drivers/gpu/drm/gma500/psb_intel_display.c ffs((dpll & dpll 341 drivers/gpu/drm/gma500/psb_intel_display.c if ((dpll & PLL_REF_INPUT_MASK) == dpll 348 drivers/gpu/drm/gma500/psb_intel_display.c if (dpll & PLL_P1_DIVIDE_BY_TWO) dpll 352 drivers/gpu/drm/gma500/psb_intel_display.c ((dpll & dpll 356 drivers/gpu/drm/gma500/psb_intel_display.c if (dpll & PLL_P2_DIVIDE_BY_4) dpll 1656 drivers/gpu/drm/i915/display/intel_ddi.c struct dpll clock; dpll 533 drivers/gpu/drm/i915/display/intel_display.c static int pnv_calc_dpll_params(int refclk, struct dpll *clock) dpll 545 drivers/gpu/drm/i915/display/intel_display.c static u32 i9xx_dpll_compute_m(struct dpll *dpll) dpll 547 drivers/gpu/drm/i915/display/intel_display.c return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); dpll 550 drivers/gpu/drm/i915/display/intel_display.c static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) dpll 562 drivers/gpu/drm/i915/display/intel_display.c static int vlv_calc_dpll_params(int refclk, struct dpll *clock) dpll 574 drivers/gpu/drm/i915/display/intel_display.c int chv_calc_dpll_params(int refclk, struct dpll *clock) dpll 595 drivers/gpu/drm/i915/display/intel_display.c const struct dpll *clock) dpll 668 drivers/gpu/drm/i915/display/intel_display.c int target, int refclk, struct dpll *match_clock, dpll 669 drivers/gpu/drm/i915/display/intel_display.c struct dpll *best_clock) dpll 672 drivers/gpu/drm/i915/display/intel_display.c struct dpll clock; dpll 726 drivers/gpu/drm/i915/display/intel_display.c int target, int refclk, struct dpll *match_clock, dpll 727 drivers/gpu/drm/i915/display/intel_display.c struct dpll *best_clock) dpll 730 drivers/gpu/drm/i915/display/intel_display.c struct dpll clock; dpll 782 drivers/gpu/drm/i915/display/intel_display.c int target, int refclk, struct dpll *match_clock, dpll 783 drivers/gpu/drm/i915/display/intel_display.c struct dpll *best_clock) dpll 786 drivers/gpu/drm/i915/display/intel_display.c struct dpll clock; dpll 833 drivers/gpu/drm/i915/display/intel_display.c const struct dpll *calculated_clock, dpll 834 drivers/gpu/drm/i915/display/intel_display.c const struct dpll *best_clock, dpll 876 drivers/gpu/drm/i915/display/intel_display.c int target, int refclk, struct dpll *match_clock, dpll 877 drivers/gpu/drm/i915/display/intel_display.c struct dpll *best_clock) dpll 881 drivers/gpu/drm/i915/display/intel_display.c struct dpll clock; dpll 936 drivers/gpu/drm/i915/display/intel_display.c int target, int refclk, struct dpll *match_clock, dpll 937 drivers/gpu/drm/i915/display/intel_display.c struct dpll *best_clock) dpll 942 drivers/gpu/drm/i915/display/intel_display.c struct dpll clock; dpll 992 drivers/gpu/drm/i915/display/intel_display.c struct dpll *best_clock) dpll 1381 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); dpll 1400 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) dpll 1431 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); dpll 1449 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) dpll 1488 drivers/gpu/drm/i915/display/intel_display.c u32 dpll = crtc_state->dpll_hw_state.dpll; dpll 1502 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS); dpll 1503 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, dpll); dpll 1518 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, dpll); dpll 1523 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, dpll); dpll 7553 drivers/gpu/drm/i915/display/intel_display.c static u32 pnv_dpll_compute_fp(struct dpll *dpll) dpll 7555 drivers/gpu/drm/i915/display/intel_display.c return (1 << dpll->n) << 16 | dpll->m2; dpll 7558 drivers/gpu/drm/i915/display/intel_display.c static u32 i9xx_dpll_compute_fp(struct dpll *dpll) dpll 7560 drivers/gpu/drm/i915/display/intel_display.c return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; dpll 7565 drivers/gpu/drm/i915/display/intel_display.c struct dpll *reduced_clock) dpll 7571 drivers/gpu/drm/i915/display/intel_display.c fp = pnv_dpll_compute_fp(&crtc_state->dpll); dpll 7575 drivers/gpu/drm/i915/display/intel_display.c fp = i9xx_dpll_compute_fp(&crtc_state->dpll); dpll 7707 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | dpll 7710 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; dpll 7714 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | dpll 7724 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | dpll 7727 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; dpll 7731 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; dpll 7749 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll & dpll 7753 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) dpll 7758 drivers/gpu/drm/i915/display/intel_display.c bestn = pipe_config->dpll.n; dpll 7759 drivers/gpu/drm/i915/display/intel_display.c bestm1 = pipe_config->dpll.m1; dpll 7760 drivers/gpu/drm/i915/display/intel_display.c bestm2 = pipe_config->dpll.m2; dpll 7761 drivers/gpu/drm/i915/display/intel_display.c bestp1 = pipe_config->dpll.p1; dpll 7762 drivers/gpu/drm/i915/display/intel_display.c bestp2 = pipe_config->dpll.p2; dpll 7851 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); dpll 7854 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) dpll 7857 drivers/gpu/drm/i915/display/intel_display.c bestn = pipe_config->dpll.n; dpll 7858 drivers/gpu/drm/i915/display/intel_display.c bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; dpll 7859 drivers/gpu/drm/i915/display/intel_display.c bestm1 = pipe_config->dpll.m1; dpll 7860 drivers/gpu/drm/i915/display/intel_display.c bestm2 = pipe_config->dpll.m2 >> 22; dpll 7861 drivers/gpu/drm/i915/display/intel_display.c bestp1 = pipe_config->dpll.p1; dpll 7862 drivers/gpu/drm/i915/display/intel_display.c bestp2 = pipe_config->dpll.p2; dpll 7863 drivers/gpu/drm/i915/display/intel_display.c vco = pipe_config->dpll.vco; dpll 7953 drivers/gpu/drm/i915/display/intel_display.c const struct dpll *dpll) dpll 7964 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll = *dpll; dpll 7999 drivers/gpu/drm/i915/display/intel_display.c struct dpll *reduced_clock) dpll 8002 drivers/gpu/drm/i915/display/intel_display.c u32 dpll; dpll 8003 drivers/gpu/drm/i915/display/intel_display.c struct dpll *clock = &crtc_state->dpll; dpll 8007 drivers/gpu/drm/i915/display/intel_display.c dpll = DPLL_VGA_MODE_DIS; dpll 8010 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLLB_MODE_LVDS; dpll 8012 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLLB_MODE_DAC_SERIAL; dpll 8016 drivers/gpu/drm/i915/display/intel_display.c dpll |= (crtc_state->pixel_multiplier - 1) dpll 8022 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_SDVO_HIGH_SPEED; dpll 8025 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_SDVO_HIGH_SPEED; dpll 8029 drivers/gpu/drm/i915/display/intel_display.c dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; dpll 8031 drivers/gpu/drm/i915/display/intel_display.c dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; dpll 8033 drivers/gpu/drm/i915/display/intel_display.c dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; dpll 8037 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; dpll 8040 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; dpll 8043 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; dpll 8046 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; dpll 8050 drivers/gpu/drm/i915/display/intel_display.c dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); dpll 8053 drivers/gpu/drm/i915/display/intel_display.c dpll |= PLL_REF_INPUT_TVCLKINBC; dpll 8056 drivers/gpu/drm/i915/display/intel_display.c dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; dpll 8058 drivers/gpu/drm/i915/display/intel_display.c dpll |= PLL_REF_INPUT_DREFCLK; dpll 8060 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_VCO_ENABLE; dpll 8061 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.dpll = dpll; dpll 8072 drivers/gpu/drm/i915/display/intel_display.c struct dpll *reduced_clock) dpll 8076 drivers/gpu/drm/i915/display/intel_display.c u32 dpll; dpll 8077 drivers/gpu/drm/i915/display/intel_display.c struct dpll *clock = &crtc_state->dpll; dpll 8081 drivers/gpu/drm/i915/display/intel_display.c dpll = DPLL_VGA_MODE_DIS; dpll 8084 drivers/gpu/drm/i915/display/intel_display.c dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; dpll 8087 drivers/gpu/drm/i915/display/intel_display.c dpll |= PLL_P1_DIVIDE_BY_TWO; dpll 8089 drivers/gpu/drm/i915/display/intel_display.c dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; dpll 8091 drivers/gpu/drm/i915/display/intel_display.c dpll |= PLL_P2_DIVIDE_BY_4; dpll 8108 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_DVO_2X_MODE; dpll 8112 drivers/gpu/drm/i915/display/intel_display.c dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; dpll 8114 drivers/gpu/drm/i915/display/intel_display.c dpll |= PLL_REF_INPUT_DREFCLK; dpll 8116 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_VCO_ENABLE; dpll 8117 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.dpll = dpll; dpll 8364 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { dpll 8406 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { dpll 8440 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { dpll 8474 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { dpll 8495 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { dpll 8516 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { dpll 8567 drivers/gpu/drm/i915/display/intel_display.c struct dpll clock; dpll 8572 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) dpll 8678 drivers/gpu/drm/i915/display/intel_display.c struct dpll clock; dpll 8683 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) dpll 8850 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); dpll 8856 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | dpll 9526 drivers/gpu/drm/i915/display/intel_display.c static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) dpll 9528 drivers/gpu/drm/i915/display/intel_display.c return i9xx_dpll_compute_m(dpll) < factor * dpll->n; dpll 9533 drivers/gpu/drm/i915/display/intel_display.c struct dpll *reduced_clock) dpll 9536 drivers/gpu/drm/i915/display/intel_display.c u32 dpll, fp, fp2; dpll 9551 drivers/gpu/drm/i915/display/intel_display.c fp = i9xx_dpll_compute_fp(&crtc_state->dpll); dpll 9553 drivers/gpu/drm/i915/display/intel_display.c if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) dpll 9565 drivers/gpu/drm/i915/display/intel_display.c dpll = 0; dpll 9568 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLLB_MODE_LVDS; dpll 9570 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLLB_MODE_DAC_SERIAL; dpll 9572 drivers/gpu/drm/i915/display/intel_display.c dpll |= (crtc_state->pixel_multiplier - 1) dpll 9577 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_SDVO_HIGH_SPEED; dpll 9580 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_SDVO_HIGH_SPEED; dpll 9598 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_SDVO_HIGH_SPEED; dpll 9601 drivers/gpu/drm/i915/display/intel_display.c dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; dpll 9603 drivers/gpu/drm/i915/display/intel_display.c dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; dpll 9605 drivers/gpu/drm/i915/display/intel_display.c switch (crtc_state->dpll.p2) { dpll 9607 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; dpll 9610 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; dpll 9613 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; dpll 9616 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; dpll 9622 drivers/gpu/drm/i915/display/intel_display.c dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; dpll 9624 drivers/gpu/drm/i915/display/intel_display.c dpll |= PLL_REF_INPUT_DREFCLK; dpll 9626 drivers/gpu/drm/i915/display/intel_display.c dpll |= DPLL_VCO_ENABLE; dpll 9628 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.dpll = dpll; dpll 9673 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { dpll 10027 drivers/gpu/drm/i915/display/intel_display.c tmp = pipe_config->dpll_hw_state.dpll; dpll 11271 drivers/gpu/drm/i915/display/intel_display.c u32 dpll = pipe_config->dpll_hw_state.dpll; dpll 11273 drivers/gpu/drm/i915/display/intel_display.c if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) dpll 11290 drivers/gpu/drm/i915/display/intel_display.c u32 dpll = pipe_config->dpll_hw_state.dpll; dpll 11292 drivers/gpu/drm/i915/display/intel_display.c struct dpll clock; dpll 11296 drivers/gpu/drm/i915/display/intel_display.c if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) dpll 11312 drivers/gpu/drm/i915/display/intel_display.c clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> dpll 11315 drivers/gpu/drm/i915/display/intel_display.c clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> dpll 11318 drivers/gpu/drm/i915/display/intel_display.c switch (dpll & DPLL_MODE_MASK) { dpll 11320 drivers/gpu/drm/i915/display/intel_display.c clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? dpll 11324 drivers/gpu/drm/i915/display/intel_display.c clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? dpll 11329 drivers/gpu/drm/i915/display/intel_display.c "mode\n", (int)(dpll & DPLL_MODE_MASK)); dpll 11342 drivers/gpu/drm/i915/display/intel_display.c clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> dpll 11350 drivers/gpu/drm/i915/display/intel_display.c if (dpll & PLL_P1_DIVIDE_BY_TWO) dpll 11353 drivers/gpu/drm/i915/display/intel_display.c clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> dpll 11356 drivers/gpu/drm/i915/display/intel_display.c if (dpll & PLL_P2_DIVIDE_BY_4) dpll 12795 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.dpll); dpll 16289 drivers/gpu/drm/i915/display/intel_display.c struct dpll clock = { dpll 16296 drivers/gpu/drm/i915/display/intel_display.c u32 dpll, fp; dpll 16305 drivers/gpu/drm/i915/display/intel_display.c dpll = DPLL_DVO_2X_MODE | dpll 16328 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); dpll 16329 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL(pipe), dpll); dpll 16340 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL(pipe), dpll); dpll 16344 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL(pipe), dpll); dpll 32 drivers/gpu/drm/i915/display/intel_display.h struct dpll; dpll 491 drivers/gpu/drm/i915/display/intel_display.h const struct dpll *dpll); dpll 506 drivers/gpu/drm/i915/display/intel_display.h struct dpll *best_clock); dpll 507 drivers/gpu/drm/i915/display/intel_display.h int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); dpll 837 drivers/gpu/drm/i915/display/intel_display_types.h struct dpll dpll; dpll 92 drivers/gpu/drm/i915/display/intel_dp.c struct dpll dpll; dpll 766 drivers/gpu/drm/i915/display/intel_dp.c &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { dpll 1751 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dpll = divisor[i].dpll; dpll 381 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->dpll = val; dpll 420 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); dpll 431 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); dpll 488 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->dpll, dpll 1753 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct dpll best_clock; dpll 3651 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->dpll, dpll 170 drivers/gpu/drm/i915/display/intel_dpll_mgr.h u32 dpll; dpll 447 drivers/gpu/drm/i915/display/intel_dvo.c u32 dpll[I915_MAX_PIPES]; dpll 484 drivers/gpu/drm/i915/display/intel_dvo.c dpll[pipe] = I915_READ(DPLL(pipe)); dpll 485 drivers/gpu/drm/i915/display/intel_dvo.c I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); dpll 492 drivers/gpu/drm/i915/display/intel_dvo.c I915_WRITE(DPLL(pipe), dpll[pipe]); dpll 1245 drivers/gpu/drm/i915/display/intel_sdvo.c struct dpll *clock = &pipe_config->dpll; dpll 2839 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); dpll 253 drivers/gpu/drm/i915/i915_drv.h struct dpll; dpll 83 drivers/gpu/drm/rcar-du/rcar_du_crtc.c struct dpll_info *dpll, dpll 147 drivers/gpu/drm/rcar-du/rcar_du_crtc.c dpll->n = n; dpll 148 drivers/gpu/drm/rcar-du/rcar_du_crtc.c dpll->m = m; dpll 149 drivers/gpu/drm/rcar-du/rcar_du_crtc.c dpll->fdpll = fdpll; dpll 150 drivers/gpu/drm/rcar-du/rcar_du_crtc.c dpll->output = output; dpll 162 drivers/gpu/drm/rcar-du/rcar_du_crtc.c dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); dpll 221 drivers/gpu/drm/rcar-du/rcar_du_crtc.c struct dpll_info dpll = { 0 }; dpll 245 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rcar_du_dpll_divider(rcrtc, &dpll, extclk, target); dpll 248 drivers/gpu/drm/rcar-du/rcar_du_crtc.c | DPLLCR_FDPLL(dpll.fdpll) dpll 249 drivers/gpu/drm/rcar-du/rcar_du_crtc.c | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m) dpll 850 drivers/ide/hpt366.c u32 dpll = (f_high << 16) | f_low | 0x100; dpll 854 drivers/ide/hpt366.c pci_write_config_dword(dev, 0x5c, dpll); dpll 871 drivers/ide/hpt366.c pci_read_config_dword (dev, 0x5c, &dpll); dpll 872 drivers/ide/hpt366.c pci_write_config_dword(dev, 0x5c, (dpll & ~0x100)); dpll 684 drivers/video/fbdev/intelfb/intelfbhw.c static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, dpll 690 drivers/video/fbdev/intelfb/intelfbhw.c if (dpll & DPLL_P1_FORCE_DIV2) dpll 693 drivers/video/fbdev/intelfb/intelfbhw.c p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; dpll 697 drivers/video/fbdev/intelfb/intelfbhw.c p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK; dpll 699 drivers/video/fbdev/intelfb/intelfbhw.c if (dpll & DPLL_P1_FORCE_DIV2) dpll 702 drivers/video/fbdev/intelfb/intelfbhw.c p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; dpll 703 drivers/video/fbdev/intelfb/intelfbhw.c p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK; dpll 1045 drivers/video/fbdev/intelfb/intelfbhw.c u32 *dpll, *fp0, *fp1; dpll 1060 drivers/video/fbdev/intelfb/intelfbhw.c dpll = &hw->dpll_b; dpll 1072 drivers/video/fbdev/intelfb/intelfbhw.c dpll = &hw->dpll_a; dpll 1108 drivers/video/fbdev/intelfb/intelfbhw.c *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE); dpll 1109 drivers/video/fbdev/intelfb/intelfbhw.c *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK); dpll 1110 drivers/video/fbdev/intelfb/intelfbhw.c *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0); dpll 1133 drivers/video/fbdev/intelfb/intelfbhw.c *dpll &= ~DPLL_P1_FORCE_DIV2; dpll 1134 drivers/video/fbdev/intelfb/intelfbhw.c *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) | dpll 1138 drivers/video/fbdev/intelfb/intelfbhw.c *dpll |= (p2 << DPLL_I9XX_P2_SHIFT); dpll 1139 drivers/video/fbdev/intelfb/intelfbhw.c *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT; dpll 1141 drivers/video/fbdev/intelfb/intelfbhw.c *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT); dpll 1281 drivers/video/fbdev/intelfb/intelfbhw.c const u32 *dpll, *fp0, *fp1, *pipe_conf; dpll 1303 drivers/video/fbdev/intelfb/intelfbhw.c dpll = &hw->dpll_b; dpll 1327 drivers/video/fbdev/intelfb/intelfbhw.c dpll = &hw->dpll_a; dpll 1407 drivers/video/fbdev/intelfb/intelfbhw.c OUTREG(dpll_reg, *dpll);