CG_VCEPLL_FUNC_CNTL 7458 drivers/gpu/drm/radeon/si.c 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
CG_VCEPLL_FUNC_CNTL 7463 drivers/gpu/drm/radeon/si.c 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
CG_VCEPLL_FUNC_CNTL 7468 drivers/gpu/drm/radeon/si.c 		if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)
CG_VCEPLL_FUNC_CNTL 7474 drivers/gpu/drm/radeon/si.c 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
CG_VCEPLL_FUNC_CNTL 7495 drivers/gpu/drm/radeon/si.c 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,
CG_VCEPLL_FUNC_CNTL 7500 drivers/gpu/drm/radeon/si.c 		WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
CG_VCEPLL_FUNC_CNTL 7515 drivers/gpu/drm/radeon/si.c 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,
CG_VCEPLL_FUNC_CNTL 7519 drivers/gpu/drm/radeon/si.c 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
CG_VCEPLL_FUNC_CNTL 7521 drivers/gpu/drm/radeon/si.c 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);
CG_VCEPLL_FUNC_CNTL 7524 drivers/gpu/drm/radeon/si.c 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
CG_VCEPLL_FUNC_CNTL 7533 drivers/gpu/drm/radeon/si.c 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);
CG_VCEPLL_FUNC_CNTL 7542 drivers/gpu/drm/radeon/si.c 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);
CG_VCEPLL_FUNC_CNTL 7553 drivers/gpu/drm/radeon/si.c 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
CG_VCEPLL_FUNC_CNTL 7558 drivers/gpu/drm/radeon/si.c 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);