CG_UPLL_FUNC_CNTL 1204 drivers/gpu/drm/radeon/evergreen.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
CG_UPLL_FUNC_CNTL 1208 drivers/gpu/drm/radeon/evergreen.c 		WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
CG_UPLL_FUNC_CNTL 1219 drivers/gpu/drm/radeon/evergreen.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
CG_UPLL_FUNC_CNTL 1222 drivers/gpu/drm/radeon/evergreen.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
CG_UPLL_FUNC_CNTL 1223 drivers/gpu/drm/radeon/evergreen.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
CG_UPLL_FUNC_CNTL 1226 drivers/gpu/drm/radeon/evergreen.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
CG_UPLL_FUNC_CNTL 1230 drivers/gpu/drm/radeon/evergreen.c 	r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
CG_UPLL_FUNC_CNTL 1235 drivers/gpu/drm/radeon/evergreen.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
CG_UPLL_FUNC_CNTL 1244 drivers/gpu/drm/radeon/evergreen.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
CG_UPLL_FUNC_CNTL 1260 drivers/gpu/drm/radeon/evergreen.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
CG_UPLL_FUNC_CNTL 1265 drivers/gpu/drm/radeon/evergreen.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
CG_UPLL_FUNC_CNTL 1267 drivers/gpu/drm/radeon/evergreen.c 	r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
CG_UPLL_FUNC_CNTL  214 drivers/gpu/drm/radeon/r600.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(
CG_UPLL_FUNC_CNTL  223 drivers/gpu/drm/radeon/r600.c 		WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
CG_UPLL_FUNC_CNTL  243 drivers/gpu/drm/radeon/r600.c 	r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
CG_UPLL_FUNC_CNTL  248 drivers/gpu/drm/radeon/r600.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
CG_UPLL_FUNC_CNTL  252 drivers/gpu/drm/radeon/r600.c 		WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,
CG_UPLL_FUNC_CNTL  256 drivers/gpu/drm/radeon/r600.c 	WREG32_P(CG_UPLL_FUNC_CNTL,
CG_UPLL_FUNC_CNTL  272 drivers/gpu/drm/radeon/r600.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
CG_UPLL_FUNC_CNTL  277 drivers/gpu/drm/radeon/r600.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
CG_UPLL_FUNC_CNTL  282 drivers/gpu/drm/radeon/r600.c 	r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
CG_UPLL_FUNC_CNTL   67 drivers/gpu/drm/radeon/rv770.c 		WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
CG_UPLL_FUNC_CNTL   85 drivers/gpu/drm/radeon/rv770.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
CG_UPLL_FUNC_CNTL   88 drivers/gpu/drm/radeon/rv770.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
CG_UPLL_FUNC_CNTL   91 drivers/gpu/drm/radeon/rv770.c 	r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
CG_UPLL_FUNC_CNTL   96 drivers/gpu/drm/radeon/rv770.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
CG_UPLL_FUNC_CNTL   99 drivers/gpu/drm/radeon/rv770.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
CG_UPLL_FUNC_CNTL  114 drivers/gpu/drm/radeon/rv770.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
CG_UPLL_FUNC_CNTL  119 drivers/gpu/drm/radeon/rv770.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
CG_UPLL_FUNC_CNTL  122 drivers/gpu/drm/radeon/rv770.c 	r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
CG_UPLL_FUNC_CNTL 7008 drivers/gpu/drm/radeon/si.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
CG_UPLL_FUNC_CNTL 7025 drivers/gpu/drm/radeon/si.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
CG_UPLL_FUNC_CNTL 7028 drivers/gpu/drm/radeon/si.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
CG_UPLL_FUNC_CNTL 7031 drivers/gpu/drm/radeon/si.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
CG_UPLL_FUNC_CNTL 7035 drivers/gpu/drm/radeon/si.c 	r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
CG_UPLL_FUNC_CNTL 7040 drivers/gpu/drm/radeon/si.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
CG_UPLL_FUNC_CNTL 7049 drivers/gpu/drm/radeon/si.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
CG_UPLL_FUNC_CNTL 7065 drivers/gpu/drm/radeon/si.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
CG_UPLL_FUNC_CNTL 7070 drivers/gpu/drm/radeon/si.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
CG_UPLL_FUNC_CNTL 7072 drivers/gpu/drm/radeon/si.c 	r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);