CG_THERMAL_CTRL  3765 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
CG_THERMAL_CTRL  6435 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
CG_THERMAL_CTRL  1273 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
CG_THERMAL_CTRL   334 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 			CG_THERMAL_CTRL, DIG_THERM_DPM,
CG_THERMAL_CTRL   894 drivers/gpu/drm/radeon/ci_dpm.c 	tmp = RREG32_SMC(CG_THERMAL_CTRL);
CG_THERMAL_CTRL   897 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32_SMC(CG_THERMAL_CTRL, tmp);
CG_THERMAL_CTRL  1410 drivers/gpu/drm/radeon/ci_dpm.c 		tmp = RREG32_SMC(CG_THERMAL_CTRL);
CG_THERMAL_CTRL  1413 drivers/gpu/drm/radeon/ci_dpm.c 		WREG32_SMC(CG_THERMAL_CTRL, tmp);
CG_THERMAL_CTRL  1458 drivers/gpu/drm/radeon/evergreen.c 		toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
CG_THERMAL_CTRL   756 drivers/gpu/drm/radeon/r600_dpm.c 	WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
CG_THERMAL_CTRL  1380 drivers/gpu/drm/radeon/rv6xx_dpm.c 		WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
CG_THERMAL_CTRL  1841 drivers/gpu/drm/radeon/rv770_dpm.c 		WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
CG_THERMAL_CTRL  1885 drivers/gpu/drm/radeon/rv770_dpm.c 	WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
CG_THERMAL_CTRL  3306 drivers/gpu/drm/radeon/si_dpm.c 		WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
CG_THERMAL_CTRL  6000 drivers/gpu/drm/radeon/si_dpm.c 	WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);