CG_SPLL_FUNC_CNTL_3 4034 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
CG_SPLL_FUNC_CNTL_3  331 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
CG_SPLL_FUNC_CNTL_3  335 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
CG_SPLL_FUNC_CNTL_3  893 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
CG_SPLL_FUNC_CNTL_3  897 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
CG_SPLL_FUNC_CNTL_3  832 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
CG_SPLL_FUNC_CNTL_3  836 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
CG_SPLL_FUNC_CNTL_3  575 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
CG_SPLL_FUNC_CNTL_3  579 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
CG_SPLL_FUNC_CNTL_3 1879 drivers/gpu/drm/radeon/ci_dpm.c 		RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
CG_SPLL_FUNC_CNTL_3 1187 drivers/gpu/drm/radeon/ni_dpm.c 	ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
CG_SPLL_FUNC_CNTL_3  206 drivers/gpu/drm/radeon/rv730_dpm.c 		RREG32(CG_SPLL_FUNC_CNTL_3);
CG_SPLL_FUNC_CNTL_3  293 drivers/gpu/drm/radeon/rv740_dpm.c 		RREG32(CG_SPLL_FUNC_CNTL_3);
CG_SPLL_FUNC_CNTL_3 1525 drivers/gpu/drm/radeon/rv770_dpm.c 		RREG32(CG_SPLL_FUNC_CNTL_3);
CG_SPLL_FUNC_CNTL_3 3574 drivers/gpu/drm/radeon/si_dpm.c 	si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);