CG_SPLL_FUNC_CNTL_2 4033 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); CG_SPLL_FUNC_CNTL_2 1418 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4); CG_SPLL_FUNC_CNTL_2 1351 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2, CG_SPLL_FUNC_CNTL_2 1466 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4); CG_SPLL_FUNC_CNTL_2 1214 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2, CG_SPLL_FUNC_CNTL_2 1877 drivers/gpu/drm/radeon/ci_dpm.c RREG32_SMC(CG_SPLL_FUNC_CNTL_2); CG_SPLL_FUNC_CNTL_2 1186 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); CG_SPLL_FUNC_CNTL_2 204 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(CG_SPLL_FUNC_CNTL_2); CG_SPLL_FUNC_CNTL_2 291 drivers/gpu/drm/radeon/rv740_dpm.c RREG32(CG_SPLL_FUNC_CNTL_2); CG_SPLL_FUNC_CNTL_2 1145 drivers/gpu/drm/radeon/rv770.c tmp = RREG32(CG_SPLL_FUNC_CNTL_2); CG_SPLL_FUNC_CNTL_2 1148 drivers/gpu/drm/radeon/rv770.c WREG32(CG_SPLL_FUNC_CNTL_2, tmp); CG_SPLL_FUNC_CNTL_2 1157 drivers/gpu/drm/radeon/rv770.c WREG32(CG_SPLL_FUNC_CNTL_2, tmp); CG_SPLL_FUNC_CNTL_2 1523 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(CG_SPLL_FUNC_CNTL_2); CG_SPLL_FUNC_CNTL_2 3995 drivers/gpu/drm/radeon/si.c tmp = RREG32(CG_SPLL_FUNC_CNTL_2); CG_SPLL_FUNC_CNTL_2 3997 drivers/gpu/drm/radeon/si.c WREG32(CG_SPLL_FUNC_CNTL_2, tmp); CG_SPLL_FUNC_CNTL_2 4005 drivers/gpu/drm/radeon/si.c tmp = RREG32(CG_SPLL_FUNC_CNTL_2); CG_SPLL_FUNC_CNTL_2 4007 drivers/gpu/drm/radeon/si.c WREG32(CG_SPLL_FUNC_CNTL_2, tmp); CG_SPLL_FUNC_CNTL_2 3573 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);