CG_SPLL_FUNC_CNTL 4032 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); CG_SPLL_FUNC_CNTL 325 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, CG_SPLL_FUNC_CNTL 327 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, CG_SPLL_FUNC_CNTL 1414 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); CG_SPLL_FUNC_CNTL 1416 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); CG_SPLL_FUNC_CNTL 887 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, CG_SPLL_FUNC_CNTL 889 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, CG_SPLL_FUNC_CNTL 1347 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, CG_SPLL_FUNC_CNTL 1349 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, CG_SPLL_FUNC_CNTL 826 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); CG_SPLL_FUNC_CNTL 828 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); CG_SPLL_FUNC_CNTL 1462 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); CG_SPLL_FUNC_CNTL 1464 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); CG_SPLL_FUNC_CNTL 569 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); CG_SPLL_FUNC_CNTL 571 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); CG_SPLL_FUNC_CNTL 1210 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, CG_SPLL_FUNC_CNTL 1212 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, CG_SPLL_FUNC_CNTL 1875 drivers/gpu/drm/radeon/ci_dpm.c RREG32_SMC(CG_SPLL_FUNC_CNTL); CG_SPLL_FUNC_CNTL 1185 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); CG_SPLL_FUNC_CNTL 322 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN); CG_SPLL_FUNC_CNTL 324 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN); CG_SPLL_FUNC_CNTL 332 drivers/gpu/drm/radeon/r600_dpm.c if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS) CG_SPLL_FUNC_CNTL 213 drivers/gpu/drm/radeon/rs780_dpm.c u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; CG_SPLL_FUNC_CNTL 989 drivers/gpu/drm/radeon/rs780_dpm.c u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); CG_SPLL_FUNC_CNTL 1011 drivers/gpu/drm/radeon/rs780_dpm.c u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); CG_SPLL_FUNC_CNTL 202 drivers/gpu/drm/radeon/rv730_dpm.c RREG32(CG_SPLL_FUNC_CNTL); CG_SPLL_FUNC_CNTL 289 drivers/gpu/drm/radeon/rv740_dpm.c RREG32(CG_SPLL_FUNC_CNTL); CG_SPLL_FUNC_CNTL 1521 drivers/gpu/drm/radeon/rv770_dpm.c RREG32(CG_SPLL_FUNC_CNTL); CG_SPLL_FUNC_CNTL 3991 drivers/gpu/drm/radeon/si.c tmp = RREG32(CG_SPLL_FUNC_CNTL); CG_SPLL_FUNC_CNTL 3993 drivers/gpu/drm/radeon/si.c WREG32(CG_SPLL_FUNC_CNTL, tmp); CG_SPLL_FUNC_CNTL 4022 drivers/gpu/drm/radeon/si.c tmp = RREG32(CG_SPLL_FUNC_CNTL); CG_SPLL_FUNC_CNTL 4024 drivers/gpu/drm/radeon/si.c WREG32(CG_SPLL_FUNC_CNTL, tmp); CG_SPLL_FUNC_CNTL 4026 drivers/gpu/drm/radeon/si.c tmp = RREG32(CG_SPLL_FUNC_CNTL); CG_SPLL_FUNC_CNTL 4028 drivers/gpu/drm/radeon/si.c WREG32(CG_SPLL_FUNC_CNTL, tmp); CG_SPLL_FUNC_CNTL 3572 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);