CG_SCLK_DPM_CTRL_3  539 drivers/gpu/drm/radeon/sumo_dpm.c 	cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
CG_SCLK_DPM_CTRL_3  543 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
CG_SCLK_DPM_CTRL_3  601 drivers/gpu/drm/radeon/sumo_dpm.c 	if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
CG_SCLK_DPM_CTRL_3  609 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);
CG_SCLK_DPM_CTRL_3  614 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);
CG_SCLK_DPM_CTRL_3  620 drivers/gpu/drm/radeon/sumo_dpm.c 		WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);
CG_SCLK_DPM_CTRL_3  622 drivers/gpu/drm/radeon/sumo_dpm.c 		WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);
CG_SCLK_DPM_CTRL_3  728 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);
CG_SCLK_DPM_CTRL_3  942 drivers/gpu/drm/radeon/sumo_dpm.c 	u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
CG_SCLK_DPM_CTRL_3  948 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
CG_SCLK_DPM_CTRL_3  965 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,
CG_SCLK_DPM_CTRL_3  992 drivers/gpu/drm/radeon/sumo_dpm.c 			WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);
CG_SCLK_DPM_CTRL_3  994 drivers/gpu/drm/radeon/sumo_dpm.c 			WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);