CG_FDO_CTRL2 6449 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; CG_FDO_CTRL2 6451 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; CG_FDO_CTRL2 6456 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; CG_FDO_CTRL2 6458 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 6460 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; CG_FDO_CTRL2 6462 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 6650 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; CG_FDO_CTRL2 6712 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; CG_FDO_CTRL2 6714 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 6716 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; CG_FDO_CTRL2 6718 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 6741 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; CG_FDO_CTRL2 6743 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 116 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c CG_FDO_CTRL2, FDO_PWM_MODE); CG_FDO_CTRL2 119 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c CG_FDO_CTRL2, TMIN); CG_FDO_CTRL2 124 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c CG_FDO_CTRL2, TMIN, 0); CG_FDO_CTRL2 126 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c CG_FDO_CTRL2, FDO_PWM_MODE, mode); CG_FDO_CTRL2 140 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode); CG_FDO_CTRL2 142 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c CG_FDO_CTRL2, TMIN, hwmgr->tmin); CG_FDO_CTRL2 354 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28); CG_FDO_CTRL2 135 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c CG_FDO_CTRL2, FDO_PWM_MODE); CG_FDO_CTRL2 138 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c CG_FDO_CTRL2, TMIN); CG_FDO_CTRL2 144 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c CG_FDO_CTRL2, TMIN, 0)); CG_FDO_CTRL2 147 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c CG_FDO_CTRL2, FDO_PWM_MODE, mode)); CG_FDO_CTRL2 164 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c CG_FDO_CTRL2, FDO_PWM_MODE, CG_FDO_CTRL2 168 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c CG_FDO_CTRL2, TMIN, CG_FDO_CTRL2 415 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28)); CG_FDO_CTRL2 96 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c CG_FDO_CTRL2, TMIN, 0)); CG_FDO_CTRL2 99 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c CG_FDO_CTRL2, FDO_PWM_MODE, mode)); CG_FDO_CTRL2 1414 drivers/gpu/drm/amd/powerplay/smu_v11_0.c CG_FDO_CTRL2, TMIN, 0)); CG_FDO_CTRL2 1417 drivers/gpu/drm/amd/powerplay/smu_v11_0.c CG_FDO_CTRL2, FDO_PWM_MODE, mode)); CG_FDO_CTRL2 941 drivers/gpu/drm/radeon/ci_dpm.c tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; CG_FDO_CTRL2 943 drivers/gpu/drm/radeon/ci_dpm.c tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; CG_FDO_CTRL2 948 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; CG_FDO_CTRL2 950 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 952 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; CG_FDO_CTRL2 954 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 1157 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; CG_FDO_CTRL2 1219 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; CG_FDO_CTRL2 1221 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 1223 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; CG_FDO_CTRL2 1225 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 1248 drivers/gpu/drm/radeon/ci_dpm.c tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; CG_FDO_CTRL2 1250 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 6014 drivers/gpu/drm/radeon/si_dpm.c tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; CG_FDO_CTRL2 6016 drivers/gpu/drm/radeon/si_dpm.c tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; CG_FDO_CTRL2 6021 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; CG_FDO_CTRL2 6023 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 6025 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; CG_FDO_CTRL2 6027 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 6218 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; CG_FDO_CTRL2 6280 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; CG_FDO_CTRL2 6282 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 6284 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; CG_FDO_CTRL2 6286 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); CG_FDO_CTRL2 6309 drivers/gpu/drm/radeon/si_dpm.c tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; CG_FDO_CTRL2 6311 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FDO_CTRL2, tmp);