CG_DISPLAY_GAP_CNTL 4152 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
CG_DISPLAY_GAP_CNTL 4163 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
CG_DISPLAY_GAP_CNTL 4266 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
CG_DISPLAY_GAP_CNTL 4275 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
CG_DISPLAY_GAP_CNTL  391 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
CG_DISPLAY_GAP_CNTL  394 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
CG_DISPLAY_GAP_CNTL 4073 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
CG_DISPLAY_GAP_CNTL 1987 drivers/gpu/drm/radeon/ci_dpm.c 	u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
CG_DISPLAY_GAP_CNTL 1999 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
CG_DISPLAY_GAP_CNTL 2048 drivers/gpu/drm/radeon/ci_dpm.c 	u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
CG_DISPLAY_GAP_CNTL 2054 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
CG_DISPLAY_GAP_CNTL 1731 drivers/gpu/drm/radeon/cypress_dpm.c 	u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
CG_DISPLAY_GAP_CNTL 1740 drivers/gpu/drm/radeon/cypress_dpm.c 	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
CG_DISPLAY_GAP_CNTL 1748 drivers/gpu/drm/radeon/cypress_dpm.c 	tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
CG_DISPLAY_GAP_CNTL 1759 drivers/gpu/drm/radeon/cypress_dpm.c 	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
CG_DISPLAY_GAP_CNTL  989 drivers/gpu/drm/radeon/rv6xx_dpm.c 		WREG32(CG_DISPLAY_GAP_CNTL, tmp);
CG_DISPLAY_GAP_CNTL 1182 drivers/gpu/drm/radeon/rv6xx_dpm.c 	u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
CG_DISPLAY_GAP_CNTL 1195 drivers/gpu/drm/radeon/rv6xx_dpm.c 	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
CG_DISPLAY_GAP_CNTL  879 drivers/gpu/drm/radeon/rv770_dpm.c 	u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
CG_DISPLAY_GAP_CNTL  884 drivers/gpu/drm/radeon/rv770_dpm.c 	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
CG_DISPLAY_GAP_CNTL 1343 drivers/gpu/drm/radeon/rv770_dpm.c 	u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
CG_DISPLAY_GAP_CNTL 1356 drivers/gpu/drm/radeon/rv770_dpm.c 	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
CG_DISPLAY_GAP_CNTL 3687 drivers/gpu/drm/radeon/si_dpm.c 	tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
CG_DISPLAY_GAP_CNTL 3698 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(CG_DISPLAY_GAP_CNTL, tmp);
CG_DISPLAY_GAP_CNTL 3801 drivers/gpu/drm/radeon/si_dpm.c 	u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
CG_DISPLAY_GAP_CNTL 3810 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(CG_DISPLAY_GAP_CNTL, tmp);