dml_pow 288 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / dml_pow( dml_pow 3466 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency dml_pow 3489 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency dml_pow 311 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / dml_pow( dml_pow 3498 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency dml_pow 3521 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency dml_pow 917 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); dml_pow 919 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c * dml_pow(2, 8)); dml_pow 923 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); dml_pow 933 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c + min_dst_y_ttu_vblank) * dml_pow(2, 2)); dml_pow 934 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); dml_pow 1312 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); dml_pow 1313 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); dml_pow 1344 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); dml_pow 1345 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); dml_pow 1403 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); dml_pow 1404 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); dml_pow 1405 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); dml_pow 1406 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); dml_pow 1407 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); dml_pow 1408 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); dml_pow 1410 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); dml_pow 1411 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); dml_pow 1416 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); dml_pow 1423 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c < (unsigned int) dml_pow(2, 13)); dml_pow 1429 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); dml_pow 1447 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c / (double) vratio_l * dml_pow(2, 2)); dml_pow 1448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); dml_pow 1452 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c / (double) vratio_c * dml_pow(2, 2)); dml_pow 1453 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { dml_pow 1457 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c (unsigned int) dml_pow(2, 17) - 1); dml_pow 1462 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c / (double) vratio_l * dml_pow(2, 2)); dml_pow 1463 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); dml_pow 1470 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) dml_pow 1471 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; dml_pow 1475 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) dml_pow 1476 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; dml_pow 1483 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) dml_pow 1484 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; dml_pow 1491 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) dml_pow 1492 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; dml_pow 1499 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); dml_pow 1500 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13)); dml_pow 1506 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); dml_pow 1507 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13)); dml_pow 1527 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c * dml_pow(2, 10)); dml_pow 1529 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c * dml_pow(2, 10)); dml_pow 1531 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c * dml_pow(2, 10)); dml_pow 1533 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c * dml_pow(2, 10)); dml_pow 1535 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); dml_pow 1537 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c * dml_pow(2, 10)); dml_pow 1539 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); dml_pow 1541 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c * dml_pow(2, 10)); dml_pow 1543 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); dml_pow 1557 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); dml_pow 1669 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); dml_pow 1699 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); dml_pow 917 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); dml_pow 919 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c * dml_pow(2, 8)); dml_pow 923 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); dml_pow 933 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c + min_dst_y_ttu_vblank) * dml_pow(2, 2)); dml_pow 934 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); dml_pow 1312 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); dml_pow 1313 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); dml_pow 1344 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); dml_pow 1345 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); dml_pow 1403 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); dml_pow 1404 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); dml_pow 1405 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); dml_pow 1406 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); dml_pow 1407 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); dml_pow 1408 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); dml_pow 1410 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); dml_pow 1411 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); dml_pow 1416 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); dml_pow 1423 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c < (unsigned int) dml_pow(2, 13)); dml_pow 1429 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); dml_pow 1447 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c / (double) vratio_l * dml_pow(2, 2)); dml_pow 1448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); dml_pow 1452 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c / (double) vratio_c * dml_pow(2, 2)); dml_pow 1453 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { dml_pow 1457 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c (unsigned int) dml_pow(2, 17) - 1); dml_pow 1462 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c / (double) vratio_l * dml_pow(2, 2)); dml_pow 1463 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); dml_pow 1470 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) dml_pow 1471 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; dml_pow 1475 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) dml_pow 1476 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; dml_pow 1483 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) dml_pow 1484 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; dml_pow 1491 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) dml_pow 1492 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; dml_pow 1499 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); dml_pow 1500 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13)); dml_pow 1506 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); dml_pow 1507 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13)); dml_pow 1527 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c * dml_pow(2, 10)); dml_pow 1529 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c * dml_pow(2, 10)); dml_pow 1531 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c * dml_pow(2, 10)); dml_pow 1533 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c * dml_pow(2, 10)); dml_pow 1535 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); dml_pow 1537 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c * dml_pow(2, 10)); dml_pow 1539 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); dml_pow 1541 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c * dml_pow(2, 10)); dml_pow 1543 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); dml_pow 1557 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); dml_pow 1669 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); dml_pow 1699 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); dml_pow 964 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); dml_pow 966 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c * dml_pow(2, 8)); dml_pow 970 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); dml_pow 979 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2)); dml_pow 980 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); dml_pow 1376 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); dml_pow 1377 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); dml_pow 1412 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); dml_pow 1413 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); dml_pow 1476 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); dml_pow 1477 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); dml_pow 1478 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); dml_pow 1479 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); dml_pow 1480 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); dml_pow 1481 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); dml_pow 1483 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); dml_pow 1484 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); dml_pow 1494 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13)); dml_pow 1501 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c < (unsigned int)dml_pow(2, 13)); dml_pow 1507 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); dml_pow 1530 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23)) dml_pow 1531 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; dml_pow 1533 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23)) dml_pow 1534 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; dml_pow 1536 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23)) dml_pow 1537 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; dml_pow 1539 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23)) dml_pow 1540 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; dml_pow 1542 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c / (double) vratio_l * dml_pow(2, 2)); dml_pow 1543 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); dml_pow 1547 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c / (double) vratio_c * dml_pow(2, 2)); dml_pow 1548 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { dml_pow 1553 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c (unsigned int)dml_pow(2, 17) - 1); dml_pow 1558 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c / (double) vratio_l * dml_pow(2, 2)); dml_pow 1559 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17)); dml_pow 1570 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) dml_pow 1571 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; dml_pow 1575 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) dml_pow 1576 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; dml_pow 1583 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) dml_pow 1584 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; dml_pow 1591 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) dml_pow 1592 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; dml_pow 1599 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); dml_pow 1600 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13)); dml_pow 1606 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); dml_pow 1607 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13)); dml_pow 1627 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c * dml_pow(2, 10)); dml_pow 1629 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c * dml_pow(2, 10)); dml_pow 1631 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c * dml_pow(2, 10)); dml_pow 1633 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c * dml_pow(2, 10)); dml_pow 1635 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); dml_pow 1637 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c * dml_pow(2, 10)); dml_pow 1639 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); dml_pow 1641 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c * dml_pow(2, 10)); dml_pow 1643 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); dml_pow 1646 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14)); dml_pow 1657 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); dml_pow 1783 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); dml_pow 1819 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); dml_pow 1136 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); dml_pow 1138 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c * dml_pow(2, 8)); dml_pow 1141 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); dml_pow 1158 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c + min_dst_y_ttu_vblank) * dml_pow(2, 2)); dml_pow 1159 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); dml_pow 1427 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); dml_pow 1437 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); dml_pow 1448 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); dml_pow 1452 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); dml_pow 1506 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 21) - 1; dml_pow 1508 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); dml_pow 1512 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->vratio_prefetch_c = (unsigned int) dml_pow(2, 21) - 1; dml_pow 1514 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); dml_pow 1519 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); dml_pow 1524 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13)); dml_pow 1529 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); dml_pow 1546 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c / (double) vratio_l * dml_pow(2, 2)); dml_pow 1547 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); dml_pow 1550 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c / (double) vratio_c * dml_pow(2, 2)); dml_pow 1551 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_c < (unsigned int) dml_pow(2, 17)); dml_pow 1554 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c / (double) vratio_l * dml_pow(2, 2)); dml_pow 1555 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); dml_pow 1562 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) dml_pow 1563 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; dml_pow 1568 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) dml_pow 1569 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; dml_pow 1574 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) dml_pow 1575 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; dml_pow 1681 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); dml_pow 1682 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13)); dml_pow 1720 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); dml_pow 1721 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13)); dml_pow 1763 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c * dml_pow(2, 10)); dml_pow 1765 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c * dml_pow(2, 10)); dml_pow 1767 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); dml_pow 1768 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); dml_pow 1800 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10)); dml_pow 1802 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c * dml_pow(2, 10)); dml_pow 1804 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); dml_pow 1805 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); dml_pow 1852 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); dml_pow 1853 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(refcyc_per_req_delivery_pre_cur0 < dml_pow(2, 13)); dml_pow 1887 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10)); dml_pow 1888 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(refcyc_per_req_delivery_cur0 < dml_pow(2, 13)); dml_pow 1896 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); dml_pow 1899 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14)); dml_pow 1910 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));