dmcu              264 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h 	struct dmcu_firmware_header_v1_0 dmcu;
dmcu              931 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
dmcu              950 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		ret = dmcu_load_iram(dmcu, params);
dmcu              237 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
dmcu              265 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
dmcu              266 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 		dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
dmcu               76 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
dmcu              114 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
dmcu              116 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 				dmcu->funcs->set_psr_wait_loop(dmcu,
dmcu              130 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
dmcu              156 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
dmcu              158 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 				dmcu->funcs->set_psr_wait_loop(dmcu,
dmcu               92 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
dmcu              104 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
dmcu              106 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 				dmcu->funcs->set_psr_wait_loop(dmcu,
dmcu              197 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
dmcu              312 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
dmcu              314 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		dmcu->funcs->set_psr_wait_loop(dmcu,
dmcu               67 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
dmcu              127 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 			dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
dmcu              129 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		dmcu->funcs->set_psr_wait_loop(dmcu,
dmcu               86 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
dmcu               99 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
dmcu              101 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 				dmcu->funcs->set_psr_wait_loop(dmcu,
dmcu              811 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->res_pool->dmcu != NULL)
dmcu              812 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
dmcu             2384 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct dmcu *dmcu = dc->res_pool->dmcu;
dmcu             2386 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dmcu)
dmcu             2387 drivers/gpu/drm/amd/display/dc/core/dc.c 		return dmcu->funcs->is_dmcu_initialized(dmcu);
dmcu             2323 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
dmcu             2329 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	if ((dmcu == NULL) ||
dmcu             2334 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
dmcu             2388 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
dmcu             2390 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_enabled)
dmcu             2391 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		dmcu->funcs->set_psr_enable(dmcu, enable, wait);
dmcu               73 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
dmcu              100 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	if (dmcu != NULL && dmcu->funcs->lock_phy)
dmcu              101 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		dmcu->funcs->lock_phy(dmcu);
dmcu              115 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	if (dmcu != NULL && dmcu->funcs->unlock_phy)
dmcu              116 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		dmcu->funcs->unlock_phy(dmcu);
dmcu              178 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
dmcu              187 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		if (dmcu != NULL && dmcu->funcs->lock_phy)
dmcu              188 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 			dmcu->funcs->lock_phy(dmcu);
dmcu              192 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		if (dmcu != NULL && dmcu->funcs->unlock_phy)
dmcu              193 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 			dmcu->funcs->unlock_phy(dmcu);
dmcu              254 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
dmcu              282 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
dmcu              283 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
dmcu              294 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
dmcu              330 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
dmcu              332 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 				dmcu->funcs->set_psr_wait_loop(dmcu,
dmcu               37 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c #define TO_DCE_DMCU(dmcu)\
dmcu               38 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	container_of(dmcu, struct dce_dmcu, base)
dmcu               62 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static bool dce_dmcu_init(struct dmcu *dmcu)
dmcu               68 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c bool dce_dmcu_load_iram(struct dmcu *dmcu,
dmcu               73 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu               96 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
dmcu               98 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              119 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
dmcu              121 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              145 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			dce_get_dmcu_psr_state(dmcu, &psr_state);
dmcu              158 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static bool dce_dmcu_setup_psr(struct dmcu *dmcu,
dmcu              162 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              240 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
dmcu              252 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
dmcu              257 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
dmcu              270 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static bool dce_is_dmcu_initialized(struct dmcu *dmcu)
dmcu              272 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              286 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dmcu *dmcu,
dmcu              289 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              292 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (dmcu->cached_wait_loop_number == wait_loop_number)
dmcu              296 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (!dce_is_dmcu_initialized(dmcu))
dmcu              304 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu->cached_wait_loop_number = wait_loop_number;
dmcu              305 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
dmcu              315 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
dmcu              317 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	*psr_wait_loop_number = dmcu->cached_wait_loop_number;
dmcu              322 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static void dcn10_get_dmcu_version(struct dmcu *dmcu)
dmcu              324 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              336 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);
dmcu              337 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA);
dmcu              338 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA);
dmcu              339 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
dmcu              348 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu,
dmcu              351 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              370 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static bool dcn10_dmcu_init(struct dmcu *dmcu)
dmcu              372 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              373 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	const struct dc_config *config = &dmcu->ctx->dc->config;
dmcu              381 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
dmcu              383 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	switch (dmcu->dmcu_state) {
dmcu              408 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
dmcu              411 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		if (dmcu->dmcu_state == DMCU_RUNNING) {
dmcu              413 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			dcn10_get_dmcu_version(dmcu);
dmcu              416 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			dcn10_dmcu_enable_fractional_pwm(dmcu,
dmcu              436 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
dmcu              441 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              445 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (dmcu->dmcu_state != DMCU_RUNNING)
dmcu              481 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
dmcu              483 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              488 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (dmcu->dmcu_state != DMCU_RUNNING)
dmcu              508 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
dmcu              510 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              518 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (dmcu->dmcu_state != DMCU_RUNNING)
dmcu              521 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dcn10_get_dmcu_psr_state(dmcu, &psr_state);
dmcu              546 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			dcn10_get_dmcu_psr_state(dmcu, &psr_state);
dmcu              563 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,
dmcu              567 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              577 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (dmcu->dmcu_state != DMCU_RUNNING)
dmcu              653 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
dmcu              665 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
dmcu              670 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
dmcu              688 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dmcu *dmcu,
dmcu              691 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              695 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (dmcu->dmcu_state != DMCU_RUNNING)
dmcu              704 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu->cached_wait_loop_number = wait_loop_number;
dmcu              705 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
dmcu              716 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
dmcu              718 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	*psr_wait_loop_number = dmcu->cached_wait_loop_number;
dmcu              722 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)
dmcu              725 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (dmcu->dmcu_state != DMCU_RUNNING)
dmcu              734 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static bool dcn20_lock_phy(struct dmcu *dmcu)
dmcu              736 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              739 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (dmcu->dmcu_state != DMCU_RUNNING)
dmcu              757 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static bool dcn20_unlock_phy(struct dmcu *dmcu)
dmcu              759 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu              762 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (dmcu->dmcu_state != DMCU_RUNNING)
dmcu              828 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dmcu *base = &dmcu_dce->base;
dmcu              839 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c struct dmcu *dce_dmcu_create(
dmcu              861 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c struct dmcu *dcn10_dmcu_create(
dmcu              884 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c struct dmcu *dcn20_dmcu_create(
dmcu              906 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c void dce_dmcu_destroy(struct dmcu **dmcu)
dmcu              908 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
dmcu              911 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		dmcu_dce->base.funcs->set_psr_enable(*dmcu, false, true);
dmcu              914 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	*dmcu = NULL;
dmcu              181 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	struct dmcu base;
dmcu              252 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h struct dmcu *dce_dmcu_create(
dmcu              258 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h struct dmcu *dcn10_dmcu_create(
dmcu              265 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h struct dmcu *dcn20_dmcu_create(
dmcu              272 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h void dce_dmcu_destroy(struct dmcu **dmcu);
dmcu              741 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	if (pool->base.dmcu != NULL)
dmcu              742 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 			dce_dmcu_destroy(&pool->base.dmcu);
dmcu              961 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	pool->base.dmcu = dce_dmcu_create(ctx,
dmcu              965 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	if (pool->base.dmcu == NULL) {
dmcu             2372 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dmcu *dmcu;
dmcu             2425 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dmcu = dc->res_pool->dmcu;
dmcu             2426 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dmcu != NULL && abm != NULL)
dmcu             2427 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
dmcu              800 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	if (pool->base.dmcu != NULL)
dmcu              801 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		dce_dmcu_destroy(&pool->base.dmcu);
dmcu             1333 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pool->base.dmcu = dce_dmcu_create(ctx,
dmcu             1337 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	if (pool->base.dmcu == NULL) {
dmcu              762 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	if (pool->base.dmcu != NULL)
dmcu              763 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dce_dmcu_destroy(&pool->base.dmcu);
dmcu             1217 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	pool->base.dmcu = dce_dmcu_create(ctx,
dmcu             1221 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	if (pool->base.dmcu == NULL) {
dmcu              612 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	if (pool->base.dmcu != NULL)
dmcu              613 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 		dce_dmcu_destroy(&pool->base.dmcu);
dmcu             1055 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	pool->base.dmcu = dce_dmcu_create(ctx,
dmcu             1059 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	if (pool->base.dmcu == NULL) {
dmcu              782 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	if (pool->base.dmcu != NULL)
dmcu              783 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 			dce_dmcu_destroy(&pool->base.dmcu);
dmcu              942 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	pool->base.dmcu = dce_dmcu_create(ctx,
dmcu              946 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	if (pool->base.dmcu == NULL) {
dmcu             1139 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	pool->base.dmcu = dce_dmcu_create(ctx,
dmcu             1143 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	if (pool->base.dmcu == NULL) {
dmcu             1332 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	pool->base.dmcu = dce_dmcu_create(ctx,
dmcu             1336 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	if (pool->base.dmcu == NULL) {
dmcu             1179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dmcu *dmcu = dc->res_pool->dmcu;
dmcu             1284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dmcu != NULL)
dmcu             1285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dmcu->funcs->dmcu_init(dmcu);
dmcu             1287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (abm != NULL && dmcu != NULL)
dmcu             1288 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
dmcu              964 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (pool->base.dmcu != NULL)
dmcu              965 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dce_dmcu_destroy(&pool->base.dmcu);
dmcu             1362 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	pool->base.dmcu = dcn10_dmcu_create(ctx,
dmcu             1366 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (pool->base.dmcu == NULL) {
dmcu             1404 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (pool->base.dmcu != NULL)
dmcu             1405 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		dce_dmcu_destroy(&pool->base.dmcu);
dmcu             3539 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	pool->base.dmcu = dcn20_dmcu_create(ctx,
dmcu             3543 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (pool->base.dmcu == NULL) {
dmcu              932 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	if (pool->base.dmcu != NULL)
dmcu              933 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		dce_dmcu_destroy(&pool->base.dmcu);
dmcu              226 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dmcu *dmcu;
dmcu               58 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h 	bool (*dmcu_init)(struct dmcu *dmcu);
dmcu               59 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h 	bool (*load_iram)(struct dmcu *dmcu,
dmcu               63 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h 	void (*set_psr_enable)(struct dmcu *dmcu, bool enable, bool wait);
dmcu               64 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h 	bool (*setup_psr)(struct dmcu *dmcu,
dmcu               67 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h 	void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state);
dmcu               68 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h 	void (*set_psr_wait_loop)(struct dmcu *dmcu,
dmcu               70 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h 	void (*get_psr_wait_loop)(struct dmcu *dmcu,
dmcu               72 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h 	bool (*is_dmcu_initialized)(struct dmcu *dmcu);
dmcu               73 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h 	bool (*lock_phy)(struct dmcu *dmcu);
dmcu               74 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h 	bool (*unlock_phy)(struct dmcu *dmcu);
dmcu              651 drivers/gpu/drm/amd/display/modules/power/power_helpers.c bool dmcu_load_iram(struct dmcu *dmcu,
dmcu              657 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 	if (dmcu == NULL)
dmcu              660 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 	if (!dmcu->funcs->is_dmcu_initialized(dmcu))
dmcu              665 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 	if (dmcu->dmcu_version.abm_version == 0x23) {
dmcu              668 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 		result = dmcu->funcs->load_iram(
dmcu              669 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 				dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
dmcu              670 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 	} else if (dmcu->dmcu_version.abm_version == 0x22) {
dmcu              673 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 		result = dmcu->funcs->load_iram(
dmcu              674 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 				dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
dmcu              678 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 		result = dmcu->funcs->load_iram(
dmcu              679 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 				dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2);
dmcu              682 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 			result = dmcu->funcs->load_iram(
dmcu              683 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 					dmcu, IRAM_RESERVE_AREA_END_V2 + 1,
dmcu               45 drivers/gpu/drm/amd/display/modules/power/power_helpers.h bool dmcu_load_iram(struct dmcu *dmcu,