CGU_SYS            22 arch/mips/lantiq/xway/clk.c #define DDR_HZ ram_clocks[ltq_cgu_r32(CGU_SYS) & 0x3]
CGU_SYS            35 arch/mips/lantiq/xway/clk.c 	if (ltq_cgu_r32(CGU_SYS) & 0x40)
CGU_SYS            42 arch/mips/lantiq/xway/clk.c 	switch (ltq_cgu_r32(CGU_SYS) & 0xc) {
CGU_SYS            56 arch/mips/lantiq/xway/clk.c 	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;
CGU_SYS            79 arch/mips/lantiq/xway/clk.c 	if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
CGU_SYS            88 arch/mips/lantiq/xway/clk.c 	if (ltq_cgu_r32(CGU_SYS) & BIT(0))
CGU_SYS            96 arch/mips/lantiq/xway/clk.c 	if (ltq_cgu_r32(CGU_SYS) & BIT(2))
CGU_SYS           177 arch/mips/lantiq/xway/clk.c 	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
CGU_SYS           249 arch/mips/lantiq/xway/clk.c 	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
CGU_SYS           333 arch/mips/lantiq/xway/clk.c 	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
CGU_SYS           483 arch/mips/lantiq/xway/sysctrl.c 		if (ltq_cgu_r32(CGU_SYS) & (1 << 5))