dm_write_reg_soc15  261 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_GSL_WINDOW, tg110->offsets.crtc, 0);
dm_write_reg_soc15  424 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	dm_write_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset, value);
dm_write_reg_soc15  518 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	dm_write_reg_soc15(
dm_write_reg_soc15  528 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	dm_write_reg_soc15(
dm_write_reg_soc15  696 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	dm_write_reg_soc15(tg->ctx,
dm_write_reg_soc15  718 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	dm_write_reg_soc15(
dm_write_reg_soc15  785 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL,
dm_write_reg_soc15  941 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, 0);
dm_write_reg_soc15  980 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 			dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);
dm_write_reg_soc15  993 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);
dm_write_reg_soc15 1067 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, 0);
dm_write_reg_soc15 1070 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, 0);
dm_write_reg_soc15 1082 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc,  value);
dm_write_reg_soc15 1083 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);
dm_write_reg_soc15 1084 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, value);
dm_write_reg_soc15 1141 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC_CNTL,