dm_read_reg_soc15  620 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);
dm_read_reg_soc15  629 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);
dm_read_reg_soc15  975 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
dm_read_reg_soc15   90 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	uint32_t value = dm_read_reg_soc15(
dm_read_reg_soc15  173 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	uint32_t value = dm_read_reg_soc15(
dm_read_reg_soc15  189 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	uint32_t value = dm_read_reg_soc15(
dm_read_reg_soc15  200 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	value = dm_read_reg_soc15(
dm_read_reg_soc15  251 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 							dm_read_reg_soc15(tg->ctx,
dm_read_reg_soc15  312 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	uint32_t pol_value = dm_read_reg_soc15(
dm_read_reg_soc15  374 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	uint32_t value = dm_read_reg_soc15(
dm_read_reg_soc15  416 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	value = dm_read_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset);
dm_read_reg_soc15  513 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	value = dm_read_reg_soc15(
dm_read_reg_soc15  608 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	value = dm_read_reg_soc15(
dm_read_reg_soc15  623 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	value = dm_read_reg_soc15(
dm_read_reg_soc15  645 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	uint32_t v_blank_start_end = dm_read_reg_soc15(
dm_read_reg_soc15  673 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	uint32_t value = dm_read_reg_soc15(
dm_read_reg_soc15  714 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	value = dm_read_reg_soc15(
dm_read_reg_soc15  755 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	uint32_t value = dm_read_reg_soc15(
dm_read_reg_soc15 1123 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CONTROL,
dm_read_reg_soc15 1183 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC_CNTL,
dm_read_reg_soc15 1191 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC0_DATA_RG,
dm_read_reg_soc15 1196 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC0_DATA_B,
dm_read_reg_soc15 1265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);