dm_pp_clocks_state  223 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c static enum dm_pp_clocks_state pp_to_dc_powerlevel_state(
dm_pp_clocks_state  194 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c enum dm_pp_clocks_state dce_get_required_clocks_state(
dm_pp_clocks_state  200 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	enum dm_pp_clocks_state low_req_clk;
dm_pp_clocks_state  288 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 		enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
dm_pp_clocks_state   35 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h enum dm_pp_clocks_state dce_get_required_clocks_state(
dm_pp_clocks_state  213 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c static enum dm_pp_clocks_state dce_get_required_clocks_state(
dm_pp_clocks_state  219 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	enum dm_pp_clocks_state low_req_clk;
dm_pp_clocks_state  363 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
dm_pp_clocks_state   62 drivers/gpu/drm/amd/display/dc/dm_services_types.h 	enum dm_pp_clocks_state clock_state;
dm_pp_clocks_state  249 drivers/gpu/drm/amd/display/dc/dm_services_types.h 	enum dm_pp_clocks_state power_level;
dm_pp_clocks_state  262 drivers/gpu/drm/amd/display/dc/dm_services_types.h 	enum dm_pp_clocks_state max_clocks_state;
dm_pp_clocks_state  260 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h 	enum dm_pp_clocks_state max_clks_state;
dm_pp_clocks_state  261 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h 	enum dm_pp_clocks_state cur_min_clks_state;