dividers          649 drivers/clk/ti/clk-44xx.c 	.dividers = omap4_trace_clk_div_div_ck_divs,
dividers          382 drivers/clk/ti/clkctrl.c 	if (ti_clk_parse_divider_data((int *)div_data->dividers, 0,
dividers          126 drivers/clk/ti/clock.h 	int *dividers;
dividers          168 drivers/clk/ti/clock.h 	const int *dividers;
dividers         1000 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 				       struct atom_clock_dividers *dividers)
dividers         1007 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 	memset(dividers, 0, sizeof(struct atom_clock_dividers));
dividers         1023 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->post_div = args.v3.ucPostDiv;
dividers         1024 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->enable_post_div = (args.v3.ucCntlFlag &
dividers         1026 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->enable_dithen = (args.v3.ucCntlFlag &
dividers         1028 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
dividers         1029 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
dividers         1030 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->ref_div = args.v3.ucRefDiv;
dividers         1031 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->vco_mode = (args.v3.ucCntlFlag &
dividers         1043 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->post_div = args.v5.ucPostDiv;
dividers         1044 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->enable_post_div = (args.v5.ucCntlFlag &
dividers         1046 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->enable_dithen = (args.v5.ucCntlFlag &
dividers         1048 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
dividers         1049 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
dividers         1050 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->ref_div = args.v5.ucRefDiv;
dividers         1051 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 			dividers->vco_mode = (args.v5.ucCntlFlag &
dividers         1061 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 		dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
dividers         1062 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 		dividers->real_clock = le32_to_cpu(args.v4.ulClock);
dividers         1072 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 		dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
dividers         1073 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 		dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
dividers         1074 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 		dividers->ref_div = args.v6_out.ucPllRefDiv;
dividers         1075 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 		dividers->post_div = args.v6_out.ucPllPostDiv;
dividers         1076 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 		dividers->flags = args.v6_out.ucPllCntlFlag;
dividers         1077 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 		dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
dividers         1078 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 		dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
dividers          161 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h 				       struct atom_clock_dividers *dividers);
dividers          214 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h 				       struct atom_clock_dividers *dividers);
dividers         1309 drivers/gpu/drm/amd/amdgpu/cik.c 	struct atom_clock_dividers dividers;
dividers         1314 drivers/gpu/drm/amd/amdgpu/cik.c 					       clock, false, &dividers);
dividers         1321 drivers/gpu/drm/amd/amdgpu/cik.c 	tmp |= dividers.post_divider;
dividers         1350 drivers/gpu/drm/amd/amdgpu/cik.c 	struct atom_clock_dividers dividers;
dividers         1355 drivers/gpu/drm/amd/amdgpu/cik.c 					       ecclk, false, &dividers);
dividers         1370 drivers/gpu/drm/amd/amdgpu/cik.c 	tmp |= dividers.post_divider;
dividers          665 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	struct atom_clock_dividers dividers;
dividers          669 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 						 sclk, false, &dividers);
dividers          673 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
dividers          906 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	struct atom_clock_dividers dividers;
dividers          929 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 							 table->entries[i].vclk, false, &dividers);
dividers          932 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
dividers          935 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 							 table->entries[i].dclk, false, &dividers);
dividers          938 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
dividers          979 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	struct atom_clock_dividers dividers;
dividers          997 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 							 table->entries[i].evclk, false, &dividers);
dividers         1000 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		pi->vce_level[i].Divider = (u8)dividers.post_div;
dividers         1040 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	struct atom_clock_dividers dividers;
dividers         1060 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 							 table->entries[i].clk, false, &dividers);
dividers         1063 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		pi->samu_level[i].Divider = (u8)dividers.post_div;
dividers         1106 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	struct atom_clock_dividers dividers;
dividers         1119 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 							 table->entries[i].clk, false, &dividers);
dividers         1122 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		pi->acp_level[i].Divider = (u8)dividers.post_div;
dividers         5250 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	struct atom_clock_dividers dividers;
dividers         5264 drivers/gpu/drm/amd/amdgpu/si_dpm.c 					     engine_clock, false, &dividers);
dividers         5268 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	reference_divider = 1 + dividers.ref_div;
dividers         5270 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
dividers         5275 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
dividers         5276 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
dividers         5287 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		u32 vco_freq = engine_clock * dividers.post_div;
dividers         7311 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	struct atom_clock_dividers dividers;
dividers         7374 drivers/gpu/drm/amd/amdgpu/si_dpm.c 					     0, false, &dividers);
dividers         7376 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		pi->ref_div = dividers.ref_div + 1;
dividers          729 drivers/gpu/drm/amd/amdgpu/vi.c 	struct atom_clock_dividers dividers;
dividers          734 drivers/gpu/drm/amd/amdgpu/vi.c 					       clock, false, &dividers);
dividers          745 drivers/gpu/drm/amd/amdgpu/vi.c 	tmp |= dividers.post_divider;
dividers          799 drivers/gpu/drm/amd/amdgpu/vi.c 	struct atom_clock_dividers dividers;
dividers          820 drivers/gpu/drm/amd/amdgpu/vi.c 					       ecclk, false, &dividers);
dividers          835 drivers/gpu/drm/amd/amdgpu/vi.c 	tmp |= dividers.post_divider;
dividers         1075 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 		struct dividers dividers)
dividers         1111 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider1);
dividers         1113 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider1);
dividers         1115 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider1);
dividers         1120 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider2);
dividers         1122 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider2);
dividers         1124 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider2);
dividers         1129 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider3);
dividers         1131 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider3);
dividers         1133 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider3);
dividers         1138 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 		struct dividers dividers)
dividers         1206 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 		struct dividers dividers)
dividers         1240 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider1);
dividers         1242 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider1);
dividers         1244 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider1);
dividers         1249 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider2);
dividers         1251 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider2);
dividers         1253 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider2);
dividers         1258 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider3);
dividers         1260 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider3);
dividers         1262 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			dividers.divider3);
dividers         1349 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	struct dividers dividers)
dividers         1372 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	p->r = dc_fixpt_div(p_last->r, dividers.divider1);
dividers         1373 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	p->g = dc_fixpt_div(p_last->g, dividers.divider1);
dividers         1374 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	p->b = dc_fixpt_div(p_last->b, dividers.divider1);
dividers         1378 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	p->r = dc_fixpt_div(p_last->r, dividers.divider2);
dividers         1379 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	p->g = dc_fixpt_div(p_last->g, dividers.divider2);
dividers         1380 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	p->b = dc_fixpt_div(p_last->b, dividers.divider2);
dividers         1384 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	p->r = dc_fixpt_div(p_last->r, dividers.divider3);
dividers         1385 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	p->g = dc_fixpt_div(p_last->g, dividers.divider3);
dividers         1386 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	p->b = dc_fixpt_div(p_last->b, dividers.divider3);
dividers         1643 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	struct dividers dividers;
dividers         1680 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 		dividers.divider1 = dc_fixpt_from_fraction(3, 2);
dividers         1681 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 		dividers.divider2 = dc_fixpt_from_int(2);
dividers         1682 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 		dividers.divider3 = dc_fixpt_from_fraction(5, 2);
dividers         1687 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 				dividers);
dividers         1690 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			scale_gamma(rgb_user, ramp, dividers);
dividers         1692 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 			scale_gamma_dx(rgb_user, ramp, dividers);
dividers         1814 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	struct dividers dividers;
dividers         1837 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	dividers.divider1 = dc_fixpt_from_fraction(3, 2);
dividers         1838 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	dividers.divider2 = dc_fixpt_from_int(2);
dividers         1839 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	dividers.divider3 = dc_fixpt_from_fraction(5, 2);
dividers         1841 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	scale_user_regamma_ramp(rgb_user, &regamma->ramp, dividers);
dividers         1874 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 	struct dividers dividers;
dividers         1909 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 		dividers.divider1 = dc_fixpt_from_fraction(3, 2);
dividers         1910 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 		dividers.divider2 = dc_fixpt_from_int(2);
dividers         1911 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 		dividers.divider3 = dc_fixpt_from_fraction(5, 2);
dividers         1916 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 				dividers);
dividers         1918 drivers/gpu/drm/amd/display/modules/color/color_gamma.c 		scale_gamma(rgb_user, ramp, dividers);
dividers          350 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 					  pp_atomctrl_clock_dividers_kong *dividers)
dividers          363 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->pll_post_divider = pll_parameters.ucPostDiv;
dividers          364 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->real_clock = le32_to_cpu(pll_parameters.ulClock);
dividers          373 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		pp_atomctrl_clock_dividers_vi *dividers)
dividers          387 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->pll_post_divider =
dividers          389 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->real_clock =
dividers          392 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->ul_fb_div.ul_fb_div_frac =
dividers          394 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->ul_fb_div.ul_fb_div =
dividers          397 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->uc_pll_ref_div =
dividers          399 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->uc_pll_post_div =
dividers          401 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->uc_pll_cntl_flag =
dividers          410 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		pp_atomctrl_clock_dividers_ai *dividers)
dividers          424 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->usSclk_fcw_frac     = le16_to_cpu(pll_patameters.usSclk_fcw_frac);
dividers          425 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->usSclk_fcw_int      = le16_to_cpu(pll_patameters.usSclk_fcw_int);
dividers          426 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->ucSclkPostDiv       = pll_patameters.ucSclkPostDiv;
dividers          427 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->ucSclkVcoMode       = pll_patameters.ucSclkVcoMode;
dividers          428 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->ucSclkPllRange      = pll_patameters.ucSclkPllRange;
dividers          429 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->ucSscEnable         = pll_patameters.ucSscEnable;
dividers          430 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->usSsc_fcw1_frac     = le16_to_cpu(pll_patameters.usSsc_fcw1_frac);
dividers          431 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->usSsc_fcw1_int      = le16_to_cpu(pll_patameters.usSsc_fcw1_int);
dividers          432 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->usPcc_fcw_int       = le16_to_cpu(pll_patameters.usPcc_fcw_int);
dividers          433 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->usSsc_fcw_slew_frac = le16_to_cpu(pll_patameters.usSsc_fcw_slew_frac);
dividers          434 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->usPcc_fcw_slew_frac = le16_to_cpu(pll_patameters.usPcc_fcw_slew_frac);
dividers          442 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		pp_atomctrl_clock_dividers_vi *dividers)
dividers          457 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->pll_post_divider =
dividers          459 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->real_clock =
dividers          462 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->ul_fb_div.ul_fb_div_frac =
dividers          464 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->ul_fb_div.ul_fb_div =
dividers          467 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->uc_pll_ref_div =
dividers          469 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->uc_pll_post_div =
dividers          471 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->uc_pll_cntl_flag =
dividers          300 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
dividers          301 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
dividers          310 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h 						 pp_atomctrl_clock_dividers_kong *dividers);
dividers          315 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
dividers          248 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 		struct pp_atomfwctrl_clock_dividers_soc15 *dividers)
dividers          266 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz);
dividers          267 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	dividers->ulDid = le32_to_cpu(pll_output->dfs_did);
dividers          268 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult);
dividers          269 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult);
dividers          270 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac);
dividers          271 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	dividers->ucPll_ss_enable = pll_output->pll_ss_enable;
dividers          220 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h 		struct pp_atomfwctrl_clock_dividers_soc15 *dividers);
dividers          439 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	pp_atomctrl_clock_dividers_kong dividers;
dividers          484 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 						      &dividers);
dividers          487 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			(uint8_t)dividers.pll_post_divider;
dividers          501 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 						      &dividers);
dividers          504 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			(uint8_t)dividers.pll_post_divider;
dividers          515 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 						      &dividers);
dividers          518 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			(uint8_t)dividers.pll_post_divider;
dividers          527 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 						      &dividers);
dividers          530 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			(uint8_t)dividers.pll_post_divider;
dividers          541 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 						      &dividers);
dividers          544 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			(uint8_t)dividers.pll_post_divider;
dividers         1489 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
dividers         1494 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			lclock, &dividers),
dividers         1498 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	*curr_lclk_did = dividers.ulDid;
dividers         1557 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
dividers         1586 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			gfx_clock, &dividers),
dividers         1592 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			cpu_to_le32(dividers.ulPll_fb_mult);
dividers         1594 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
dividers         1596 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			cpu_to_le32(dividers.ulPll_ss_fbsmult);
dividers         1598 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			cpu_to_le16(dividers.usPll_ss_slew_frac);
dividers         1599 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
dividers         1622 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
dividers         1646 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			soc_clock, &dividers),
dividers         1650 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	*current_soc_did = (uint8_t)dividers.ulDid;
dividers         1758 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
dividers         1786 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),
dividers         1794 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);
dividers         1795 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	current_memclk_level->Did = (uint8_t)(dividers.ulDid);
dividers         1929 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
dividers         1934 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			eclock, &dividers),
dividers         1938 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	*current_eclk_did = (uint8_t)dividers.ulDid;
dividers         1982 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
dividers         1986 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			vclock, &dividers),
dividers         1990 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	*current_vclk_did = (uint8_t)dividers.ulDid;
dividers         1998 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
dividers         2002 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			dclock, &dividers),
dividers         2006 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	*current_dclk_did = (uint8_t)dividers.ulDid;
dividers          299 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers          311 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);
dividers          319 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	ref_divider = 1 + dividers.uc_pll_ref_div;
dividers          322 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
dividers          326 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			SPLL_REF_DIV, dividers.uc_pll_ref_div);
dividers          328 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			SPLL_PDIV_A,  dividers.uc_pll_post_div);
dividers          341 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		uint32_t vco_freq = clock * dividers.uc_pll_post_div;
dividers          364 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
dividers         1380 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1403 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->ACPILevel.SclkFrequency,  &dividers);
dividers         1409 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
dividers         1521 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1537 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				table->UvdLevel[count].VclkFrequency, &dividers);
dividers         1541 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
dividers         1544 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				table->UvdLevel[count].DclkFrequency, &dividers);
dividers         1548 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
dividers         1562 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1576 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				table->VceLevel[count].Frequency, &dividers);
dividers         1581 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
dividers         1594 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1607 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				table->AcpLevel[count].Frequency, &dividers);
dividers         1611 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
dividers          861 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers          873 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);
dividers          881 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	ref_divider = 1 + dividers.uc_pll_ref_div;
dividers          884 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
dividers          888 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			SPLL_REF_DIV, dividers.uc_pll_ref_div);
dividers          890 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			SPLL_PDIV_A,  dividers.uc_pll_post_div);
dividers          904 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		uint32_t vco_freq = clock * dividers.uc_pll_post_div;
dividers          933 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
dividers         1307 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1338 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			table->ACPILevel.SclkFrequency,  &dividers);
dividers         1343 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
dividers         1427 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1448 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				table->VceLevel[count].Frequency, &dividers);
dividers         1453 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
dividers         1466 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1485 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				table->AcpLevel[count].Frequency, &dividers);
dividers         1489 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
dividers         1563 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1584 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				table->UvdLevel[count].VclkFrequency, &dividers);
dividers         1588 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
dividers         1591 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				table->UvdLevel[count].DclkFrequency, &dividers);
dividers         1595 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
dividers          799 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	pp_atomctrl_clock_dividers_vi dividers;
dividers          811 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
dividers          819 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	reference_divider = 1 + dividers.uc_pll_ref_div;
dividers          822 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
dividers          826 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
dividers          828 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		CG_SPLL_FUNC_CNTL, SPLL_PDIV_A,  dividers.uc_pll_post_div);
dividers          842 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
dividers          868 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
dividers         1427 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1451 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		table->ACPILevel.SclkFrequency,  &dividers);
dividers         1457 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
dividers          846 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct pp_atomctrl_clock_dividers_ai dividers;
dividers          855 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
dividers          857 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
dividers          858 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
dividers          859 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
dividers          860 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		sclk_setting->PllRange = dividers.ucSclkPllRange;
dividers          862 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
dividers          864 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		sclk_setting->SSc_En = dividers.ucSscEnable;
dividers          865 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
dividers          866 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
dividers          867 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
dividers         1291 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1323 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				table->VceLevel[count].Frequency, &dividers);
dividers         1328 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
dividers         1397 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1428 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				table->UvdLevel[count].VclkFrequency, &dividers);
dividers         1432 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
dividers         1435 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				table->UvdLevel[count].DclkFrequency, &dividers);
dividers         1439 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
dividers         1831 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	pp_atomctrl_clock_dividers_vi dividers;
dividers         1989 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], &dividers);
dividers         1993 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
dividers         1995 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
dividers          542 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	pp_atomctrl_clock_dividers_vi dividers;
dividers          554 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
dividers          562 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	reference_divider = 1 + dividers.uc_pll_ref_div;
dividers          565 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
dividers          569 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
dividers          571 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		CG_SPLL_FUNC_CNTL, SPLL_PDIV_A,  dividers.uc_pll_post_div);
dividers          585 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
dividers          611 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
dividers         1180 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1199 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->ACPILevel.SclkFrequency,  &dividers);
dividers         1206 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
dividers         1313 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	pp_atomctrl_clock_dividers_vi dividers;
dividers         1342 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 					&dividers);
dividers         1348 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
dividers         1351 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 							  table->UvdLevel[count].DclkFrequency, &dividers);
dividers         1357 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 					(uint8_t)dividers.pll_post_divider;
dividers         1373 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	pp_atomctrl_clock_dividers_vi dividers;
dividers         1400 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 					table->VceLevel[count].Frequency, &dividers);
dividers         1405 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
dividers         1418 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	pp_atomctrl_clock_dividers_vi dividers;
dividers         1445 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			table->AcpLevel[count].Frequency, &dividers);
dividers         1449 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
dividers          721 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct pp_atomctrl_clock_dividers_ai dividers;
dividers          730 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
dividers          732 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
dividers          733 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
dividers          734 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
dividers          735 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		sclk_setting->PllRange = dividers.ucSclkPllRange;
dividers          737 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
dividers          739 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		sclk_setting->SSc_En = dividers.ucSscEnable;
dividers          740 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
dividers          741 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
dividers          742 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
dividers         1208 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1240 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				table->VceLevel[count].Frequency, &dividers);
dividers         1245 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
dividers         1321 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct pp_atomctrl_clock_dividers_vi dividers;
dividers         1352 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				table->UvdLevel[count].VclkFrequency, &dividers);
dividers         1356 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
dividers         1359 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				table->UvdLevel[count].DclkFrequency, &dividers);
dividers         1363 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
dividers         1936 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	pp_atomctrl_clock_dividers_vi dividers;
dividers         2111 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				smu_data->bif_sclk_table[i], &dividers);
dividers         2118 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 					PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
dividers         2121 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 					PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
dividers         1305 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	} dividers[] = {
dividers         1315 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
dividers         1317 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 			for (i = 0; i < dividers[d].n_dividers; i++) {
dividers         1318 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 				unsigned int p = dividers[d].list[i];
dividers         2281 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	static const int dividers[] = {  2,  4,  6,  8, 10, 12,  14,  16,
dividers         2291 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
dividers         2292 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		dco = afe_clock * dividers[d];
dividers         2299 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 				best_div = dividers[d];
dividers         2557 drivers/gpu/drm/radeon/btc_dpm.c 	struct atom_clock_dividers dividers;
dividers         2609 drivers/gpu/drm/radeon/btc_dpm.c 					     0, false, &dividers);
dividers         2611 drivers/gpu/drm/radeon/btc_dpm.c 		pi->ref_div = dividers.ref_div + 1;
dividers         2652 drivers/gpu/drm/radeon/ci_dpm.c 	struct atom_clock_dividers dividers;
dividers         2669 drivers/gpu/drm/radeon/ci_dpm.c 						     table->UvdLevel[count].VclkFrequency, false, &dividers);
dividers         2673 drivers/gpu/drm/radeon/ci_dpm.c 		table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
dividers         2677 drivers/gpu/drm/radeon/ci_dpm.c 						     table->UvdLevel[count].DclkFrequency, false, &dividers);
dividers         2681 drivers/gpu/drm/radeon/ci_dpm.c 		table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
dividers         2695 drivers/gpu/drm/radeon/ci_dpm.c 	struct atom_clock_dividers dividers;
dividers         2710 drivers/gpu/drm/radeon/ci_dpm.c 						     table->VceLevel[count].Frequency, false, &dividers);
dividers         2714 drivers/gpu/drm/radeon/ci_dpm.c 		table->VceLevel[count].Divider = (u8)dividers.post_divider;
dividers         2728 drivers/gpu/drm/radeon/ci_dpm.c 	struct atom_clock_dividers dividers;
dividers         2743 drivers/gpu/drm/radeon/ci_dpm.c 						     table->AcpLevel[count].Frequency, false, &dividers);
dividers         2747 drivers/gpu/drm/radeon/ci_dpm.c 		table->AcpLevel[count].Divider = (u8)dividers.post_divider;
dividers         2760 drivers/gpu/drm/radeon/ci_dpm.c 	struct atom_clock_dividers dividers;
dividers         2775 drivers/gpu/drm/radeon/ci_dpm.c 						     table->SamuLevel[count].Frequency, false, &dividers);
dividers         2779 drivers/gpu/drm/radeon/ci_dpm.c 		table->SamuLevel[count].Divider = (u8)dividers.post_divider;
dividers         2993 drivers/gpu/drm/radeon/ci_dpm.c 	struct atom_clock_dividers dividers;
dividers         3014 drivers/gpu/drm/radeon/ci_dpm.c 					     table->ACPILevel.SclkFrequency, false, &dividers);
dividers         3018 drivers/gpu/drm/radeon/ci_dpm.c 	table->ACPILevel.SclkDid = (u8)dividers.post_divider;
dividers         3164 drivers/gpu/drm/radeon/ci_dpm.c 	struct atom_clock_dividers dividers;
dividers         3176 drivers/gpu/drm/radeon/ci_dpm.c 					     engine_clock, false, &dividers);
dividers         3180 drivers/gpu/drm/radeon/ci_dpm.c 	reference_divider = 1 + dividers.ref_div;
dividers         3181 drivers/gpu/drm/radeon/ci_dpm.c 	fbdiv = dividers.fb_div & 0x3FFFFFF;
dividers         3189 drivers/gpu/drm/radeon/ci_dpm.c 		u32 vco_freq = engine_clock * dividers.post_div;
dividers         3210 drivers/gpu/drm/radeon/ci_dpm.c 	sclk->SclkDid = (u8)dividers.post_divider;
dividers         9432 drivers/gpu/drm/radeon/cik.c 	struct atom_clock_dividers dividers;
dividers         9436 drivers/gpu/drm/radeon/cik.c 					   clock, false, &dividers);
dividers         9442 drivers/gpu/drm/radeon/cik.c 	tmp |= dividers.post_divider;
dividers         9471 drivers/gpu/drm/radeon/cik.c 	struct atom_clock_dividers dividers;
dividers         9475 drivers/gpu/drm/radeon/cik.c 					   ecclk, false, &dividers);
dividers         9489 drivers/gpu/drm/radeon/cik.c 	tmp |= dividers.post_divider;
dividers          495 drivers/gpu/drm/radeon/cypress_dpm.c 	struct atom_clock_dividers dividers;
dividers          502 drivers/gpu/drm/radeon/cypress_dpm.c 					     memory_clock, strobe_mode, &dividers);
dividers          510 drivers/gpu/drm/radeon/cypress_dpm.c 			dividers.post_div = 1;
dividers          513 drivers/gpu/drm/radeon/cypress_dpm.c 	ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
dividers          520 drivers/gpu/drm/radeon/cypress_dpm.c 	mpll_ad_func_cntl |= CLKR(dividers.ref_div);
dividers          521 drivers/gpu/drm/radeon/cypress_dpm.c 	mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
dividers          522 drivers/gpu/drm/radeon/cypress_dpm.c 	mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
dividers          523 drivers/gpu/drm/radeon/cypress_dpm.c 	mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
dividers          526 drivers/gpu/drm/radeon/cypress_dpm.c 	if (dividers.vco_mode)
dividers          537 drivers/gpu/drm/radeon/cypress_dpm.c 		mpll_dq_func_cntl |= CLKR(dividers.ref_div);
dividers          538 drivers/gpu/drm/radeon/cypress_dpm.c 		mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
dividers          539 drivers/gpu/drm/radeon/cypress_dpm.c 		mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
dividers          540 drivers/gpu/drm/radeon/cypress_dpm.c 		mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
dividers          548 drivers/gpu/drm/radeon/cypress_dpm.c 		if (dividers.vco_mode)
dividers          556 drivers/gpu/drm/radeon/cypress_dpm.c 		u32 vco_freq = memory_clock * dividers.post_div;
dividers          561 drivers/gpu/drm/radeon/cypress_dpm.c 			u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
dividers          564 drivers/gpu/drm/radeon/cypress_dpm.c 				(0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
dividers         2026 drivers/gpu/drm/radeon/cypress_dpm.c 	struct atom_clock_dividers dividers;
dividers         2057 drivers/gpu/drm/radeon/cypress_dpm.c 					     0, false, &dividers);
dividers         2059 drivers/gpu/drm/radeon/cypress_dpm.c 		pi->ref_div = dividers.ref_div + 1;
dividers         1149 drivers/gpu/drm/radeon/evergreen.c 	struct atom_clock_dividers dividers;
dividers         1152 drivers/gpu/drm/radeon/evergreen.c 					   clock, false, &dividers);
dividers         1156 drivers/gpu/drm/radeon/evergreen.c 	WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK));
dividers          539 drivers/gpu/drm/radeon/kv_dpm.c 	struct atom_clock_dividers dividers;
dividers          543 drivers/gpu/drm/radeon/kv_dpm.c 					     sclk, false, &dividers);
dividers          547 drivers/gpu/drm/radeon/kv_dpm.c 	pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
dividers          824 drivers/gpu/drm/radeon/kv_dpm.c 	struct atom_clock_dividers dividers;
dividers          847 drivers/gpu/drm/radeon/kv_dpm.c 						     table->entries[i].vclk, false, &dividers);
dividers          850 drivers/gpu/drm/radeon/kv_dpm.c 		pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
dividers          853 drivers/gpu/drm/radeon/kv_dpm.c 						     table->entries[i].dclk, false, &dividers);
dividers          856 drivers/gpu/drm/radeon/kv_dpm.c 		pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
dividers          897 drivers/gpu/drm/radeon/kv_dpm.c 	struct atom_clock_dividers dividers;
dividers          915 drivers/gpu/drm/radeon/kv_dpm.c 						     table->entries[i].evclk, false, &dividers);
dividers          918 drivers/gpu/drm/radeon/kv_dpm.c 		pi->vce_level[i].Divider = (u8)dividers.post_div;
dividers          958 drivers/gpu/drm/radeon/kv_dpm.c 	struct atom_clock_dividers dividers;
dividers          978 drivers/gpu/drm/radeon/kv_dpm.c 						     table->entries[i].clk, false, &dividers);
dividers          981 drivers/gpu/drm/radeon/kv_dpm.c 		pi->samu_level[i].Divider = (u8)dividers.post_div;
dividers         1024 drivers/gpu/drm/radeon/kv_dpm.c 	struct atom_clock_dividers dividers;
dividers         1037 drivers/gpu/drm/radeon/kv_dpm.c 						     table->entries[i].clk, false, &dividers);
dividers         1040 drivers/gpu/drm/radeon/kv_dpm.c 		pi->acp_level[i].Divider = (u8)dividers.post_div;
dividers         2724 drivers/gpu/drm/radeon/ni.c 	struct atom_clock_dividers dividers;
dividers         2728 drivers/gpu/drm/radeon/ni.c 					   ecclk, false, &dividers);
dividers         2740 drivers/gpu/drm/radeon/ni.c 	WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK));
dividers         2004 drivers/gpu/drm/radeon/ni_dpm.c 	struct atom_clock_dividers dividers;
dividers         2018 drivers/gpu/drm/radeon/ni_dpm.c 					     engine_clock, false, &dividers);
dividers         2022 drivers/gpu/drm/radeon/ni_dpm.c 	reference_divider = 1 + dividers.ref_div;
dividers         2025 drivers/gpu/drm/radeon/ni_dpm.c 	tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
dividers         2030 drivers/gpu/drm/radeon/ni_dpm.c 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
dividers         2031 drivers/gpu/drm/radeon/ni_dpm.c 	spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
dividers         2042 drivers/gpu/drm/radeon/ni_dpm.c 		u32 vco_freq = engine_clock * dividers.post_div;
dividers         2177 drivers/gpu/drm/radeon/ni_dpm.c 	struct atom_clock_dividers dividers;
dividers         2184 drivers/gpu/drm/radeon/ni_dpm.c 					     memory_clock, strobe_mode, &dividers);
dividers         2192 drivers/gpu/drm/radeon/ni_dpm.c 			dividers.post_div = 1;
dividers         2195 drivers/gpu/drm/radeon/ni_dpm.c 	ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
dividers         2202 drivers/gpu/drm/radeon/ni_dpm.c 	mpll_ad_func_cntl |= CLKR(dividers.ref_div);
dividers         2203 drivers/gpu/drm/radeon/ni_dpm.c 	mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
dividers         2204 drivers/gpu/drm/radeon/ni_dpm.c 	mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
dividers         2205 drivers/gpu/drm/radeon/ni_dpm.c 	mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
dividers         2208 drivers/gpu/drm/radeon/ni_dpm.c 	if (dividers.vco_mode)
dividers         2219 drivers/gpu/drm/radeon/ni_dpm.c 		mpll_dq_func_cntl |= CLKR(dividers.ref_div);
dividers         2220 drivers/gpu/drm/radeon/ni_dpm.c 		mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
dividers         2221 drivers/gpu/drm/radeon/ni_dpm.c 		mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
dividers         2222 drivers/gpu/drm/radeon/ni_dpm.c 		mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
dividers         2230 drivers/gpu/drm/radeon/ni_dpm.c 		if (dividers.vco_mode)
dividers         2238 drivers/gpu/drm/radeon/ni_dpm.c 		u32 vco_freq = memory_clock * dividers.post_div;
dividers         2243 drivers/gpu/drm/radeon/ni_dpm.c 			u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
dividers         2246 drivers/gpu/drm/radeon/ni_dpm.c 				(0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
dividers         4051 drivers/gpu/drm/radeon/ni_dpm.c 	struct atom_clock_dividers dividers;
dividers         4106 drivers/gpu/drm/radeon/ni_dpm.c 					     0, false, &dividers);
dividers         4108 drivers/gpu/drm/radeon/ni_dpm.c 		pi->ref_div = dividers.ref_div + 1;
dividers          294 drivers/gpu/drm/radeon/radeon.h 				   struct atom_clock_dividers *dividers);
dividers         2841 drivers/gpu/drm/radeon/radeon_atombios.c 				   struct atom_clock_dividers *dividers)
dividers         2848 drivers/gpu/drm/radeon/radeon_atombios.c 	memset(dividers, 0, sizeof(struct atom_clock_dividers));
dividers         2861 drivers/gpu/drm/radeon/radeon_atombios.c 		dividers->post_div = args.v1.ucPostDiv;
dividers         2862 drivers/gpu/drm/radeon/radeon_atombios.c 		dividers->fb_div = args.v1.ucFbDiv;
dividers         2863 drivers/gpu/drm/radeon/radeon_atombios.c 		dividers->enable_post_div = true;
dividers         2875 drivers/gpu/drm/radeon/radeon_atombios.c 			dividers->post_div = args.v2.ucPostDiv;
dividers         2876 drivers/gpu/drm/radeon/radeon_atombios.c 			dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
dividers         2877 drivers/gpu/drm/radeon/radeon_atombios.c 			dividers->ref_div = args.v2.ucAction;
dividers         2879 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
dividers         2881 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
dividers         2883 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
dividers         2890 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->post_div = args.v3.ucPostDiv;
dividers         2891 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->enable_post_div = (args.v3.ucCntlFlag &
dividers         2893 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->enable_dithen = (args.v3.ucCntlFlag &
dividers         2895 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
dividers         2896 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
dividers         2897 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->ref_div = args.v3.ucRefDiv;
dividers         2898 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->vco_mode = (args.v3.ucCntlFlag &
dividers         2910 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->post_div = args.v5.ucPostDiv;
dividers         2911 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->enable_post_div = (args.v5.ucCntlFlag &
dividers         2913 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->enable_dithen = (args.v5.ucCntlFlag &
dividers         2915 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
dividers         2916 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
dividers         2917 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->ref_div = args.v5.ucRefDiv;
dividers         2918 drivers/gpu/drm/radeon/radeon_atombios.c 				dividers->vco_mode = (args.v5.ucCntlFlag &
dividers         2929 drivers/gpu/drm/radeon/radeon_atombios.c 		dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
dividers         2930 drivers/gpu/drm/radeon/radeon_atombios.c 		dividers->real_clock = le32_to_cpu(args.v4.ulClock);
dividers         2940 drivers/gpu/drm/radeon/radeon_atombios.c 		dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
dividers         2941 drivers/gpu/drm/radeon/radeon_atombios.c 		dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
dividers         2942 drivers/gpu/drm/radeon/radeon_atombios.c 		dividers->ref_div = args.v6_out.ucPllRefDiv;
dividers         2943 drivers/gpu/drm/radeon/radeon_atombios.c 		dividers->post_div = args.v6_out.ucPllPostDiv;
dividers         2944 drivers/gpu/drm/radeon/radeon_atombios.c 		dividers->flags = args.v6_out.ucPllCntlFlag;
dividers         2945 drivers/gpu/drm/radeon/radeon_atombios.c 		dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
dividers         2946 drivers/gpu/drm/radeon/radeon_atombios.c 		dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
dividers           79 drivers/gpu/drm/radeon/rs780_dpm.c 	struct atom_clock_dividers dividers;
dividers           84 drivers/gpu/drm/radeon/rs780_dpm.c 					     default_state->sclk_low, false, &dividers);
dividers           88 drivers/gpu/drm/radeon/rs780_dpm.c 	r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
dividers           89 drivers/gpu/drm/radeon/rs780_dpm.c 	r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
dividers           90 drivers/gpu/drm/radeon/rs780_dpm.c 	r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
dividers           92 drivers/gpu/drm/radeon/rs780_dpm.c 	if (dividers.enable_post_div)
dividers         1035 drivers/gpu/drm/radeon/rs780_dpm.c 	struct atom_clock_dividers dividers;
dividers         1046 drivers/gpu/drm/radeon/rs780_dpm.c 						     ps->sclk_high, false, &dividers);
dividers         1050 drivers/gpu/drm/radeon/rs780_dpm.c 		rs780_force_fbdiv(rdev, dividers.fb_div);
dividers         1053 drivers/gpu/drm/radeon/rs780_dpm.c 						     ps->sclk_low, false, &dividers);
dividers         1057 drivers/gpu/drm/radeon/rs780_dpm.c 		rs780_force_fbdiv(rdev, dividers.fb_div);
dividers          142 drivers/gpu/drm/radeon/rv6xx_dpm.c 	struct atom_clock_dividers dividers;
dividers          145 drivers/gpu/drm/radeon/rv6xx_dpm.c 					     clock, false, &dividers);
dividers          149 drivers/gpu/drm/radeon/rv6xx_dpm.c 	if (dividers.enable_post_div)
dividers          150 drivers/gpu/drm/radeon/rv6xx_dpm.c 		step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4);
dividers          526 drivers/gpu/drm/radeon/rv6xx_dpm.c 						struct atom_clock_dividers *dividers,
dividers          529 drivers/gpu/drm/radeon/rv6xx_dpm.c 	return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) /
dividers          530 drivers/gpu/drm/radeon/rv6xx_dpm.c 		(dividers->ref_div + 1);
dividers          553 drivers/gpu/drm/radeon/rv6xx_dpm.c 	struct atom_clock_dividers dividers;
dividers          560 drivers/gpu/drm/radeon/rv6xx_dpm.c 		if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers) == 0) {
dividers          561 drivers/gpu/drm/radeon/rv6xx_dpm.c 			vco_freq = rv6xx_calculate_vco_frequency(ref_clk, &dividers,
dividers          567 drivers/gpu/drm/radeon/rv6xx_dpm.c 									      (ref_clk / (dividers.ref_div + 1)),
dividers          573 drivers/gpu/drm/radeon/rv6xx_dpm.c 									      (ref_clk / (dividers.ref_div + 1)));
dividers          600 drivers/gpu/drm/radeon/rv6xx_dpm.c 	struct atom_clock_dividers dividers;
dividers          602 drivers/gpu/drm/radeon/rv6xx_dpm.c 	if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, &dividers))
dividers          606 drivers/gpu/drm/radeon/rv6xx_dpm.c 	rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div);
dividers          607 drivers/gpu/drm/radeon/rv6xx_dpm.c 	rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div);
dividers          608 drivers/gpu/drm/radeon/rv6xx_dpm.c 	rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div);
dividers          610 drivers/gpu/drm/radeon/rv6xx_dpm.c 	if (dividers.enable_post_div)
dividers          633 drivers/gpu/drm/radeon/rv6xx_dpm.c 						     struct atom_clock_dividers *dividers,
dividers          646 drivers/gpu/drm/radeon/rv6xx_dpm.c 			*dividers = req_dividers;
dividers          656 drivers/gpu/drm/radeon/rv6xx_dpm.c 	struct atom_clock_dividers dividers;
dividers          666 drivers/gpu/drm/radeon/rv6xx_dpm.c 							 &dividers,
dividers          672 drivers/gpu/drm/radeon/rv6xx_dpm.c 							 &dividers,
dividers          678 drivers/gpu/drm/radeon/rv6xx_dpm.c 							 &dividers,
dividers          685 drivers/gpu/drm/radeon/rv6xx_dpm.c 									     (ref_clk / (dividers.ref_div + 1)),
dividers          691 drivers/gpu/drm/radeon/rv6xx_dpm.c 									     (ref_clk / (dividers.ref_div + 1)));
dividers         1935 drivers/gpu/drm/radeon/rv6xx_dpm.c 	struct atom_clock_dividers dividers;
dividers         1958 drivers/gpu/drm/radeon/rv6xx_dpm.c 					     0, false, &dividers);
dividers         1960 drivers/gpu/drm/radeon/rv6xx_dpm.c 		pi->spll_ref_div = dividers.ref_div + 1;
dividers         1965 drivers/gpu/drm/radeon/rv6xx_dpm.c 					     0, false, &dividers);
dividers         1967 drivers/gpu/drm/radeon/rv6xx_dpm.c 		pi->mpll_ref_div = dividers.ref_div + 1;
dividers           44 drivers/gpu/drm/radeon/rv730_dpm.c 	struct atom_clock_dividers dividers;
dividers           57 drivers/gpu/drm/radeon/rv730_dpm.c 					     engine_clock, false, &dividers);
dividers           61 drivers/gpu/drm/radeon/rv730_dpm.c 	reference_divider = 1 + dividers.ref_div;
dividers           63 drivers/gpu/drm/radeon/rv730_dpm.c 	if (dividers.enable_post_div)
dividers           64 drivers/gpu/drm/radeon/rv730_dpm.c 		post_divider = ((dividers.post_div >> 4) & 0xf) +
dividers           65 drivers/gpu/drm/radeon/rv730_dpm.c 			(dividers.post_div & 0xf) + 2;
dividers           74 drivers/gpu/drm/radeon/rv730_dpm.c 	if (dividers.enable_post_div)
dividers           79 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
dividers           80 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
dividers           81 drivers/gpu/drm/radeon/rv730_dpm.c 	spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);
dividers          130 drivers/gpu/drm/radeon/rv730_dpm.c 	struct atom_clock_dividers dividers;
dividers          135 drivers/gpu/drm/radeon/rv730_dpm.c 					     memory_clock, false, &dividers);
dividers          139 drivers/gpu/drm/radeon/rv730_dpm.c 	reference_divider = dividers.ref_div + 1;
dividers          141 drivers/gpu/drm/radeon/rv730_dpm.c 	if (dividers.enable_post_div)
dividers          142 drivers/gpu/drm/radeon/rv730_dpm.c 		post_divider = ((dividers.post_div >> 4) & 0xf) +
dividers          143 drivers/gpu/drm/radeon/rv730_dpm.c 			(dividers.post_div & 0xf) + 2;
dividers          148 drivers/gpu/drm/radeon/rv730_dpm.c 	if (dividers.enable_post_div)
dividers          154 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div);
dividers          155 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf);
dividers          156 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf);
dividers          159 drivers/gpu/drm/radeon/rv730_dpm.c 	mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div);
dividers          160 drivers/gpu/drm/radeon/rv730_dpm.c 	if (dividers.enable_dithen)
dividers          173 drivers/gpu/drm/radeon/rv730_dpm.c 			u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000);
dividers          124 drivers/gpu/drm/radeon/rv740_dpm.c 	struct atom_clock_dividers dividers;
dividers          137 drivers/gpu/drm/radeon/rv740_dpm.c 					     engine_clock, false, &dividers);
dividers          141 drivers/gpu/drm/radeon/rv740_dpm.c 	reference_divider = 1 + dividers.ref_div;
dividers          143 drivers/gpu/drm/radeon/rv740_dpm.c 	tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
dividers          148 drivers/gpu/drm/radeon/rv740_dpm.c 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
dividers          149 drivers/gpu/drm/radeon/rv740_dpm.c 	spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
dividers          160 drivers/gpu/drm/radeon/rv740_dpm.c 		u32 vco_freq = engine_clock * dividers.post_div;
dividers          199 drivers/gpu/drm/radeon/rv740_dpm.c 	struct atom_clock_dividers dividers;
dividers          205 drivers/gpu/drm/radeon/rv740_dpm.c 					     memory_clock, false, &dividers);
dividers          209 drivers/gpu/drm/radeon/rv740_dpm.c 	ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
dividers          216 drivers/gpu/drm/radeon/rv740_dpm.c 	mpll_ad_func_cntl |= CLKR(dividers.ref_div);
dividers          217 drivers/gpu/drm/radeon/rv740_dpm.c 	mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
dividers          218 drivers/gpu/drm/radeon/rv740_dpm.c 	mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
dividers          219 drivers/gpu/drm/radeon/rv740_dpm.c 	mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
dividers          222 drivers/gpu/drm/radeon/rv740_dpm.c 	if (dividers.vco_mode)
dividers          233 drivers/gpu/drm/radeon/rv740_dpm.c 		mpll_dq_func_cntl |= CLKR(dividers.ref_div);
dividers          234 drivers/gpu/drm/radeon/rv740_dpm.c 		mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
dividers          235 drivers/gpu/drm/radeon/rv740_dpm.c 		mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
dividers          236 drivers/gpu/drm/radeon/rv740_dpm.c 		mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
dividers          239 drivers/gpu/drm/radeon/rv740_dpm.c 		if (dividers.vco_mode)
dividers          247 drivers/gpu/drm/radeon/rv740_dpm.c 		u32 vco_freq = memory_clock * dividers.post_div;
dividers          252 drivers/gpu/drm/radeon/rv740_dpm.c 			u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
dividers          255 drivers/gpu/drm/radeon/rv740_dpm.c 				(dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000);
dividers          320 drivers/gpu/drm/radeon/rv770_dpm.c 							     struct atom_clock_dividers *dividers,
dividers          332 drivers/gpu/drm/radeon/rv770_dpm.c 	post_divider = dividers->post_div;
dividers          333 drivers/gpu/drm/radeon/rv770_dpm.c 	reference_divider = dividers->ref_div;
dividers          402 drivers/gpu/drm/radeon/rv770_dpm.c 	struct atom_clock_dividers dividers;
dividers          410 drivers/gpu/drm/radeon/rv770_dpm.c 					     memory_clock, false, &dividers);
dividers          414 drivers/gpu/drm/radeon/rv770_dpm.c 	if ((dividers.ref_div < 1) || (dividers.ref_div > 5))
dividers          419 drivers/gpu/drm/radeon/rv770_dpm.c 							 &dividers, &clkf, &clkfrac);
dividers          421 drivers/gpu/drm/radeon/rv770_dpm.c 	ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk);
dividers          432 drivers/gpu/drm/radeon/rv770_dpm.c 	mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);
dividers          438 drivers/gpu/drm/radeon/rv770_dpm.c 	if (dividers.vco_mode)
dividers          447 drivers/gpu/drm/radeon/rv770_dpm.c 								 &dividers, &clkf, &clkfrac);
dividers          451 drivers/gpu/drm/radeon/rv770_dpm.c 		ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk);
dividers          460 drivers/gpu/drm/radeon/rv770_dpm.c 		mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);
dividers          466 drivers/gpu/drm/radeon/rv770_dpm.c 		if (dividers.vco_mode)
dividers          488 drivers/gpu/drm/radeon/rv770_dpm.c 	struct atom_clock_dividers dividers;
dividers          506 drivers/gpu/drm/radeon/rv770_dpm.c 					     engine_clock, false, &dividers);
dividers          510 drivers/gpu/drm/radeon/rv770_dpm.c 	reference_divider = 1 + dividers.ref_div;
dividers          512 drivers/gpu/drm/radeon/rv770_dpm.c 	if (dividers.enable_post_div)
dividers          513 drivers/gpu/drm/radeon/rv770_dpm.c 		post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2;
dividers          521 drivers/gpu/drm/radeon/rv770_dpm.c 	if (dividers.enable_post_div)
dividers          526 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
dividers          527 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
dividers          528 drivers/gpu/drm/radeon/rv770_dpm.c 	spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);
dividers         2346 drivers/gpu/drm/radeon/rv770_dpm.c 	struct atom_clock_dividers dividers;
dividers         2374 drivers/gpu/drm/radeon/rv770_dpm.c 					     0, false, &dividers);
dividers         2376 drivers/gpu/drm/radeon/rv770_dpm.c 		pi->ref_div = dividers.ref_div + 1;
dividers         4788 drivers/gpu/drm/radeon/si_dpm.c 	struct atom_clock_dividers dividers;
dividers         4802 drivers/gpu/drm/radeon/si_dpm.c 					     engine_clock, false, &dividers);
dividers         4806 drivers/gpu/drm/radeon/si_dpm.c 	reference_divider = 1 + dividers.ref_div;
dividers         4808 drivers/gpu/drm/radeon/si_dpm.c 	tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
dividers         4813 drivers/gpu/drm/radeon/si_dpm.c 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
dividers         4814 drivers/gpu/drm/radeon/si_dpm.c 	spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
dividers         4825 drivers/gpu/drm/radeon/si_dpm.c 		u32 vco_freq = engine_clock * dividers.post_div;
dividers         6906 drivers/gpu/drm/radeon/si_dpm.c 	struct atom_clock_dividers dividers;
dividers         6984 drivers/gpu/drm/radeon/si_dpm.c 					     0, false, &dividers);
dividers         6986 drivers/gpu/drm/radeon/si_dpm.c 		pi->ref_div = dividers.ref_div + 1;
dividers          551 drivers/gpu/drm/radeon/sumo_dpm.c 	struct atom_clock_dividers dividers;
dividers          555 drivers/gpu/drm/radeon/sumo_dpm.c 					     pl->sclk, false, &dividers);
dividers          559 drivers/gpu/drm/radeon/sumo_dpm.c 	sumo_set_divider_value(rdev, index, dividers.post_div);
dividers          786 drivers/gpu/drm/radeon/sumo_dpm.c 	struct atom_clock_dividers dividers;
dividers          791 drivers/gpu/drm/radeon/sumo_dpm.c 					     false, &dividers);
dividers          795 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);
dividers          368 drivers/gpu/drm/radeon/trinity_dpm.c 	struct atom_clock_dividers dividers;
dividers          375 drivers/gpu/drm/radeon/trinity_dpm.c 					     25000, false, &dividers);
dividers          383 drivers/gpu/drm/radeon/trinity_dpm.c 	value |= PDS_DIV(dividers.post_div);
dividers          587 drivers/gpu/drm/radeon/trinity_dpm.c 	struct atom_clock_dividers  dividers;
dividers          593 drivers/gpu/drm/radeon/trinity_dpm.c 					     sclk, false, &dividers);
dividers          599 drivers/gpu/drm/radeon/trinity_dpm.c 	value |= CLK_DIVIDER(dividers.post_div);
dividers          603 drivers/gpu/drm/radeon/trinity_dpm.c 					     sclk/2, false, &dividers);
dividers          609 drivers/gpu/drm/radeon/trinity_dpm.c 	value |= PD_SCLK_DIVIDER(dividers.post_div);
dividers          245 sound/soc/sunxi/sun4i-i2s.c 	const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers;
dividers          250 sound/soc/sunxi/sun4i-i2s.c 		const struct sun4i_i2s_clk_div *bdiv = &dividers[i];
dividers          263 sound/soc/sunxi/sun4i-i2s.c 	const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers;
dividers          268 sound/soc/sunxi/sun4i-i2s.c 		const struct sun4i_i2s_clk_div *mdiv = &dividers[i];