div_reg           489 drivers/clk/bcm/clk-bcm2835.c 	u32 div_reg;
div_reg           997 drivers/clk/bcm/clk-bcm2835.c 	div = cprman_read(cprman, data->div_reg);
div_reg          1083 drivers/clk/bcm/clk-bcm2835.c 	cprman_write(cprman, data->div_reg, div);
div_reg          1874 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_OTPDIV,
div_reg          1886 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_TIMERDIV,
div_reg          1897 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_TSENSDIV,
div_reg          1904 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_TECDIV,
div_reg          1913 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_H264DIV,
div_reg          1921 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_ISPDIV,
div_reg          1934 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_SDCDIV,
div_reg          1942 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_V3DDIV,
div_reg          1956 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_VPUDIV,
div_reg          1968 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_AVEODIV,
div_reg          1976 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_CAM0DIV,
div_reg          1984 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_CAM1DIV,
div_reg          1992 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_DFTDIV,
div_reg          1999 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_DPIDIV,
div_reg          2009 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_EMMCDIV,
div_reg          2019 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_EMMC2DIV,
div_reg          2029 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_GP0DIV,
div_reg          2038 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_GP1DIV,
div_reg          2048 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_GP2DIV,
div_reg          2058 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_HSMDIV,
div_reg          2066 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_PCMDIV,
div_reg          2076 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_PWMDIV,
div_reg          2085 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_SLIMDIV,
div_reg          2094 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_SMIDIV,
div_reg          2102 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_UARTDIV,
div_reg          2112 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_VECDIV,
div_reg          2127 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_DSI0EDIV,
div_reg          2135 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_DSI1EDIV,
div_reg          2143 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_DSI0PDIV,
div_reg          2151 drivers/clk/bcm/clk-bcm2835.c 		.div_reg = CM_DSI1PDIV,
div_reg            22 drivers/clk/clk-vt8500.c 	void __iomem	*div_reg;
div_reg           118 drivers/clk/clk-vt8500.c 	u32 div = readl(cdev->div_reg) & cdev->div_mask;
div_reg           189 drivers/clk/clk-vt8500.c 	writel(divisor, cdev->div_reg);
div_reg           225 drivers/clk/clk-vt8500.c 	u32 en_reg, div_reg;
div_reg           255 drivers/clk/clk-vt8500.c 	rc = of_property_read_u32(node, "divisor-reg", &div_reg);
div_reg           257 drivers/clk/clk-vt8500.c 		dev_clk->div_reg = pmc_base + div_reg;
div_reg           226 drivers/clk/hisilicon/clk-hi3620.c 	u32			div_reg;
div_reg           242 drivers/clk/hisilicon/clk-hi3620.c 	void __iomem	*div_reg;
div_reg           372 drivers/clk/hisilicon/clk-hi3620.c 	val = readl_relaxed(mclk->div_reg);
div_reg           374 drivers/clk/hisilicon/clk-hi3620.c 	writel_relaxed(val, mclk->div_reg);
div_reg           432 drivers/clk/hisilicon/clk-hi3620.c 	mclk->div_reg = base + mmc_clk->div_reg;
div_reg           370 drivers/clk/ingenic/cgu.c 	u32 div_reg, div;
div_reg           375 drivers/clk/ingenic/cgu.c 		div_reg = readl(cgu->base + clk_info->div.reg);
div_reg           376 drivers/clk/ingenic/cgu.c 		div = (div_reg >> clk_info->div.shift) &
div_reg           471 drivers/clk/mediatek/clk-mt8516.c 		.div_reg = _reg,				\
div_reg           276 drivers/clk/mediatek/clk-mtk.c 			mcd->flags, base +  mcd->div_reg, mcd->div_shift,
div_reg           183 drivers/clk/mediatek/clk-mtk.h 	u32 div_reg;
div_reg           194 drivers/clk/mediatek/clk-mtk.h 		.div_reg = _reg,				\
div_reg            69 drivers/clk/samsung/clk-cpu.c static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
div_reg            74 drivers/clk/samsung/clk-cpu.c 		if (!(readl(div_reg) & mask))
div_reg            78 drivers/clk/samsung/clk-cpu.c 	if (!(readl(div_reg) & mask))
div_reg            29 drivers/clk/socfpga/clk-gate-a10.c 	else if (socfpgaclk->div_reg) {
div_reg            30 drivers/clk/socfpga/clk-gate-a10.c 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
div_reg            98 drivers/clk/socfpga/clk-gate-a10.c 	u32 div_reg[3];
div_reg           130 drivers/clk/socfpga/clk-gate-a10.c 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
div_reg           132 drivers/clk/socfpga/clk-gate-a10.c 		socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0];
div_reg           133 drivers/clk/socfpga/clk-gate-a10.c 		socfpga_clk->shift = div_reg[1];
div_reg           134 drivers/clk/socfpga/clk-gate-a10.c 		socfpga_clk->width = div_reg[2];
div_reg           136 drivers/clk/socfpga/clk-gate-a10.c 		socfpga_clk->div_reg = NULL;
div_reg            22 drivers/clk/socfpga/clk-gate-s10.c 	} else if (socfpgaclk->div_reg) {
div_reg            23 drivers/clk/socfpga/clk-gate-s10.c 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
div_reg            36 drivers/clk/socfpga/clk-gate-s10.c 	val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
div_reg            72 drivers/clk/socfpga/clk-gate-s10.c 			      unsigned long gate_idx, unsigned long div_reg,
div_reg            93 drivers/clk/socfpga/clk-gate-s10.c 	if (div_reg)
div_reg            94 drivers/clk/socfpga/clk-gate-s10.c 		socfpga_clk->div_reg = regbase + div_reg;
div_reg            96 drivers/clk/socfpga/clk-gate-s10.c 		socfpga_clk->div_reg = NULL;
div_reg            98 drivers/clk/socfpga/clk-gate.c 	else if (socfpgaclk->div_reg) {
div_reg            99 drivers/clk/socfpga/clk-gate.c 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
div_reg           102 drivers/clk/socfpga/clk-gate.c 		if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
div_reg           174 drivers/clk/socfpga/clk-gate.c 	u32 div_reg[3];
div_reg           211 drivers/clk/socfpga/clk-gate.c 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
div_reg           213 drivers/clk/socfpga/clk-gate.c 		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
div_reg           214 drivers/clk/socfpga/clk-gate.c 		socfpga_clk->shift = div_reg[1];
div_reg           215 drivers/clk/socfpga/clk-gate.c 		socfpga_clk->width = div_reg[2];
div_reg           217 drivers/clk/socfpga/clk-gate.c 		socfpga_clk->div_reg = NULL;
div_reg            28 drivers/clk/socfpga/clk-periph-a10.c 	} else if (socfpgaclk->div_reg) {
div_reg            29 drivers/clk/socfpga/clk-periph-a10.c 		div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
div_reg            71 drivers/clk/socfpga/clk-periph-a10.c 	u32 div_reg[3];
div_reg            81 drivers/clk/socfpga/clk-periph-a10.c 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
div_reg            83 drivers/clk/socfpga/clk-periph-a10.c 		periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0];
div_reg            84 drivers/clk/socfpga/clk-periph-a10.c 		periph_clk->shift = div_reg[1];
div_reg            85 drivers/clk/socfpga/clk-periph-a10.c 		periph_clk->width = div_reg[2];
div_reg            87 drivers/clk/socfpga/clk-periph-a10.c 		periph_clk->div_reg = NULL;
div_reg            26 drivers/clk/socfpga/clk-periph.c 		if (socfpgaclk->div_reg) {
div_reg            27 drivers/clk/socfpga/clk-periph.c 			val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
div_reg            61 drivers/clk/socfpga/clk-periph.c 	u32 div_reg[3];
div_reg            71 drivers/clk/socfpga/clk-periph.c 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
div_reg            73 drivers/clk/socfpga/clk-periph.c 		periph_clk->div_reg = clk_mgr_base_addr + div_reg[0];
div_reg            74 drivers/clk/socfpga/clk-periph.c 		periph_clk->shift = div_reg[1];
div_reg            75 drivers/clk/socfpga/clk-periph.c 		periph_clk->width = div_reg[2];
div_reg            77 drivers/clk/socfpga/clk-periph.c 		periph_clk->div_reg = NULL;
div_reg           233 drivers/clk/socfpga/clk-s10.c 					clks[i].gate_idx, clks[i].div_reg,
div_reg            47 drivers/clk/socfpga/clk.h 	void __iomem *div_reg;
div_reg            60 drivers/clk/socfpga/clk.h 	void __iomem *div_reg;
div_reg            55 drivers/clk/socfpga/stratix10-clk.h 	unsigned long		div_reg;
div_reg          3453 drivers/net/ethernet/netronome/nfp/bpf/jit.c 	[BPF_ALU | BPF_DIV | BPF_X] =	div_reg,
div_reg           254 sound/soc/jz4740/jz4740-i2s.c 	uint32_t ctrl, div_reg;
div_reg           259 sound/soc/jz4740/jz4740-i2s.c 	div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
div_reg           281 sound/soc/jz4740/jz4740-i2s.c 		div_reg &= ~I2SDIV_DV_MASK;
div_reg           282 sound/soc/jz4740/jz4740-i2s.c 		div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
div_reg           288 sound/soc/jz4740/jz4740-i2s.c 			div_reg &= ~I2SDIV_IDV_MASK;
div_reg           289 sound/soc/jz4740/jz4740-i2s.c 			div_reg |= (div - 1) << I2SDIV_IDV_SHIFT;
div_reg           291 sound/soc/jz4740/jz4740-i2s.c 			div_reg &= ~I2SDIV_DV_MASK;
div_reg           292 sound/soc/jz4740/jz4740-i2s.c 			div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
div_reg           297 sound/soc/jz4740/jz4740-i2s.c 	jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);