div_mask          158 drivers/clk/actions/owl-factor.c 	val &= div_mask(factor_hw);
div_mask          193 drivers/clk/actions/owl-factor.c 	if (val > div_mask(factor_hw))
div_mask          194 drivers/clk/actions/owl-factor.c 		val = div_mask(factor_hw);
div_mask          198 drivers/clk/actions/owl-factor.c 	reg &= ~(div_mask(factor_hw) << factor_hw->shift);
div_mask           56 drivers/clk/at91/at91sam9x5.c 	.div_mask = GENMASK(17, 16),
div_mask          169 drivers/clk/at91/clk-peripheral.c 			   periph->layout->div_mask | periph->layout->cmd |
div_mask          171 drivers/clk/at91/clk-peripheral.c 			   field_prep(periph->layout->div_mask, periph->div) |
div_mask          232 drivers/clk/at91/clk-peripheral.c 		periph->div = field_get(periph->layout->div_mask, status);
div_mask          352 drivers/clk/at91/clk-peripheral.c 	if (layout->div_mask)
div_mask          100 drivers/clk/at91/dt-compat.c 	.div_mask = GENMASK(17, 16),
div_mask           86 drivers/clk/at91/pmc.h 	u32 div_mask;
div_mask           23 drivers/clk/clk-vt8500.c 	unsigned int	div_mask;
div_mask          118 drivers/clk/clk-vt8500.c 	u32 div = readl(cdev->div_reg) & cdev->div_mask;
div_mask          121 drivers/clk/clk-vt8500.c 	if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
div_mask          126 drivers/clk/clk-vt8500.c 		div = (cdev->div_mask + 1);
div_mask          150 drivers/clk/clk-vt8500.c 	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
div_mask          169 drivers/clk/clk-vt8500.c 	if (divisor == cdev->div_mask + 1)
div_mask          173 drivers/clk/clk-vt8500.c 	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
div_mask          181 drivers/clk/clk-vt8500.c 	if (divisor > cdev->div_mask) {
div_mask          262 drivers/clk/clk-vt8500.c 		dev_clk->div_mask = 0x1f;
div_mask          264 drivers/clk/clk-vt8500.c 		of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
div_mask           52 drivers/clk/hisilicon/clkdivider-hi6220.c 	val &= div_mask(dclk->width);
div_mask           82 drivers/clk/hisilicon/clkdivider-hi6220.c 	data &= ~(div_mask(dclk->width) << dclk->shift);
div_mask          117 drivers/clk/hisilicon/clkdivider-hi6220.c 	max_div = div_mask(width) + 1;
div_mask           66 drivers/clk/imx/clk-fixup-div.c 	if (value > div_mask(div))
div_mask           67 drivers/clk/imx/clk-fixup-div.c 		value = div_mask(div);
div_mask           72 drivers/clk/imx/clk-fixup-div.c 	val &= ~(div_mask(div) << div->shift);
div_mask           45 drivers/clk/imx/clk-pllv3.c 	u32		div_mask;
div_mask          117 drivers/clk/imx/clk-pllv3.c 	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;
div_mask          145 drivers/clk/imx/clk-pllv3.c 	val &= ~(pll->div_mask << pll->div_shift);
div_mask          165 drivers/clk/imx/clk-pllv3.c 	u32 div = readl_relaxed(pll->base) & pll->div_mask;
div_mask          200 drivers/clk/imx/clk-pllv3.c 	val &= ~pll->div_mask;
div_mask          222 drivers/clk/imx/clk-pllv3.c 	u32 div = readl_relaxed(pll->base) & pll->div_mask;
div_mask          287 drivers/clk/imx/clk-pllv3.c 	val &= ~pll->div_mask;
div_mask          355 drivers/clk/imx/clk-pllv3.c 	mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
div_mask          378 drivers/clk/imx/clk-pllv3.c 		val &= ~pll->div_mask;	/* clear bit for mfi=20 */
div_mask          380 drivers/clk/imx/clk-pllv3.c 		val |= pll->div_mask;	/* set bit for mfi=22 */
div_mask          415 drivers/clk/imx/clk-pllv3.c 			  u32 div_mask)
div_mask          473 drivers/clk/imx/clk-pllv3.c 	pll->div_mask = div_mask;
div_mask           61 drivers/clk/imx/clk.h #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
div_mask           62 drivers/clk/imx/clk.h 	to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
div_mask          130 drivers/clk/imx/clk.h 		const char *parent_name, void __iomem *base, u32 div_mask);
div_mask           29 drivers/clk/mmp/clk-mix.c 	unsigned int div_mask = (1 << mix->reg_info.width_div) - 1;
div_mask           34 drivers/clk/mmp/clk-mix.c 		return div_mask;
div_mask           36 drivers/clk/mmp/clk-mix.c 		return 1 << div_mask;
div_mask           43 drivers/clk/mmp/clk-mix.c 	return div_mask + 1;
div_mask          952 drivers/clk/nxp/clk-lpc32xx.c 	val &= div_mask(divider->width);
div_mask          968 drivers/clk/nxp/clk-lpc32xx.c 		bestdiv &= div_mask(divider->width);
div_mask          988 drivers/clk/nxp/clk-lpc32xx.c 				  div_mask(divider->width) << divider->shift,
div_mask         1475 drivers/clk/nxp/clk-lpc32xx.c static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate)
div_mask         1481 drivers/clk/nxp/clk-lpc32xx.c 	if (!(val & div_mask)) {
div_mask         1483 drivers/clk/nxp/clk-lpc32xx.c 		val |= BIT(__ffs(div_mask));
div_mask         1486 drivers/clk/nxp/clk-lpc32xx.c 	regmap_update_bits(clk_regmap, reg, gate | div_mask, val);
div_mask           29 drivers/clk/rockchip/clk-half-divider.c 	val &= div_mask(divider->width);
div_mask           46 drivers/clk/rockchip/clk-half-divider.c 	maxdiv = div_mask(width);
div_mask           88 drivers/clk/rockchip/clk-half-divider.c 		bestdiv = div_mask(width);
div_mask          118 drivers/clk/rockchip/clk-half-divider.c 	value =  min_t(unsigned int, value, div_mask(divider->width));
div_mask          126 drivers/clk/rockchip/clk-half-divider.c 		val = div_mask(divider->width) << (divider->shift + 16);
div_mask          129 drivers/clk/rockchip/clk-half-divider.c 		val &= ~(div_mask(divider->width) << divider->shift);
div_mask          230 drivers/clk/samsung/clk-cpu.c 	unsigned long div = 0, div_mask = DIV_MASK;
div_mask          252 drivers/clk/samsung/clk-cpu.c 		div_mask |= E4210_DIV0_ATB_MASK;
div_mask          255 drivers/clk/samsung/clk-cpu.c 	exynos_set_safe_div(base, div, div_mask);
div_mask          340 drivers/clk/samsung/clk-cpu.c 	unsigned long div = 0, div_mask = DIV_MASK;
div_mask          351 drivers/clk/samsung/clk-cpu.c 	exynos5433_set_safe_div(base, div, div_mask);
div_mask           17 drivers/clk/tegra/clk-divider.c #define get_max_div(d) div_mask(d)
div_mask           44 drivers/clk/tegra/clk-divider.c 	div = reg & div_mask(divider);
div_mask           91 drivers/clk/tegra/clk-divider.c 	val &= ~(div_mask(divider) << divider->shift);
div_mask           39 drivers/clk/tegra/clk-utils.c 	if (divider_ux1 > div_mask(width))
div_mask           40 drivers/clk/tegra/clk-utils.c 		return div_mask(width);
div_mask           45 drivers/clk/ti/divider.c 		return div_mask(divider);
div_mask           47 drivers/clk/ti/divider.c 		return 1 << div_mask(divider);
div_mask           50 drivers/clk/ti/divider.c 	return div_mask(divider) + 1;
div_mask          104 drivers/clk/ti/divider.c 	val &= div_mask(divider);
div_mask          254 drivers/clk/ti/divider.c 	if (value > div_mask(divider))
div_mask          255 drivers/clk/ti/divider.c 		value = div_mask(divider);
div_mask          258 drivers/clk/ti/divider.c 		val = div_mask(divider) << (divider->shift + 16);
div_mask          261 drivers/clk/ti/divider.c 		val &= ~(div_mask(divider) << divider->shift);
div_mask          283 drivers/clk/ti/divider.c 	divider->context = val & div_mask(divider);
div_mask          300 drivers/clk/ti/divider.c 	val &= ~(div_mask(divider) << divider->shift);
div_mask          690 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	val &= div_mask(width);
div_mask          732 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	val &= ~(div_mask(width) << shift);
div_mask           94 drivers/i2c/busses/i2c-brcmstb.c 	u32 div_mask;
div_mask          126 drivers/i2c/busses/i2c-brcmstb.c 		.div_mask = 0
div_mask          131 drivers/i2c/busses/i2c-brcmstb.c 		.div_mask = 0
div_mask          136 drivers/i2c/busses/i2c-brcmstb.c 		.div_mask = 0
div_mask          141 drivers/i2c/busses/i2c-brcmstb.c 		.div_mask = 0
div_mask          146 drivers/i2c/busses/i2c-brcmstb.c 		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
div_mask          151 drivers/i2c/busses/i2c-brcmstb.c 		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
div_mask          156 drivers/i2c/busses/i2c-brcmstb.c 		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
div_mask          161 drivers/i2c/busses/i2c-brcmstb.c 		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
div_mask          555 drivers/i2c/busses/i2c-brcmstb.c 						     bsc_clk[i].div_mask);
div_mask          522 drivers/mfd/db8500-prcmu.c 	u32 div_mask;
div_mask          529 drivers/mfd/db8500-prcmu.c 		.div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
div_mask          534 drivers/mfd/db8500-prcmu.c 		.div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
div_mask          539 drivers/mfd/db8500-prcmu.c 		.div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
div_mask          733 drivers/mfd/db8500-prcmu.c 	u32 div_mask;
div_mask          743 drivers/mfd/db8500-prcmu.c 		div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
div_mask          748 drivers/mfd/db8500-prcmu.c 		div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
div_mask          759 drivers/mfd/db8500-prcmu.c 	if (val & div_mask) {
div_mask          766 drivers/mfd/db8500-prcmu.c 			if ((val & mask & ~div_mask) != bits) {
div_mask         1609 drivers/mfd/db8500-prcmu.c 	div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
div_mask         1974 drivers/mfd/db8500-prcmu.c 	val &= ~dsiescclk[n].div_mask;
div_mask          138 drivers/sh/clk/cpg.c 	idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask;
div_mask          154 drivers/sh/clk/cpg.c 	value &= ~(clk->div_mask << clk->enable_bit);
div_mask          167 drivers/sh/clk/cpg.c 	if (clk->div_mask == SH_CLK_DIV6_MSK) {
div_mask          190 drivers/sh/clk/cpg.c 		val |= clk->div_mask;
div_mask           60 include/linux/sh_clk.h 	unsigned int		div_mask;
div_mask          157 include/linux/sh_clk.h 	.div_mask = SH_CLK_DIV4_MSK,				\
div_mask          181 include/linux/sh_clk.h 	.div_mask = SH_CLK_DIV6_MSK,				\
div_mask          193 include/linux/sh_clk.h 	.div_mask	= SH_CLK_DIV6_MSK,			\