div_data 623 drivers/clk/clk-npcm7xx.c const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i]; div_data 625 drivers/clk/clk-npcm7xx.c hw = clk_hw_register_divider(NULL, div_data->name, div_data 626 drivers/clk/clk-npcm7xx.c div_data->parent_name, div_data 627 drivers/clk/clk-npcm7xx.c div_data->flags, div_data 628 drivers/clk/clk-npcm7xx.c clk_base + div_data->reg, div_data 629 drivers/clk/clk-npcm7xx.c div_data->shift, div_data->width, div_data 630 drivers/clk/clk-npcm7xx.c div_data->clk_divider_flags, &npcm7xx_clk_lock); div_data 636 drivers/clk/clk-npcm7xx.c if (div_data->onecell_idx >= 0) div_data 637 drivers/clk/clk-npcm7xx.c npcm7xx_clk_data->hws[div_data->onecell_idx] = hw; div_data 578 drivers/clk/clk-stm32f4.c static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = { div_data 838 drivers/clk/clk-stm32f4.c div_data[i].shift, div_data 839 drivers/clk/clk-stm32f4.c div_data[i].width, div_data 840 drivers/clk/clk-stm32f4.c div_data[i].flag_div, div_data 841 drivers/clk/clk-stm32f4.c div_data[i].div_table, div_data 731 drivers/clk/sunxi/clk-sunxi.c static const struct div_data sun4i_axi_data __initconst = { div_data 749 drivers/clk/sunxi/clk-sunxi.c static const struct div_data sun8i_a23_axi_data __initconst = { div_data 754 drivers/clk/sunxi/clk-sunxi.c static const struct div_data sun4i_ahb_data __initconst = { div_data 768 drivers/clk/sunxi/clk-sunxi.c static const struct div_data sun4i_apb0_data __initconst = { div_data 776 drivers/clk/sunxi/clk-sunxi.c const struct div_data *data) div_data 368 drivers/clk/ti/clkctrl.c const struct omap_clkctrl_div_data *div_data = data->data; div_data 377 drivers/clk/ti/clkctrl.c div->flags = div_data->flags; div_data 382 drivers/clk/ti/clkctrl.c if (ti_clk_parse_divider_data((int *)div_data->dividers, 0, div_data 383 drivers/clk/ti/clkctrl.c div_data->max_div, div_flags,