dispc_ops 39 drivers/gpu/drm/omapdrm/dss/base.c const struct dispc_ops *dispc_get_ops(struct dss_device *dss) dispc_ops 41 drivers/gpu/drm/omapdrm/dss/base.c return dss->dispc_ops; dispc_ops 4692 drivers/gpu/drm/omapdrm/dss/dispc.c static const struct dispc_ops dispc_ops = { dispc_ops 4836 drivers/gpu/drm/omapdrm/dss/dispc.c dss->dispc_ops = &dispc_ops; dispc_ops 4858 drivers/gpu/drm/omapdrm/dss/dispc.c dss->dispc_ops = NULL; dispc_ops 260 drivers/gpu/drm/omapdrm/dss/dss.h const struct dispc_ops *dispc_ops; dispc_ops 628 drivers/gpu/drm/omapdrm/dss/omapdss.h const struct dispc_ops *dispc_get_ops(struct dss_device *dss); dispc_ops 106 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_enable(priv->dispc, channel, true); dispc_ops 131 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_enable(priv->dispc, channel, enable); dispc_ops 144 drivers/gpu/drm/omapdrm/omap_crtc.c framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, dispc_ops 146 drivers/gpu/drm/omapdrm/omap_crtc.c vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel); dispc_ops 166 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_enable(priv->dispc, channel, enable); dispc_ops 189 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel, dispc_ops 224 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel, dispc_ops 303 drivers/gpu/drm/omapdrm/omap_crtc.c if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) { dispc_ops 407 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_setup(priv->dispc, omap_crtc->channel, &info); dispc_ops 448 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->runtime_get(priv->dispc); dispc_ops 486 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->runtime_put(priv->dispc); dispc_ops 506 drivers/gpu/drm/omapdrm/omap_crtc.c r = priv->dispc_ops->mgr_check_timings(priv->dispc, dispc_ops 622 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_set_gamma(priv->dispc, omap_crtc->channel, dispc_ops 647 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_go(priv->dispc, omap_crtc->channel); dispc_ops 836 drivers/gpu/drm/omapdrm/omap_crtc.c if (priv->dispc_ops->mgr_gamma_size(priv->dispc, channel)) { dispc_ops 70 drivers/gpu/drm/omapdrm/omap_drv.c priv->dispc_ops->runtime_get(priv->dispc); dispc_ops 114 drivers/gpu/drm/omapdrm/omap_drv.c priv->dispc_ops->runtime_put(priv->dispc); dispc_ops 196 drivers/gpu/drm/omapdrm/omap_drv.c unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc); dispc_ops 233 drivers/gpu/drm/omapdrm/omap_drv.c int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc); dispc_ops 234 drivers/gpu/drm/omapdrm/omap_drv.c int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc); dispc_ops 576 drivers/gpu/drm/omapdrm/omap_drv.c priv->dispc_ops = dispc_get_ops(priv->dss); dispc_ops 588 drivers/gpu/drm/omapdrm/omap_drv.c if (priv->dispc_ops->get_memory_bandwidth_limit) dispc_ops 590 drivers/gpu/drm/omapdrm/omap_drv.c priv->dispc_ops->get_memory_bandwidth_limit(priv->dispc); dispc_ops 50 drivers/gpu/drm/omapdrm/omap_drv.h const struct dispc_ops *dispc_ops; dispc_ops 32 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->write_irqenable(priv->dispc, irqmask); dispc_ops 86 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, channel); dispc_ops 124 drivers/gpu/drm/omapdrm/omap_irq.c priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, dispc_ops 151 drivers/gpu/drm/omapdrm/omap_irq.c priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, dispc_ops 216 drivers/gpu/drm/omapdrm/omap_irq.c irqstatus = priv->dispc_ops->read_irqstatus(priv->dispc); dispc_ops 217 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->clear_irqstatus(priv->dispc, irqstatus); dispc_ops 218 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->read_irqstatus(priv->dispc); /* flush posted write */ dispc_ops 226 drivers/gpu/drm/omapdrm/omap_irq.c if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel)) { dispc_ops 231 drivers/gpu/drm/omapdrm/omap_irq.c if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, channel)) dispc_ops 234 drivers/gpu/drm/omapdrm/omap_irq.c if (irqstatus & priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, channel)) dispc_ops 268 drivers/gpu/drm/omapdrm/omap_irq.c unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc); dispc_ops 286 drivers/gpu/drm/omapdrm/omap_irq.c priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, i); dispc_ops 288 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->runtime_get(priv->dispc); dispc_ops 289 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->clear_irqstatus(priv->dispc, 0xffffffff); dispc_ops 290 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->runtime_put(priv->dispc); dispc_ops 292 drivers/gpu/drm/omapdrm/omap_irq.c ret = priv->dispc_ops->request_irq(priv->dispc, omap_irq_handler, dev); dispc_ops 310 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->free_irq(priv->dispc, dev); dispc_ops 73 drivers/gpu/drm/omapdrm/omap_plane.c ret = priv->dispc_ops->ovl_setup(priv->dispc, omap_plane->id, &info, dispc_ops 79 drivers/gpu/drm/omapdrm/omap_plane.c priv->dispc_ops->ovl_enable(priv->dispc, omap_plane->id, false); dispc_ops 83 drivers/gpu/drm/omapdrm/omap_plane.c priv->dispc_ops->ovl_enable(priv->dispc, omap_plane->id, true); dispc_ops 96 drivers/gpu/drm/omapdrm/omap_plane.c priv->dispc_ops->ovl_enable(priv->dispc, omap_plane->id, false); dispc_ops 255 drivers/gpu/drm/omapdrm/omap_plane.c unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc); dispc_ops 274 drivers/gpu/drm/omapdrm/omap_plane.c formats = priv->dispc_ops->ovl_get_color_modes(priv->dispc, id);