dev_priv 38 drivers/gpu/drm/gma500/accel_2d.c void psb_spank(struct drm_psb_private *dev_priv) dev_priv 59 drivers/gpu/drm/gma500/accel_2d.c PSB_WSGX32(dev_priv->gtt.gatt_start, PSB_CR_BIF_TWOD_REQ_BASE); dev_priv 70 drivers/gpu/drm/gma500/accel_2d.c static int psb_2d_wait_available(struct drm_psb_private *dev_priv, dev_priv 79 drivers/gpu/drm/gma500/accel_2d.c psb_spank(dev_priv); dev_priv 95 drivers/gpu/drm/gma500/accel_2d.c static int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf, dev_priv 103 drivers/gpu/drm/gma500/accel_2d.c spin_lock_irqsave(&dev_priv->lock_2d, flags); dev_priv 107 drivers/gpu/drm/gma500/accel_2d.c ret = psb_2d_wait_available(dev_priv, submit_size); dev_priv 118 drivers/gpu/drm/gma500/accel_2d.c spin_unlock_irqrestore(&dev_priv->lock_2d, flags); dev_priv 159 drivers/gpu/drm/gma500/accel_2d.c static int psb_accel_2d_copy(struct drm_psb_private *dev_priv, dev_priv 216 drivers/gpu/drm/gma500/accel_2d.c return psbfb_2d_submit(dev_priv, buffer, buf - buffer); dev_priv 233 drivers/gpu/drm/gma500/accel_2d.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 274 drivers/gpu/drm/gma500/accel_2d.c psb_accel_2d_copy(dev_priv, dev_priv 315 drivers/gpu/drm/gma500/accel_2d.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 320 drivers/gpu/drm/gma500/accel_2d.c spin_lock_irqsave(&dev_priv->lock_2d, flags); dev_priv 349 drivers/gpu/drm/gma500/accel_2d.c spin_unlock_irqrestore(&dev_priv->lock_2d, flags); dev_priv 19 drivers/gpu/drm/gma500/backlight.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 20 drivers/gpu/drm/gma500/backlight.c backlight_update_status(dev_priv->backlight_device); dev_priv 27 drivers/gpu/drm/gma500/backlight.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 28 drivers/gpu/drm/gma500/backlight.c dev_priv->backlight_enabled = true; dev_priv 29 drivers/gpu/drm/gma500/backlight.c if (dev_priv->backlight_device) { dev_priv 30 drivers/gpu/drm/gma500/backlight.c dev_priv->backlight_device->props.brightness = dev_priv->backlight_level; dev_priv 39 drivers/gpu/drm/gma500/backlight.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 40 drivers/gpu/drm/gma500/backlight.c dev_priv->backlight_enabled = false; dev_priv 41 drivers/gpu/drm/gma500/backlight.c if (dev_priv->backlight_device) { dev_priv 42 drivers/gpu/drm/gma500/backlight.c dev_priv->backlight_device->props.brightness = 0; dev_priv 51 drivers/gpu/drm/gma500/backlight.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 52 drivers/gpu/drm/gma500/backlight.c dev_priv->backlight_level = v; dev_priv 53 drivers/gpu/drm/gma500/backlight.c if (dev_priv->backlight_device && dev_priv->backlight_enabled) { dev_priv 54 drivers/gpu/drm/gma500/backlight.c dev_priv->backlight_device->props.brightness = v; dev_priv 63 drivers/gpu/drm/gma500/backlight.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 64 drivers/gpu/drm/gma500/backlight.c dev_priv->backlight_enabled = true; dev_priv 65 drivers/gpu/drm/gma500/backlight.c return dev_priv->ops->backlight_init(dev); dev_priv 74 drivers/gpu/drm/gma500/backlight.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 75 drivers/gpu/drm/gma500/backlight.c if (dev_priv->backlight_device) { dev_priv 76 drivers/gpu/drm/gma500/backlight.c dev_priv->backlight_device->props.brightness = 0; dev_priv 77 drivers/gpu/drm/gma500/backlight.c backlight_update_status(dev_priv->backlight_device); dev_priv 78 drivers/gpu/drm/gma500/backlight.c backlight_device_unregister(dev_priv->backlight_device); dev_priv 15 drivers/gpu/drm/gma500/blitter.c int gma_blt_wait_idle(struct drm_psb_private *dev_priv) dev_priv 21 drivers/gpu/drm/gma500/blitter.c if (IS_CDV(dev_priv->dev)) dev_priv 14 drivers/gpu/drm/gma500/blitter.h extern int gma_blt_wait_idle(struct drm_psb_private *dev_priv); dev_priv 41 drivers/gpu/drm/gma500/cdv_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 47 drivers/gpu/drm/gma500/cdv_device.c cdv_intel_crt_init(dev, &dev_priv->mode_dev); dev_priv 48 drivers/gpu/drm/gma500/cdv_device.c cdv_intel_lvds_init(dev, &dev_priv->mode_dev); dev_priv 52 drivers/gpu/drm/gma500/cdv_device.c cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB); dev_priv 54 drivers/gpu/drm/gma500/cdv_device.c cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_B); dev_priv 58 drivers/gpu/drm/gma500/cdv_device.c cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC); dev_priv 60 drivers/gpu/drm/gma500/cdv_device.c cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_C); dev_priv 147 drivers/gpu/drm/gma500/cdv_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 162 drivers/gpu/drm/gma500/cdv_device.c dev_priv->backlight_device = cdv_backlight_device; dev_priv 163 drivers/gpu/drm/gma500/cdv_device.c dev_priv->backlight_enabled = true; dev_priv 207 drivers/gpu/drm/gma500/cdv_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 212 drivers/gpu/drm/gma500/cdv_device.c dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT, dev_priv 214 drivers/gpu/drm/gma500/cdv_device.c dev_priv->ospm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT, dev_priv 218 drivers/gpu/drm/gma500/cdv_device.c pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); dev_priv 223 drivers/gpu/drm/gma500/cdv_device.c outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); dev_priv 227 drivers/gpu/drm/gma500/cdv_device.c u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); dev_priv 257 drivers/gpu/drm/gma500/cdv_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 258 drivers/gpu/drm/gma500/cdv_device.c struct psb_save_area *regs = &dev_priv->regs; dev_priv 311 drivers/gpu/drm/gma500/cdv_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 312 drivers/gpu/drm/gma500/cdv_device.c struct psb_save_area *regs = &dev_priv->regs; dev_priv 379 drivers/gpu/drm/gma500/cdv_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 383 drivers/gpu/drm/gma500/cdv_device.c pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); dev_priv 388 drivers/gpu/drm/gma500/cdv_device.c outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); dev_priv 391 drivers/gpu/drm/gma500/cdv_device.c pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); dev_priv 401 drivers/gpu/drm/gma500/cdv_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 405 drivers/gpu/drm/gma500/cdv_device.c pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); dev_priv 410 drivers/gpu/drm/gma500/cdv_device.c outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); dev_priv 413 drivers/gpu/drm/gma500/cdv_device.c pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); dev_priv 423 drivers/gpu/drm/gma500/cdv_device.c struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private, dev_priv 425 drivers/gpu/drm/gma500/cdv_device.c struct drm_device *dev = dev_priv->dev; dev_priv 436 drivers/gpu/drm/gma500/cdv_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 437 drivers/gpu/drm/gma500/cdv_device.c schedule_work(&dev_priv->hotplug_work); dev_priv 464 drivers/gpu/drm/gma500/cdv_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 468 drivers/gpu/drm/gma500/cdv_device.c prop = dev_priv->force_audio_property; dev_priv 479 drivers/gpu/drm/gma500/cdv_device.c dev_priv->force_audio_property = prop; dev_priv 493 drivers/gpu/drm/gma500/cdv_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 497 drivers/gpu/drm/gma500/cdv_device.c prop = dev_priv->broadcast_rgb_property; dev_priv 508 drivers/gpu/drm/gma500/cdv_device.c dev_priv->broadcast_rgb_property = prop; dev_priv 570 drivers/gpu/drm/gma500/cdv_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 571 drivers/gpu/drm/gma500/cdv_device.c INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func); dev_priv 575 drivers/gpu/drm/gma500/cdv_device.c dev_priv->regmap = cdv_regmap; dev_priv 456 drivers/gpu/drm/gma500/cdv_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 459 drivers/gpu/drm/gma500/cdv_intel_display.c crtc = dev_priv->pipe_to_crtc_mapping[pipe]; dev_priv 490 drivers/gpu/drm/gma500/cdv_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 548 drivers/gpu/drm/gma500/cdv_intel_display.c dev_priv->ops->disable_sr(dev); dev_priv 575 drivers/gpu/drm/gma500/cdv_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 578 drivers/gpu/drm/gma500/cdv_intel_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 625 drivers/gpu/drm/gma500/cdv_intel_display.c if (dev_priv->dplla_96mhz) dev_priv 646 drivers/gpu/drm/gma500/cdv_intel_display.c if (is_lvds && dev_priv->lvds_use_ssc) { dev_priv 647 drivers/gpu/drm/gma500/cdv_intel_display.c refclk = dev_priv->lvds_ssc_freq * 1000; dev_priv 648 drivers/gpu/drm/gma500/cdv_intel_display.c DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); dev_priv 692 drivers/gpu/drm/gma500/cdv_intel_display.c switch (dev_priv->edp.bpp) { dev_priv 842 drivers/gpu/drm/gma500/cdv_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 845 drivers/gpu/drm/gma500/cdv_intel_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 850 drivers/gpu/drm/gma500/cdv_intel_display.c struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; dev_priv 868 drivers/gpu/drm/gma500/cdv_intel_display.c (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN); dev_priv 923 drivers/gpu/drm/gma500/cdv_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 924 drivers/gpu/drm/gma500/cdv_intel_display.c struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; dev_priv 925 drivers/gpu/drm/gma500/cdv_intel_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 326 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 344 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 382 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; dev_priv 417 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; dev_priv 445 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; dev_priv 496 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; dev_priv 514 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 517 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_psb_private *dev_priv = connector->dev->dev_private; dev_priv 529 drivers/gpu/drm/gma500/cdv_intel_dp.c (cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp) dev_priv 573 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 850 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 898 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_psb_private *dev_priv = encoder->dev->dev_private; dev_priv 900 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; dev_priv 911 drivers/gpu/drm/gma500/cdv_intel_dp.c bpp = dev_priv->edp.bpp; dev_priv 990 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 1009 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp = intel_encoder->dev_priv; dev_priv 1015 drivers/gpu/drm/gma500/cdv_intel_dp.c bpp = dev_priv->edp.bpp; dev_priv 1045 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; dev_priv 1111 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1173 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; dev_priv 1234 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1308 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1367 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1392 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1417 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1436 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1502 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1596 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1682 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1705 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1732 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1766 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; dev_priv 1781 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 1799 drivers/gpu/drm/gma500/cdv_intel_dp.c if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) { dev_priv 1801 drivers/gpu/drm/gma500/cdv_intel_dp.c drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); dev_priv 1822 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1846 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_psb_private *dev_priv = connector->dev->dev_private; dev_priv 1848 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = encoder->dev_priv; dev_priv 1855 drivers/gpu/drm/gma500/cdv_intel_dp.c if (property == dev_priv->force_audio_property) { dev_priv 1876 drivers/gpu/drm/gma500/cdv_intel_dp.c if (property == dev_priv->broadcast_rgb_property) { dev_priv 1901 drivers/gpu/drm/gma500/cdv_intel_dp.c struct cdv_intel_dp *intel_dp = gma_encoder->dev_priv; dev_priv 1955 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 1959 drivers/gpu/drm/gma500/cdv_intel_dp.c if (!dev_priv->child_dev_num) dev_priv 1962 drivers/gpu/drm/gma500/cdv_intel_dp.c for (i = 0; i < dev_priv->child_dev_num; i++) { dev_priv 1963 drivers/gpu/drm/gma500/cdv_intel_dp.c p_child = dev_priv->child_dev + i; dev_priv 2033 drivers/gpu/drm/gma500/cdv_intel_dp.c gma_encoder->dev_priv=intel_dp; dev_priv 69 drivers/gpu/drm/gma500/cdv_intel_hdmi.c struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv; dev_priv 97 drivers/gpu/drm/gma500/cdv_intel_hdmi.c struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv; dev_priv 113 drivers/gpu/drm/gma500/cdv_intel_hdmi.c struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv; dev_priv 122 drivers/gpu/drm/gma500/cdv_intel_hdmi.c struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv; dev_priv 132 drivers/gpu/drm/gma500/cdv_intel_hdmi.c struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv; dev_priv 321 drivers/gpu/drm/gma500/cdv_intel_hdmi.c gma_encoder->dev_priv = hdmi_priv; dev_priv 58 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 68 drivers/gpu/drm/gma500/cdv_intel_lvds.c retval = ((dev_priv->regs.saveBLC_PWM_CTL & dev_priv 82 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 83 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct psb_intel_i2c_chan *lvds_i2c_bus = dev_priv->lvds_i2c_bus; dev_priv 100 drivers/gpu/drm/gma500/cdv_intel_lvds.c if (dev_priv->lvds_bl->pol == BLC_POLARITY_INVERSE) dev_priv 103 drivers/gpu/drm/gma500/cdv_intel_lvds.c out_buf[0] = dev_priv->lvds_bl->brightnesscmd; dev_priv 116 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 128 drivers/gpu/drm/gma500/cdv_intel_lvds.c if (dev_priv->lvds_bl->pol == BLC_POLARITY_INVERSE) dev_priv 144 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 146 drivers/gpu/drm/gma500/cdv_intel_lvds.c if (!dev_priv->lvds_bl) { dev_priv 151 drivers/gpu/drm/gma500/cdv_intel_lvds.c if (dev_priv->lvds_bl->type == BLC_I2C_TYPE) dev_priv 165 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 176 drivers/gpu/drm/gma500/cdv_intel_lvds.c blc_pwm_ctl = dev_priv->regs.saveBLC_PWM_CTL & dev_priv 178 drivers/gpu/drm/gma500/cdv_intel_lvds.c dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl | dev_priv 189 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 203 drivers/gpu/drm/gma500/cdv_intel_lvds.c dev_priv->mode_dev.backlight_duty_cycle); dev_priv 238 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 240 drivers/gpu/drm/gma500/cdv_intel_lvds.c dev_priv->mode_dev.panel_fixed_mode; dev_priv 264 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 265 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; dev_priv 311 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 312 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; dev_priv 329 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 330 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; dev_priv 344 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 369 drivers/gpu/drm/gma500/cdv_intel_lvds.c if (dev_priv->lvds_dither) dev_priv 381 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 383 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; dev_priv 522 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 525 drivers/gpu/drm/gma500/cdv_intel_lvds.c if (!dev_priv->child_dev_num) dev_priv 528 drivers/gpu/drm/gma500/cdv_intel_lvds.c for (i = 0; i < dev_priv->child_dev_num; i++) { dev_priv 529 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct child_device_config *child = dev_priv->child_dev + i; dev_priv 555 drivers/gpu/drm/gma500/cdv_intel_lvds.c if (dev_priv->opregion.vbt) dev_priv 579 drivers/gpu/drm/gma500/cdv_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 584 drivers/gpu/drm/gma500/cdv_intel_lvds.c if (!dev_priv->lvds_enabled_in_vbt) dev_priv 607 drivers/gpu/drm/gma500/cdv_intel_lvds.c gma_encoder->dev_priv = lvds_priv; dev_priv 639 drivers/gpu/drm/gma500/cdv_intel_lvds.c dev_priv->backlight_property, dev_priv 655 drivers/gpu/drm/gma500/cdv_intel_lvds.c dev_priv->lvds_i2c_bus = gma_encoder->i2c_bus; dev_priv 693 drivers/gpu/drm/gma500/cdv_intel_lvds.c if (dev_priv->lfp_lvds_vbt_mode) { dev_priv 695 drivers/gpu/drm/gma500/cdv_intel_lvds.c drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); dev_priv 104 drivers/gpu/drm/gma500/framebuffer.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 111 drivers/gpu/drm/gma500/framebuffer.c unsigned long phys_addr = (unsigned long)dev_priv->stolen_base + dev_priv 307 drivers/gpu/drm/gma500/framebuffer.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 373 drivers/gpu/drm/gma500/framebuffer.c memset(dev_priv->vram_addr + backing->offset, 0, size); dev_priv 392 drivers/gpu/drm/gma500/framebuffer.c if (dev_priv->ops->accel_2d && pitch_lines > 8) /* 2D engine */ dev_priv 406 drivers/gpu/drm/gma500/framebuffer.c info->screen_base = dev_priv->vram_addr + backing->offset; dev_priv 409 drivers/gpu/drm/gma500/framebuffer.c if (dev_priv->gtt.stolen_size) { dev_priv 411 drivers/gpu/drm/gma500/framebuffer.c info->apertures->ranges[0].size = dev_priv->gtt.stolen_size; dev_priv 464 drivers/gpu/drm/gma500/framebuffer.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 479 drivers/gpu/drm/gma500/framebuffer.c if (fb_size > dev_priv->vram_stolen_size) { dev_priv 509 drivers/gpu/drm/gma500/framebuffer.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 518 drivers/gpu/drm/gma500/framebuffer.c dev_priv->fbdev = fbdev; dev_priv 549 drivers/gpu/drm/gma500/framebuffer.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 551 drivers/gpu/drm/gma500/framebuffer.c if (!dev_priv->fbdev) dev_priv 554 drivers/gpu/drm/gma500/framebuffer.c psb_fbdev_destroy(dev, dev_priv->fbdev); dev_priv 555 drivers/gpu/drm/gma500/framebuffer.c kfree(dev_priv->fbdev); dev_priv 556 drivers/gpu/drm/gma500/framebuffer.c dev_priv->fbdev = NULL; dev_priv 566 drivers/gpu/drm/gma500/framebuffer.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 572 drivers/gpu/drm/gma500/framebuffer.c if (!dev_priv->backlight_property) dev_priv 573 drivers/gpu/drm/gma500/framebuffer.c dev_priv->backlight_property = drm_property_create_range(dev, 0, dev_priv 575 drivers/gpu/drm/gma500/framebuffer.c dev_priv->ops->output_init(dev); dev_priv 590 drivers/gpu/drm/gma500/framebuffer.c crtc_mask = dev_priv->ops->sdvo_mask; dev_priv 594 drivers/gpu/drm/gma500/framebuffer.c crtc_mask = dev_priv->ops->lvds_mask; dev_priv 606 drivers/gpu/drm/gma500/framebuffer.c crtc_mask = dev_priv->ops->hdmi_mask; dev_priv 625 drivers/gpu/drm/gma500/framebuffer.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 626 drivers/gpu/drm/gma500/framebuffer.c struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; dev_priv 642 drivers/gpu/drm/gma500/framebuffer.c for (i = 0; i < dev_priv->num_pipe; i++) dev_priv 650 drivers/gpu/drm/gma500/framebuffer.c if (dev_priv->ops->errata) dev_priv 651 drivers/gpu/drm/gma500/framebuffer.c dev_priv->ops->errata(dev); dev_priv 653 drivers/gpu/drm/gma500/framebuffer.c dev_priv->modeset = true; dev_priv 658 drivers/gpu/drm/gma500/framebuffer.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 659 drivers/gpu/drm/gma500/framebuffer.c if (dev_priv->modeset) { dev_priv 136 drivers/gpu/drm/gma500/gem.c struct drm_psb_private *dev_priv; dev_priv 140 drivers/gpu/drm/gma500/gem.c dev_priv = dev->dev_private; dev_priv 146 drivers/gpu/drm/gma500/gem.c mutex_lock(&dev_priv->mmap_mutex); dev_priv 166 drivers/gpu/drm/gma500/gem.c pfn = (dev_priv->stolen_base + r->offset) >> PAGE_SHIFT; dev_priv 171 drivers/gpu/drm/gma500/gem.c mutex_unlock(&dev_priv->mmap_mutex); dev_priv 16 drivers/gpu/drm/gma500/gma_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 27 drivers/gpu/drm/gma500/gma_device.c dev_priv->core_freq = 100; dev_priv 30 drivers/gpu/drm/gma500/gma_device.c dev_priv->core_freq = 133; dev_priv 33 drivers/gpu/drm/gma500/gma_device.c dev_priv->core_freq = 150; dev_priv 36 drivers/gpu/drm/gma500/gma_device.c dev_priv->core_freq = 178; dev_priv 39 drivers/gpu/drm/gma500/gma_device.c dev_priv->core_freq = 200; dev_priv 44 drivers/gpu/drm/gma500/gma_device.c dev_priv->core_freq = 266; dev_priv 47 drivers/gpu/drm/gma500/gma_device.c dev_priv->core_freq = 0; dev_priv 54 drivers/gpu/drm/gma500/gma_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 59 drivers/gpu/drm/gma500/gma_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 139 drivers/gpu/drm/gma500/gma_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 141 drivers/gpu/drm/gma500/gma_display.c const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; dev_priv 165 drivers/gpu/drm/gma500/gma_display.c dev_priv->regs.pipe[0].palette[i] = dev_priv 192 drivers/gpu/drm/gma500/gma_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 195 drivers/gpu/drm/gma500/gma_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 203 drivers/gpu/drm/gma500/gma_display.c dev_priv->ops->disable_sr(dev); dev_priv 313 drivers/gpu/drm/gma500/gma_display.c dev_priv->ops->update_wm(dev, crtc); dev_priv 325 drivers/gpu/drm/gma500/gma_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 385 drivers/gpu/drm/gma500/gma_display.c if (dev_priv->ops->cursor_needs_phys) { dev_priv 399 drivers/gpu/drm/gma500/gma_display.c tmp_dst = dev_priv->vram_addr + cursor_gt->offset; dev_priv 508 drivers/gpu/drm/gma500/gma_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 511 drivers/gpu/drm/gma500/gma_display.c if (!dev_priv->rpm_enabled) dev_priv 527 drivers/gpu/drm/gma500/gma_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 530 drivers/gpu/drm/gma500/gma_display.c const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; dev_priv 570 drivers/gpu/drm/gma500/gma_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 573 drivers/gpu/drm/gma500/gma_display.c const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; dev_priv 57 drivers/gpu/drm/gma500/gtt.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 60 drivers/gpu/drm/gma500/gtt.c offset = r->resource.start - dev_priv->gtt_mem->start; dev_priv 62 drivers/gpu/drm/gma500/gtt.c return dev_priv->gtt_map + (offset >> PAGE_SHIFT); dev_priv 126 drivers/gpu/drm/gma500/gtt.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 134 drivers/gpu/drm/gma500/gtt.c pte = psb_gtt_mask_pte(page_to_pfn(dev_priv->scratch_page), dev_priv 239 drivers/gpu/drm/gma500/gtt.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 240 drivers/gpu/drm/gma500/gtt.c u32 gpu_base = dev_priv->gtt.gatt_start; dev_priv 242 drivers/gpu/drm/gma500/gtt.c mutex_lock(&dev_priv->gtt_mutex); dev_priv 253 drivers/gpu/drm/gma500/gtt.c psb_mmu_insert_pages(psb_mmu_get_default_pd(dev_priv->mmu), dev_priv 259 drivers/gpu/drm/gma500/gtt.c mutex_unlock(&dev_priv->gtt_mutex); dev_priv 277 drivers/gpu/drm/gma500/gtt.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 278 drivers/gpu/drm/gma500/gtt.c u32 gpu_base = dev_priv->gtt.gatt_start; dev_priv 282 drivers/gpu/drm/gma500/gtt.c mutex_lock(&dev_priv->gtt_mutex); dev_priv 285 drivers/gpu/drm/gma500/gtt.c ret = gma_blt_wait_idle(dev_priv); dev_priv 295 drivers/gpu/drm/gma500/gtt.c psb_mmu_remove_pages(psb_mmu_get_default_pd(dev_priv->mmu), dev_priv 302 drivers/gpu/drm/gma500/gtt.c mutex_unlock(&dev_priv->gtt_mutex); dev_priv 327 drivers/gpu/drm/gma500/gtt.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 329 drivers/gpu/drm/gma500/gtt.c struct resource *r = dev_priv->gtt_mem; dev_priv 336 drivers/gpu/drm/gma500/gtt.c end = r->start + dev_priv->gtt.stolen_size - 1; dev_priv 339 drivers/gpu/drm/gma500/gtt.c start = r->start + dev_priv->gtt.stolen_size; dev_priv 352 drivers/gpu/drm/gma500/gtt.c ret = allocate_resource(dev_priv->gtt_mem, >->resource, dev_priv 384 drivers/gpu/drm/gma500/gtt.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 385 drivers/gpu/drm/gma500/gtt.c init_rwsem(&dev_priv->gtt.sem); dev_priv 390 drivers/gpu/drm/gma500/gtt.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 392 drivers/gpu/drm/gma500/gtt.c if (dev_priv->gtt_map) { dev_priv 393 drivers/gpu/drm/gma500/gtt.c iounmap(dev_priv->gtt_map); dev_priv 394 drivers/gpu/drm/gma500/gtt.c dev_priv->gtt_map = NULL; dev_priv 396 drivers/gpu/drm/gma500/gtt.c if (dev_priv->gtt_initialized) { dev_priv 398 drivers/gpu/drm/gma500/gtt.c dev_priv->gmch_ctrl); dev_priv 399 drivers/gpu/drm/gma500/gtt.c PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL); dev_priv 402 drivers/gpu/drm/gma500/gtt.c if (dev_priv->vram_addr) dev_priv 403 drivers/gpu/drm/gma500/gtt.c iounmap(dev_priv->gtt_map); dev_priv 408 drivers/gpu/drm/gma500/gtt.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 419 drivers/gpu/drm/gma500/gtt.c mutex_init(&dev_priv->gtt_mutex); dev_priv 420 drivers/gpu/drm/gma500/gtt.c mutex_init(&dev_priv->mmap_mutex); dev_priv 424 drivers/gpu/drm/gma500/gtt.c pg = &dev_priv->gtt; dev_priv 427 drivers/gpu/drm/gma500/gtt.c pci_read_config_word(dev->pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl); dev_priv 429 drivers/gpu/drm/gma500/gtt.c dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED); dev_priv 431 drivers/gpu/drm/gma500/gtt.c dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL); dev_priv 432 drivers/gpu/drm/gma500/gtt.c PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL); dev_priv 436 drivers/gpu/drm/gma500/gtt.c dev_priv->gtt_initialized = 1; dev_priv 438 drivers/gpu/drm/gma500/gtt.c pg->gtt_phys_start = dev_priv->pge_ctl & PAGE_MASK; dev_priv 455 drivers/gpu/drm/gma500/gtt.c pg->gtt_start = dev_priv->pge_ctl; dev_priv 461 drivers/gpu/drm/gma500/gtt.c dev_priv->gtt_mem = &dev->pdev->resource[PSB_GATT_RESOURCE]; dev_priv 479 drivers/gpu/drm/gma500/gtt.c dev_priv->gtt_mem = &fudge; dev_priv 482 drivers/gpu/drm/gma500/gtt.c pci_read_config_dword(dev->pdev, PSB_BSM, &dev_priv->stolen_base); dev_priv 483 drivers/gpu/drm/gma500/gtt.c vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base dev_priv 489 drivers/gpu/drm/gma500/gtt.c dev_priv->stolen_base, vram_stolen_size / 1024); dev_priv 500 drivers/gpu/drm/gma500/gtt.c dev_priv->vram_stolen_size = vram_stolen_size; dev_priv 506 drivers/gpu/drm/gma500/gtt.c dev_priv->gtt_map = ioremap_nocache(pg->gtt_phys_start, dev_priv 508 drivers/gpu/drm/gma500/gtt.c if (!dev_priv->gtt_map) { dev_priv 515 drivers/gpu/drm/gma500/gtt.c dev_priv->vram_addr = ioremap_wc(dev_priv->stolen_base, dev_priv 518 drivers/gpu/drm/gma500/gtt.c if (!dev_priv->vram_addr) { dev_priv 528 drivers/gpu/drm/gma500/gtt.c pfn_base = dev_priv->stolen_base >> PAGE_SHIFT; dev_priv 534 drivers/gpu/drm/gma500/gtt.c iowrite32(pte, dev_priv->gtt_map + i); dev_priv 541 drivers/gpu/drm/gma500/gtt.c pfn_base = page_to_pfn(dev_priv->scratch_page); dev_priv 544 drivers/gpu/drm/gma500/gtt.c iowrite32(pte, dev_priv->gtt_map + i); dev_priv 546 drivers/gpu/drm/gma500/gtt.c (void) ioread32(dev_priv->gtt_map + i - 1); dev_priv 556 drivers/gpu/drm/gma500/gtt.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 557 drivers/gpu/drm/gma500/gtt.c struct resource *r = dev_priv->gtt_mem->child; dev_priv 562 drivers/gpu/drm/gma500/gtt.c mutex_lock(&dev_priv->gtt_mutex); dev_priv 575 drivers/gpu/drm/gma500/gtt.c mutex_unlock(&dev_priv->gtt_mutex); dev_priv 45 drivers/gpu/drm/gma500/intel_bios.c parse_edp(struct drm_psb_private *dev_priv, struct bdb_header *bdb) dev_priv 54 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.bpp = 18; dev_priv 56 drivers/gpu/drm/gma500/intel_bios.c if (dev_priv->edp.support) { dev_priv 58 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.bpp); dev_priv 63 drivers/gpu/drm/gma500/intel_bios.c panel_type = dev_priv->panel_type; dev_priv 66 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.bpp = 18; dev_priv 69 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.bpp = 24; dev_priv 72 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.bpp = 30; dev_priv 80 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.pps = *edp_pps; dev_priv 83 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8, dev_priv 84 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.pps.t9, dev_priv->edp.pps.t10, dev_priv 85 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.pps.t11_t12); dev_priv 87 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.rate = edp_link_params->rate ? DP_LINK_BW_2_7 : dev_priv 91 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.lanes = 1; dev_priv 94 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.lanes = 2; dev_priv 98 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.lanes = 4; dev_priv 102 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); dev_priv 106 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0; dev_priv 109 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1; dev_priv 112 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2; dev_priv 115 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; dev_priv 120 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; dev_priv 123 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1; dev_priv 126 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2; dev_priv 129 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; dev_priv 133 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.vswing, dev_priv->edp.preemphasis); dev_priv 188 drivers/gpu/drm/gma500/intel_bios.c static void parse_backlight_data(struct drm_psb_private *dev_priv, dev_priv 198 drivers/gpu/drm/gma500/intel_bios.c dev_priv->lvds_bl = NULL; dev_priv 210 drivers/gpu/drm/gma500/intel_bios.c dev_err(dev_priv->dev->dev, "out of memory for backlight data\n"); dev_priv 213 drivers/gpu/drm/gma500/intel_bios.c dev_priv->lvds_bl = lvds_bl; dev_priv 217 drivers/gpu/drm/gma500/intel_bios.c static void parse_lfp_panel_data(struct drm_psb_private *dev_priv, dev_priv 227 drivers/gpu/drm/gma500/intel_bios.c dev_priv->lvds_dither = 0; dev_priv 228 drivers/gpu/drm/gma500/intel_bios.c dev_priv->lvds_vbt = 0; dev_priv 234 drivers/gpu/drm/gma500/intel_bios.c dev_priv->lvds_dither = lvds_options->pixel_dither; dev_priv 235 drivers/gpu/drm/gma500/intel_bios.c dev_priv->panel_type = lvds_options->panel_type; dev_priv 251 drivers/gpu/drm/gma500/intel_bios.c dev_err(dev_priv->dev->dev, "out of memory for fixed panel mode\n"); dev_priv 255 drivers/gpu/drm/gma500/intel_bios.c dev_priv->lvds_vbt = 1; dev_priv 259 drivers/gpu/drm/gma500/intel_bios.c dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode; dev_priv 262 drivers/gpu/drm/gma500/intel_bios.c dev_dbg(dev_priv->dev->dev, "ignoring invalid LVDS VBT\n"); dev_priv 263 drivers/gpu/drm/gma500/intel_bios.c dev_priv->lvds_vbt = 0; dev_priv 270 drivers/gpu/drm/gma500/intel_bios.c static void parse_sdvo_panel_data(struct drm_psb_private *dev_priv, dev_priv 277 drivers/gpu/drm/gma500/intel_bios.c dev_priv->sdvo_lvds_vbt_mode = NULL; dev_priv 295 drivers/gpu/drm/gma500/intel_bios.c dev_priv->sdvo_lvds_vbt_mode = panel_fixed_mode; dev_priv 300 drivers/gpu/drm/gma500/intel_bios.c static void parse_general_features(struct drm_psb_private *dev_priv, dev_priv 306 drivers/gpu/drm/gma500/intel_bios.c dev_priv->int_tv_support = 1; dev_priv 307 drivers/gpu/drm/gma500/intel_bios.c dev_priv->int_crt_support = 1; dev_priv 311 drivers/gpu/drm/gma500/intel_bios.c dev_priv->int_tv_support = general->int_tv_support; dev_priv 312 drivers/gpu/drm/gma500/intel_bios.c dev_priv->int_crt_support = general->int_crt_support; dev_priv 313 drivers/gpu/drm/gma500/intel_bios.c dev_priv->lvds_use_ssc = general->enable_ssc; dev_priv 315 drivers/gpu/drm/gma500/intel_bios.c if (dev_priv->lvds_use_ssc) { dev_priv 316 drivers/gpu/drm/gma500/intel_bios.c dev_priv->lvds_ssc_freq dev_priv 323 drivers/gpu/drm/gma500/intel_bios.c parse_sdvo_device_mapping(struct drm_psb_private *dev_priv, dev_priv 378 drivers/gpu/drm/gma500/intel_bios.c p_mapping = &(dev_priv->sdvo_mappings[p_child->dvo_port - 1]); dev_priv 414 drivers/gpu/drm/gma500/intel_bios.c parse_driver_features(struct drm_psb_private *dev_priv, dev_priv 424 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.support = 1; dev_priv 426 drivers/gpu/drm/gma500/intel_bios.c dev_priv->lvds_enabled_in_vbt = driver->lvds_config != 0; dev_priv 431 drivers/gpu/drm/gma500/intel_bios.c dev_priv->dplla_96mhz = true; dev_priv 433 drivers/gpu/drm/gma500/intel_bios.c dev_priv->dplla_96mhz = false; dev_priv 437 drivers/gpu/drm/gma500/intel_bios.c parse_device_mapping(struct drm_psb_private *dev_priv, dev_priv 479 drivers/gpu/drm/gma500/intel_bios.c dev_priv->child_dev = kcalloc(count, sizeof(*p_child), GFP_KERNEL); dev_priv 480 drivers/gpu/drm/gma500/intel_bios.c if (!dev_priv->child_dev) { dev_priv 485 drivers/gpu/drm/gma500/intel_bios.c dev_priv->child_dev_num = count; dev_priv 493 drivers/gpu/drm/gma500/intel_bios.c child_dev_ptr = dev_priv->child_dev + count; dev_priv 518 drivers/gpu/drm/gma500/intel_bios.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 527 drivers/gpu/drm/gma500/intel_bios.c dev_priv->panel_type = 0xff; dev_priv 530 drivers/gpu/drm/gma500/intel_bios.c if (dev_priv->opregion.vbt) { dev_priv 531 drivers/gpu/drm/gma500/intel_bios.c struct vbt_header *vbt = dev_priv->opregion.vbt; dev_priv 537 drivers/gpu/drm/gma500/intel_bios.c dev_priv->opregion.vbt = NULL; dev_priv 562 drivers/gpu/drm/gma500/intel_bios.c parse_general_features(dev_priv, bdb); dev_priv 563 drivers/gpu/drm/gma500/intel_bios.c parse_driver_features(dev_priv, bdb); dev_priv 564 drivers/gpu/drm/gma500/intel_bios.c parse_lfp_panel_data(dev_priv, bdb); dev_priv 565 drivers/gpu/drm/gma500/intel_bios.c parse_sdvo_panel_data(dev_priv, bdb); dev_priv 566 drivers/gpu/drm/gma500/intel_bios.c parse_sdvo_device_mapping(dev_priv, bdb); dev_priv 567 drivers/gpu/drm/gma500/intel_bios.c parse_device_mapping(dev_priv, bdb); dev_priv 568 drivers/gpu/drm/gma500/intel_bios.c parse_backlight_data(dev_priv, bdb); dev_priv 569 drivers/gpu/drm/gma500/intel_bios.c parse_edp(dev_priv, bdb); dev_priv 582 drivers/gpu/drm/gma500/intel_bios.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 584 drivers/gpu/drm/gma500/intel_bios.c kfree(dev_priv->sdvo_lvds_vbt_mode); dev_priv 585 drivers/gpu/drm/gma500/intel_bios.c kfree(dev_priv->lfp_lvds_vbt_mode); dev_priv 586 drivers/gpu/drm/gma500/intel_bios.c kfree(dev_priv->lvds_bl); dev_priv 55 drivers/gpu/drm/gma500/intel_gmbus.c #define GMBUS_REG_READ(reg) ioread32(dev_priv->gmbus_reg + (reg)) dev_priv 56 drivers/gpu/drm/gma500/intel_gmbus.c #define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg)) dev_priv 71 drivers/gpu/drm/gma500/intel_gmbus.c struct drm_psb_private *dev_priv; dev_priv 78 drivers/gpu/drm/gma500/intel_gmbus.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 82 drivers/gpu/drm/gma500/intel_gmbus.c static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable) dev_priv 105 drivers/gpu/drm/gma500/intel_gmbus.c struct drm_psb_private *dev_priv = gpio->dev_priv; dev_priv 119 drivers/gpu/drm/gma500/intel_gmbus.c struct drm_psb_private *dev_priv = gpio->dev_priv; dev_priv 129 drivers/gpu/drm/gma500/intel_gmbus.c struct drm_psb_private *dev_priv = gpio->dev_priv; dev_priv 139 drivers/gpu/drm/gma500/intel_gmbus.c struct drm_psb_private *dev_priv = gpio->dev_priv; dev_priv 156 drivers/gpu/drm/gma500/intel_gmbus.c struct drm_psb_private *dev_priv = gpio->dev_priv; dev_priv 171 drivers/gpu/drm/gma500/intel_gmbus.c intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin) dev_priv 193 drivers/gpu/drm/gma500/intel_gmbus.c gpio->dev_priv = dev_priv; dev_priv 199 drivers/gpu/drm/gma500/intel_gmbus.c gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev; dev_priv 219 drivers/gpu/drm/gma500/intel_gmbus.c intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv, dev_priv 229 drivers/gpu/drm/gma500/intel_gmbus.c gma_intel_i2c_reset(dev_priv->dev); dev_priv 231 drivers/gpu/drm/gma500/intel_gmbus.c intel_i2c_quirk_set(dev_priv, true); dev_priv 240 drivers/gpu/drm/gma500/intel_gmbus.c intel_i2c_quirk_set(dev_priv, false); dev_priv 253 drivers/gpu/drm/gma500/intel_gmbus.c struct drm_psb_private *dev_priv = adapter->algo_data; dev_priv 257 drivers/gpu/drm/gma500/intel_gmbus.c return intel_i2c_quirk_xfer(dev_priv, dev_priv 354 drivers/gpu/drm/gma500/intel_gmbus.c bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff); dev_priv 358 drivers/gpu/drm/gma500/intel_gmbus.c return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num); dev_priv 397 drivers/gpu/drm/gma500/intel_gmbus.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 400 drivers/gpu/drm/gma500/intel_gmbus.c dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus), dev_priv 402 drivers/gpu/drm/gma500/intel_gmbus.c if (dev_priv->gmbus == NULL) dev_priv 406 drivers/gpu/drm/gma500/intel_gmbus.c dev_priv->gmbus_reg = dev_priv->aux_reg; dev_priv 408 drivers/gpu/drm/gma500/intel_gmbus.c dev_priv->gmbus_reg = dev_priv->vdc_reg; dev_priv 411 drivers/gpu/drm/gma500/intel_gmbus.c struct intel_gmbus *bus = &dev_priv->gmbus[i]; dev_priv 421 drivers/gpu/drm/gma500/intel_gmbus.c bus->adapter.algo_data = dev_priv; dev_priv 432 drivers/gpu/drm/gma500/intel_gmbus.c bus->force_bit = intel_gpio_create(dev_priv, i); dev_priv 435 drivers/gpu/drm/gma500/intel_gmbus.c gma_intel_i2c_reset(dev_priv->dev); dev_priv 441 drivers/gpu/drm/gma500/intel_gmbus.c struct intel_gmbus *bus = &dev_priv->gmbus[i]; dev_priv 444 drivers/gpu/drm/gma500/intel_gmbus.c kfree(dev_priv->gmbus); dev_priv 445 drivers/gpu/drm/gma500/intel_gmbus.c dev_priv->gmbus = NULL; dev_priv 468 drivers/gpu/drm/gma500/intel_gmbus.c struct drm_psb_private *dev_priv = adapter->algo_data; dev_priv 469 drivers/gpu/drm/gma500/intel_gmbus.c bus->force_bit = intel_gpio_create(dev_priv, dev_priv 483 drivers/gpu/drm/gma500/intel_gmbus.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 486 drivers/gpu/drm/gma500/intel_gmbus.c if (dev_priv->gmbus == NULL) dev_priv 490 drivers/gpu/drm/gma500/intel_gmbus.c struct intel_gmbus *bus = &dev_priv->gmbus[i]; dev_priv 498 drivers/gpu/drm/gma500/intel_gmbus.c dev_priv->gmbus_reg = NULL; /* iounmap is done in driver_unload */ dev_priv 499 drivers/gpu/drm/gma500/intel_gmbus.c kfree(dev_priv->gmbus); dev_priv 500 drivers/gpu/drm/gma500/intel_gmbus.c dev_priv->gmbus = NULL; dev_priv 44 drivers/gpu/drm/gma500/mdfld_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 60 drivers/gpu/drm/gma500/mdfld_device.c adjusted_level = level * dev_priv->blc_adj2; dev_priv 62 drivers/gpu/drm/gma500/mdfld_device.c dev_priv->brightness_adjusted = adjusted_level; dev_priv 65 drivers/gpu/drm/gma500/mdfld_device.c if (dev_priv->dpi_panel_on[0] || dev_priv 66 drivers/gpu/drm/gma500/mdfld_device.c dev_priv->dpi_panel_on[2]) dev_priv 68 drivers/gpu/drm/gma500/mdfld_device.c dev_priv->brightness_adjusted); dev_priv 70 drivers/gpu/drm/gma500/mdfld_device.c if (dev_priv->dpi_panel_on[0]) dev_priv 72 drivers/gpu/drm/gma500/mdfld_device.c dev_priv->brightness_adjusted); dev_priv 75 drivers/gpu/drm/gma500/mdfld_device.c if (dev_priv->dpi_panel_on[2]) dev_priv 77 drivers/gpu/drm/gma500/mdfld_device.c dev_priv->brightness_adjusted); dev_priv 82 drivers/gpu/drm/gma500/mdfld_device.c dev_priv->brightness = level; dev_priv 90 drivers/gpu/drm/gma500/mdfld_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 92 drivers/gpu/drm/gma500/mdfld_device.c DRM_DEBUG_DRIVER("brightness = 0x%x \n", dev_priv->brightness); dev_priv 95 drivers/gpu/drm/gma500/mdfld_device.c return dev_priv->brightness; dev_priv 105 drivers/gpu/drm/gma500/mdfld_device.c struct drm_psb_private *dev_priv = (struct drm_psb_private *) dev_priv 108 drivers/gpu/drm/gma500/mdfld_device.c dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX; dev_priv 109 drivers/gpu/drm/gma500/mdfld_device.c dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX; dev_priv 158 drivers/gpu/drm/gma500/mdfld_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 159 drivers/gpu/drm/gma500/mdfld_device.c struct medfield_state *regs = &dev_priv->regs.mdfld; dev_priv 160 drivers/gpu/drm/gma500/mdfld_device.c struct psb_pipe *pipe = &dev_priv->regs.pipe[pipenum]; dev_priv 161 drivers/gpu/drm/gma500/mdfld_device.c const struct psb_offset *map = &dev_priv->regmap[pipenum]; dev_priv 235 drivers/gpu/drm/gma500/mdfld_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 237 drivers/gpu/drm/gma500/mdfld_device.c struct medfield_state *regs = &dev_priv->regs.mdfld; dev_priv 238 drivers/gpu/drm/gma500/mdfld_device.c struct psb_pipe *pipe = &dev_priv->regs.pipe[pipenum]; dev_priv 239 drivers/gpu/drm/gma500/mdfld_device.c const struct psb_offset *map = &dev_priv->regmap[pipenum]; dev_priv 254 drivers/gpu/drm/gma500/mdfld_device.c dsi_config = dev_priv->dsi_configs[0]; dev_priv 262 drivers/gpu/drm/gma500/mdfld_device.c dsi_config = dev_priv->dsi_configs[1]; dev_priv 510 drivers/gpu/drm/gma500/mdfld_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 513 drivers/gpu/drm/gma500/mdfld_device.c dev_priv->regmap = mdfld_regmap; dev_priv 121 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 125 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c u32 dspcntr = dev_priv->dspcntr[pipe]; dev_priv 183 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 185 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c if (!dev_priv->dpi_panel_on[pipe]) { dev_priv 204 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 206 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c if (dev_priv->dpi_panel_on[pipe]) { dev_priv 644 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 664 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c dev_priv->dpi_panel_on[pipe] = true; dev_priv 678 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c dev_priv->dpi_panel_on[pipe] = false; dev_priv 824 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 835 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c pipeconf = dev_priv->pipeconf[pipe]; dev_priv 836 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c dspcntr = dev_priv->dspcntr[pipe]; dev_priv 902 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c dev_priv->dpi_panel_on[pipe] = true; dev_priv 98 drivers/gpu/drm/gma500/mdfld_dsi_output.c struct drm_psb_private *dev_priv; dev_priv 107 drivers/gpu/drm/gma500/mdfld_dsi_output.c dev_priv = dev->dev_private; dev_priv 126 drivers/gpu/drm/gma500/mdfld_dsi_output.c dev_priv->mipi_ctrl_display = gen_ctrl_val; dev_priv 137 drivers/gpu/drm/gma500/mdfld_dsi_output.c struct drm_psb_private *dev_priv; dev_priv 149 drivers/gpu/drm/gma500/mdfld_dsi_output.c dev_priv = dev->dev_private; dev_priv 152 drivers/gpu/drm/gma500/mdfld_dsi_output.c dsi_config = dev_priv->dsi_configs[1]; dev_priv 154 drivers/gpu/drm/gma500/mdfld_dsi_output.c dsi_config = dev_priv->dsi_configs[0]; dev_priv 181 drivers/gpu/drm/gma500/mdfld_dsi_output.c gen_ctrl_val = dev_priv->mipi_ctrl_display; dev_priv 490 drivers/gpu/drm/gma500/mdfld_dsi_output.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 538 drivers/gpu/drm/gma500/mdfld_dsi_output.c if (pipe && dev_priv->dsi_configs[0]) { dev_priv 540 drivers/gpu/drm/gma500/mdfld_dsi_output.c dev_priv->dsi_configs[1] = dsi_config; dev_priv 543 drivers/gpu/drm/gma500/mdfld_dsi_output.c dev_priv->dsi_configs[0] = dsi_config; dev_priv 569 drivers/gpu/drm/gma500/mdfld_dsi_output.c dev_priv->backlight_property, dev_priv 599 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 600 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 44 drivers/gpu/drm/gma500/mdfld_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 45 drivers/gpu/drm/gma500/mdfld_intel_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 72 drivers/gpu/drm/gma500/mdfld_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 73 drivers/gpu/drm/gma500/mdfld_intel_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 158 drivers/gpu/drm/gma500/mdfld_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 162 drivers/gpu/drm/gma500/mdfld_intel_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 231 drivers/gpu/drm/gma500/mdfld_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 232 drivers/gpu/drm/gma500/mdfld_intel_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 298 drivers/gpu/drm/gma500/mdfld_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 301 drivers/gpu/drm/gma500/mdfld_intel_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 302 drivers/gpu/drm/gma500/mdfld_intel_display.c u32 pipeconf = dev_priv->pipeconf[pipe]; dev_priv 584 drivers/gpu/drm/gma500/mdfld_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 593 drivers/gpu/drm/gma500/mdfld_intel_display.c (dev_priv->core_freq == 166)) dev_priv 596 drivers/gpu/drm/gma500/mdfld_intel_display.c (dev_priv->core_freq == 100 || dev_priv 597 drivers/gpu/drm/gma500/mdfld_intel_display.c dev_priv->core_freq == 200)) dev_priv 605 drivers/gpu/drm/gma500/mdfld_intel_display.c (dev_priv->core_freq == 166)) dev_priv 608 drivers/gpu/drm/gma500/mdfld_intel_display.c (dev_priv->core_freq == 100 || dev_priv 609 drivers/gpu/drm/gma500/mdfld_intel_display.c dev_priv->core_freq == 200)) dev_priv 664 drivers/gpu/drm/gma500/mdfld_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 666 drivers/gpu/drm/gma500/mdfld_intel_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 845 drivers/gpu/drm/gma500/mdfld_intel_display.c dev_priv->pipeconf[pipe] = PIPEACONF_ENABLE; /* FIXME_JLIU7 REG_READ(pipeconf_reg); */ dev_priv 848 drivers/gpu/drm/gma500/mdfld_intel_display.c dev_priv->dspcntr[pipe] = REG_READ(map->cntr); dev_priv 849 drivers/gpu/drm/gma500/mdfld_intel_display.c dev_priv->dspcntr[pipe] |= pipe << DISPPLANE_SEL_PIPE_POS; dev_priv 850 drivers/gpu/drm/gma500/mdfld_intel_display.c dev_priv->dspcntr[pipe] |= DISPLAY_PLANE_ENABLE; dev_priv 872 drivers/gpu/drm/gma500/mdfld_intel_display.c dev_priv->core_freq == 166) { dev_priv 880 drivers/gpu/drm/gma500/mdfld_intel_display.c (dev_priv->core_freq == 100 || dev_priv 881 drivers/gpu/drm/gma500/mdfld_intel_display.c dev_priv->core_freq == 200)) { dev_priv 890 drivers/gpu/drm/gma500/mdfld_intel_display.c clk_byte = dev_priv->bpp / 8; dev_priv 892 drivers/gpu/drm/gma500/mdfld_intel_display.c clk_byte = dev_priv->bpp2 / 8; dev_priv 1000 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->conf, dev_priv->pipeconf[pipe]); dev_priv 1004 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]); dev_priv 36 drivers/gpu/drm/gma500/mdfld_output.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 37 drivers/gpu/drm/gma500/mdfld_output.c return dev_priv->mdfld_panel_id; dev_priv 64 drivers/gpu/drm/gma500/mdfld_output.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 67 drivers/gpu/drm/gma500/mdfld_output.c dev_priv->mdfld_panel_id = TC35876X; dev_priv 69 drivers/gpu/drm/gma500/mdfld_output.c mdfld_init_panel(dev, 0, dev_priv->mdfld_panel_id); dev_priv 38 drivers/gpu/drm/gma500/mdfld_tmd_vid.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 39 drivers/gpu/drm/gma500/mdfld_tmd_vid.c struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD; dev_priv 21 drivers/gpu/drm/gma500/mid_bios.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 47 drivers/gpu/drm/gma500/mid_bios.c dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE; dev_priv 50 drivers/gpu/drm/gma500/mid_bios.c dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display"); dev_priv 53 drivers/gpu/drm/gma500/mid_bios.c if (dev_priv->iLVDS_enable) { dev_priv 54 drivers/gpu/drm/gma500/mid_bios.c dev_priv->is_lvds_on = true; dev_priv 55 drivers/gpu/drm/gma500/mid_bios.c dev_priv->is_mipi_on = false; dev_priv 57 drivers/gpu/drm/gma500/mid_bios.c dev_priv->is_mipi_on = true; dev_priv 58 drivers/gpu/drm/gma500/mid_bios.c dev_priv->is_lvds_on = false; dev_priv 61 drivers/gpu/drm/gma500/mid_bios.c dev_priv->video_device_fuse = fuse_value; dev_priv 69 drivers/gpu/drm/gma500/mid_bios.c dev_priv->fuse_reg_value = fuse_value; dev_priv 73 drivers/gpu/drm/gma500/mid_bios.c dev_priv->core_freq = 200; dev_priv 76 drivers/gpu/drm/gma500/mid_bios.c dev_priv->core_freq = 100; dev_priv 79 drivers/gpu/drm/gma500/mid_bios.c dev_priv->core_freq = 166; dev_priv 84 drivers/gpu/drm/gma500/mid_bios.c dev_priv->core_freq = 0; dev_priv 86 drivers/gpu/drm/gma500/mid_bios.c dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq); dev_priv 93 drivers/gpu/drm/gma500/mid_bios.c static void mid_get_pci_revID(struct drm_psb_private *dev_priv) dev_priv 96 drivers/gpu/drm/gma500/mid_bios.c int domain = pci_domain_nr(dev_priv->dev->pdev->bus); dev_priv 105 drivers/gpu/drm/gma500/mid_bios.c dev_priv->platform_rev_id = (uint8_t) platform_rev_id; dev_priv 107 drivers/gpu/drm/gma500/mid_bios.c dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n", dev_priv 108 drivers/gpu/drm/gma500/mid_bios.c dev_priv->platform_rev_id); dev_priv 161 drivers/gpu/drm/gma500/mid_bios.c static int mid_get_vbt_data_r0(struct drm_psb_private *dev_priv, u32 addr) dev_priv 178 drivers/gpu/drm/gma500/mid_bios.c dev_priv->gct_data.bpi = bpi; dev_priv 179 drivers/gpu/drm/gma500/mid_bios.c dev_priv->gct_data.pt = gct.PD.PanelType; dev_priv 180 drivers/gpu/drm/gma500/mid_bios.c dev_priv->gct_data.DTD = gct.panel[bpi].DTD; dev_priv 181 drivers/gpu/drm/gma500/mid_bios.c dev_priv->gct_data.Panel_Port_Control = dev_priv 183 drivers/gpu/drm/gma500/mid_bios.c dev_priv->gct_data.Panel_MIPI_Display_Descriptor = dev_priv 189 drivers/gpu/drm/gma500/mid_bios.c static int mid_get_vbt_data_r1(struct drm_psb_private *dev_priv, u32 addr) dev_priv 206 drivers/gpu/drm/gma500/mid_bios.c dev_priv->gct_data.bpi = bpi; dev_priv 207 drivers/gpu/drm/gma500/mid_bios.c dev_priv->gct_data.pt = gct.PD.PanelType; dev_priv 208 drivers/gpu/drm/gma500/mid_bios.c dev_priv->gct_data.DTD = gct.panel[bpi].DTD; dev_priv 209 drivers/gpu/drm/gma500/mid_bios.c dev_priv->gct_data.Panel_Port_Control = dev_priv 211 drivers/gpu/drm/gma500/mid_bios.c dev_priv->gct_data.Panel_MIPI_Display_Descriptor = dev_priv 217 drivers/gpu/drm/gma500/mid_bios.c static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv, u32 addr) dev_priv 222 drivers/gpu/drm/gma500/mid_bios.c struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD; dev_priv 240 drivers/gpu/drm/gma500/mid_bios.c dev_priv->gct_data.bpi = vbt.primary_panel_idx; dev_priv 241 drivers/gpu/drm/gma500/mid_bios.c dev_priv->gct_data.Panel_MIPI_Display_Descriptor = dev_priv 269 drivers/gpu/drm/gma500/mid_bios.c static void mid_get_vbt_data(struct drm_psb_private *dev_priv) dev_priv 271 drivers/gpu/drm/gma500/mid_bios.c struct drm_device *dev = dev_priv->dev; dev_priv 304 drivers/gpu/drm/gma500/mid_bios.c ret = mid_get_vbt_data_r0(dev_priv, addr); dev_priv 307 drivers/gpu/drm/gma500/mid_bios.c ret = mid_get_vbt_data_r1(dev_priv, addr); dev_priv 310 drivers/gpu/drm/gma500/mid_bios.c ret = mid_get_vbt_data_r10(dev_priv, addr); dev_priv 320 drivers/gpu/drm/gma500/mid_bios.c dev_priv->has_gct = true; dev_priv 325 drivers/gpu/drm/gma500/mid_bios.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 327 drivers/gpu/drm/gma500/mid_bios.c mid_get_vbt_data(dev_priv); dev_priv 328 drivers/gpu/drm/gma500/mid_bios.c mid_get_pci_revID(dev_priv); dev_priv 77 drivers/gpu/drm/gma500/mmu.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 105 drivers/gpu/drm/gma500/mmu.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 131 drivers/gpu/drm/gma500/mmu.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 241 drivers/gpu/drm/gma500/mmu.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 431 drivers/gpu/drm/gma500/mmu.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 444 drivers/gpu/drm/gma500/mmu.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 85 drivers/gpu/drm/gma500/oaktrail_crtc.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 89 drivers/gpu/drm/gma500/oaktrail_crtc.c switch (dev_priv->core_freq) { dev_priv 217 drivers/gpu/drm/gma500/oaktrail_crtc.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 220 drivers/gpu/drm/gma500/oaktrail_crtc.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 364 drivers/gpu/drm/gma500/oaktrail_crtc.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 366 drivers/gpu/drm/gma500/oaktrail_crtc.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 501 drivers/gpu/drm/gma500/oaktrail_crtc.c refclk = is_sdvo ? 96000 : dev_priv->core_freq * 1000; dev_priv 592 drivers/gpu/drm/gma500/oaktrail_crtc.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 596 drivers/gpu/drm/gma500/oaktrail_crtc.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 26 drivers/gpu/drm/gma500/oaktrail_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 27 drivers/gpu/drm/gma500/oaktrail_device.c if (dev_priv->iLVDS_enable) dev_priv 28 drivers/gpu/drm/gma500/oaktrail_device.c oaktrail_lvds_init(dev, &dev_priv->mode_dev); dev_priv 31 drivers/gpu/drm/gma500/oaktrail_device.c if (dev_priv->hdmi_priv) dev_priv 32 drivers/gpu/drm/gma500/oaktrail_device.c oaktrail_hdmi_init(dev, &dev_priv->mode_dev); dev_priv 57 drivers/gpu/drm/gma500/oaktrail_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 74 drivers/gpu/drm/gma500/oaktrail_device.c blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1; dev_priv 80 drivers/gpu/drm/gma500/oaktrail_device.c blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2; dev_priv 102 drivers/gpu/drm/gma500/oaktrail_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 108 drivers/gpu/drm/gma500/oaktrail_device.c dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX; dev_priv 109 drivers/gpu/drm/gma500/oaktrail_device.c dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX; dev_priv 114 drivers/gpu/drm/gma500/oaktrail_device.c core_clock = dev_priv->core_freq; dev_priv 139 drivers/gpu/drm/gma500/oaktrail_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 161 drivers/gpu/drm/gma500/oaktrail_device.c dev_priv->backlight_device = oaktrail_backlight_device; dev_priv 181 drivers/gpu/drm/gma500/oaktrail_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 182 drivers/gpu/drm/gma500/oaktrail_device.c struct psb_save_area *regs = &dev_priv->regs; dev_priv 226 drivers/gpu/drm/gma500/oaktrail_device.c if (dev_priv->hdmi_priv) dev_priv 260 drivers/gpu/drm/gma500/oaktrail_device.c if (dev_priv->iLVDS_enable) { dev_priv 295 drivers/gpu/drm/gma500/oaktrail_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 296 drivers/gpu/drm/gma500/oaktrail_device.c struct psb_save_area *regs = &dev_priv->regs; dev_priv 336 drivers/gpu/drm/gma500/oaktrail_device.c if (dev_priv->iLVDS_enable) dev_priv 357 drivers/gpu/drm/gma500/oaktrail_device.c if (dev_priv->hdmi_priv) dev_priv 360 drivers/gpu/drm/gma500/oaktrail_device.c if (dev_priv->iLVDS_enable) { dev_priv 410 drivers/gpu/drm/gma500/oaktrail_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 415 drivers/gpu/drm/gma500/oaktrail_device.c outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC); dev_priv 418 drivers/gpu/drm/gma500/oaktrail_device.c pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); dev_priv 434 drivers/gpu/drm/gma500/oaktrail_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 438 drivers/gpu/drm/gma500/oaktrail_device.c pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC); dev_priv 440 drivers/gpu/drm/gma500/oaktrail_device.c outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC)); dev_priv 443 drivers/gpu/drm/gma500/oaktrail_device.c pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); dev_priv 506 drivers/gpu/drm/gma500/oaktrail_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 512 drivers/gpu/drm/gma500/oaktrail_device.c dev_priv->regmap = oaktrail_regmap; dev_priv 517 drivers/gpu/drm/gma500/oaktrail_device.c if (!dev_priv->has_gct) { dev_priv 529 drivers/gpu/drm/gma500/oaktrail_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 533 drivers/gpu/drm/gma500/oaktrail_device.c if (!dev_priv->has_gct) dev_priv 132 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 133 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; dev_priv 147 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 148 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; dev_priv 268 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 269 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; dev_priv 498 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 499 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; dev_priv 533 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 534 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; dev_priv 685 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 723 drivers/gpu/drm/gma500/oaktrail_hdmi.c dev_priv->hdmi_priv = hdmi_dev; dev_priv 738 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 739 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; dev_priv 755 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 756 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; dev_priv 757 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct psb_state *regs = &dev_priv->regs.psb; dev_priv 758 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct psb_pipe *pipeb = &dev_priv->regs.pipe[1]; dev_priv 808 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 809 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; dev_priv 810 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct psb_state *regs = &dev_priv->regs.psb; dev_priv 811 drivers/gpu/drm/gma500/oaktrail_hdmi.c struct psb_pipe *pipeb = &dev_priv->regs.pipe[1]; dev_priv 38 drivers/gpu/drm/gma500/oaktrail_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 49 drivers/gpu/drm/gma500/oaktrail_lvds.c dev_priv->is_lvds_on = true; dev_priv 50 drivers/gpu/drm/gma500/oaktrail_lvds.c if (dev_priv->ops->lvds_bl_power) dev_priv 51 drivers/gpu/drm/gma500/oaktrail_lvds.c dev_priv->ops->lvds_bl_power(dev, true); dev_priv 53 drivers/gpu/drm/gma500/oaktrail_lvds.c if (dev_priv->ops->lvds_bl_power) dev_priv 54 drivers/gpu/drm/gma500/oaktrail_lvds.c dev_priv->ops->lvds_bl_power(dev, false); dev_priv 60 drivers/gpu/drm/gma500/oaktrail_lvds.c dev_priv->is_lvds_on = false; dev_priv 84 drivers/gpu/drm/gma500/oaktrail_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 85 drivers/gpu/drm/gma500/oaktrail_lvds.c struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; dev_priv 107 drivers/gpu/drm/gma500/oaktrail_lvds.c if (mode_dev->panel_wants_dither || dev_priv->lvds_dither) dev_priv 155 drivers/gpu/drm/gma500/oaktrail_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 157 drivers/gpu/drm/gma500/oaktrail_lvds.c struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; dev_priv 171 drivers/gpu/drm/gma500/oaktrail_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 181 drivers/gpu/drm/gma500/oaktrail_lvds.c ret = ((dev_priv->regs.saveBLC_PWM_CTL & dev_priv 191 drivers/gpu/drm/gma500/oaktrail_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 193 drivers/gpu/drm/gma500/oaktrail_lvds.c struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; dev_priv 215 drivers/gpu/drm/gma500/oaktrail_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 216 drivers/gpu/drm/gma500/oaktrail_lvds.c struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD; dev_priv 221 drivers/gpu/drm/gma500/oaktrail_lvds.c if (dev_priv->has_gct) { dev_priv 266 drivers/gpu/drm/gma500/oaktrail_lvds.c if (dev_priv->lfp_lvds_vbt_mode) dev_priv 269 drivers/gpu/drm/gma500/oaktrail_lvds.c dev_priv->lfp_lvds_vbt_mode); dev_priv 293 drivers/gpu/drm/gma500/oaktrail_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 308 drivers/gpu/drm/gma500/oaktrail_lvds.c dev_priv->is_lvds_on = true; dev_priv 330 drivers/gpu/drm/gma500/oaktrail_lvds.c dev_priv->backlight_property, dev_priv 334 drivers/gpu/drm/gma500/oaktrail_lvds.c if (dev_priv->has_gct) dev_priv 335 drivers/gpu/drm/gma500/oaktrail_lvds.c mode_dev->panel_wants_dither = (dev_priv->gct_data. dev_priv 337 drivers/gpu/drm/gma500/oaktrail_lvds.c if (dev_priv->lvds_dither) dev_priv 352 drivers/gpu/drm/gma500/oaktrail_lvds.c i2c_adap = i2c_get_adapter(dev_priv->ops->i2c_bus); dev_priv 355 drivers/gpu/drm/gma500/oaktrail_lvds.c if (edid == NULL && dev_priv->lpc_gpio_base) { dev_priv 136 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 144 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c chan->reg = dev_priv->lpc_gpio_base; dev_priv 150 drivers/gpu/drm/gma500/opregion.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 151 drivers/gpu/drm/gma500/opregion.c struct opregion_asle *asle = dev_priv->opregion.asle; dev_priv 152 drivers/gpu/drm/gma500/opregion.c struct backlight_device *bd = dev_priv->backlight_device; dev_priv 177 drivers/gpu/drm/gma500/opregion.c struct drm_psb_private *dev_priv = dev_priv 193 drivers/gpu/drm/gma500/opregion.c asle_stat |= asle_set_backlight(dev_priv->dev, asle->bclp); dev_priv 201 drivers/gpu/drm/gma500/opregion.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 203 drivers/gpu/drm/gma500/opregion.c if (dev_priv->opregion.asle) dev_priv 204 drivers/gpu/drm/gma500/opregion.c schedule_work(&dev_priv->opregion.asle_work); dev_priv 214 drivers/gpu/drm/gma500/opregion.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 215 drivers/gpu/drm/gma500/opregion.c struct opregion_asle *asle = dev_priv->opregion.asle; dev_priv 220 drivers/gpu/drm/gma500/opregion.c psb_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE); dev_priv 221 drivers/gpu/drm/gma500/opregion.c psb_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE); dev_priv 261 drivers/gpu/drm/gma500/opregion.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 262 drivers/gpu/drm/gma500/opregion.c struct psb_intel_opregion *opregion = &dev_priv->opregion; dev_priv 281 drivers/gpu/drm/gma500/opregion.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 282 drivers/gpu/drm/gma500/opregion.c struct psb_intel_opregion *opregion = &dev_priv->opregion; dev_priv 307 drivers/gpu/drm/gma500/opregion.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 308 drivers/gpu/drm/gma500/opregion.c struct psb_intel_opregion *opregion = &dev_priv->opregion; dev_priv 49 drivers/gpu/drm/gma500/power.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 52 drivers/gpu/drm/gma500/power.c dev_priv->apm_base = dev_priv->apm_reg & 0xffff; dev_priv 53 drivers/gpu/drm/gma500/power.c dev_priv->ospm_base &= 0xffff; dev_priv 55 drivers/gpu/drm/gma500/power.c dev_priv->display_power = true; /* We start active */ dev_priv 56 drivers/gpu/drm/gma500/power.c dev_priv->display_count = 0; /* Currently no users */ dev_priv 57 drivers/gpu/drm/gma500/power.c dev_priv->suspended = false; /* And not suspended */ dev_priv 61 drivers/gpu/drm/gma500/power.c if (dev_priv->ops->init_pm) dev_priv 62 drivers/gpu/drm/gma500/power.c dev_priv->ops->init_pm(dev); dev_priv 85 drivers/gpu/drm/gma500/power.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 87 drivers/gpu/drm/gma500/power.c if (dev_priv->suspended) dev_priv 89 drivers/gpu/drm/gma500/power.c dev_priv->ops->save_regs(dev); dev_priv 90 drivers/gpu/drm/gma500/power.c dev_priv->ops->power_down(dev); dev_priv 91 drivers/gpu/drm/gma500/power.c dev_priv->display_power = false; dev_priv 103 drivers/gpu/drm/gma500/power.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 106 drivers/gpu/drm/gma500/power.c dev_priv->ops->power_up(dev); dev_priv 107 drivers/gpu/drm/gma500/power.c dev_priv->suspended = false; dev_priv 108 drivers/gpu/drm/gma500/power.c dev_priv->display_power = true; dev_priv 110 drivers/gpu/drm/gma500/power.c PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL); dev_priv 112 drivers/gpu/drm/gma500/power.c dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED); dev_priv 115 drivers/gpu/drm/gma500/power.c dev_priv->ops->restore_regs(dev); dev_priv 127 drivers/gpu/drm/gma500/power.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 130 drivers/gpu/drm/gma500/power.c if (dev_priv->suspended) dev_priv 135 drivers/gpu/drm/gma500/power.c dev_priv->regs.saveBSM = bsm; dev_priv 137 drivers/gpu/drm/gma500/power.c dev_priv->regs.saveVBT = vbt; dev_priv 138 drivers/gpu/drm/gma500/power.c pci_read_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, &dev_priv->msi_addr); dev_priv 139 drivers/gpu/drm/gma500/power.c pci_read_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, &dev_priv->msi_data); dev_priv 144 drivers/gpu/drm/gma500/power.c dev_priv->suspended = true; dev_priv 157 drivers/gpu/drm/gma500/power.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 160 drivers/gpu/drm/gma500/power.c if (!dev_priv->suspended) dev_priv 165 drivers/gpu/drm/gma500/power.c pci_write_config_dword(pdev, 0x5c, dev_priv->regs.saveBSM); dev_priv 166 drivers/gpu/drm/gma500/power.c pci_write_config_dword(pdev, 0xFC, dev_priv->regs.saveVBT); dev_priv 168 drivers/gpu/drm/gma500/power.c pci_write_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, dev_priv->msi_addr); dev_priv 169 drivers/gpu/drm/gma500/power.c pci_write_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, dev_priv->msi_data); dev_priv 175 drivers/gpu/drm/gma500/power.c dev_priv->suspended = false; dev_priv 176 drivers/gpu/drm/gma500/power.c return !dev_priv->suspended; dev_priv 192 drivers/gpu/drm/gma500/power.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 195 drivers/gpu/drm/gma500/power.c if (!dev_priv->suspended) { dev_priv 196 drivers/gpu/drm/gma500/power.c if (dev_priv->display_count) { dev_priv 237 drivers/gpu/drm/gma500/power.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 238 drivers/gpu/drm/gma500/power.c return dev_priv->display_power; dev_priv 251 drivers/gpu/drm/gma500/power.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 257 drivers/gpu/drm/gma500/power.c if (dev_priv->display_power) { dev_priv 258 drivers/gpu/drm/gma500/power.c dev_priv->display_count++; dev_priv 272 drivers/gpu/drm/gma500/power.c dev_priv->display_count++; dev_priv 290 drivers/gpu/drm/gma500/power.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 293 drivers/gpu/drm/gma500/power.c dev_priv->display_count--; dev_priv 294 drivers/gpu/drm/gma500/power.c WARN_ON(dev_priv->display_count < 0); dev_priv 312 drivers/gpu/drm/gma500/power.c struct drm_psb_private *dev_priv = drmdev->dev_private; dev_priv 313 drivers/gpu/drm/gma500/power.c if (dev_priv->display_count) dev_priv 21 drivers/gpu/drm/gma500/psb_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 22 drivers/gpu/drm/gma500/psb_device.c psb_intel_lvds_init(dev, &dev_priv->mode_dev); dev_priv 58 drivers/gpu/drm/gma500/psb_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 67 drivers/gpu/drm/gma500/psb_device.c if (!dev_priv->lvds_bl) { dev_priv 71 drivers/gpu/drm/gma500/psb_device.c bl_max_freq = dev_priv->lvds_bl->freq; dev_priv 74 drivers/gpu/drm/gma500/psb_device.c core_clock = dev_priv->core_freq; dev_priv 113 drivers/gpu/drm/gma500/psb_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 135 drivers/gpu/drm/gma500/psb_device.c dev_priv->backlight_device = psb_backlight_device; dev_priv 138 drivers/gpu/drm/gma500/psb_device.c psb_lid_timer_init(dev_priv); dev_priv 152 drivers/gpu/drm/gma500/psb_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 170 drivers/gpu/drm/gma500/psb_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 173 drivers/gpu/drm/gma500/psb_device.c struct psb_state *regs = &dev_priv->regs.psb; dev_priv 189 drivers/gpu/drm/gma500/psb_device.c dev_priv->ops->save_crtc(crtc); dev_priv 208 drivers/gpu/drm/gma500/psb_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 211 drivers/gpu/drm/gma500/psb_device.c struct psb_state *regs = &dev_priv->regs.psb; dev_priv 229 drivers/gpu/drm/gma500/psb_device.c dev_priv->ops->restore_crtc(crtc); dev_priv 303 drivers/gpu/drm/gma500/psb_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 304 drivers/gpu/drm/gma500/psb_device.c dev_priv->regmap = psb_regmap; dev_priv 314 drivers/gpu/drm/gma500/psb_device.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 315 drivers/gpu/drm/gma500/psb_device.c psb_lid_timer_takedown(dev_priv); dev_priv 109 drivers/gpu/drm/gma500/psb_drv.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 110 drivers/gpu/drm/gma500/psb_drv.c struct psb_gtt *pg = &dev_priv->gtt; dev_priv 123 drivers/gpu/drm/gma500/psb_drv.c dev_priv->gatt_free_offset = pg->mmu_gatt_start + dev_priv 126 drivers/gpu/drm/gma500/psb_drv.c spin_lock_init(&dev_priv->irqmask_lock); dev_priv 127 drivers/gpu/drm/gma500/psb_drv.c spin_lock_init(&dev_priv->lock_2d); dev_priv 138 drivers/gpu/drm/gma500/psb_drv.c psb_spank(dev_priv); dev_priv 149 drivers/gpu/drm/gma500/psb_drv.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 153 drivers/gpu/drm/gma500/psb_drv.c if (dev_priv) { dev_priv 154 drivers/gpu/drm/gma500/psb_drv.c if (dev_priv->backlight_device) dev_priv 158 drivers/gpu/drm/gma500/psb_drv.c if (dev_priv->ops->chip_teardown) dev_priv 159 drivers/gpu/drm/gma500/psb_drv.c dev_priv->ops->chip_teardown(dev); dev_priv 163 drivers/gpu/drm/gma500/psb_drv.c if (dev_priv->pf_pd) { dev_priv 164 drivers/gpu/drm/gma500/psb_drv.c psb_mmu_free_pagedir(dev_priv->pf_pd); dev_priv 165 drivers/gpu/drm/gma500/psb_drv.c dev_priv->pf_pd = NULL; dev_priv 167 drivers/gpu/drm/gma500/psb_drv.c if (dev_priv->mmu) { dev_priv 168 drivers/gpu/drm/gma500/psb_drv.c struct psb_gtt *pg = &dev_priv->gtt; dev_priv 173 drivers/gpu/drm/gma500/psb_drv.c (dev_priv->mmu), dev_priv 175 drivers/gpu/drm/gma500/psb_drv.c dev_priv->vram_stolen_size >> PAGE_SHIFT); dev_priv 177 drivers/gpu/drm/gma500/psb_drv.c psb_mmu_driver_takedown(dev_priv->mmu); dev_priv 178 drivers/gpu/drm/gma500/psb_drv.c dev_priv->mmu = NULL; dev_priv 181 drivers/gpu/drm/gma500/psb_drv.c if (dev_priv->scratch_page) { dev_priv 182 drivers/gpu/drm/gma500/psb_drv.c set_pages_wb(dev_priv->scratch_page, 1); dev_priv 183 drivers/gpu/drm/gma500/psb_drv.c __free_page(dev_priv->scratch_page); dev_priv 184 drivers/gpu/drm/gma500/psb_drv.c dev_priv->scratch_page = NULL; dev_priv 186 drivers/gpu/drm/gma500/psb_drv.c if (dev_priv->vdc_reg) { dev_priv 187 drivers/gpu/drm/gma500/psb_drv.c iounmap(dev_priv->vdc_reg); dev_priv 188 drivers/gpu/drm/gma500/psb_drv.c dev_priv->vdc_reg = NULL; dev_priv 190 drivers/gpu/drm/gma500/psb_drv.c if (dev_priv->sgx_reg) { dev_priv 191 drivers/gpu/drm/gma500/psb_drv.c iounmap(dev_priv->sgx_reg); dev_priv 192 drivers/gpu/drm/gma500/psb_drv.c dev_priv->sgx_reg = NULL; dev_priv 194 drivers/gpu/drm/gma500/psb_drv.c if (dev_priv->aux_reg) { dev_priv 195 drivers/gpu/drm/gma500/psb_drv.c iounmap(dev_priv->aux_reg); dev_priv 196 drivers/gpu/drm/gma500/psb_drv.c dev_priv->aux_reg = NULL; dev_priv 198 drivers/gpu/drm/gma500/psb_drv.c pci_dev_put(dev_priv->aux_pdev); dev_priv 199 drivers/gpu/drm/gma500/psb_drv.c pci_dev_put(dev_priv->lpc_pdev); dev_priv 204 drivers/gpu/drm/gma500/psb_drv.c kfree(dev_priv); dev_priv 212 drivers/gpu/drm/gma500/psb_drv.c struct drm_psb_private *dev_priv; dev_priv 221 drivers/gpu/drm/gma500/psb_drv.c dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); dev_priv 222 drivers/gpu/drm/gma500/psb_drv.c if (dev_priv == NULL) dev_priv 225 drivers/gpu/drm/gma500/psb_drv.c dev_priv->ops = (struct psb_ops *)flags; dev_priv 226 drivers/gpu/drm/gma500/psb_drv.c dev_priv->dev = dev; dev_priv 227 drivers/gpu/drm/gma500/psb_drv.c dev->dev_private = (void *) dev_priv; dev_priv 229 drivers/gpu/drm/gma500/psb_drv.c pg = &dev_priv->gtt; dev_priv 233 drivers/gpu/drm/gma500/psb_drv.c dev_priv->num_pipe = dev_priv->ops->pipes; dev_priv 237 drivers/gpu/drm/gma500/psb_drv.c dev_priv->vdc_reg = dev_priv 239 drivers/gpu/drm/gma500/psb_drv.c if (!dev_priv->vdc_reg) dev_priv 242 drivers/gpu/drm/gma500/psb_drv.c dev_priv->sgx_reg = ioremap(resource_start + dev_priv->ops->sgx_offset, dev_priv 244 drivers/gpu/drm/gma500/psb_drv.c if (!dev_priv->sgx_reg) dev_priv 250 drivers/gpu/drm/gma500/psb_drv.c dev_priv->aux_pdev = dev_priv 254 drivers/gpu/drm/gma500/psb_drv.c if (dev_priv->aux_pdev) { dev_priv 255 drivers/gpu/drm/gma500/psb_drv.c resource_start = pci_resource_start(dev_priv->aux_pdev, dev_priv 257 drivers/gpu/drm/gma500/psb_drv.c resource_len = pci_resource_len(dev_priv->aux_pdev, dev_priv 259 drivers/gpu/drm/gma500/psb_drv.c dev_priv->aux_reg = ioremap_nocache(resource_start, dev_priv 261 drivers/gpu/drm/gma500/psb_drv.c if (!dev_priv->aux_reg) dev_priv 267 drivers/gpu/drm/gma500/psb_drv.c dev_priv->aux_reg = dev_priv->vdc_reg; dev_priv 270 drivers/gpu/drm/gma500/psb_drv.c dev_priv->gmbus_reg = dev_priv->aux_reg; dev_priv 272 drivers/gpu/drm/gma500/psb_drv.c dev_priv->lpc_pdev = dev_priv 275 drivers/gpu/drm/gma500/psb_drv.c if (dev_priv->lpc_pdev) { dev_priv 276 drivers/gpu/drm/gma500/psb_drv.c pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA, dev_priv 277 drivers/gpu/drm/gma500/psb_drv.c &dev_priv->lpc_gpio_base); dev_priv 278 drivers/gpu/drm/gma500/psb_drv.c pci_write_config_dword(dev_priv->lpc_pdev, PSB_LPC_GBA, dev_priv 279 drivers/gpu/drm/gma500/psb_drv.c (u32)dev_priv->lpc_gpio_base | (1L<<31)); dev_priv 280 drivers/gpu/drm/gma500/psb_drv.c pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA, dev_priv 281 drivers/gpu/drm/gma500/psb_drv.c &dev_priv->lpc_gpio_base); dev_priv 282 drivers/gpu/drm/gma500/psb_drv.c dev_priv->lpc_gpio_base &= 0xffc0; dev_priv 283 drivers/gpu/drm/gma500/psb_drv.c if (dev_priv->lpc_gpio_base) dev_priv 285 drivers/gpu/drm/gma500/psb_drv.c dev_priv->lpc_gpio_base); dev_priv 287 drivers/gpu/drm/gma500/psb_drv.c pci_dev_put(dev_priv->lpc_pdev); dev_priv 288 drivers/gpu/drm/gma500/psb_drv.c dev_priv->lpc_pdev = NULL; dev_priv 292 drivers/gpu/drm/gma500/psb_drv.c dev_priv->gmbus_reg = dev_priv->vdc_reg; dev_priv 297 drivers/gpu/drm/gma500/psb_drv.c ret = dev_priv->ops->chip_setup(dev); dev_priv 306 drivers/gpu/drm/gma500/psb_drv.c dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO); dev_priv 307 drivers/gpu/drm/gma500/psb_drv.c if (!dev_priv->scratch_page) dev_priv 310 drivers/gpu/drm/gma500/psb_drv.c set_pages_uc(dev_priv->scratch_page, 1); dev_priv 316 drivers/gpu/drm/gma500/psb_drv.c dev_priv->mmu = psb_mmu_driver_init(dev, 1, 0, 0); dev_priv 317 drivers/gpu/drm/gma500/psb_drv.c if (!dev_priv->mmu) dev_priv 320 drivers/gpu/drm/gma500/psb_drv.c dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0); dev_priv 321 drivers/gpu/drm/gma500/psb_drv.c if (!dev_priv->pf_pd) dev_priv 330 drivers/gpu/drm/gma500/psb_drv.c ret = psb_mmu_insert_pfn_sequence(psb_mmu_get_default_pd(dev_priv->mmu), dev_priv 331 drivers/gpu/drm/gma500/psb_drv.c dev_priv->stolen_base >> PAGE_SHIFT, dev_priv 336 drivers/gpu/drm/gma500/psb_drv.c psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0); dev_priv 337 drivers/gpu/drm/gma500/psb_drv.c psb_mmu_set_pd_context(dev_priv->pf_pd, 1); dev_priv 345 drivers/gpu/drm/gma500/psb_drv.c ret = drm_vblank_init(dev, dev_priv->num_pipe); dev_priv 353 drivers/gpu/drm/gma500/psb_drv.c dev_priv->vdc_irq_mask = 0; dev_priv 354 drivers/gpu/drm/gma500/psb_drv.c dev_priv->pipestat[0] = 0; dev_priv 355 drivers/gpu/drm/gma500/psb_drv.c dev_priv->pipestat[1] = 0; dev_priv 356 drivers/gpu/drm/gma500/psb_drv.c dev_priv->pipestat[2] = 0; dev_priv 357 drivers/gpu/drm/gma500/psb_drv.c spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); dev_priv 361 drivers/gpu/drm/gma500/psb_drv.c spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); dev_priv 415 drivers/gpu/drm/gma500/psb_drv.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 418 drivers/gpu/drm/gma500/psb_drv.c if (runtime_allowed == 1 && dev_priv->is_lvds_on) { dev_priv 421 drivers/gpu/drm/gma500/psb_drv.c dev_priv->rpm_enabled = 1; dev_priv 685 drivers/gpu/drm/gma500/psb_drv.h psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); dev_priv 688 drivers/gpu/drm/gma500/psb_drv.h psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); dev_priv 700 drivers/gpu/drm/gma500/psb_drv.h extern void psb_spank(struct drm_psb_private *dev_priv); dev_priv 703 drivers/gpu/drm/gma500/psb_drv.h extern void psb_lid_timer_init(struct drm_psb_private *dev_priv); dev_priv 704 drivers/gpu/drm/gma500/psb_drv.h extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv); dev_priv 705 drivers/gpu/drm/gma500/psb_drv.h extern void psb_print_pagefault(struct drm_psb_private *dev_priv); dev_priv 813 drivers/gpu/drm/gma500/psb_drv.h struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 814 drivers/gpu/drm/gma500/psb_drv.h return ioread32(dev_priv->vdc_reg + reg); dev_priv 819 drivers/gpu/drm/gma500/psb_drv.h struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 820 drivers/gpu/drm/gma500/psb_drv.h return ioread32(dev_priv->aux_reg + reg); dev_priv 845 drivers/gpu/drm/gma500/psb_drv.h struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 846 drivers/gpu/drm/gma500/psb_drv.h iowrite32((val), dev_priv->vdc_reg + (reg)); dev_priv 852 drivers/gpu/drm/gma500/psb_drv.h struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 853 drivers/gpu/drm/gma500/psb_drv.h iowrite32((val), dev_priv->aux_reg + (reg)); dev_priv 873 drivers/gpu/drm/gma500/psb_drv.h struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 874 drivers/gpu/drm/gma500/psb_drv.h iowrite16((val), dev_priv->vdc_reg + (reg)); dev_priv 882 drivers/gpu/drm/gma500/psb_drv.h struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 883 drivers/gpu/drm/gma500/psb_drv.h iowrite8((val), dev_priv->vdc_reg + (reg)); dev_priv 888 drivers/gpu/drm/gma500/psb_drv.h #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs)) dev_priv 889 drivers/gpu/drm/gma500/psb_drv.h #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs)) dev_priv 895 drivers/gpu/drm/gma500/psb_drv.h if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \ dev_priv 900 drivers/gpu/drm/gma500/psb_drv.h ioread32(dev_priv->sgx_reg + (_offs)); \ dev_priv 903 drivers/gpu/drm/gma500/psb_drv.h #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs)) dev_priv 905 drivers/gpu/drm/gma500/psb_drv.h #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs)) dev_priv 909 drivers/gpu/drm/gma500/psb_drv.h #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs)) dev_priv 910 drivers/gpu/drm/gma500/psb_drv.h #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs)) dev_priv 98 drivers/gpu/drm/gma500/psb_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 102 drivers/gpu/drm/gma500/psb_intel_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 301 drivers/gpu/drm/gma500/psb_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 303 drivers/gpu/drm/gma500/psb_intel_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 308 drivers/gpu/drm/gma500/psb_intel_display.c struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; dev_priv 326 drivers/gpu/drm/gma500/psb_intel_display.c is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS & dev_priv 383 drivers/gpu/drm/gma500/psb_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 384 drivers/gpu/drm/gma500/psb_intel_display.c struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; dev_priv 385 drivers/gpu/drm/gma500/psb_intel_display.c const struct psb_offset *map = &dev_priv->regmap[pipe]; dev_priv 450 drivers/gpu/drm/gma500/psb_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 455 drivers/gpu/drm/gma500/psb_intel_display.c if (dev_priv->ops->cursor_needs_phys) { dev_priv 466 drivers/gpu/drm/gma500/psb_intel_display.c gma_crtc->cursor_addr = dev_priv->stolen_base + dev_priv 480 drivers/gpu/drm/gma500/psb_intel_display.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 501 drivers/gpu/drm/gma500/psb_intel_display.c drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs); dev_priv 504 drivers/gpu/drm/gma500/psb_intel_display.c gma_crtc->clock_funcs = dev_priv->ops->clock_funcs; dev_priv 517 drivers/gpu/drm/gma500/psb_intel_display.c dev_priv->ops->crtc_helper); dev_priv 521 drivers/gpu/drm/gma500/psb_intel_display.c BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || dev_priv 522 drivers/gpu/drm/gma500/psb_intel_display.c dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL); dev_priv 523 drivers/gpu/drm/gma500/psb_intel_display.c dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base; dev_priv 524 drivers/gpu/drm/gma500/psb_intel_display.c dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base; dev_priv 121 drivers/gpu/drm/gma500/psb_intel_drv.h void *dev_priv; /* For sdvo_priv, lvds_priv, etc... */ dev_priv 60 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 67 drivers/gpu/drm/gma500/psb_intel_lvds.c ret = dev_priv->regs.saveBLC_PWM_CTL; dev_priv 76 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); dev_priv 89 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = dev_priv 92 drivers/gpu/drm/gma500/psb_intel_lvds.c struct psb_intel_i2c_chan *lvds_i2c_bus = dev_priv->lvds_i2c_bus; dev_priv 109 drivers/gpu/drm/gma500/psb_intel_lvds.c if (dev_priv->lvds_bl->pol == BLC_POLARITY_INVERSE) dev_priv 112 drivers/gpu/drm/gma500/psb_intel_lvds.c out_buf[0] = dev_priv->lvds_bl->brightnesscmd; dev_priv 117 drivers/gpu/drm/gma500/psb_intel_lvds.c dev_priv->lvds_bl->brightnesscmd, dev_priv 129 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = dev_priv 142 drivers/gpu/drm/gma500/psb_intel_lvds.c if (dev_priv->lvds_bl->pol == BLC_POLARITY_INVERSE) dev_priv 162 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 166 drivers/gpu/drm/gma500/psb_intel_lvds.c if (!dev_priv->lvds_bl) { dev_priv 171 drivers/gpu/drm/gma500/psb_intel_lvds.c if (dev_priv->lvds_bl->type == BLC_I2C_TYPE) dev_priv 184 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 193 drivers/gpu/drm/gma500/psb_intel_lvds.c dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl | dev_priv 197 drivers/gpu/drm/gma500/psb_intel_lvds.c blc_pwm_ctl = dev_priv->regs.saveBLC_PWM_CTL & dev_priv 199 drivers/gpu/drm/gma500/psb_intel_lvds.c dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl | dev_priv 209 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 210 drivers/gpu/drm/gma500/psb_intel_lvds.c struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; dev_priv 255 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = dev_priv 259 drivers/gpu/drm/gma500/psb_intel_lvds.c (struct psb_intel_lvds_priv *)gma_encoder->dev_priv; dev_priv 272 drivers/gpu/drm/gma500/psb_intel_lvds.c dev_priv->backlight_duty_cycle = (dev_priv->regs.saveBLC_PWM_CTL & dev_priv 279 drivers/gpu/drm/gma500/psb_intel_lvds.c if (dev_priv->backlight_duty_cycle == 0) dev_priv 280 drivers/gpu/drm/gma500/psb_intel_lvds.c dev_priv->backlight_duty_cycle = dev_priv 298 drivers/gpu/drm/gma500/psb_intel_lvds.c (struct psb_intel_lvds_priv *)gma_encoder->dev_priv; dev_priv 336 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = connector->dev->dev_private; dev_priv 339 drivers/gpu/drm/gma500/psb_intel_lvds.c dev_priv->mode_dev.panel_fixed_mode; dev_priv 342 drivers/gpu/drm/gma500/psb_intel_lvds.c fixed_mode = dev_priv->mode_dev.panel_fixed_mode2; dev_priv 366 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 367 drivers/gpu/drm/gma500/psb_intel_lvds.c struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; dev_priv 427 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 428 drivers/gpu/drm/gma500/psb_intel_lvds.c struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; dev_priv 445 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 446 drivers/gpu/drm/gma500/psb_intel_lvds.c struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; dev_priv 460 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 482 drivers/gpu/drm/gma500/psb_intel_lvds.c if (dev_priv->lvds_dither) dev_priv 494 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 495 drivers/gpu/drm/gma500/psb_intel_lvds.c struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; dev_priv 497 drivers/gpu/drm/gma500/psb_intel_lvds.c struct psb_intel_lvds_priv *lvds_priv = gma_encoder->dev_priv; dev_priv 526 drivers/gpu/drm/gma500/psb_intel_lvds.c struct psb_intel_lvds_priv *lvds_priv = gma_encoder->dev_priv; dev_priv 653 drivers/gpu/drm/gma500/psb_intel_lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 675 drivers/gpu/drm/gma500/psb_intel_lvds.c gma_encoder->dev_priv = lvds_priv; dev_priv 705 drivers/gpu/drm/gma500/psb_intel_lvds.c dev_priv->backlight_property, dev_priv 719 drivers/gpu/drm/gma500/psb_intel_lvds.c dev_priv->lvds_i2c_bus = lvds_priv->i2c_bus; dev_priv 755 drivers/gpu/drm/gma500/psb_intel_lvds.c if (dev_priv->lfp_lvds_vbt_mode) { dev_priv 757 drivers/gpu/drm/gma500/psb_intel_lvds.c drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); dev_priv 1245 drivers/gpu/drm/gma500/psb_intel_sdvo.c sdvo = iout->dev_priv; dev_priv 1318 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_psb_private *dev_priv = connector->dev->dev_private; dev_priv 1321 drivers/gpu/drm/gma500/psb_intel_sdvo.c &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter); dev_priv 1587 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_psb_private *dev_priv = connector->dev->dev_private; dev_priv 1600 drivers/gpu/drm/gma500/psb_intel_sdvo.c if (dev_priv->sdvo_lvds_vbt_mode != NULL) { dev_priv 1602 drivers/gpu/drm/gma500/psb_intel_sdvo.c dev_priv->sdvo_lvds_vbt_mode); dev_priv 1671 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_psb_private *dev_priv = connector->dev->dev_private; dev_priv 1680 drivers/gpu/drm/gma500/psb_intel_sdvo.c if (property == dev_priv->force_audio_property) { dev_priv 1701 drivers/gpu/drm/gma500/psb_intel_sdvo.c if (property == dev_priv->broadcast_rgb_property) { dev_priv 1927 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo_select_ddc_bus(struct drm_psb_private *dev_priv, dev_priv 1933 drivers/gpu/drm/gma500/psb_intel_sdvo.c mapping = &(dev_priv->sdvo_mappings[0]); dev_priv 1935 drivers/gpu/drm/gma500/psb_intel_sdvo.c mapping = &(dev_priv->sdvo_mappings[1]); dev_priv 1944 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo_select_i2c_bus(struct drm_psb_private *dev_priv, dev_priv 1951 drivers/gpu/drm/gma500/psb_intel_sdvo.c mapping = &dev_priv->sdvo_mappings[0]; dev_priv 1953 drivers/gpu/drm/gma500/psb_intel_sdvo.c mapping = &dev_priv->sdvo_mappings[1]; dev_priv 1963 drivers/gpu/drm/gma500/psb_intel_sdvo.c sdvo->i2c = &dev_priv->gmbus[pin].adapter; dev_priv 1967 drivers/gpu/drm/gma500/psb_intel_sdvo.c sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter; dev_priv 1979 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 1983 drivers/gpu/drm/gma500/psb_intel_sdvo.c my_mapping = &dev_priv->sdvo_mappings[0]; dev_priv 1984 drivers/gpu/drm/gma500/psb_intel_sdvo.c other_mapping = &dev_priv->sdvo_mappings[1]; dev_priv 1986 drivers/gpu/drm/gma500/psb_intel_sdvo.c my_mapping = &dev_priv->sdvo_mappings[1]; dev_priv 1987 drivers/gpu/drm/gma500/psb_intel_sdvo.c other_mapping = &dev_priv->sdvo_mappings[0]; dev_priv 2516 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 2527 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo_select_i2c_bus(dev_priv, psb_intel_sdvo, sdvo_reg); dev_priv 2551 drivers/gpu/drm/gma500/psb_intel_sdvo.c dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; dev_priv 2553 drivers/gpu/drm/gma500/psb_intel_sdvo.c dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; dev_priv 2568 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo_select_ddc_bus(dev_priv, psb_intel_sdvo, sdvo_reg); dev_priv 73 drivers/gpu/drm/gma500/psb_irq.c psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) dev_priv 75 drivers/gpu/drm/gma500/psb_irq.c if ((dev_priv->pipestat[pipe] & mask) != mask) { dev_priv 77 drivers/gpu/drm/gma500/psb_irq.c dev_priv->pipestat[pipe] |= mask; dev_priv 79 drivers/gpu/drm/gma500/psb_irq.c if (gma_power_begin(dev_priv->dev, false)) { dev_priv 84 drivers/gpu/drm/gma500/psb_irq.c gma_power_end(dev_priv->dev); dev_priv 90 drivers/gpu/drm/gma500/psb_irq.c psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) dev_priv 92 drivers/gpu/drm/gma500/psb_irq.c if ((dev_priv->pipestat[pipe] & mask) != 0) { dev_priv 94 drivers/gpu/drm/gma500/psb_irq.c dev_priv->pipestat[pipe] &= ~mask; dev_priv 95 drivers/gpu/drm/gma500/psb_irq.c if (gma_power_begin(dev_priv->dev, false)) { dev_priv 100 drivers/gpu/drm/gma500/psb_irq.c gma_power_end(dev_priv->dev); dev_priv 105 drivers/gpu/drm/gma500/psb_irq.c static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe) dev_priv 107 drivers/gpu/drm/gma500/psb_irq.c if (gma_power_begin(dev_priv->dev, false)) { dev_priv 109 drivers/gpu/drm/gma500/psb_irq.c dev_priv->vdc_irq_mask |= pipe_event; dev_priv 110 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); dev_priv 111 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); dev_priv 112 drivers/gpu/drm/gma500/psb_irq.c gma_power_end(dev_priv->dev); dev_priv 116 drivers/gpu/drm/gma500/psb_irq.c static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe) dev_priv 118 drivers/gpu/drm/gma500/psb_irq.c if (dev_priv->pipestat[pipe] == 0) { dev_priv 119 drivers/gpu/drm/gma500/psb_irq.c if (gma_power_begin(dev_priv->dev, false)) { dev_priv 121 drivers/gpu/drm/gma500/psb_irq.c dev_priv->vdc_irq_mask &= ~pipe_event; dev_priv 122 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); dev_priv 123 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); dev_priv 124 drivers/gpu/drm/gma500/psb_irq.c gma_power_end(dev_priv->dev); dev_priv 135 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev_priv 140 drivers/gpu/drm/gma500/psb_irq.c uint32_t pipe_enable = dev_priv->pipestat[pipe]; dev_priv 141 drivers/gpu/drm/gma500/psb_irq.c uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16; dev_priv 145 drivers/gpu/drm/gma500/psb_irq.c spin_lock(&dev_priv->irqmask_lock); dev_priv 151 drivers/gpu/drm/gma500/psb_irq.c spin_unlock(&dev_priv->irqmask_lock); dev_priv 195 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 245 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 250 drivers/gpu/drm/gma500/psb_irq.c spin_lock(&dev_priv->irqmask_lock); dev_priv 267 drivers/gpu/drm/gma500/psb_irq.c vdc_stat &= dev_priv->vdc_irq_mask; dev_priv 268 drivers/gpu/drm/gma500/psb_irq.c spin_unlock(&dev_priv->irqmask_lock); dev_priv 284 drivers/gpu/drm/gma500/psb_irq.c if (hotplug_int && dev_priv->ops->hotplug) { dev_priv 285 drivers/gpu/drm/gma500/psb_irq.c handled = dev_priv->ops->hotplug(dev); dev_priv 301 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev_priv 305 drivers/gpu/drm/gma500/psb_irq.c spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); dev_priv 315 drivers/gpu/drm/gma500/psb_irq.c dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG; dev_priv 317 drivers/gpu/drm/gma500/psb_irq.c dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG; dev_priv 327 drivers/gpu/drm/gma500/psb_irq.c if (dev_priv->ops->hotplug) dev_priv 328 drivers/gpu/drm/gma500/psb_irq.c dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC; dev_priv 329 drivers/gpu/drm/gma500/psb_irq.c dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG; dev_priv 332 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); dev_priv 333 drivers/gpu/drm/gma500/psb_irq.c spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); dev_priv 338 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 341 drivers/gpu/drm/gma500/psb_irq.c spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); dev_priv 349 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); dev_priv 353 drivers/gpu/drm/gma500/psb_irq.c psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); dev_priv 355 drivers/gpu/drm/gma500/psb_irq.c psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); dev_priv 358 drivers/gpu/drm/gma500/psb_irq.c psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); dev_priv 360 drivers/gpu/drm/gma500/psb_irq.c psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); dev_priv 363 drivers/gpu/drm/gma500/psb_irq.c psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); dev_priv 365 drivers/gpu/drm/gma500/psb_irq.c psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); dev_priv 367 drivers/gpu/drm/gma500/psb_irq.c if (dev_priv->ops->hotplug_enable) dev_priv 368 drivers/gpu/drm/gma500/psb_irq.c dev_priv->ops->hotplug_enable(dev, true); dev_priv 370 drivers/gpu/drm/gma500/psb_irq.c spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); dev_priv 376 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 379 drivers/gpu/drm/gma500/psb_irq.c spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); dev_priv 381 drivers/gpu/drm/gma500/psb_irq.c if (dev_priv->ops->hotplug_enable) dev_priv 382 drivers/gpu/drm/gma500/psb_irq.c dev_priv->ops->hotplug_enable(dev, false); dev_priv 387 drivers/gpu/drm/gma500/psb_irq.c psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); dev_priv 390 drivers/gpu/drm/gma500/psb_irq.c psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); dev_priv 393 drivers/gpu/drm/gma500/psb_irq.c psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); dev_priv 395 drivers/gpu/drm/gma500/psb_irq.c dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG | dev_priv 400 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); dev_priv 401 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); dev_priv 407 drivers/gpu/drm/gma500/psb_irq.c spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); dev_priv 412 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev_priv 430 drivers/gpu/drm/gma500/psb_irq.c psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE); dev_priv 445 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev_priv 449 drivers/gpu/drm/gma500/psb_irq.c spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); dev_priv 452 drivers/gpu/drm/gma500/psb_irq.c mid_enable_pipe_event(dev_priv, 0); dev_priv 455 drivers/gpu/drm/gma500/psb_irq.c spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); dev_priv 461 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev_priv 470 drivers/gpu/drm/gma500/psb_irq.c psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE); dev_priv 483 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev_priv 487 drivers/gpu/drm/gma500/psb_irq.c spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); dev_priv 489 drivers/gpu/drm/gma500/psb_irq.c mid_disable_pipe_event(dev_priv, 0); dev_priv 492 drivers/gpu/drm/gma500/psb_irq.c spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); dev_priv 502 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 520 drivers/gpu/drm/gma500/psb_irq.c spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); dev_priv 523 drivers/gpu/drm/gma500/psb_irq.c dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG; dev_priv 525 drivers/gpu/drm/gma500/psb_irq.c dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG; dev_priv 527 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); dev_priv 528 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); dev_priv 529 drivers/gpu/drm/gma500/psb_irq.c psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE); dev_priv 531 drivers/gpu/drm/gma500/psb_irq.c spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); dev_priv 541 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 546 drivers/gpu/drm/gma500/psb_irq.c spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); dev_priv 549 drivers/gpu/drm/gma500/psb_irq.c dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG; dev_priv 551 drivers/gpu/drm/gma500/psb_irq.c dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG; dev_priv 553 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); dev_priv 554 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); dev_priv 555 drivers/gpu/drm/gma500/psb_irq.c psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE); dev_priv 557 drivers/gpu/drm/gma500/psb_irq.c spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); dev_priv 565 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev_priv 579 drivers/gpu/drm/gma500/psb_irq.c spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); dev_priv 581 drivers/gpu/drm/gma500/psb_irq.c mid_enable_pipe_event(dev_priv, pipe); dev_priv 582 drivers/gpu/drm/gma500/psb_irq.c psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE); dev_priv 584 drivers/gpu/drm/gma500/psb_irq.c spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); dev_priv 594 drivers/gpu/drm/gma500/psb_irq.c struct drm_psb_private *dev_priv = dev_priv 598 drivers/gpu/drm/gma500/psb_irq.c if (!dev_priv->dsr_enable) dev_priv 601 drivers/gpu/drm/gma500/psb_irq.c spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); dev_priv 603 drivers/gpu/drm/gma500/psb_irq.c mid_disable_pipe_event(dev_priv, pipe); dev_priv 604 drivers/gpu/drm/gma500/psb_irq.c psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE); dev_priv 606 drivers/gpu/drm/gma500/psb_irq.c spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); dev_priv 16 drivers/gpu/drm/gma500/psb_lid.c struct drm_psb_private *dev_priv = from_timer(dev_priv, t, lid_timer); dev_priv 17 drivers/gpu/drm/gma500/psb_lid.c struct drm_device *dev = (struct drm_device *)dev_priv->dev; dev_priv 18 drivers/gpu/drm/gma500/psb_lid.c struct timer_list *lid_timer = &dev_priv->lid_timer; dev_priv 20 drivers/gpu/drm/gma500/psb_lid.c u32 __iomem *lid_state = dev_priv->opregion.lid_state; dev_priv 23 drivers/gpu/drm/gma500/psb_lid.c if (readl(lid_state) == dev_priv->lid_last_state) dev_priv 49 drivers/gpu/drm/gma500/psb_lid.c dev_priv->lid_last_state = readl(lid_state); dev_priv 52 drivers/gpu/drm/gma500/psb_lid.c spin_lock_irqsave(&dev_priv->lid_lock, irq_flags); dev_priv 57 drivers/gpu/drm/gma500/psb_lid.c spin_unlock_irqrestore(&dev_priv->lid_lock, irq_flags); dev_priv 60 drivers/gpu/drm/gma500/psb_lid.c void psb_lid_timer_init(struct drm_psb_private *dev_priv) dev_priv 62 drivers/gpu/drm/gma500/psb_lid.c struct timer_list *lid_timer = &dev_priv->lid_timer; dev_priv 65 drivers/gpu/drm/gma500/psb_lid.c spin_lock_init(&dev_priv->lid_lock); dev_priv 66 drivers/gpu/drm/gma500/psb_lid.c spin_lock_irqsave(&dev_priv->lid_lock, irq_flags); dev_priv 73 drivers/gpu/drm/gma500/psb_lid.c spin_unlock_irqrestore(&dev_priv->lid_lock, irq_flags); dev_priv 76 drivers/gpu/drm/gma500/psb_lid.c void psb_lid_timer_takedown(struct drm_psb_private *dev_priv) dev_priv 78 drivers/gpu/drm/gma500/psb_lid.c del_timer_sync(&dev_priv->lid_timer); dev_priv 532 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c struct drm_psb_private *dev_priv = dev->dev_private; dev_priv 577 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c tc35876x_brightness_control(dev, dev_priv->brightness_adjusted); dev_priv 98 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv; dev_priv 103 drivers/gpu/drm/i810/i810_dma.c dev_priv = dev->dev_private; dev_priv 104 drivers/gpu/drm/i810/i810_dma.c buf = dev_priv->mmap_buffer; dev_priv 131 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 141 drivers/gpu/drm/i810/i810_dma.c dev_priv->mmap_buffer = buf; dev_priv 145 drivers/gpu/drm/i810/i810_dma.c dev_priv->mmap_buffer = NULL; dev_priv 217 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev_priv 220 drivers/gpu/drm/i810/i810_dma.c if (dev_priv->ring.virtual_start) dev_priv 221 drivers/gpu/drm/i810/i810_dma.c drm_legacy_ioremapfree(&dev_priv->ring.map, dev); dev_priv 222 drivers/gpu/drm/i810/i810_dma.c if (dev_priv->hw_status_page) { dev_priv 224 drivers/gpu/drm/i810/i810_dma.c dev_priv->hw_status_page, dev_priv 225 drivers/gpu/drm/i810/i810_dma.c dev_priv->dma_status_page); dev_priv 243 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 244 drivers/gpu/drm/i810/i810_dma.c drm_i810_ring_buffer_t *ring = &(dev_priv->ring); dev_priv 276 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 277 drivers/gpu/drm/i810/i810_dma.c drm_i810_ring_buffer_t *ring = &(dev_priv->ring); dev_priv 286 drivers/gpu/drm/i810/i810_dma.c static int i810_freelist_init(struct drm_device *dev, drm_i810_private_t *dev_priv) dev_priv 290 drivers/gpu/drm/i810/i810_dma.c u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx); dev_priv 322 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv, dev_priv 326 drivers/gpu/drm/i810/i810_dma.c memset(dev_priv, 0, sizeof(drm_i810_private_t)); dev_priv 332 drivers/gpu/drm/i810/i810_dma.c dev_priv->sarea_map = r_list->map; dev_priv 336 drivers/gpu/drm/i810/i810_dma.c if (!dev_priv->sarea_map) { dev_priv 337 drivers/gpu/drm/i810/i810_dma.c dev->dev_private = (void *)dev_priv; dev_priv 342 drivers/gpu/drm/i810/i810_dma.c dev_priv->mmio_map = drm_legacy_findmap(dev, init->mmio_offset); dev_priv 343 drivers/gpu/drm/i810/i810_dma.c if (!dev_priv->mmio_map) { dev_priv 344 drivers/gpu/drm/i810/i810_dma.c dev->dev_private = (void *)dev_priv; dev_priv 352 drivers/gpu/drm/i810/i810_dma.c dev->dev_private = (void *)dev_priv; dev_priv 358 drivers/gpu/drm/i810/i810_dma.c dev_priv->sarea_priv = (drm_i810_sarea_t *) dev_priv 359 drivers/gpu/drm/i810/i810_dma.c ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset); dev_priv 361 drivers/gpu/drm/i810/i810_dma.c dev_priv->ring.Start = init->ring_start; dev_priv 362 drivers/gpu/drm/i810/i810_dma.c dev_priv->ring.End = init->ring_end; dev_priv 363 drivers/gpu/drm/i810/i810_dma.c dev_priv->ring.Size = init->ring_size; dev_priv 365 drivers/gpu/drm/i810/i810_dma.c dev_priv->ring.map.offset = dev->agp->base + init->ring_start; dev_priv 366 drivers/gpu/drm/i810/i810_dma.c dev_priv->ring.map.size = init->ring_size; dev_priv 367 drivers/gpu/drm/i810/i810_dma.c dev_priv->ring.map.type = _DRM_AGP; dev_priv 368 drivers/gpu/drm/i810/i810_dma.c dev_priv->ring.map.flags = 0; dev_priv 369 drivers/gpu/drm/i810/i810_dma.c dev_priv->ring.map.mtrr = 0; dev_priv 371 drivers/gpu/drm/i810/i810_dma.c drm_legacy_ioremap(&dev_priv->ring.map, dev); dev_priv 373 drivers/gpu/drm/i810/i810_dma.c if (dev_priv->ring.map.handle == NULL) { dev_priv 374 drivers/gpu/drm/i810/i810_dma.c dev->dev_private = (void *)dev_priv; dev_priv 381 drivers/gpu/drm/i810/i810_dma.c dev_priv->ring.virtual_start = dev_priv->ring.map.handle; dev_priv 383 drivers/gpu/drm/i810/i810_dma.c dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; dev_priv 385 drivers/gpu/drm/i810/i810_dma.c dev_priv->w = init->w; dev_priv 386 drivers/gpu/drm/i810/i810_dma.c dev_priv->h = init->h; dev_priv 387 drivers/gpu/drm/i810/i810_dma.c dev_priv->pitch = init->pitch; dev_priv 388 drivers/gpu/drm/i810/i810_dma.c dev_priv->back_offset = init->back_offset; dev_priv 389 drivers/gpu/drm/i810/i810_dma.c dev_priv->depth_offset = init->depth_offset; dev_priv 390 drivers/gpu/drm/i810/i810_dma.c dev_priv->front_offset = init->front_offset; dev_priv 392 drivers/gpu/drm/i810/i810_dma.c dev_priv->overlay_offset = init->overlay_offset; dev_priv 393 drivers/gpu/drm/i810/i810_dma.c dev_priv->overlay_physical = init->overlay_physical; dev_priv 395 drivers/gpu/drm/i810/i810_dma.c dev_priv->front_di1 = init->front_offset | init->pitch_bits; dev_priv 396 drivers/gpu/drm/i810/i810_dma.c dev_priv->back_di1 = init->back_offset | init->pitch_bits; dev_priv 397 drivers/gpu/drm/i810/i810_dma.c dev_priv->zi1 = init->depth_offset | init->pitch_bits; dev_priv 400 drivers/gpu/drm/i810/i810_dma.c dev_priv->hw_status_page = dev_priv 402 drivers/gpu/drm/i810/i810_dma.c &dev_priv->dma_status_page); dev_priv 403 drivers/gpu/drm/i810/i810_dma.c if (!dev_priv->hw_status_page) { dev_priv 404 drivers/gpu/drm/i810/i810_dma.c dev->dev_private = (void *)dev_priv; dev_priv 409 drivers/gpu/drm/i810/i810_dma.c DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); dev_priv 411 drivers/gpu/drm/i810/i810_dma.c I810_WRITE(0x02080, dev_priv->dma_status_page); dev_priv 415 drivers/gpu/drm/i810/i810_dma.c if (i810_freelist_init(dev, dev_priv) != 0) { dev_priv 416 drivers/gpu/drm/i810/i810_dma.c dev->dev_private = (void *)dev_priv; dev_priv 422 drivers/gpu/drm/i810/i810_dma.c dev->dev_private = (void *)dev_priv; dev_priv 430 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv; dev_priv 437 drivers/gpu/drm/i810/i810_dma.c dev_priv = kmalloc(sizeof(drm_i810_private_t), GFP_KERNEL); dev_priv 438 drivers/gpu/drm/i810/i810_dma.c if (dev_priv == NULL) dev_priv 440 drivers/gpu/drm/i810/i810_dma.c retcode = i810_dma_initialize(dev, dev_priv, init); dev_priv 463 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 495 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 529 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 536 drivers/gpu/drm/i810/i810_dma.c if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) { dev_priv 541 drivers/gpu/drm/i810/i810_dma.c tmp, dev_priv->front_di1, dev_priv->back_di1); dev_priv 546 drivers/gpu/drm/i810/i810_dma.c OUT_RING(dev_priv->zi1); dev_priv 563 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 564 drivers/gpu/drm/i810/i810_dma.c drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 596 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 597 drivers/gpu/drm/i810/i810_dma.c drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 600 drivers/gpu/drm/i810/i810_dma.c int pitch = dev_priv->pitch; dev_priv 605 drivers/gpu/drm/i810/i810_dma.c if (dev_priv->current_page == 1) { dev_priv 629 drivers/gpu/drm/i810/i810_dma.c pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) dev_priv 648 drivers/gpu/drm/i810/i810_dma.c OUT_RING(dev_priv->back_offset + start); dev_priv 659 drivers/gpu/drm/i810/i810_dma.c OUT_RING(dev_priv->depth_offset + start); dev_priv 669 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 670 drivers/gpu/drm/i810/i810_dma.c drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 673 drivers/gpu/drm/i810/i810_dma.c int pitch = dev_priv->pitch; dev_priv 693 drivers/gpu/drm/i810/i810_dma.c pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) dev_priv 700 drivers/gpu/drm/i810/i810_dma.c if (dev_priv->current_page == 0) dev_priv 701 drivers/gpu/drm/i810/i810_dma.c OUT_RING(dev_priv->front_offset + start); dev_priv 703 drivers/gpu/drm/i810/i810_dma.c OUT_RING(dev_priv->back_offset + start); dev_priv 705 drivers/gpu/drm/i810/i810_dma.c if (dev_priv->current_page == 0) dev_priv 706 drivers/gpu/drm/i810/i810_dma.c OUT_RING(dev_priv->back_offset + start); dev_priv 708 drivers/gpu/drm/i810/i810_dma.c OUT_RING(dev_priv->front_offset + start); dev_priv 716 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 718 drivers/gpu/drm/i810/i810_dma.c drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 775 drivers/gpu/drm/i810/i810_dma.c dev_priv->counter++; dev_priv 783 drivers/gpu/drm/i810/i810_dma.c OUT_RING(dev_priv->counter); dev_priv 795 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 796 drivers/gpu/drm/i810/i810_dma.c int pitch = dev_priv->pitch; dev_priv 800 drivers/gpu/drm/i810/i810_dma.c dev_priv->current_page, dev_priv 801 drivers/gpu/drm/i810/i810_dma.c dev_priv->sarea_priv->pf_current_page); dev_priv 816 drivers/gpu/drm/i810/i810_dma.c if (dev_priv->current_page == 0) { dev_priv 817 drivers/gpu/drm/i810/i810_dma.c OUT_RING(dev_priv->back_offset); dev_priv 818 drivers/gpu/drm/i810/i810_dma.c dev_priv->current_page = 1; dev_priv 820 drivers/gpu/drm/i810/i810_dma.c OUT_RING(dev_priv->front_offset); dev_priv 821 drivers/gpu/drm/i810/i810_dma.c dev_priv->current_page = 0; dev_priv 835 drivers/gpu/drm/i810/i810_dma.c dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; dev_priv 841 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 853 drivers/gpu/drm/i810/i810_dma.c i810_wait_ring(dev, dev_priv->ring.Size - 8); dev_priv 858 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 870 drivers/gpu/drm/i810/i810_dma.c i810_wait_ring(dev, dev_priv->ring.Size - 8); dev_priv 933 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; dev_priv 934 drivers/gpu/drm/i810/i810_dma.c u32 *hw_status = dev_priv->hw_status_page; dev_priv 936 drivers/gpu/drm/i810/i810_dma.c dev_priv->sarea_priv; dev_priv 951 drivers/gpu/drm/i810/i810_dma.c sarea_priv->last_enqueue = dev_priv->counter - 1; dev_priv 987 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; dev_priv 988 drivers/gpu/drm/i810/i810_dma.c u32 *hw_status = dev_priv->hw_status_page; dev_priv 990 drivers/gpu/drm/i810/i810_dma.c dev_priv->sarea_priv; dev_priv 1001 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; dev_priv 1002 drivers/gpu/drm/i810/i810_dma.c u32 *hw_status = dev_priv->hw_status_page; dev_priv 1004 drivers/gpu/drm/i810/i810_dma.c dev_priv->sarea_priv; dev_priv 1037 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 1039 drivers/gpu/drm/i810/i810_dma.c drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 1058 drivers/gpu/drm/i810/i810_dma.c dev_priv->counter++; dev_priv 1059 drivers/gpu/drm/i810/i810_dma.c DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter); dev_priv 1096 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; dev_priv 1097 drivers/gpu/drm/i810/i810_dma.c u32 *hw_status = dev_priv->hw_status_page; dev_priv 1099 drivers/gpu/drm/i810/i810_dma.c dev_priv->sarea_priv; dev_priv 1110 drivers/gpu/drm/i810/i810_dma.c sarea_priv->last_enqueue = dev_priv->counter - 1; dev_priv 1119 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; dev_priv 1121 drivers/gpu/drm/i810/i810_dma.c return (int)(((u32 *) (dev_priv->hw_status_page))[4]); dev_priv 1127 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; dev_priv 1130 drivers/gpu/drm/i810/i810_dma.c ov->offset = dev_priv->overlay_offset; dev_priv 1131 drivers/gpu/drm/i810/i810_dma.c ov->physical = dev_priv->overlay_physical; dev_priv 1139 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; dev_priv 1148 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; dev_priv 1153 drivers/gpu/drm/i810/i810_dma.c I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000); dev_priv 1162 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 1165 drivers/gpu/drm/i810/i810_dma.c dev_priv->page_flipping = 1; dev_priv 1166 drivers/gpu/drm/i810/i810_dma.c dev_priv->current_page = 0; dev_priv 1167 drivers/gpu/drm/i810/i810_dma.c dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; dev_priv 1172 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 1175 drivers/gpu/drm/i810/i810_dma.c if (dev_priv->current_page != 0) dev_priv 1178 drivers/gpu/drm/i810/i810_dma.c dev_priv->page_flipping = 0; dev_priv 1185 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 1191 drivers/gpu/drm/i810/i810_dma.c if (!dev_priv->page_flipping) dev_priv 1225 drivers/gpu/drm/i810/i810_dma.c drm_i810_private_t *dev_priv = dev->dev_private; dev_priv 1226 drivers/gpu/drm/i810/i810_dma.c if (dev_priv->page_flipping) dev_priv 135 drivers/gpu/drm/i810/i810_drv.h dev_priv->mmio_map->handle) dev_priv 151 drivers/gpu/drm/i810/i810_drv.h if (dev_priv->ring.space < n*4) \ dev_priv 153 drivers/gpu/drm/i810/i810_drv.h dev_priv->ring.space -= n*4; \ dev_priv 154 drivers/gpu/drm/i810/i810_drv.h outring = dev_priv->ring.tail; \ dev_priv 155 drivers/gpu/drm/i810/i810_drv.h ringmask = dev_priv->ring.tail_mask; \ dev_priv 156 drivers/gpu/drm/i810/i810_drv.h virt = dev_priv->ring.virtual_start; \ dev_priv 162 drivers/gpu/drm/i810/i810_drv.h dev_priv->ring.tail = outring; \ dev_priv 213 drivers/gpu/drm/i915/display/dvo_ch7017.c dvo->dev_priv = priv; dev_priv 398 drivers/gpu/drm/i915/display/dvo_ch7017.c struct ch7017_priv *priv = dvo->dev_priv; dev_priv 402 drivers/gpu/drm/i915/display/dvo_ch7017.c dvo->dev_priv = NULL; dev_priv 138 drivers/gpu/drm/i915/display/dvo_ch7xxx.c struct ch7xxx_priv *ch7xxx = dvo->dev_priv; dev_priv 176 drivers/gpu/drm/i915/display/dvo_ch7xxx.c struct ch7xxx_priv *ch7xxx = dvo->dev_priv; dev_priv 213 drivers/gpu/drm/i915/display/dvo_ch7xxx.c dvo->dev_priv = ch7xxx; dev_priv 350 drivers/gpu/drm/i915/display/dvo_ch7xxx.c struct ch7xxx_priv *ch7xxx = dvo->dev_priv; dev_priv 354 drivers/gpu/drm/i915/display/dvo_ch7xxx.c dvo->dev_priv = NULL; dev_priv 194 drivers/gpu/drm/i915/display/dvo_ivch.c struct ivch_priv *priv = dvo->dev_priv; dev_priv 237 drivers/gpu/drm/i915/display/dvo_ivch.c struct ivch_priv *priv = dvo->dev_priv; dev_priv 275 drivers/gpu/drm/i915/display/dvo_ivch.c dvo->dev_priv = priv; dev_priv 331 drivers/gpu/drm/i915/display/dvo_ivch.c struct ivch_priv *priv = dvo->dev_priv; dev_priv 401 drivers/gpu/drm/i915/display/dvo_ivch.c struct ivch_priv *priv = dvo->dev_priv; dev_priv 486 drivers/gpu/drm/i915/display/dvo_ivch.c struct ivch_priv *priv = dvo->dev_priv; dev_priv 490 drivers/gpu/drm/i915/display/dvo_ivch.c dvo->dev_priv = NULL; dev_priv 395 drivers/gpu/drm/i915/display/dvo_ns2501.c struct ns2501_priv *ns = dvo->dev_priv; dev_priv 440 drivers/gpu/drm/i915/display/dvo_ns2501.c struct ns2501_priv *ns = dvo->dev_priv; dev_priv 484 drivers/gpu/drm/i915/display/dvo_ns2501.c dvo->dev_priv = ns; dev_priv 554 drivers/gpu/drm/i915/display/dvo_ns2501.c struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv); dev_priv 658 drivers/gpu/drm/i915/display/dvo_ns2501.c struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv); dev_priv 694 drivers/gpu/drm/i915/display/dvo_ns2501.c struct ns2501_priv *ns = dvo->dev_priv; dev_priv 698 drivers/gpu/drm/i915/display/dvo_ns2501.c dvo->dev_priv = NULL; dev_priv 71 drivers/gpu/drm/i915/display/dvo_sil164.c struct sil164_priv *sil = dvo->dev_priv; dev_priv 108 drivers/gpu/drm/i915/display/dvo_sil164.c struct sil164_priv *sil = dvo->dev_priv; dev_priv 145 drivers/gpu/drm/i915/display/dvo_sil164.c dvo->dev_priv = sil; dev_priv 263 drivers/gpu/drm/i915/display/dvo_sil164.c struct sil164_priv *sil = dvo->dev_priv; dev_priv 267 drivers/gpu/drm/i915/display/dvo_sil164.c dvo->dev_priv = NULL; dev_priv 96 drivers/gpu/drm/i915/display/dvo_tfp410.c struct tfp410_priv *tfp = dvo->dev_priv; dev_priv 133 drivers/gpu/drm/i915/display/dvo_tfp410.c struct tfp410_priv *tfp = dvo->dev_priv; dev_priv 181 drivers/gpu/drm/i915/display/dvo_tfp410.c dvo->dev_priv = tfp; dev_priv 302 drivers/gpu/drm/i915/display/dvo_tfp410.c struct tfp410_priv *tfp = dvo->dev_priv; dev_priv 306 drivers/gpu/drm/i915/display/dvo_tfp410.c dvo->dev_priv = NULL; dev_priv 38 drivers/gpu/drm/i915/display/icl_dsi.c static inline int header_credits_available(struct drm_i915_private *dev_priv, dev_priv 45 drivers/gpu/drm/i915/display/icl_dsi.c static inline int payload_credits_available(struct drm_i915_private *dev_priv, dev_priv 52 drivers/gpu/drm/i915/display/icl_dsi.c static void wait_for_header_credits(struct drm_i915_private *dev_priv, dev_priv 55 drivers/gpu/drm/i915/display/icl_dsi.c if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= dev_priv 60 drivers/gpu/drm/i915/display/icl_dsi.c static void wait_for_payload_credits(struct drm_i915_private *dev_priv, dev_priv 63 drivers/gpu/drm/i915/display/icl_dsi.c if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= dev_priv 78 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 88 drivers/gpu/drm/i915/display/icl_dsi.c wait_for_header_credits(dev_priv, dsi_trans); dev_priv 89 drivers/gpu/drm/i915/display/icl_dsi.c wait_for_payload_credits(dev_priv, dsi_trans); dev_priv 105 drivers/gpu/drm/i915/display/icl_dsi.c wait_for_header_credits(dev_priv, dsi_trans); dev_priv 121 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); dev_priv 129 drivers/gpu/drm/i915/display/icl_dsi.c free_credits = payload_credits_available(dev_priv, dsi_trans); dev_priv 148 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); dev_priv 154 drivers/gpu/drm/i915/display/icl_dsi.c free_credits = header_credits_available(dev_priv, dsi_trans); dev_priv 203 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 268 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 306 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 331 drivers/gpu/drm/i915/display/icl_dsi.c static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, dev_priv 339 drivers/gpu/drm/i915/display/icl_dsi.c intel_display_power_get(dev_priv, dev_priv 348 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 359 drivers/gpu/drm/i915/display/icl_dsi.c get_dsi_io_power_domains(dev_priv, intel_dsi); dev_priv 364 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 369 drivers/gpu/drm/i915/display/icl_dsi.c intel_combo_phy_power_up_lanes(dev_priv, phy, true, dev_priv 375 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 407 drivers/gpu/drm/i915/display/icl_dsi.c if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) { dev_priv 424 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 476 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 495 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 533 drivers/gpu/drm/i915/display/icl_dsi.c if (IS_GEN(dev_priv, 11)) { dev_priv 550 drivers/gpu/drm/i915/display/icl_dsi.c if (IS_ELKHARTLAKE(dev_priv)) { dev_priv 561 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 566 drivers/gpu/drm/i915/display/icl_dsi.c mutex_lock(&dev_priv->dpll_lock); dev_priv 572 drivers/gpu/drm/i915/display/icl_dsi.c mutex_unlock(&dev_priv->dpll_lock); dev_priv 577 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 582 drivers/gpu/drm/i915/display/icl_dsi.c mutex_lock(&dev_priv->dpll_lock); dev_priv 588 drivers/gpu/drm/i915/display/icl_dsi.c mutex_unlock(&dev_priv->dpll_lock); dev_priv 594 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 600 drivers/gpu/drm/i915/display/icl_dsi.c mutex_lock(&dev_priv->dpll_lock); dev_priv 610 drivers/gpu/drm/i915/display/icl_dsi.c if (INTEL_GEN(dev_priv) >= 12) dev_priv 619 drivers/gpu/drm/i915/display/icl_dsi.c mutex_unlock(&dev_priv->dpll_lock); dev_priv 626 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 688 drivers/gpu/drm/i915/display/icl_dsi.c if (INTEL_GEN(dev_priv) >= 12) { dev_priv 768 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 877 drivers/gpu/drm/i915/display/icl_dsi.c if (INTEL_GEN(dev_priv) >= 12) { dev_priv 888 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 901 drivers/gpu/drm/i915/display/icl_dsi.c if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), dev_priv 909 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 960 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 984 drivers/gpu/drm/i915/display/icl_dsi.c if (IS_GEN(dev_priv, 11)) dev_priv 990 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1066 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1081 drivers/gpu/drm/i915/display/icl_dsi.c if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), dev_priv 1101 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1142 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1164 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1173 drivers/gpu/drm/i915/display/icl_dsi.c intel_display_power_put(dev_priv, dev_priv 1244 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1250 drivers/gpu/drm/i915/display/icl_dsi.c cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state); dev_priv 1302 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1310 drivers/gpu/drm/i915/display/icl_dsi.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 1337 drivers/gpu/drm/i915/display/icl_dsi.c intel_display_power_put(dev_priv, encoder->power_domain, wakeref); dev_priv 1430 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1431 drivers/gpu/drm/i915/display/icl_dsi.c struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; dev_priv 1546 drivers/gpu/drm/i915/display/icl_dsi.c void icl_dsi_init(struct drm_i915_private *dev_priv) dev_priv 1548 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_device *dev = &dev_priv->drm; dev_priv 1556 drivers/gpu/drm/i915/display/icl_dsi.c if (!intel_bios_is_dsi_present(dev_priv, &port)) dev_priv 1615 drivers/gpu/drm/i915/display/icl_dsi.c if (dev_priv->vbt.dsi.config->dual_link) dev_priv 1620 drivers/gpu/drm/i915/display/icl_dsi.c intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; dev_priv 1621 drivers/gpu/drm/i915/display/icl_dsi.c intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; dev_priv 57 drivers/gpu/drm/i915/display/intel_atomic.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 61 drivers/gpu/drm/i915/display/intel_atomic.c if (property == dev_priv->force_audio_property) dev_priv 63 drivers/gpu/drm/i915/display/intel_atomic.c else if (property == dev_priv->broadcast_rgb_property) dev_priv 89 drivers/gpu/drm/i915/display/intel_atomic.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 93 drivers/gpu/drm/i915/display/intel_atomic.c if (property == dev_priv->force_audio_property) { dev_priv 98 drivers/gpu/drm/i915/display/intel_atomic.c if (property == dev_priv->broadcast_rgb_property) { dev_priv 233 drivers/gpu/drm/i915/display/intel_atomic.c struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); dev_priv 257 drivers/gpu/drm/i915/display/intel_atomic.c if (IS_GEN(dev_priv, 9) && dev_priv 258 drivers/gpu/drm/i915/display/intel_atomic.c !IS_GEMINILAKE(dev_priv)) { dev_priv 260 drivers/gpu/drm/i915/display/intel_atomic.c } else if (icl_is_hdr_plane(dev_priv, plane->id)) { dev_priv 273 drivers/gpu/drm/i915/display/intel_atomic.c } else if (INTEL_GEN(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) { dev_priv 311 drivers/gpu/drm/i915/display/intel_atomic.c int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, dev_priv 375 drivers/gpu/drm/i915/display/intel_atomic.c plane = drm_plane_from_index(&dev_priv->drm, i); dev_priv 45 drivers/gpu/drm/i915/display/intel_atomic.h int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, dev_priv 288 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 314 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 335 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 375 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 376 drivers/gpu/drm/i915/display/intel_audio.c struct i915_audio_component *acomp = dev_priv->audio_component; dev_priv 422 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 423 drivers/gpu/drm/i915/display/intel_audio.c struct i915_audio_component *acomp = dev_priv->audio_component; dev_priv 474 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 481 drivers/gpu/drm/i915/display/intel_audio.c mutex_lock(&dev_priv->av_mutex); dev_priv 499 drivers/gpu/drm/i915/display/intel_audio.c mutex_unlock(&dev_priv->av_mutex); dev_priv 506 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 516 drivers/gpu/drm/i915/display/intel_audio.c mutex_lock(&dev_priv->av_mutex); dev_priv 549 drivers/gpu/drm/i915/display/intel_audio.c mutex_unlock(&dev_priv->av_mutex); dev_priv 556 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 569 drivers/gpu/drm/i915/display/intel_audio.c if (HAS_PCH_IBX(dev_priv)) { dev_priv 572 drivers/gpu/drm/i915/display/intel_audio.c } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 602 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 625 drivers/gpu/drm/i915/display/intel_audio.c if (HAS_PCH_IBX(dev_priv)) { dev_priv 630 drivers/gpu/drm/i915/display/intel_audio.c } else if (IS_VALLEYVIEW(dev_priv) || dev_priv 631 drivers/gpu/drm/i915/display/intel_audio.c IS_CHERRYVIEW(dev_priv)) { dev_priv 690 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 691 drivers/gpu/drm/i915/display/intel_audio.c struct i915_audio_component *acomp = dev_priv->audio_component; dev_priv 712 drivers/gpu/drm/i915/display/intel_audio.c if (dev_priv->display.audio_codec_enable) dev_priv 713 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->display.audio_codec_enable(encoder, dev_priv 717 drivers/gpu/drm/i915/display/intel_audio.c mutex_lock(&dev_priv->av_mutex); dev_priv 721 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->av_enc_map[pipe] = encoder; dev_priv 722 drivers/gpu/drm/i915/display/intel_audio.c mutex_unlock(&dev_priv->av_mutex); dev_priv 733 drivers/gpu/drm/i915/display/intel_audio.c intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld, dev_priv 751 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 752 drivers/gpu/drm/i915/display/intel_audio.c struct i915_audio_component *acomp = dev_priv->audio_component; dev_priv 757 drivers/gpu/drm/i915/display/intel_audio.c if (dev_priv->display.audio_codec_disable) dev_priv 758 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->display.audio_codec_disable(encoder, dev_priv 762 drivers/gpu/drm/i915/display/intel_audio.c mutex_lock(&dev_priv->av_mutex); dev_priv 764 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->av_enc_map[pipe] = NULL; dev_priv 765 drivers/gpu/drm/i915/display/intel_audio.c mutex_unlock(&dev_priv->av_mutex); dev_priv 776 drivers/gpu/drm/i915/display/intel_audio.c intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false); dev_priv 783 drivers/gpu/drm/i915/display/intel_audio.c void intel_init_audio_hooks(struct drm_i915_private *dev_priv) dev_priv 785 drivers/gpu/drm/i915/display/intel_audio.c if (IS_G4X(dev_priv)) { dev_priv 786 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; dev_priv 787 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; dev_priv 788 drivers/gpu/drm/i915/display/intel_audio.c } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 789 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; dev_priv 790 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; dev_priv 791 drivers/gpu/drm/i915/display/intel_audio.c } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) { dev_priv 792 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; dev_priv 793 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; dev_priv 794 drivers/gpu/drm/i915/display/intel_audio.c } else if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 795 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; dev_priv 796 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; dev_priv 800 drivers/gpu/drm/i915/display/intel_audio.c static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv, dev_priv 808 drivers/gpu/drm/i915/display/intel_audio.c state = drm_atomic_state_alloc(&dev_priv->drm); dev_priv 824 drivers/gpu/drm/i915/display/intel_audio.c ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, dev_priv 845 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = kdev_to_i915(kdev); dev_priv 851 drivers/gpu/drm/i915/display/intel_audio.c ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); dev_priv 854 drivers/gpu/drm/i915/display/intel_audio.c if (dev_priv->audio_power_refcount++ == 0) dev_priv 855 drivers/gpu/drm/i915/display/intel_audio.c if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) dev_priv 856 drivers/gpu/drm/i915/display/intel_audio.c glk_force_audio_cdclk(dev_priv, true); dev_priv 864 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = kdev_to_i915(kdev); dev_priv 867 drivers/gpu/drm/i915/display/intel_audio.c if (--dev_priv->audio_power_refcount == 0) dev_priv 868 drivers/gpu/drm/i915/display/intel_audio.c if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) dev_priv 869 drivers/gpu/drm/i915/display/intel_audio.c glk_force_audio_cdclk(dev_priv, false); dev_priv 871 drivers/gpu/drm/i915/display/intel_audio.c intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie); dev_priv 877 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = kdev_to_i915(kdev); dev_priv 881 drivers/gpu/drm/i915/display/intel_audio.c if (!IS_GEN(dev_priv, 9)) dev_priv 908 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = kdev_to_i915(kdev); dev_priv 910 drivers/gpu/drm/i915/display/intel_audio.c if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) dev_priv 913 drivers/gpu/drm/i915/display/intel_audio.c return dev_priv->cdclk.hw.cdclk; dev_priv 926 drivers/gpu/drm/i915/display/intel_audio.c static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, dev_priv 933 drivers/gpu/drm/i915/display/intel_audio.c if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map))) dev_priv 936 drivers/gpu/drm/i915/display/intel_audio.c encoder = dev_priv->av_enc_map[pipe]; dev_priv 951 drivers/gpu/drm/i915/display/intel_audio.c for_each_pipe(dev_priv, pipe) { dev_priv 952 drivers/gpu/drm/i915/display/intel_audio.c encoder = dev_priv->av_enc_map[pipe]; dev_priv 969 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = kdev_to_i915(kdev); dev_priv 970 drivers/gpu/drm/i915/display/intel_audio.c struct i915_audio_component *acomp = dev_priv->audio_component; dev_priv 976 drivers/gpu/drm/i915/display/intel_audio.c if (!HAS_DDI(dev_priv)) dev_priv 980 drivers/gpu/drm/i915/display/intel_audio.c mutex_lock(&dev_priv->av_mutex); dev_priv 983 drivers/gpu/drm/i915/display/intel_audio.c encoder = get_saved_enc(dev_priv, port, pipe); dev_priv 998 drivers/gpu/drm/i915/display/intel_audio.c mutex_unlock(&dev_priv->av_mutex); dev_priv 1007 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = kdev_to_i915(kdev); dev_priv 1012 drivers/gpu/drm/i915/display/intel_audio.c mutex_lock(&dev_priv->av_mutex); dev_priv 1014 drivers/gpu/drm/i915/display/intel_audio.c intel_encoder = get_saved_enc(dev_priv, port, pipe); dev_priv 1017 drivers/gpu/drm/i915/display/intel_audio.c mutex_unlock(&dev_priv->av_mutex); dev_priv 1029 drivers/gpu/drm/i915/display/intel_audio.c mutex_unlock(&dev_priv->av_mutex); dev_priv 1047 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); dev_priv 1056 drivers/gpu/drm/i915/display/intel_audio.c drm_modeset_lock_all(&dev_priv->drm); dev_priv 1062 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->audio_component = acomp; dev_priv 1063 drivers/gpu/drm/i915/display/intel_audio.c drm_modeset_unlock_all(&dev_priv->drm); dev_priv 1072 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); dev_priv 1074 drivers/gpu/drm/i915/display/intel_audio.c drm_modeset_lock_all(&dev_priv->drm); dev_priv 1077 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->audio_component = NULL; dev_priv 1078 drivers/gpu/drm/i915/display/intel_audio.c drm_modeset_unlock_all(&dev_priv->drm); dev_priv 1104 drivers/gpu/drm/i915/display/intel_audio.c static void i915_audio_component_init(struct drm_i915_private *dev_priv) dev_priv 1108 drivers/gpu/drm/i915/display/intel_audio.c ret = component_add_typed(dev_priv->drm.dev, dev_priv 1117 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->audio_component_registered = true; dev_priv 1127 drivers/gpu/drm/i915/display/intel_audio.c static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) dev_priv 1129 drivers/gpu/drm/i915/display/intel_audio.c if (!dev_priv->audio_component_registered) dev_priv 1132 drivers/gpu/drm/i915/display/intel_audio.c component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); dev_priv 1133 drivers/gpu/drm/i915/display/intel_audio.c dev_priv->audio_component_registered = false; dev_priv 1142 drivers/gpu/drm/i915/display/intel_audio.c void intel_audio_init(struct drm_i915_private *dev_priv) dev_priv 1144 drivers/gpu/drm/i915/display/intel_audio.c if (intel_lpe_audio_init(dev_priv) < 0) dev_priv 1145 drivers/gpu/drm/i915/display/intel_audio.c i915_audio_component_init(dev_priv); dev_priv 1153 drivers/gpu/drm/i915/display/intel_audio.c void intel_audio_deinit(struct drm_i915_private *dev_priv) dev_priv 1155 drivers/gpu/drm/i915/display/intel_audio.c if ((dev_priv)->lpe_audio.platdev != NULL) dev_priv 1156 drivers/gpu/drm/i915/display/intel_audio.c intel_lpe_audio_teardown(dev_priv); dev_priv 1158 drivers/gpu/drm/i915/display/intel_audio.c i915_audio_component_cleanup(dev_priv); dev_priv 14 drivers/gpu/drm/i915/display/intel_audio.h void intel_init_audio_hooks(struct drm_i915_private *dev_priv); dev_priv 21 drivers/gpu/drm/i915/display/intel_audio.h void intel_audio_init(struct drm_i915_private *dev_priv); dev_priv 22 drivers/gpu/drm/i915/display/intel_audio.h void intel_audio_deinit(struct drm_i915_private *dev_priv); dev_priv 207 drivers/gpu/drm/i915/display/intel_bios.c parse_lfp_panel_data(struct drm_i915_private *dev_priv, dev_priv 224 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.lvds_dither = lvds_options->pixel_dither; dev_priv 226 drivers/gpu/drm/i915/display/intel_bios.c ret = intel_opregion_get_panel_type(dev_priv); dev_priv 241 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.panel_type = panel_type; dev_priv 252 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT; dev_priv 256 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT; dev_priv 260 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; dev_priv 283 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; dev_priv 295 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val; dev_priv 297 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.bios_lvds_val); dev_priv 303 drivers/gpu/drm/i915/display/intel_bios.c parse_lfp_backlight(struct drm_i915_private *dev_priv, dev_priv 308 drivers/gpu/drm/i915/display/intel_bios.c int panel_type = dev_priv->vbt.panel_type; dev_priv 322 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM; dev_priv 323 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.backlight.present) { dev_priv 329 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI; dev_priv 335 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.backlight.type = method->type; dev_priv 336 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.backlight.controller = method->controller; dev_priv 339 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; dev_priv 340 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm; dev_priv 341 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.backlight.min_brightness = entry->min_brightness; dev_priv 344 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.backlight.pwm_freq_hz, dev_priv 345 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.backlight.active_low_pwm ? "low" : "high", dev_priv 346 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.backlight.min_brightness, dev_priv 348 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.backlight.controller); dev_priv 353 drivers/gpu/drm/i915/display/intel_bios.c parse_sdvo_panel_data(struct drm_i915_private *dev_priv, dev_priv 386 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode; dev_priv 392 drivers/gpu/drm/i915/display/intel_bios.c static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, dev_priv 395 drivers/gpu/drm/i915/display/intel_bios.c switch (INTEL_GEN(dev_priv)) { dev_priv 407 drivers/gpu/drm/i915/display/intel_bios.c parse_general_features(struct drm_i915_private *dev_priv, dev_priv 416 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.int_tv_support = general->int_tv_support; dev_priv 419 drivers/gpu/drm/i915/display/intel_bios.c (HAS_DDI(dev_priv) || IS_VALLEYVIEW(dev_priv))) dev_priv 420 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.int_crt_support = general->int_crt_support; dev_priv 421 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.lvds_use_ssc = general->enable_ssc; dev_priv 422 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.lvds_ssc_freq = dev_priv 423 drivers/gpu/drm/i915/display/intel_bios.c intel_bios_ssc_frequency(dev_priv, general->ssc_freq); dev_priv 424 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.display_clock_mode = general->display_clock_mode; dev_priv 425 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted; dev_priv 427 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.orientation = general->rotate_180 ? dev_priv 431 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; dev_priv 434 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.int_tv_support, dev_priv 435 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.int_crt_support, dev_priv 436 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.lvds_use_ssc, dev_priv 437 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.lvds_ssc_freq, dev_priv 438 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.display_clock_mode, dev_priv 439 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.fdi_rx_polarity_inverted); dev_priv 449 drivers/gpu/drm/i915/display/intel_bios.c parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) dev_priv 459 drivers/gpu/drm/i915/display/intel_bios.c if (!IS_GEN_RANGE(dev_priv, 3, 7)) { dev_priv 464 drivers/gpu/drm/i915/display/intel_bios.c for (i = 0, count = 0; i < dev_priv->vbt.child_dev_num; i++) { dev_priv 465 drivers/gpu/drm/i915/display/intel_bios.c child = dev_priv->vbt.child_dev + i; dev_priv 486 drivers/gpu/drm/i915/display/intel_bios.c mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1]; dev_priv 520 drivers/gpu/drm/i915/display/intel_bios.c parse_driver_features(struct drm_i915_private *dev_priv, dev_priv 529 drivers/gpu/drm/i915/display/intel_bios.c if (INTEL_GEN(dev_priv) >= 5) { dev_priv 536 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.int_lvds_support = 0; dev_priv 552 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.int_lvds_support = 0; dev_priv 563 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; dev_priv 564 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.enable = driver->psr_enabled; dev_priv 568 drivers/gpu/drm/i915/display/intel_bios.c parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) dev_priv 573 drivers/gpu/drm/i915/display/intel_bios.c int panel_type = dev_priv->vbt.panel_type; dev_priv 581 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.bpp = 18; dev_priv 584 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.bpp = 24; dev_priv 587 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.bpp = 30; dev_priv 595 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.pps = *edp_pps; dev_priv 599 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.rate = DP_LINK_BW_1_62; dev_priv 602 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.rate = DP_LINK_BW_2_7; dev_priv 612 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.lanes = 1; dev_priv 615 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.lanes = 2; dev_priv 618 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.lanes = 4; dev_priv 628 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0; dev_priv 631 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1; dev_priv 634 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2; dev_priv 637 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; dev_priv 647 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; dev_priv 650 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1; dev_priv 653 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2; dev_priv 656 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; dev_priv 669 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.low_vswing = dev_priv 673 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.low_vswing = vswing == 0; dev_priv 679 drivers/gpu/drm/i915/display/intel_bios.c parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) dev_priv 683 drivers/gpu/drm/i915/display/intel_bios.c int panel_type = dev_priv->vbt.panel_type; dev_priv 693 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.full_link = psr_table->full_link; dev_priv 694 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup; dev_priv 697 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 : dev_priv 702 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT; dev_priv 705 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT; dev_priv 708 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT; dev_priv 711 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT; dev_priv 724 drivers/gpu/drm/i915/display/intel_bios.c (IS_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) || dev_priv 725 drivers/gpu/drm/i915/display/intel_bios.c INTEL_GEN(dev_priv) >= 10)) { dev_priv 728 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.tp1_wakeup_time_us = 500; dev_priv 731 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.tp1_wakeup_time_us = 100; dev_priv 734 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.tp1_wakeup_time_us = 0; dev_priv 741 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.tp1_wakeup_time_us = 2500; dev_priv 747 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500; dev_priv 750 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100; dev_priv 753 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 0; dev_priv 760 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500; dev_priv 764 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100; dev_priv 765 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100; dev_priv 787 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time; dev_priv 790 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = dev_priv->vbt.psr.tp2_tp3_wakeup_time_us; dev_priv 794 drivers/gpu/drm/i915/display/intel_bios.c static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv, dev_priv 797 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.dsi.config->dual_link || version < 197) { dev_priv 798 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.bl_ports = BIT(port); dev_priv 799 drivers/gpu/drm/i915/display/intel_bios.c if (dev_priv->vbt.dsi.config->cabc_supported) dev_priv 800 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.cabc_ports = BIT(port); dev_priv 805 drivers/gpu/drm/i915/display/intel_bios.c switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) { dev_priv 807 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.bl_ports = BIT(PORT_A); dev_priv 810 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.bl_ports = BIT(PORT_C); dev_priv 814 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C); dev_priv 818 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.dsi.config->cabc_supported) dev_priv 821 drivers/gpu/drm/i915/display/intel_bios.c switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) { dev_priv 823 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.cabc_ports = BIT(PORT_A); dev_priv 826 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.cabc_ports = BIT(PORT_C); dev_priv 830 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.cabc_ports = dev_priv 837 drivers/gpu/drm/i915/display/intel_bios.c parse_mipi_config(struct drm_i915_private *dev_priv, dev_priv 843 drivers/gpu/drm/i915/display/intel_bios.c int panel_type = dev_priv->vbt.panel_type; dev_priv 847 drivers/gpu/drm/i915/display/intel_bios.c if (!intel_bios_is_dsi_present(dev_priv, &port)) dev_priv 851 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID; dev_priv 878 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL); dev_priv 879 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.dsi.config) dev_priv 882 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL); dev_priv 883 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.dsi.pps) { dev_priv 884 drivers/gpu/drm/i915/display/intel_bios.c kfree(dev_priv->vbt.dsi.config); dev_priv 888 drivers/gpu/drm/i915/display/intel_bios.c parse_dsi_backlight_ports(dev_priv, bdb->version, port); dev_priv 897 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.orientation = dev_priv 901 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.orientation = dev_priv 905 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.orientation = dev_priv 909 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.orientation = dev_priv 915 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID; dev_priv 1078 drivers/gpu/drm/i915/display/intel_bios.c static int get_init_otp_deassert_fragment_len(struct drm_i915_private *dev_priv) dev_priv 1080 drivers/gpu/drm/i915/display/intel_bios.c const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; dev_priv 1083 drivers/gpu/drm/i915/display/intel_bios.c if (WARN_ON(!data || dev_priv->vbt.dsi.seq_version != 1)) dev_priv 1111 drivers/gpu/drm/i915/display/intel_bios.c static void fixup_mipi_sequences(struct drm_i915_private *dev_priv) dev_priv 1117 drivers/gpu/drm/i915/display/intel_bios.c if (!IS_VALLEYVIEW(dev_priv)) dev_priv 1121 drivers/gpu/drm/i915/display/intel_bios.c if (dev_priv->vbt.dsi.config->is_cmd_mode || dev_priv 1122 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.seq_version != 1) dev_priv 1126 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] || dev_priv 1127 drivers/gpu/drm/i915/display/intel_bios.c !dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] || dev_priv 1128 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) dev_priv 1132 drivers/gpu/drm/i915/display/intel_bios.c len = get_init_otp_deassert_fragment_len(dev_priv); dev_priv 1139 drivers/gpu/drm/i915/display/intel_bios.c init_otp = (u8 *)dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; dev_priv 1140 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL); dev_priv 1141 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.dsi.deassert_seq) dev_priv 1143 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET; dev_priv 1144 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END; dev_priv 1146 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] = dev_priv 1147 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.deassert_seq; dev_priv 1151 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1; dev_priv 1155 drivers/gpu/drm/i915/display/intel_bios.c parse_mipi_sequence(struct drm_i915_private *dev_priv, dev_priv 1158 drivers/gpu/drm/i915/display/intel_bios.c int panel_type = dev_priv->vbt.panel_type; dev_priv 1166 drivers/gpu/drm/i915/display/intel_bios.c if (dev_priv->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID) dev_priv 1207 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.sequence[seq_id] = data + index; dev_priv 1219 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.data = data; dev_priv 1220 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.size = seq_size; dev_priv 1221 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.seq_version = sequence->version; dev_priv 1223 drivers/gpu/drm/i915/display/intel_bios.c fixup_mipi_sequences(dev_priv); dev_priv 1230 drivers/gpu/drm/i915/display/intel_bios.c memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence)); dev_priv 1259 drivers/gpu/drm/i915/display/intel_bios.c static void sanitize_ddc_pin(struct drm_i915_private *dev_priv, dev_priv 1262 drivers/gpu/drm/i915/display/intel_bios.c struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; dev_priv 1268 drivers/gpu/drm/i915/display/intel_bios.c p = get_port_by_ddc_pin(dev_priv, info->alternate_ddc_pin); dev_priv 1287 drivers/gpu/drm/i915/display/intel_bios.c info = &dev_priv->vbt.ddi_port_info[p]; dev_priv 1310 drivers/gpu/drm/i915/display/intel_bios.c static void sanitize_aux_ch(struct drm_i915_private *dev_priv, dev_priv 1313 drivers/gpu/drm/i915/display/intel_bios.c struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; dev_priv 1319 drivers/gpu/drm/i915/display/intel_bios.c p = get_port_by_aux_ch(dev_priv, info->alternate_aux_channel); dev_priv 1338 drivers/gpu/drm/i915/display/intel_bios.c info = &dev_priv->vbt.ddi_port_info[p]; dev_priv 1365 drivers/gpu/drm/i915/display/intel_bios.c static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) dev_priv 1370 drivers/gpu/drm/i915/display/intel_bios.c if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { dev_priv 1373 drivers/gpu/drm/i915/display/intel_bios.c } else if (HAS_PCH_CNP(dev_priv)) { dev_priv 1419 drivers/gpu/drm/i915/display/intel_bios.c static void parse_ddi_port(struct drm_i915_private *dev_priv, dev_priv 1431 drivers/gpu/drm/i915/display/intel_bios.c info = &dev_priv->vbt.ddi_port_info[port]; dev_priv 1465 drivers/gpu/drm/i915/display/intel_bios.c HAS_LSPCON(dev_priv) && child->lspcon, dev_priv 1487 drivers/gpu/drm/i915/display/intel_bios.c ddc_pin = map_ddc_pin(dev_priv, child->ddc_pin); dev_priv 1488 drivers/gpu/drm/i915/display/intel_bios.c if (intel_gmbus_is_valid_pin(dev_priv, ddc_pin)) { dev_priv 1490 drivers/gpu/drm/i915/display/intel_bios.c sanitize_ddc_pin(dev_priv, port); dev_priv 1501 drivers/gpu/drm/i915/display/intel_bios.c sanitize_aux_ch(dev_priv, port); dev_priv 1571 drivers/gpu/drm/i915/display/intel_bios.c static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version) dev_priv 1576 drivers/gpu/drm/i915/display/intel_bios.c if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv)) dev_priv 1582 drivers/gpu/drm/i915/display/intel_bios.c for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { dev_priv 1583 drivers/gpu/drm/i915/display/intel_bios.c child = dev_priv->vbt.child_dev + i; dev_priv 1585 drivers/gpu/drm/i915/display/intel_bios.c parse_ddi_port(dev_priv, child, bdb_version); dev_priv 1590 drivers/gpu/drm/i915/display/intel_bios.c parse_general_definitions(struct drm_i915_private *dev_priv, dev_priv 1615 drivers/gpu/drm/i915/display/intel_bios.c if (intel_gmbus_is_valid_pin(dev_priv, bus_pin)) dev_priv 1616 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.crt_ddc_pin = bus_pin; dev_priv 1663 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.child_dev = kcalloc(count, sizeof(*child), GFP_KERNEL); dev_priv 1664 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.child_dev) { dev_priv 1669 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.child_dev_num = count; dev_priv 1684 drivers/gpu/drm/i915/display/intel_bios.c memcpy(dev_priv->vbt.child_dev + count, child, dev_priv 1692 drivers/gpu/drm/i915/display/intel_bios.c init_vbt_defaults(struct drm_i915_private *dev_priv) dev_priv 1696 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; dev_priv 1699 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.backlight.present = true; dev_priv 1702 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.lvds_dither = 1; dev_priv 1705 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; dev_priv 1708 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.int_tv_support = 1; dev_priv 1709 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.int_crt_support = 1; dev_priv 1712 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.int_lvds_support = 1; dev_priv 1715 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.lvds_use_ssc = 1; dev_priv 1720 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev_priv, dev_priv 1721 drivers/gpu/drm/i915/display/intel_bios.c !HAS_PCH_SPLIT(dev_priv)); dev_priv 1722 drivers/gpu/drm/i915/display/intel_bios.c DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq); dev_priv 1726 drivers/gpu/drm/i915/display/intel_bios.c &dev_priv->vbt.ddi_port_info[port]; dev_priv 1734 drivers/gpu/drm/i915/display/intel_bios.c init_vbt_missing_defaults(struct drm_i915_private *dev_priv) dev_priv 1740 drivers/gpu/drm/i915/display/intel_bios.c &dev_priv->vbt.ddi_port_info[port]; dev_priv 1741 drivers/gpu/drm/i915/display/intel_bios.c enum phy phy = intel_port_to_phy(dev_priv, port); dev_priv 1747 drivers/gpu/drm/i915/display/intel_bios.c if (intel_phy_is_tc(dev_priv, phy)) dev_priv 1839 drivers/gpu/drm/i915/display/intel_bios.c void intel_bios_init(struct drm_i915_private *dev_priv) dev_priv 1841 drivers/gpu/drm/i915/display/intel_bios.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 1842 drivers/gpu/drm/i915/display/intel_bios.c const struct vbt_header *vbt = dev_priv->opregion.vbt; dev_priv 1846 drivers/gpu/drm/i915/display/intel_bios.c if (!HAS_DISPLAY(dev_priv)) { dev_priv 1851 drivers/gpu/drm/i915/display/intel_bios.c init_vbt_defaults(dev_priv); dev_priv 1874 drivers/gpu/drm/i915/display/intel_bios.c parse_general_features(dev_priv, bdb); dev_priv 1875 drivers/gpu/drm/i915/display/intel_bios.c parse_general_definitions(dev_priv, bdb); dev_priv 1876 drivers/gpu/drm/i915/display/intel_bios.c parse_lfp_panel_data(dev_priv, bdb); dev_priv 1877 drivers/gpu/drm/i915/display/intel_bios.c parse_lfp_backlight(dev_priv, bdb); dev_priv 1878 drivers/gpu/drm/i915/display/intel_bios.c parse_sdvo_panel_data(dev_priv, bdb); dev_priv 1879 drivers/gpu/drm/i915/display/intel_bios.c parse_driver_features(dev_priv, bdb); dev_priv 1880 drivers/gpu/drm/i915/display/intel_bios.c parse_edp(dev_priv, bdb); dev_priv 1881 drivers/gpu/drm/i915/display/intel_bios.c parse_psr(dev_priv, bdb); dev_priv 1882 drivers/gpu/drm/i915/display/intel_bios.c parse_mipi_config(dev_priv, bdb); dev_priv 1883 drivers/gpu/drm/i915/display/intel_bios.c parse_mipi_sequence(dev_priv, bdb); dev_priv 1886 drivers/gpu/drm/i915/display/intel_bios.c parse_sdvo_device_mapping(dev_priv, bdb->version); dev_priv 1887 drivers/gpu/drm/i915/display/intel_bios.c parse_ddi_ports(dev_priv, bdb->version); dev_priv 1892 drivers/gpu/drm/i915/display/intel_bios.c init_vbt_missing_defaults(dev_priv); dev_priv 1903 drivers/gpu/drm/i915/display/intel_bios.c void intel_bios_driver_remove(struct drm_i915_private *dev_priv) dev_priv 1905 drivers/gpu/drm/i915/display/intel_bios.c kfree(dev_priv->vbt.child_dev); dev_priv 1906 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.child_dev = NULL; dev_priv 1907 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.child_dev_num = 0; dev_priv 1908 drivers/gpu/drm/i915/display/intel_bios.c kfree(dev_priv->vbt.sdvo_lvds_vbt_mode); dev_priv 1909 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; dev_priv 1910 drivers/gpu/drm/i915/display/intel_bios.c kfree(dev_priv->vbt.lfp_lvds_vbt_mode); dev_priv 1911 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.lfp_lvds_vbt_mode = NULL; dev_priv 1912 drivers/gpu/drm/i915/display/intel_bios.c kfree(dev_priv->vbt.dsi.data); dev_priv 1913 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.data = NULL; dev_priv 1914 drivers/gpu/drm/i915/display/intel_bios.c kfree(dev_priv->vbt.dsi.pps); dev_priv 1915 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.pps = NULL; dev_priv 1916 drivers/gpu/drm/i915/display/intel_bios.c kfree(dev_priv->vbt.dsi.config); dev_priv 1917 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.config = NULL; dev_priv 1918 drivers/gpu/drm/i915/display/intel_bios.c kfree(dev_priv->vbt.dsi.deassert_seq); dev_priv 1919 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.deassert_seq = NULL; dev_priv 1929 drivers/gpu/drm/i915/display/intel_bios.c bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv) dev_priv 1934 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.int_tv_support) dev_priv 1937 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.child_dev_num) dev_priv 1940 drivers/gpu/drm/i915/display/intel_bios.c for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { dev_priv 1941 drivers/gpu/drm/i915/display/intel_bios.c child = dev_priv->vbt.child_dev + i; dev_priv 1971 drivers/gpu/drm/i915/display/intel_bios.c bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin) dev_priv 1976 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.child_dev_num) dev_priv 1979 drivers/gpu/drm/i915/display/intel_bios.c for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { dev_priv 1980 drivers/gpu/drm/i915/display/intel_bios.c child = dev_priv->vbt.child_dev + i; dev_priv 1990 drivers/gpu/drm/i915/display/intel_bios.c if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin)) dev_priv 2006 drivers/gpu/drm/i915/display/intel_bios.c if (dev_priv->opregion.vbt) dev_priv 2020 drivers/gpu/drm/i915/display/intel_bios.c bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port) dev_priv 2034 drivers/gpu/drm/i915/display/intel_bios.c if (HAS_DDI(dev_priv)) { dev_priv 2036 drivers/gpu/drm/i915/display/intel_bios.c &dev_priv->vbt.ddi_port_info[port]; dev_priv 2047 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.child_dev_num) dev_priv 2050 drivers/gpu/drm/i915/display/intel_bios.c for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { dev_priv 2051 drivers/gpu/drm/i915/display/intel_bios.c child = dev_priv->vbt.child_dev + i; dev_priv 2070 drivers/gpu/drm/i915/display/intel_bios.c bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port) dev_priv 2082 drivers/gpu/drm/i915/display/intel_bios.c if (HAS_DDI(dev_priv)) dev_priv 2083 drivers/gpu/drm/i915/display/intel_bios.c return dev_priv->vbt.ddi_port_info[port].supports_edp; dev_priv 2085 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.child_dev_num) dev_priv 2088 drivers/gpu/drm/i915/display/intel_bios.c for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { dev_priv 2089 drivers/gpu/drm/i915/display/intel_bios.c child = dev_priv->vbt.child_dev + i; dev_priv 2135 drivers/gpu/drm/i915/display/intel_bios.c bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, dev_priv 2141 drivers/gpu/drm/i915/display/intel_bios.c for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { dev_priv 2142 drivers/gpu/drm/i915/display/intel_bios.c child = dev_priv->vbt.child_dev + i; dev_priv 2158 drivers/gpu/drm/i915/display/intel_bios.c bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, dev_priv 2165 drivers/gpu/drm/i915/display/intel_bios.c for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { dev_priv 2166 drivers/gpu/drm/i915/display/intel_bios.c child = dev_priv->vbt.child_dev + i; dev_priv 2174 drivers/gpu/drm/i915/display/intel_bios.c (dvo_port == DVO_PORT_MIPIB && INTEL_GEN(dev_priv) >= 11) || dev_priv 2175 drivers/gpu/drm/i915/display/intel_bios.c (dvo_port == DVO_PORT_MIPIC && INTEL_GEN(dev_priv) < 11)) { dev_priv 2227 drivers/gpu/drm/i915/display/intel_bios.c enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, dev_priv 2231 drivers/gpu/drm/i915/display/intel_bios.c &dev_priv->vbt.ddi_port_info[port]; dev_priv 230 drivers/gpu/drm/i915/display/intel_bios.h void intel_bios_init(struct drm_i915_private *dev_priv); dev_priv 231 drivers/gpu/drm/i915/display/intel_bios.h void intel_bios_driver_remove(struct drm_i915_private *dev_priv); dev_priv 233 drivers/gpu/drm/i915/display/intel_bios.h bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); dev_priv 234 drivers/gpu/drm/i915/display/intel_bios.h bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); dev_priv 235 drivers/gpu/drm/i915/display/intel_bios.h bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); dev_priv 236 drivers/gpu/drm/i915/display/intel_bios.h bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); dev_priv 237 drivers/gpu/drm/i915/display/intel_bios.h bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); dev_priv 238 drivers/gpu/drm/i915/display/intel_bios.h bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); dev_priv 243 drivers/gpu/drm/i915/display/intel_bios.h enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port); dev_priv 25 drivers/gpu/drm/i915/display/intel_bw.c static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv, dev_priv 31 drivers/gpu/drm/i915/display/intel_bw.c ret = sandybridge_pcode_read(dev_priv, dev_priv 64 drivers/gpu/drm/i915/display/intel_bw.c static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, dev_priv 71 drivers/gpu/drm/i915/display/intel_bw.c ret = sandybridge_pcode_read(dev_priv, dev_priv 90 drivers/gpu/drm/i915/display/intel_bw.c static int icl_get_qgv_points(struct drm_i915_private *dev_priv, dev_priv 95 drivers/gpu/drm/i915/display/intel_bw.c ret = icl_pcode_read_mem_global_info(dev_priv, qi); dev_priv 105 drivers/gpu/drm/i915/display/intel_bw.c ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i); dev_priv 145 drivers/gpu/drm/i915/display/intel_bw.c static int icl_get_bw_info(struct drm_i915_private *dev_priv) dev_priv 157 drivers/gpu/drm/i915/display/intel_bw.c ret = icl_get_qgv_points(dev_priv, &qi); dev_priv 173 drivers/gpu/drm/i915/display/intel_bw.c for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { dev_priv 174 drivers/gpu/drm/i915/display/intel_bw.c struct intel_bw_info *bi = &dev_priv->max_bw[i]; dev_priv 211 drivers/gpu/drm/i915/display/intel_bw.c static unsigned int icl_max_bw(struct drm_i915_private *dev_priv, dev_priv 216 drivers/gpu/drm/i915/display/intel_bw.c for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { dev_priv 218 drivers/gpu/drm/i915/display/intel_bw.c &dev_priv->max_bw[i]; dev_priv 234 drivers/gpu/drm/i915/display/intel_bw.c void intel_bw_init_hw(struct drm_i915_private *dev_priv) dev_priv 236 drivers/gpu/drm/i915/display/intel_bw.c if (IS_GEN(dev_priv, 11)) dev_priv 237 drivers/gpu/drm/i915/display/intel_bw.c icl_get_bw_info(dev_priv); dev_priv 240 drivers/gpu/drm/i915/display/intel_bw.c static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv, dev_priv 243 drivers/gpu/drm/i915/display/intel_bw.c if (IS_GEN(dev_priv, 11)) dev_priv 249 drivers/gpu/drm/i915/display/intel_bw.c return min3(icl_max_bw(dev_priv, num_planes, 0), dev_priv 250 drivers/gpu/drm/i915/display/intel_bw.c icl_max_bw(dev_priv, num_planes, 1), dev_priv 251 drivers/gpu/drm/i915/display/intel_bw.c icl_max_bw(dev_priv, num_planes, 2)); dev_priv 301 drivers/gpu/drm/i915/display/intel_bw.c static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv, dev_priv 307 drivers/gpu/drm/i915/display/intel_bw.c for_each_pipe(dev_priv, pipe) dev_priv 313 drivers/gpu/drm/i915/display/intel_bw.c static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv, dev_priv 319 drivers/gpu/drm/i915/display/intel_bw.c for_each_pipe(dev_priv, pipe) dev_priv 328 drivers/gpu/drm/i915/display/intel_bw.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 332 drivers/gpu/drm/i915/display/intel_bw.c &dev_priv->bw_obj); dev_priv 341 drivers/gpu/drm/i915/display/intel_bw.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 350 drivers/gpu/drm/i915/display/intel_bw.c if (INTEL_GEN(dev_priv) < 11) dev_priv 388 drivers/gpu/drm/i915/display/intel_bw.c data_rate = intel_bw_data_rate(dev_priv, bw_state); dev_priv 389 drivers/gpu/drm/i915/display/intel_bw.c num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state); dev_priv 391 drivers/gpu/drm/i915/display/intel_bw.c max_data_rate = intel_max_data_rate(dev_priv, num_active_planes); dev_priv 428 drivers/gpu/drm/i915/display/intel_bw.c int intel_bw_init(struct drm_i915_private *dev_priv) dev_priv 436 drivers/gpu/drm/i915/display/intel_bw.c drm_atomic_private_obj_init(&dev_priv->drm, &dev_priv->bw_obj, dev_priv 26 drivers/gpu/drm/i915/display/intel_bw.h void intel_bw_init_hw(struct drm_i915_private *dev_priv); dev_priv 27 drivers/gpu/drm/i915/display/intel_bw.h int intel_bw_init(struct drm_i915_private *dev_priv); dev_priv 56 drivers/gpu/drm/i915/display/intel_cdclk.c static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 62 drivers/gpu/drm/i915/display/intel_cdclk.c static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 68 drivers/gpu/drm/i915/display/intel_cdclk.c static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 74 drivers/gpu/drm/i915/display/intel_cdclk.c static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 80 drivers/gpu/drm/i915/display/intel_cdclk.c static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 86 drivers/gpu/drm/i915/display/intel_cdclk.c static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 92 drivers/gpu/drm/i915/display/intel_cdclk.c static void i85x_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 95 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 134 drivers/gpu/drm/i915/display/intel_cdclk.c static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 137 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 158 drivers/gpu/drm/i915/display/intel_cdclk.c static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 161 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 182 drivers/gpu/drm/i915/display/intel_cdclk.c static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) dev_priv 226 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_GM45(dev_priv)) dev_priv 228 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_G45(dev_priv)) dev_priv 230 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_I965GM(dev_priv)) dev_priv 232 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_PINEVIEW(dev_priv)) dev_priv 234 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_G33(dev_priv)) dev_priv 239 drivers/gpu/drm/i915/display/intel_cdclk.c tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? dev_priv 251 drivers/gpu/drm/i915/display/intel_cdclk.c static void g33_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 254 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 263 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = intel_hpll_vco(dev_priv); dev_priv 299 drivers/gpu/drm/i915/display/intel_cdclk.c static void pnv_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 302 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 332 drivers/gpu/drm/i915/display/intel_cdclk.c static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 335 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 343 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = intel_hpll_vco(dev_priv); dev_priv 376 drivers/gpu/drm/i915/display/intel_cdclk.c static void gm45_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 379 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 383 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = intel_hpll_vco(dev_priv); dev_priv 406 drivers/gpu/drm/i915/display/intel_cdclk.c static void hsw_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 418 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_HSW_ULT(dev_priv)) dev_priv 424 drivers/gpu/drm/i915/display/intel_cdclk.c static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) dev_priv 426 drivers/gpu/drm/i915/display/intel_cdclk.c int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? dev_priv 434 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) dev_priv 444 drivers/gpu/drm/i915/display/intel_cdclk.c static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) dev_priv 446 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_VALLEYVIEW(dev_priv)) { dev_priv 459 drivers/gpu/drm/i915/display/intel_cdclk.c return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; dev_priv 463 drivers/gpu/drm/i915/display/intel_cdclk.c static void vlv_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 468 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_iosf_sb_get(dev_priv, dev_priv 471 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = vlv_get_hpll_vco(dev_priv); dev_priv 472 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", dev_priv 476 drivers/gpu/drm/i915/display/intel_cdclk.c val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); dev_priv 478 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_iosf_sb_put(dev_priv, dev_priv 481 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_VALLEYVIEW(dev_priv)) dev_priv 489 drivers/gpu/drm/i915/display/intel_cdclk.c static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) dev_priv 493 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 498 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { dev_priv 500 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 525 drivers/gpu/drm/i915/display/intel_cdclk.c static void vlv_set_cdclk(struct drm_i915_private *dev_priv, dev_priv 551 drivers/gpu/drm/i915/display/intel_cdclk.c wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); dev_priv 553 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_iosf_sb_get(dev_priv, dev_priv 558 drivers/gpu/drm/i915/display/intel_cdclk.c val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); dev_priv 561 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); dev_priv 562 drivers/gpu/drm/i915/display/intel_cdclk.c if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & dev_priv 571 drivers/gpu/drm/i915/display/intel_cdclk.c divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, dev_priv 575 drivers/gpu/drm/i915/display/intel_cdclk.c val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); dev_priv 578 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); dev_priv 580 drivers/gpu/drm/i915/display/intel_cdclk.c if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & dev_priv 587 drivers/gpu/drm/i915/display/intel_cdclk.c val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); dev_priv 598 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); dev_priv 600 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_iosf_sb_put(dev_priv, dev_priv 605 drivers/gpu/drm/i915/display/intel_cdclk.c intel_update_cdclk(dev_priv); dev_priv 607 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_program_pfi_credits(dev_priv); dev_priv 609 drivers/gpu/drm/i915/display/intel_cdclk.c intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); dev_priv 612 drivers/gpu/drm/i915/display/intel_cdclk.c static void chv_set_cdclk(struct drm_i915_private *dev_priv, dev_priv 637 drivers/gpu/drm/i915/display/intel_cdclk.c wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); dev_priv 639 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_punit_get(dev_priv); dev_priv 640 drivers/gpu/drm/i915/display/intel_cdclk.c val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); dev_priv 643 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); dev_priv 644 drivers/gpu/drm/i915/display/intel_cdclk.c if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & dev_priv 650 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_punit_put(dev_priv); dev_priv 652 drivers/gpu/drm/i915/display/intel_cdclk.c intel_update_cdclk(dev_priv); dev_priv 654 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_program_pfi_credits(dev_priv); dev_priv 656 drivers/gpu/drm/i915/display/intel_cdclk.c intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); dev_priv 686 drivers/gpu/drm/i915/display/intel_cdclk.c static void bdw_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 713 drivers/gpu/drm/i915/display/intel_cdclk.c static void bdw_set_cdclk(struct drm_i915_private *dev_priv, dev_priv 729 drivers/gpu/drm/i915/display/intel_cdclk.c ret = sandybridge_pcode_write(dev_priv, dev_priv 779 drivers/gpu/drm/i915/display/intel_cdclk.c sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, dev_priv 784 drivers/gpu/drm/i915/display/intel_cdclk.c intel_update_cdclk(dev_priv); dev_priv 822 drivers/gpu/drm/i915/display/intel_cdclk.c static void skl_dpll0_update(struct drm_i915_private *dev_priv, dev_priv 862 drivers/gpu/drm/i915/display/intel_cdclk.c static void skl_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 867 drivers/gpu/drm/i915/display/intel_cdclk.c skl_dpll0_update(dev_priv, cdclk_state); dev_priv 929 drivers/gpu/drm/i915/display/intel_cdclk.c static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, dev_priv 932 drivers/gpu/drm/i915/display/intel_cdclk.c bool changed = dev_priv->skl_preferred_vco_freq != vco; dev_priv 934 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->skl_preferred_vco_freq = vco; dev_priv 937 drivers/gpu/drm/i915/display/intel_cdclk.c intel_update_max_cdclk(dev_priv); dev_priv 940 drivers/gpu/drm/i915/display/intel_cdclk.c static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) dev_priv 972 drivers/gpu/drm/i915/display/intel_cdclk.c if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) dev_priv 975 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = vco; dev_priv 978 drivers/gpu/drm/i915/display/intel_cdclk.c skl_set_preferred_cdclk_vco(dev_priv, vco); dev_priv 981 drivers/gpu/drm/i915/display/intel_cdclk.c static void skl_dpll0_disable(struct drm_i915_private *dev_priv) dev_priv 984 drivers/gpu/drm/i915/display/intel_cdclk.c if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) dev_priv 987 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = 0; dev_priv 990 drivers/gpu/drm/i915/display/intel_cdclk.c static void skl_set_cdclk(struct drm_i915_private *dev_priv, dev_priv 1007 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000); dev_priv 1009 drivers/gpu/drm/i915/display/intel_cdclk.c ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, dev_priv 1022 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); dev_priv 1042 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != 0 && dev_priv 1043 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != vco) dev_priv 1044 drivers/gpu/drm/i915/display/intel_cdclk.c skl_dpll0_disable(dev_priv); dev_priv 1048 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != vco) { dev_priv 1060 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != vco) dev_priv 1061 drivers/gpu/drm/i915/display/intel_cdclk.c skl_dpll0_enable(dev_priv, vco); dev_priv 1076 drivers/gpu/drm/i915/display/intel_cdclk.c sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, dev_priv 1079 drivers/gpu/drm/i915/display/intel_cdclk.c intel_update_cdclk(dev_priv); dev_priv 1082 drivers/gpu/drm/i915/display/intel_cdclk.c static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) dev_priv 1094 drivers/gpu/drm/i915/display/intel_cdclk.c intel_update_cdclk(dev_priv); dev_priv 1095 drivers/gpu/drm/i915/display/intel_cdclk.c intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); dev_priv 1098 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco == 0 || dev_priv 1099 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) dev_priv 1110 drivers/gpu/drm/i915/display/intel_cdclk.c skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); dev_priv 1119 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.cdclk = 0; dev_priv 1121 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = -1; dev_priv 1124 drivers/gpu/drm/i915/display/intel_cdclk.c static void skl_init_cdclk(struct drm_i915_private *dev_priv) dev_priv 1128 drivers/gpu/drm/i915/display/intel_cdclk.c skl_sanitize_cdclk(dev_priv); dev_priv 1130 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.cdclk != 0 && dev_priv 1131 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != 0) { dev_priv 1136 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->skl_preferred_vco_freq == 0) dev_priv 1137 drivers/gpu/drm/i915/display/intel_cdclk.c skl_set_preferred_cdclk_vco(dev_priv, dev_priv 1138 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco); dev_priv 1142 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state = dev_priv->cdclk.hw; dev_priv 1144 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = dev_priv->skl_preferred_vco_freq; dev_priv 1150 drivers/gpu/drm/i915/display/intel_cdclk.c skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); dev_priv 1153 drivers/gpu/drm/i915/display/intel_cdclk.c static void skl_uninit_cdclk(struct drm_i915_private *dev_priv) dev_priv 1155 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; dev_priv 1161 drivers/gpu/drm/i915/display/intel_cdclk.c skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); dev_priv 1193 drivers/gpu/drm/i915/display/intel_cdclk.c static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) dev_priv 1197 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk == dev_priv->cdclk.hw.bypass) dev_priv 1215 drivers/gpu/drm/i915/display/intel_cdclk.c return dev_priv->cdclk.hw.ref * ratio; dev_priv 1218 drivers/gpu/drm/i915/display/intel_cdclk.c static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) dev_priv 1222 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk == dev_priv->cdclk.hw.bypass) dev_priv 1236 drivers/gpu/drm/i915/display/intel_cdclk.c return dev_priv->cdclk.hw.ref * ratio; dev_priv 1239 drivers/gpu/drm/i915/display/intel_cdclk.c static void bxt_de_pll_update(struct drm_i915_private *dev_priv, dev_priv 1258 drivers/gpu/drm/i915/display/intel_cdclk.c static void bxt_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 1264 drivers/gpu/drm/i915/display/intel_cdclk.c bxt_de_pll_update(dev_priv, cdclk_state); dev_priv 1278 drivers/gpu/drm/i915/display/intel_cdclk.c WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); dev_priv 1303 drivers/gpu/drm/i915/display/intel_cdclk.c static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) dev_priv 1308 drivers/gpu/drm/i915/display/intel_cdclk.c if (intel_de_wait_for_clear(dev_priv, dev_priv 1312 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = 0; dev_priv 1315 drivers/gpu/drm/i915/display/intel_cdclk.c static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) dev_priv 1317 drivers/gpu/drm/i915/display/intel_cdclk.c int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); dev_priv 1328 drivers/gpu/drm/i915/display/intel_cdclk.c if (intel_de_wait_for_set(dev_priv, dev_priv 1332 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = vco; dev_priv 1335 drivers/gpu/drm/i915/display/intel_cdclk.c static void bxt_set_cdclk(struct drm_i915_private *dev_priv, dev_priv 1347 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); dev_priv 1354 drivers/gpu/drm/i915/display/intel_cdclk.c WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); dev_priv 1370 drivers/gpu/drm/i915/display/intel_cdclk.c ret = sandybridge_pcode_write_timeout(dev_priv, dev_priv 1379 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != 0 && dev_priv 1380 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != vco) dev_priv 1381 drivers/gpu/drm/i915/display/intel_cdclk.c bxt_de_pll_disable(dev_priv); dev_priv 1383 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != vco) dev_priv 1384 drivers/gpu/drm/i915/display/intel_cdclk.c bxt_de_pll_enable(dev_priv, vco); dev_priv 1400 drivers/gpu/drm/i915/display/intel_cdclk.c intel_wait_for_vblank(dev_priv, pipe); dev_priv 1408 drivers/gpu/drm/i915/display/intel_cdclk.c ret = sandybridge_pcode_write_timeout(dev_priv, dev_priv 1417 drivers/gpu/drm/i915/display/intel_cdclk.c intel_update_cdclk(dev_priv); dev_priv 1420 drivers/gpu/drm/i915/display/intel_cdclk.c static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) dev_priv 1424 drivers/gpu/drm/i915/display/intel_cdclk.c intel_update_cdclk(dev_priv); dev_priv 1425 drivers/gpu/drm/i915/display/intel_cdclk.c intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); dev_priv 1427 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco == 0 || dev_priv 1428 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) dev_priv 1446 drivers/gpu/drm/i915/display/intel_cdclk.c skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); dev_priv 1451 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.cdclk >= 500000) dev_priv 1462 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.cdclk = 0; dev_priv 1465 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = -1; dev_priv 1468 drivers/gpu/drm/i915/display/intel_cdclk.c static void bxt_init_cdclk(struct drm_i915_private *dev_priv) dev_priv 1472 drivers/gpu/drm/i915/display/intel_cdclk.c bxt_sanitize_cdclk(dev_priv); dev_priv 1474 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.cdclk != 0 && dev_priv 1475 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != 0) dev_priv 1478 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state = dev_priv->cdclk.hw; dev_priv 1485 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_GEMINILAKE(dev_priv)) { dev_priv 1487 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk); dev_priv 1490 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk); dev_priv 1494 drivers/gpu/drm/i915/display/intel_cdclk.c bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); dev_priv 1497 drivers/gpu/drm/i915/display/intel_cdclk.c static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) dev_priv 1499 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; dev_priv 1505 drivers/gpu/drm/i915/display/intel_cdclk.c bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); dev_priv 1528 drivers/gpu/drm/i915/display/intel_cdclk.c static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv, dev_priv 1550 drivers/gpu/drm/i915/display/intel_cdclk.c static void cnl_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 1556 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_cdclk_pll_update(dev_priv, cdclk_state); dev_priv 1588 drivers/gpu/drm/i915/display/intel_cdclk.c static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) dev_priv 1600 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = 0; dev_priv 1603 drivers/gpu/drm/i915/display/intel_cdclk.c static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) dev_priv 1605 drivers/gpu/drm/i915/display/intel_cdclk.c int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); dev_priv 1618 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = vco; dev_priv 1621 drivers/gpu/drm/i915/display/intel_cdclk.c static void cnl_set_cdclk(struct drm_i915_private *dev_priv, dev_priv 1630 drivers/gpu/drm/i915/display/intel_cdclk.c ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, dev_priv 1643 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); dev_priv 1654 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != 0 && dev_priv 1655 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != vco) dev_priv 1656 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_cdclk_pll_disable(dev_priv); dev_priv 1658 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != vco) dev_priv 1659 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_cdclk_pll_enable(dev_priv, vco); dev_priv 1669 drivers/gpu/drm/i915/display/intel_cdclk.c intel_wait_for_vblank(dev_priv, pipe); dev_priv 1672 drivers/gpu/drm/i915/display/intel_cdclk.c sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, dev_priv 1675 drivers/gpu/drm/i915/display/intel_cdclk.c intel_update_cdclk(dev_priv); dev_priv 1681 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; dev_priv 1684 drivers/gpu/drm/i915/display/intel_cdclk.c static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) dev_priv 1688 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk == dev_priv->cdclk.hw.bypass) dev_priv 1697 drivers/gpu/drm/i915/display/intel_cdclk.c ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28; dev_priv 1700 drivers/gpu/drm/i915/display/intel_cdclk.c ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44; dev_priv 1704 drivers/gpu/drm/i915/display/intel_cdclk.c return dev_priv->cdclk.hw.ref * ratio; dev_priv 1707 drivers/gpu/drm/i915/display/intel_cdclk.c static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv) dev_priv 1711 drivers/gpu/drm/i915/display/intel_cdclk.c intel_update_cdclk(dev_priv); dev_priv 1712 drivers/gpu/drm/i915/display/intel_cdclk.c intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); dev_priv 1714 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco == 0 || dev_priv 1715 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) dev_priv 1733 drivers/gpu/drm/i915/display/intel_cdclk.c skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); dev_priv 1743 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.cdclk = 0; dev_priv 1746 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco = -1; dev_priv 1780 drivers/gpu/drm/i915/display/intel_cdclk.c static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) dev_priv 1784 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk == dev_priv->cdclk.hw.bypass) dev_priv 1795 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON(dev_priv->cdclk.hw.ref != 19200 && dev_priv 1796 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.ref != 38400); dev_priv 1802 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON(dev_priv->cdclk.hw.ref != 24000); dev_priv 1805 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON(dev_priv->cdclk.hw.ref != 19200 && dev_priv 1806 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.ref != 38400 && dev_priv 1807 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.ref != 24000); dev_priv 1811 drivers/gpu/drm/i915/display/intel_cdclk.c ratio = cdclk / (dev_priv->cdclk.hw.ref / 2); dev_priv 1813 drivers/gpu/drm/i915/display/intel_cdclk.c return dev_priv->cdclk.hw.ref * ratio; dev_priv 1816 drivers/gpu/drm/i915/display/intel_cdclk.c static void icl_set_cdclk(struct drm_i915_private *dev_priv, dev_priv 1824 drivers/gpu/drm/i915/display/intel_cdclk.c ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, dev_priv 1834 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != 0 && dev_priv 1835 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != vco) dev_priv 1836 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_cdclk_pll_disable(dev_priv); dev_priv 1838 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.vco != vco) dev_priv 1839 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_cdclk_pll_enable(dev_priv, vco); dev_priv 1849 drivers/gpu/drm/i915/display/intel_cdclk.c sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, dev_priv 1852 drivers/gpu/drm/i915/display/intel_cdclk.c intel_update_cdclk(dev_priv); dev_priv 1858 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; dev_priv 1861 drivers/gpu/drm/i915/display/intel_cdclk.c static u8 icl_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) dev_priv 1863 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_ELKHARTLAKE(dev_priv)) { dev_priv 1880 drivers/gpu/drm/i915/display/intel_cdclk.c static void icl_get_cdclk(struct drm_i915_private *dev_priv, dev_priv 1928 drivers/gpu/drm/i915/display/intel_cdclk.c icl_calc_voltage_level(dev_priv, cdclk_state->cdclk); dev_priv 1931 drivers/gpu/drm/i915/display/intel_cdclk.c static void icl_init_cdclk(struct drm_i915_private *dev_priv) dev_priv 1937 drivers/gpu/drm/i915/display/intel_cdclk.c intel_update_cdclk(dev_priv); dev_priv 1938 drivers/gpu/drm/i915/display/intel_cdclk.c intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); dev_priv 1941 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) dev_priv 1950 drivers/gpu/drm/i915/display/intel_cdclk.c skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk)) dev_priv 1958 drivers/gpu/drm/i915/display/intel_cdclk.c sanitized_state.ref = dev_priv->cdclk.hw.ref; dev_priv 1960 drivers/gpu/drm/i915/display/intel_cdclk.c sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv, dev_priv 1963 drivers/gpu/drm/i915/display/intel_cdclk.c icl_calc_voltage_level(dev_priv, dev_priv 1966 drivers/gpu/drm/i915/display/intel_cdclk.c icl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE); dev_priv 1969 drivers/gpu/drm/i915/display/intel_cdclk.c static void icl_uninit_cdclk(struct drm_i915_private *dev_priv) dev_priv 1971 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; dev_priv 1975 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.voltage_level = icl_calc_voltage_level(dev_priv, dev_priv 1978 drivers/gpu/drm/i915/display/intel_cdclk.c icl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); dev_priv 1981 drivers/gpu/drm/i915/display/intel_cdclk.c static void cnl_init_cdclk(struct drm_i915_private *dev_priv) dev_priv 1985 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_sanitize_cdclk(dev_priv); dev_priv 1987 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.cdclk != 0 && dev_priv 1988 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.vco != 0) dev_priv 1991 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state = dev_priv->cdclk.hw; dev_priv 1994 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); dev_priv 1997 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); dev_priv 2000 drivers/gpu/drm/i915/display/intel_cdclk.c static void cnl_uninit_cdclk(struct drm_i915_private *dev_priv) dev_priv 2002 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; dev_priv 2008 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); dev_priv 2076 drivers/gpu/drm/i915/display/intel_cdclk.c bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv, dev_priv 2081 drivers/gpu/drm/i915/display/intel_cdclk.c if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv)) dev_priv 2118 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 2120 drivers/gpu/drm/i915/display/intel_cdclk.c swap(state->cdclk.logical, dev_priv->cdclk.logical); dev_priv 2121 drivers/gpu/drm/i915/display/intel_cdclk.c swap(state->cdclk.actual, dev_priv->cdclk.actual); dev_priv 2142 drivers/gpu/drm/i915/display/intel_cdclk.c static void intel_set_cdclk(struct drm_i915_private *dev_priv, dev_priv 2146 drivers/gpu/drm/i915/display/intel_cdclk.c if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state)) dev_priv 2149 drivers/gpu/drm/i915/display/intel_cdclk.c if (WARN_ON_ONCE(!dev_priv->display.set_cdclk)) dev_priv 2154 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe); dev_priv 2156 drivers/gpu/drm/i915/display/intel_cdclk.c if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state), dev_priv 2158 drivers/gpu/drm/i915/display/intel_cdclk.c intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]"); dev_priv 2174 drivers/gpu/drm/i915/display/intel_cdclk.c intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, dev_priv 2180 drivers/gpu/drm/i915/display/intel_cdclk.c intel_set_cdclk(dev_priv, new_state, pipe); dev_priv 2194 drivers/gpu/drm/i915/display/intel_cdclk.c intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, dev_priv 2200 drivers/gpu/drm/i915/display/intel_cdclk.c intel_set_cdclk(dev_priv, new_state, pipe); dev_priv 2203 drivers/gpu/drm/i915/display/intel_cdclk.c static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, dev_priv 2206 drivers/gpu/drm/i915/display/intel_cdclk.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 2208 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_GEN(dev_priv, 9) || dev_priv 2209 drivers/gpu/drm/i915/display/intel_cdclk.c IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) dev_priv 2211 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_CHERRYVIEW(dev_priv)) dev_priv 2219 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = dev_priv 2226 drivers/gpu/drm/i915/display/intel_cdclk.c min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate); dev_priv 2229 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) dev_priv 2241 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { dev_priv 2244 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) { dev_priv 2254 drivers/gpu/drm/i915/display/intel_cdclk.c if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) dev_priv 2264 drivers/gpu/drm/i915/display/intel_cdclk.c if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && dev_priv 2273 drivers/gpu/drm/i915/display/intel_cdclk.c IS_VALLEYVIEW(dev_priv)) dev_priv 2282 drivers/gpu/drm/i915/display/intel_cdclk.c IS_GEMINILAKE(dev_priv)) dev_priv 2285 drivers/gpu/drm/i915/display/intel_cdclk.c if (min_cdclk > dev_priv->max_cdclk_freq) { dev_priv 2287 drivers/gpu/drm/i915/display/intel_cdclk.c min_cdclk, dev_priv->max_cdclk_freq); dev_priv 2296 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 2302 drivers/gpu/drm/i915/display/intel_cdclk.c memcpy(state->min_cdclk, dev_priv->min_cdclk, dev_priv 2314 drivers/gpu/drm/i915/display/intel_cdclk.c for_each_pipe(dev_priv, pipe) dev_priv 2331 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 2338 drivers/gpu/drm/i915/display/intel_cdclk.c memcpy(state->min_voltage_level, dev_priv->min_voltage_level, dev_priv 2350 drivers/gpu/drm/i915/display/intel_cdclk.c for_each_pipe(dev_priv, pipe) dev_priv 2359 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 2366 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); dev_priv 2370 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_calc_voltage_level(dev_priv, cdclk); dev_priv 2373 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk = vlv_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk); dev_priv 2377 drivers/gpu/drm/i915/display/intel_cdclk.c vlv_calc_voltage_level(dev_priv, cdclk); dev_priv 2418 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 2425 drivers/gpu/drm/i915/display/intel_cdclk.c vco = dev_priv->skl_preferred_vco_freq; dev_priv 2489 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 2496 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_GEMINILAKE(dev_priv)) { dev_priv 2498 drivers/gpu/drm/i915/display/intel_cdclk.c vco = glk_de_pll_vco(dev_priv, cdclk); dev_priv 2501 drivers/gpu/drm/i915/display/intel_cdclk.c vco = bxt_de_pll_vco(dev_priv, cdclk); dev_priv 2510 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_GEMINILAKE(dev_priv)) { dev_priv 2512 drivers/gpu/drm/i915/display/intel_cdclk.c vco = glk_de_pll_vco(dev_priv, cdclk); dev_priv 2515 drivers/gpu/drm/i915/display/intel_cdclk.c vco = bxt_de_pll_vco(dev_priv, cdclk); dev_priv 2531 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 2539 drivers/gpu/drm/i915/display/intel_cdclk.c vco = cnl_cdclk_pll_vco(dev_priv, cdclk); dev_priv 2549 drivers/gpu/drm/i915/display/intel_cdclk.c vco = cnl_cdclk_pll_vco(dev_priv, cdclk); dev_priv 2564 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 2573 drivers/gpu/drm/i915/display/intel_cdclk.c vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk); dev_priv 2578 drivers/gpu/drm/i915/display/intel_cdclk.c max(icl_calc_voltage_level(dev_priv, cdclk), dev_priv 2583 drivers/gpu/drm/i915/display/intel_cdclk.c vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk); dev_priv 2588 drivers/gpu/drm/i915/display/intel_cdclk.c icl_calc_voltage_level(dev_priv, cdclk); dev_priv 2596 drivers/gpu/drm/i915/display/intel_cdclk.c static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) dev_priv 2598 drivers/gpu/drm/i915/display/intel_cdclk.c int max_cdclk_freq = dev_priv->max_cdclk_freq; dev_priv 2600 drivers/gpu/drm/i915/display/intel_cdclk.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 2602 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_GEN(dev_priv, 9) || dev_priv 2603 drivers/gpu/drm/i915/display/intel_cdclk.c IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) dev_priv 2605 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_CHERRYVIEW(dev_priv)) dev_priv 2607 drivers/gpu/drm/i915/display/intel_cdclk.c else if (INTEL_GEN(dev_priv) < 4) dev_priv 2621 drivers/gpu/drm/i915/display/intel_cdclk.c void intel_update_max_cdclk(struct drm_i915_private *dev_priv) dev_priv 2623 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_ELKHARTLAKE(dev_priv)) { dev_priv 2624 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.ref == 24000) dev_priv 2625 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = 552000; dev_priv 2627 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = 556800; dev_priv 2628 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (INTEL_GEN(dev_priv) >= 11) { dev_priv 2629 drivers/gpu/drm/i915/display/intel_cdclk.c if (dev_priv->cdclk.hw.ref == 24000) dev_priv 2630 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = 648000; dev_priv 2632 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = 652800; dev_priv 2633 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_CANNONLAKE(dev_priv)) { dev_priv 2634 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = 528000; dev_priv 2635 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_GEN9_BC(dev_priv)) { dev_priv 2639 drivers/gpu/drm/i915/display/intel_cdclk.c vco = dev_priv->skl_preferred_vco_freq; dev_priv 2656 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); dev_priv 2657 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_GEMINILAKE(dev_priv)) { dev_priv 2658 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = 316800; dev_priv 2659 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_BROXTON(dev_priv)) { dev_priv 2660 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = 624000; dev_priv 2661 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_BROADWELL(dev_priv)) { dev_priv 2669 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = 450000; dev_priv 2670 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_BDW_ULX(dev_priv)) dev_priv 2671 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = 450000; dev_priv 2672 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_BDW_ULT(dev_priv)) dev_priv 2673 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = 540000; dev_priv 2675 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = 675000; dev_priv 2676 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_CHERRYVIEW(dev_priv)) { dev_priv 2677 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = 320000; dev_priv 2678 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_VALLEYVIEW(dev_priv)) { dev_priv 2679 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = 400000; dev_priv 2682 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; dev_priv 2685 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); dev_priv 2688 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_cdclk_freq); dev_priv 2691 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->max_dotclk_freq); dev_priv 2700 drivers/gpu/drm/i915/display/intel_cdclk.c void intel_update_cdclk(struct drm_i915_private *dev_priv) dev_priv 2702 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); dev_priv 2710 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 2712 drivers/gpu/drm/i915/display/intel_cdclk.c DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); dev_priv 2715 drivers/gpu/drm/i915/display/intel_cdclk.c static int cnp_rawclk(struct drm_i915_private *dev_priv) dev_priv 2736 drivers/gpu/drm/i915/display/intel_cdclk.c if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) dev_priv 2744 drivers/gpu/drm/i915/display/intel_cdclk.c static int pch_rawclk(struct drm_i915_private *dev_priv) dev_priv 2749 drivers/gpu/drm/i915/display/intel_cdclk.c static int vlv_hrawclk(struct drm_i915_private *dev_priv) dev_priv 2752 drivers/gpu/drm/i915/display/intel_cdclk.c return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", dev_priv 2756 drivers/gpu/drm/i915/display/intel_cdclk.c static int g4x_hrawclk(struct drm_i915_private *dev_priv) dev_priv 2789 drivers/gpu/drm/i915/display/intel_cdclk.c void intel_update_rawclk(struct drm_i915_private *dev_priv) dev_priv 2791 drivers/gpu/drm/i915/display/intel_cdclk.c if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) dev_priv 2792 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->rawclk_freq = cnp_rawclk(dev_priv); dev_priv 2793 drivers/gpu/drm/i915/display/intel_cdclk.c else if (HAS_PCH_SPLIT(dev_priv)) dev_priv 2794 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->rawclk_freq = pch_rawclk(dev_priv); dev_priv 2795 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 2796 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->rawclk_freq = vlv_hrawclk(dev_priv); dev_priv 2797 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) dev_priv 2798 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->rawclk_freq = g4x_hrawclk(dev_priv); dev_priv 2803 drivers/gpu/drm/i915/display/intel_cdclk.c DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); dev_priv 2810 drivers/gpu/drm/i915/display/intel_cdclk.c void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv 2812 drivers/gpu/drm/i915/display/intel_cdclk.c if (INTEL_GEN(dev_priv) >= 11) { dev_priv 2813 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.set_cdclk = icl_set_cdclk; dev_priv 2814 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk; dev_priv 2815 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_CANNONLAKE(dev_priv)) { dev_priv 2816 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.set_cdclk = cnl_set_cdclk; dev_priv 2817 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk; dev_priv 2818 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_GEN9_LP(dev_priv)) { dev_priv 2819 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.set_cdclk = bxt_set_cdclk; dev_priv 2820 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; dev_priv 2821 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_GEN9_BC(dev_priv)) { dev_priv 2822 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.set_cdclk = skl_set_cdclk; dev_priv 2823 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk; dev_priv 2824 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_BROADWELL(dev_priv)) { dev_priv 2825 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.set_cdclk = bdw_set_cdclk; dev_priv 2826 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk; dev_priv 2827 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_CHERRYVIEW(dev_priv)) { dev_priv 2828 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.set_cdclk = chv_set_cdclk; dev_priv 2829 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; dev_priv 2830 drivers/gpu/drm/i915/display/intel_cdclk.c } else if (IS_VALLEYVIEW(dev_priv)) { dev_priv 2831 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.set_cdclk = vlv_set_cdclk; dev_priv 2832 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; dev_priv 2835 drivers/gpu/drm/i915/display/intel_cdclk.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 2836 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = icl_get_cdclk; dev_priv 2837 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_CANNONLAKE(dev_priv)) dev_priv 2838 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = cnl_get_cdclk; dev_priv 2839 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_GEN9_LP(dev_priv)) dev_priv 2840 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = bxt_get_cdclk; dev_priv 2841 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_GEN9_BC(dev_priv)) dev_priv 2842 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = skl_get_cdclk; dev_priv 2843 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_BROADWELL(dev_priv)) dev_priv 2844 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = bdw_get_cdclk; dev_priv 2845 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_HASWELL(dev_priv)) dev_priv 2846 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = hsw_get_cdclk; dev_priv 2847 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 2848 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = vlv_get_cdclk; dev_priv 2849 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) dev_priv 2850 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; dev_priv 2851 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_GEN(dev_priv, 5)) dev_priv 2852 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; dev_priv 2853 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_GM45(dev_priv)) dev_priv 2854 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = gm45_get_cdclk; dev_priv 2855 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_G45(dev_priv)) dev_priv 2856 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = g33_get_cdclk; dev_priv 2857 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_I965GM(dev_priv)) dev_priv 2858 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = i965gm_get_cdclk; dev_priv 2859 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_I965G(dev_priv)) dev_priv 2860 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; dev_priv 2861 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_PINEVIEW(dev_priv)) dev_priv 2862 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = pnv_get_cdclk; dev_priv 2863 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_G33(dev_priv)) dev_priv 2864 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = g33_get_cdclk; dev_priv 2865 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_I945GM(dev_priv)) dev_priv 2866 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = i945gm_get_cdclk; dev_priv 2867 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_I945G(dev_priv)) dev_priv 2868 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; dev_priv 2869 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_I915GM(dev_priv)) dev_priv 2870 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = i915gm_get_cdclk; dev_priv 2871 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_I915G(dev_priv)) dev_priv 2872 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; dev_priv 2873 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_I865G(dev_priv)) dev_priv 2874 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; dev_priv 2875 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_I85X(dev_priv)) dev_priv 2876 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = i85x_get_cdclk; dev_priv 2877 drivers/gpu/drm/i915/display/intel_cdclk.c else if (IS_I845G(dev_priv)) dev_priv 2878 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; dev_priv 2880 drivers/gpu/drm/i915/display/intel_cdclk.c WARN(!IS_I830(dev_priv), dev_priv 2882 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; dev_priv 21 drivers/gpu/drm/i915/display/intel_cdclk.h void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); dev_priv 22 drivers/gpu/drm/i915/display/intel_cdclk.h void intel_update_max_cdclk(struct drm_i915_private *dev_priv); dev_priv 23 drivers/gpu/drm/i915/display/intel_cdclk.h void intel_update_cdclk(struct drm_i915_private *dev_priv); dev_priv 24 drivers/gpu/drm/i915/display/intel_cdclk.h void intel_update_rawclk(struct drm_i915_private *dev_priv); dev_priv 25 drivers/gpu/drm/i915/display/intel_cdclk.h bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv, dev_priv 34 drivers/gpu/drm/i915/display/intel_cdclk.h intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, dev_priv 39 drivers/gpu/drm/i915/display/intel_cdclk.h intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, dev_priv 141 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 157 drivers/gpu/drm/i915/display/intel_color.c if (INTEL_GEN(dev_priv) >= 7) { dev_priv 169 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 192 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 199 drivers/gpu/drm/i915/display/intel_color.c (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || dev_priv 200 drivers/gpu/drm/i915/display/intel_color.c IS_GEN_RANGE(dev_priv, 9, 10)); dev_priv 258 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 284 drivers/gpu/drm/i915/display/intel_color.c WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_GEMINILAKE(dev_priv)); dev_priv 297 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 326 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 392 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 396 drivers/gpu/drm/i915/display/intel_color.c if (HAS_GMCH(dev_priv)) { dev_priv 398 drivers/gpu/drm/i915/display/intel_color.c assert_dsi_pll_enabled(dev_priv); dev_priv 400 drivers/gpu/drm/i915/display/intel_color.c assert_pll_enabled(dev_priv, pipe); dev_priv 412 drivers/gpu/drm/i915/display/intel_color.c if (HAS_GMCH(dev_priv)) dev_priv 428 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 441 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 456 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 466 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 483 drivers/gpu/drm/i915/display/intel_color.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 492 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 523 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 560 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 587 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 613 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 626 drivers/gpu/drm/i915/display/intel_color.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { dev_priv 682 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 684 drivers/gpu/drm/i915/display/intel_color.c const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; dev_priv 721 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 723 drivers/gpu/drm/i915/display/intel_color.c const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; dev_priv 790 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 803 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 832 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 919 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 946 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 981 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 983 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.load_luts(crtc_state); dev_priv 988 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 990 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_commit(crtc_state); dev_priv 1044 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 1046 drivers/gpu/drm/i915/display/intel_color.c return dev_priv->display.color_check(crtc_state); dev_priv 1051 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 1053 drivers/gpu/drm/i915/display/intel_color.c if (dev_priv->display.read_luts) dev_priv 1054 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.read_luts(crtc_state); dev_priv 1060 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1068 drivers/gpu/drm/i915/display/intel_color.c (INTEL_GEN(dev_priv) < 9 && dev_priv 1076 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1091 drivers/gpu/drm/i915/display/intel_color.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { dev_priv 1126 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 1142 drivers/gpu/drm/i915/display/intel_color.c degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size; dev_priv 1143 drivers/gpu/drm/i915/display/intel_color.c gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size; dev_priv 1144 drivers/gpu/drm/i915/display/intel_color.c degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests; dev_priv 1145 drivers/gpu/drm/i915/display/intel_color.c gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests; dev_priv 1437 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1438 drivers/gpu/drm/i915/display/intel_color.c bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0; dev_priv 1442 drivers/gpu/drm/i915/display/intel_color.c if (HAS_GMCH(dev_priv)) { dev_priv 1443 drivers/gpu/drm/i915/display/intel_color.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 1444 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_check = chv_color_check; dev_priv 1445 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_commit = i9xx_color_commit; dev_priv 1446 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.load_luts = chv_load_luts; dev_priv 1447 drivers/gpu/drm/i915/display/intel_color.c } else if (INTEL_GEN(dev_priv) >= 4) { dev_priv 1448 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_check = i9xx_color_check; dev_priv 1449 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_commit = i9xx_color_commit; dev_priv 1450 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.load_luts = i965_load_luts; dev_priv 1452 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_check = i9xx_color_check; dev_priv 1453 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_commit = i9xx_color_commit; dev_priv 1454 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.load_luts = i9xx_load_luts; dev_priv 1457 drivers/gpu/drm/i915/display/intel_color.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 1458 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_check = icl_color_check; dev_priv 1459 drivers/gpu/drm/i915/display/intel_color.c else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 1460 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_check = glk_color_check; dev_priv 1461 drivers/gpu/drm/i915/display/intel_color.c else if (INTEL_GEN(dev_priv) >= 7) dev_priv 1462 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_check = ivb_color_check; dev_priv 1464 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_check = ilk_color_check; dev_priv 1466 drivers/gpu/drm/i915/display/intel_color.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 1467 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_commit = skl_color_commit; dev_priv 1468 drivers/gpu/drm/i915/display/intel_color.c else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) dev_priv 1469 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_commit = hsw_color_commit; dev_priv 1471 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_commit = ilk_color_commit; dev_priv 1473 drivers/gpu/drm/i915/display/intel_color.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 1474 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.load_luts = icl_load_luts; dev_priv 1475 drivers/gpu/drm/i915/display/intel_color.c else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) dev_priv 1476 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.load_luts = glk_load_luts; dev_priv 1477 drivers/gpu/drm/i915/display/intel_color.c else if (INTEL_GEN(dev_priv) >= 8) dev_priv 1478 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.load_luts = bdw_load_luts; dev_priv 1479 drivers/gpu/drm/i915/display/intel_color.c else if (INTEL_GEN(dev_priv) >= 7) dev_priv 1480 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.load_luts = ivb_load_luts; dev_priv 1482 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.load_luts = ilk_load_luts; dev_priv 1486 drivers/gpu/drm/i915/display/intel_color.c INTEL_INFO(dev_priv)->color.degamma_lut_size, dev_priv 1488 drivers/gpu/drm/i915/display/intel_color.c INTEL_INFO(dev_priv)->color.gamma_lut_size); dev_priv 46 drivers/gpu/drm/i915/display/intel_combo_phy.c cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) dev_priv 76 drivers/gpu/drm/i915/display/intel_combo_phy.c static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, dev_priv 82 drivers/gpu/drm/i915/display/intel_combo_phy.c procmon = cnl_get_procmon_ref_values(dev_priv, phy); dev_priv 93 drivers/gpu/drm/i915/display/intel_combo_phy.c static bool check_phy_reg(struct drm_i915_private *dev_priv, dev_priv 110 drivers/gpu/drm/i915/display/intel_combo_phy.c static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, dev_priv 116 drivers/gpu/drm/i915/display/intel_combo_phy.c procmon = cnl_get_procmon_ref_values(dev_priv, phy); dev_priv 118 drivers/gpu/drm/i915/display/intel_combo_phy.c ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), dev_priv 120 drivers/gpu/drm/i915/display/intel_combo_phy.c ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), dev_priv 122 drivers/gpu/drm/i915/display/intel_combo_phy.c ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), dev_priv 128 drivers/gpu/drm/i915/display/intel_combo_phy.c static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv) dev_priv 134 drivers/gpu/drm/i915/display/intel_combo_phy.c static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv) dev_priv 139 drivers/gpu/drm/i915/display/intel_combo_phy.c if (!cnl_combo_phy_enabled(dev_priv)) dev_priv 142 drivers/gpu/drm/i915/display/intel_combo_phy.c ret = cnl_verify_procmon_ref_values(dev_priv, phy); dev_priv 144 drivers/gpu/drm/i915/display/intel_combo_phy.c ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5, dev_priv 150 drivers/gpu/drm/i915/display/intel_combo_phy.c static void cnl_combo_phys_init(struct drm_i915_private *dev_priv) dev_priv 159 drivers/gpu/drm/i915/display/intel_combo_phy.c cnl_set_procmon_ref_values(dev_priv, PHY_A); dev_priv 170 drivers/gpu/drm/i915/display/intel_combo_phy.c static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) dev_priv 174 drivers/gpu/drm/i915/display/intel_combo_phy.c if (!cnl_combo_phy_verify_state(dev_priv)) dev_priv 182 drivers/gpu/drm/i915/display/intel_combo_phy.c static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, dev_priv 186 drivers/gpu/drm/i915/display/intel_combo_phy.c if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) dev_priv 194 drivers/gpu/drm/i915/display/intel_combo_phy.c static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, dev_priv 199 drivers/gpu/drm/i915/display/intel_combo_phy.c if (!icl_combo_phy_enabled(dev_priv, phy)) dev_priv 202 drivers/gpu/drm/i915/display/intel_combo_phy.c ret = cnl_verify_procmon_ref_values(dev_priv, phy); dev_priv 205 drivers/gpu/drm/i915/display/intel_combo_phy.c ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), dev_priv 208 drivers/gpu/drm/i915/display/intel_combo_phy.c ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), dev_priv 214 drivers/gpu/drm/i915/display/intel_combo_phy.c void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, dev_priv 292 drivers/gpu/drm/i915/display/intel_combo_phy.c static void icl_combo_phys_init(struct drm_i915_private *dev_priv) dev_priv 296 drivers/gpu/drm/i915/display/intel_combo_phy.c for_each_combo_phy(dev_priv, phy) { dev_priv 299 drivers/gpu/drm/i915/display/intel_combo_phy.c if (icl_combo_phy_verify_state(dev_priv, phy)) { dev_priv 310 drivers/gpu/drm/i915/display/intel_combo_phy.c if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) dev_priv 322 drivers/gpu/drm/i915/display/intel_combo_phy.c if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) dev_priv 323 drivers/gpu/drm/i915/display/intel_combo_phy.c val = ehl_combo_phy_a_mux(dev_priv, val); dev_priv 328 drivers/gpu/drm/i915/display/intel_combo_phy.c cnl_set_procmon_ref_values(dev_priv, phy); dev_priv 346 drivers/gpu/drm/i915/display/intel_combo_phy.c static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) dev_priv 350 drivers/gpu/drm/i915/display/intel_combo_phy.c for_each_combo_phy_reverse(dev_priv, phy) { dev_priv 354 drivers/gpu/drm/i915/display/intel_combo_phy.c !icl_combo_phy_verify_state(dev_priv, phy)) dev_priv 363 drivers/gpu/drm/i915/display/intel_combo_phy.c if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) dev_priv 14 drivers/gpu/drm/i915/display/intel_combo_phy.h void intel_combo_phy_init(struct drm_i915_private *dev_priv); dev_priv 15 drivers/gpu/drm/i915/display/intel_combo_phy.h void intel_combo_phy_uninit(struct drm_i915_private *dev_priv); dev_priv 16 drivers/gpu/drm/i915/display/intel_combo_phy.h void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, dev_priv 223 drivers/gpu/drm/i915/display/intel_connector.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 226 drivers/gpu/drm/i915/display/intel_connector.c prop = dev_priv->force_audio_property; dev_priv 235 drivers/gpu/drm/i915/display/intel_connector.c dev_priv->force_audio_property = prop; dev_priv 250 drivers/gpu/drm/i915/display/intel_connector.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 253 drivers/gpu/drm/i915/display/intel_connector.c prop = dev_priv->broadcast_rgb_property; dev_priv 262 drivers/gpu/drm/i915/display/intel_connector.c dev_priv->broadcast_rgb_property = prop; dev_priv 73 drivers/gpu/drm/i915/display/intel_crt.c bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, dev_priv 81 drivers/gpu/drm/i915/display/intel_crt.c if (HAS_PCH_CPT(dev_priv)) dev_priv 92 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 97 drivers/gpu/drm/i915/display/intel_crt.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 102 drivers/gpu/drm/i915/display/intel_crt.c ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); dev_priv 104 drivers/gpu/drm/i915/display/intel_crt.c intel_display_power_put(dev_priv, encoder->power_domain, wakeref); dev_priv 111 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 143 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 153 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); dev_priv 162 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 168 drivers/gpu/drm/i915/display/intel_crt.c if (INTEL_GEN(dev_priv) >= 5) dev_priv 179 drivers/gpu/drm/i915/display/intel_crt.c if (HAS_PCH_LPT(dev_priv)) dev_priv 181 drivers/gpu/drm/i915/display/intel_crt.c else if (HAS_PCH_CPT(dev_priv)) dev_priv 186 drivers/gpu/drm/i915/display/intel_crt.c if (!HAS_PCH_SPLIT(dev_priv)) dev_priv 231 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 235 drivers/gpu/drm/i915/display/intel_crt.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); dev_priv 242 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 248 drivers/gpu/drm/i915/display/intel_crt.c lpt_disable_pch_transcoder(dev_priv); dev_priv 249 drivers/gpu/drm/i915/display/intel_crt.c lpt_disable_iclkip(dev_priv); dev_priv 255 drivers/gpu/drm/i915/display/intel_crt.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); dev_priv 262 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 266 drivers/gpu/drm/i915/display/intel_crt.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); dev_priv 273 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 279 drivers/gpu/drm/i915/display/intel_crt.c intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); dev_priv 281 drivers/gpu/drm/i915/display/intel_crt.c dev_priv->display.fdi_link_train(crtc, crtc_state); dev_priv 290 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 298 drivers/gpu/drm/i915/display/intel_crt.c intel_wait_for_vblank(dev_priv, pipe); dev_priv 299 drivers/gpu/drm/i915/display/intel_crt.c intel_wait_for_vblank(dev_priv, pipe); dev_priv 300 drivers/gpu/drm/i915/display/intel_crt.c intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); dev_priv 301 drivers/gpu/drm/i915/display/intel_crt.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); dev_priv 316 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 317 drivers/gpu/drm/i915/display/intel_crt.c int max_dotclk = dev_priv->max_dotclk_freq; dev_priv 326 drivers/gpu/drm/i915/display/intel_crt.c if (HAS_PCH_LPT(dev_priv)) dev_priv 328 drivers/gpu/drm/i915/display/intel_crt.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 334 drivers/gpu/drm/i915/display/intel_crt.c else if (IS_GEN_RANGE(dev_priv, 3, 4)) dev_priv 345 drivers/gpu/drm/i915/display/intel_crt.c if (HAS_PCH_LPT(dev_priv) && dev_priv 391 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 407 drivers/gpu/drm/i915/display/intel_crt.c if (HAS_PCH_LPT(dev_priv)) { dev_priv 426 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 432 drivers/gpu/drm/i915/display/intel_crt.c bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); dev_priv 446 drivers/gpu/drm/i915/display/intel_crt.c if (intel_de_wait_for_clear(dev_priv, dev_priv 473 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 491 drivers/gpu/drm/i915/display/intel_crt.c reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); dev_priv 500 drivers/gpu/drm/i915/display/intel_crt.c if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg, dev_priv 516 drivers/gpu/drm/i915/display/intel_crt.c intel_hpd_enable(dev_priv, crt->base.hpd_pin); dev_priv 524 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 529 drivers/gpu/drm/i915/display/intel_crt.c if (HAS_PCH_SPLIT(dev_priv)) dev_priv 532 drivers/gpu/drm/i915/display/intel_crt.c if (IS_VALLEYVIEW(dev_priv)) dev_priv 540 drivers/gpu/drm/i915/display/intel_crt.c if (IS_G45(dev_priv)) dev_priv 547 drivers/gpu/drm/i915/display/intel_crt.c i915_hotplug_interrupt_update(dev_priv, dev_priv 551 drivers/gpu/drm/i915/display/intel_crt.c if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN, dev_priv 563 drivers/gpu/drm/i915/display/intel_crt.c i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); dev_priv 605 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); dev_priv 612 drivers/gpu/drm/i915/display/intel_crt.c i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); dev_priv 642 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 643 drivers/gpu/drm/i915/display/intel_crt.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 677 drivers/gpu/drm/i915/display/intel_crt.c if (!IS_GEN(dev_priv, 2)) { dev_priv 685 drivers/gpu/drm/i915/display/intel_crt.c intel_wait_for_vblank(dev_priv, pipe); dev_priv 789 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 801 drivers/gpu/drm/i915/display/intel_crt.c wakeref = intel_display_power_get(dev_priv, dev_priv 810 drivers/gpu/drm/i915/display/intel_crt.c wakeref = intel_display_power_get(dev_priv, dev_priv 813 drivers/gpu/drm/i915/display/intel_crt.c if (I915_HAS_HOTPLUG(dev_priv)) { dev_priv 835 drivers/gpu/drm/i915/display/intel_crt.c if (I915_HAS_HOTPLUG(dev_priv)) { dev_priv 851 drivers/gpu/drm/i915/display/intel_crt.c else if (INTEL_GEN(dev_priv) < 4) dev_priv 866 drivers/gpu/drm/i915/display/intel_crt.c intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); dev_priv 872 drivers/gpu/drm/i915/display/intel_crt.c intel_display_power_flush_work(dev_priv); dev_priv 880 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 887 drivers/gpu/drm/i915/display/intel_crt.c wakeref = intel_display_power_get(dev_priv, dev_priv 890 drivers/gpu/drm/i915/display/intel_crt.c i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); dev_priv 892 drivers/gpu/drm/i915/display/intel_crt.c if (ret || !IS_G4X(dev_priv)) dev_priv 896 drivers/gpu/drm/i915/display/intel_crt.c i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); dev_priv 900 drivers/gpu/drm/i915/display/intel_crt.c intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); dev_priv 907 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->dev); dev_priv 910 drivers/gpu/drm/i915/display/intel_crt.c if (INTEL_GEN(dev_priv) >= 5) { dev_priv 949 drivers/gpu/drm/i915/display/intel_crt.c void intel_crt_init(struct drm_i915_private *dev_priv) dev_priv 957 drivers/gpu/drm/i915/display/intel_crt.c if (HAS_PCH_SPLIT(dev_priv)) dev_priv 959 drivers/gpu/drm/i915/display/intel_crt.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 993 drivers/gpu/drm/i915/display/intel_crt.c drm_connector_init(&dev_priv->drm, &intel_connector->base, dev_priv 996 drivers/gpu/drm/i915/display/intel_crt.c drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, dev_priv 1003 drivers/gpu/drm/i915/display/intel_crt.c if (IS_I830(dev_priv)) dev_priv 1008 drivers/gpu/drm/i915/display/intel_crt.c if (IS_GEN(dev_priv, 2)) dev_priv 1018 drivers/gpu/drm/i915/display/intel_crt.c if (I915_HAS_HOTPLUG(dev_priv) && dev_priv 1024 drivers/gpu/drm/i915/display/intel_crt.c if (HAS_DDI(dev_priv)) { dev_priv 1035 drivers/gpu/drm/i915/display/intel_crt.c if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 1052 drivers/gpu/drm/i915/display/intel_crt.c if (!I915_HAS_HOTPLUG(dev_priv)) dev_priv 1065 drivers/gpu/drm/i915/display/intel_crt.c if (HAS_PCH_LPT(dev_priv)) { dev_priv 1069 drivers/gpu/drm/i915/display/intel_crt.c dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; dev_priv 16 drivers/gpu/drm/i915/display/intel_crt.h bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, dev_priv 18 drivers/gpu/drm/i915/display/intel_crt.h void intel_crt_init(struct drm_i915_private *dev_priv); dev_priv 590 drivers/gpu/drm/i915/display/intel_ddi.c bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) dev_priv 592 drivers/gpu/drm/i915/display/intel_ddi.c if (dev_priv->vbt.edp.low_vswing) { dev_priv 602 drivers/gpu/drm/i915/display/intel_ddi.c skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) dev_priv 604 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_SKL_ULX(dev_priv)) { dev_priv 607 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_SKL_ULT(dev_priv)) { dev_priv 617 drivers/gpu/drm/i915/display/intel_ddi.c kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) dev_priv 619 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) { dev_priv 622 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { dev_priv 632 drivers/gpu/drm/i915/display/intel_ddi.c skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) dev_priv 634 drivers/gpu/drm/i915/display/intel_ddi.c if (dev_priv->vbt.edp.low_vswing) { dev_priv 635 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || dev_priv 636 drivers/gpu/drm/i915/display/intel_ddi.c IS_CFL_ULX(dev_priv)) { dev_priv 639 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || dev_priv 640 drivers/gpu/drm/i915/display/intel_ddi.c IS_CFL_ULT(dev_priv)) { dev_priv 649 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) dev_priv 650 drivers/gpu/drm/i915/display/intel_ddi.c return kbl_get_buf_trans_dp(dev_priv, n_entries); dev_priv 652 drivers/gpu/drm/i915/display/intel_ddi.c return skl_get_buf_trans_dp(dev_priv, n_entries); dev_priv 656 drivers/gpu/drm/i915/display/intel_ddi.c skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) dev_priv 658 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || dev_priv 659 drivers/gpu/drm/i915/display/intel_ddi.c IS_CFL_ULX(dev_priv)) { dev_priv 678 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, dev_priv 681 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { dev_priv 683 drivers/gpu/drm/i915/display/intel_ddi.c kbl_get_buf_trans_dp(dev_priv, n_entries); dev_priv 686 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_SKYLAKE(dev_priv)) { dev_priv 688 drivers/gpu/drm/i915/display/intel_ddi.c skl_get_buf_trans_dp(dev_priv, n_entries); dev_priv 691 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_BROADWELL(dev_priv)) { dev_priv 694 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_HASWELL(dev_priv)) { dev_priv 704 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, dev_priv 707 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_GEN9_BC(dev_priv)) { dev_priv 709 drivers/gpu/drm/i915/display/intel_ddi.c skl_get_buf_trans_edp(dev_priv, n_entries); dev_priv 712 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_BROADWELL(dev_priv)) { dev_priv 713 drivers/gpu/drm/i915/display/intel_ddi.c return bdw_get_buf_trans_edp(dev_priv, n_entries); dev_priv 714 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_HASWELL(dev_priv)) { dev_priv 724 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, dev_priv 727 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_BROADWELL(dev_priv)) { dev_priv 730 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_HASWELL(dev_priv)) { dev_priv 740 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, dev_priv 743 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_GEN9_BC(dev_priv)) { dev_priv 744 drivers/gpu/drm/i915/display/intel_ddi.c return skl_get_buf_trans_hdmi(dev_priv, n_entries); dev_priv 745 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_BROADWELL(dev_priv)) { dev_priv 748 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_HASWELL(dev_priv)) { dev_priv 758 drivers/gpu/drm/i915/display/intel_ddi.c bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) dev_priv 765 drivers/gpu/drm/i915/display/intel_ddi.c bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) dev_priv 767 drivers/gpu/drm/i915/display/intel_ddi.c if (dev_priv->vbt.edp.low_vswing) { dev_priv 772 drivers/gpu/drm/i915/display/intel_ddi.c return bxt_get_buf_trans_dp(dev_priv, n_entries); dev_priv 776 drivers/gpu/drm/i915/display/intel_ddi.c bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) dev_priv 783 drivers/gpu/drm/i915/display/intel_ddi.c cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) dev_priv 804 drivers/gpu/drm/i915/display/intel_ddi.c cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) dev_priv 825 drivers/gpu/drm/i915/display/intel_ddi.c cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) dev_priv 829 drivers/gpu/drm/i915/display/intel_ddi.c if (dev_priv->vbt.edp.low_vswing) { dev_priv 845 drivers/gpu/drm/i915/display/intel_ddi.c return cnl_get_buf_trans_dp(dev_priv, n_entries); dev_priv 850 drivers/gpu/drm/i915/display/intel_ddi.c icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, dev_priv 859 drivers/gpu/drm/i915/display/intel_ddi.c } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { dev_priv 868 drivers/gpu/drm/i915/display/intel_ddi.c static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) dev_priv 871 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, port); dev_priv 873 drivers/gpu/drm/i915/display/intel_ddi.c level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; dev_priv 875 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11) { dev_priv 876 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_phy_is_combo(dev_priv, phy)) dev_priv 877 drivers/gpu/drm/i915/display/intel_ddi.c icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, dev_priv 882 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_CANNONLAKE(dev_priv)) { dev_priv 883 drivers/gpu/drm/i915/display/intel_ddi.c cnl_get_buf_trans_hdmi(dev_priv, &n_entries); dev_priv 885 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_GEN9_LP(dev_priv)) { dev_priv 886 drivers/gpu/drm/i915/display/intel_ddi.c bxt_get_buf_trans_hdmi(dev_priv, &n_entries); dev_priv 888 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_GEN9_BC(dev_priv)) { dev_priv 889 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); dev_priv 891 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_BROADWELL(dev_priv)) { dev_priv 892 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); dev_priv 894 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_HASWELL(dev_priv)) { dev_priv 895 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); dev_priv 922 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 929 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, dev_priv 932 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, dev_priv 935 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, dev_priv 939 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_GEN9_BC(dev_priv) && dev_priv 940 drivers/gpu/drm/i915/display/intel_ddi.c dev_priv->vbt.ddi_port_info[port].dp_boost_level) dev_priv 959 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 965 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); dev_priv 973 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_GEN9_BC(dev_priv) && dev_priv 974 drivers/gpu/drm/i915/display/intel_ddi.c dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) dev_priv 984 drivers/gpu/drm/i915/display/intel_ddi.c static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, dev_priv 1069 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1090 drivers/gpu/drm/i915/display/intel_ddi.c rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | dev_priv 1179 drivers/gpu/drm/i915/display/intel_ddi.c intel_wait_ddi_buf_idle(dev_priv, PORT_E); dev_priv 1228 drivers/gpu/drm/i915/display/intel_ddi.c static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, dev_priv 1243 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) { dev_priv 1330 drivers/gpu/drm/i915/display/intel_ddi.c int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, dev_priv 1372 drivers/gpu/drm/i915/display/intel_ddi.c ref_clock = cnl_hdmi_pll_ref_clock(dev_priv); dev_priv 1386 drivers/gpu/drm/i915/display/intel_ddi.c static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, dev_priv 1408 drivers/gpu/drm/i915/display/intel_ddi.c static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv, dev_priv 1414 drivers/gpu/drm/i915/display/intel_ddi.c ref_clock = dev_priv->cdclk.hw.ref; dev_priv 1488 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1491 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, port); dev_priv 1494 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_phy_is_combo(dev_priv, phy)) { dev_priv 1495 drivers/gpu/drm/i915/display/intel_ddi.c link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); dev_priv 1497 drivers/gpu/drm/i915/display/intel_ddi.c enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv, dev_priv 1501 drivers/gpu/drm/i915/display/intel_ddi.c link_clock = icl_calc_tbt_pll_link(dev_priv, port); dev_priv 1503 drivers/gpu/drm/i915/display/intel_ddi.c link_clock = icl_calc_mg_pll_link(dev_priv, pll_state); dev_priv 1514 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1519 drivers/gpu/drm/i915/display/intel_ddi.c link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); dev_priv 1610 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1626 drivers/gpu/drm/i915/display/intel_ddi.c link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); dev_priv 1629 drivers/gpu/drm/i915/display/intel_ddi.c link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); dev_priv 1681 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1683 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 1685 drivers/gpu/drm/i915/display/intel_ddi.c else if (IS_CANNONLAKE(dev_priv)) dev_priv 1687 drivers/gpu/drm/i915/display/intel_ddi.c else if (IS_GEN9_LP(dev_priv)) dev_priv 1689 drivers/gpu/drm/i915/display/intel_ddi.c else if (IS_GEN9_BC(dev_priv)) dev_priv 1691 drivers/gpu/drm/i915/display/intel_ddi.c else if (INTEL_GEN(dev_priv) <= 8) dev_priv 1698 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1752 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1768 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1776 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 12) dev_priv 1854 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1859 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 12) { dev_priv 1868 drivers/gpu/drm/i915/display/intel_ddi.c if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && dev_priv 1880 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1886 drivers/gpu/drm/i915/display/intel_ddi.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 1903 drivers/gpu/drm/i915/display/intel_ddi.c intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); dev_priv 1910 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1920 drivers/gpu/drm/i915/display/intel_ddi.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 1930 drivers/gpu/drm/i915/display/intel_ddi.c if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) dev_priv 1964 drivers/gpu/drm/i915/display/intel_ddi.c intel_display_power_put(dev_priv, encoder->power_domain, wakeref); dev_priv 1973 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1983 drivers/gpu/drm/i915/display/intel_ddi.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 1992 drivers/gpu/drm/i915/display/intel_ddi.c if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) { dev_priv 2015 drivers/gpu/drm/i915/display/intel_ddi.c for_each_pipe(dev_priv, p) { dev_priv 2020 drivers/gpu/drm/i915/display/intel_ddi.c trans_wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 2025 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 12) { dev_priv 2034 drivers/gpu/drm/i915/display/intel_ddi.c intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), dev_priv 2064 drivers/gpu/drm/i915/display/intel_ddi.c if (*pipe_mask && IS_GEN9_LP(dev_priv)) { dev_priv 2073 drivers/gpu/drm/i915/display/intel_ddi.c intel_display_power_put(dev_priv, encoder->power_domain, wakeref); dev_priv 2114 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2116 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, encoder->port); dev_priv 2128 drivers/gpu/drm/i915/display/intel_ddi.c if (!intel_phy_is_tc(dev_priv, phy) || dev_priv 2130 drivers/gpu/drm/i915/display/intel_ddi.c intel_display_power_get(dev_priv, dev_priv 2138 drivers/gpu/drm/i915/display/intel_ddi.c intel_phy_is_tc(dev_priv, phy)) dev_priv 2139 drivers/gpu/drm/i915/display/intel_ddi.c intel_display_power_get(dev_priv, dev_priv 2146 drivers/gpu/drm/i915/display/intel_ddi.c intel_display_power_get(dev_priv, dev_priv 2153 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 2159 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 12) dev_priv 2170 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 2174 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 12) dev_priv 2183 drivers/gpu/drm/i915/display/intel_ddi.c static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, dev_priv 2201 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2206 drivers/gpu/drm/i915/display/intel_ddi.c iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; dev_priv 2208 drivers/gpu/drm/i915/display/intel_ddi.c iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; dev_priv 2215 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); dev_priv 2217 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); dev_priv 2219 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); dev_priv 2235 drivers/gpu/drm/i915/display/intel_ddi.c _skl_ddi_set_iboost(dev_priv, port, iboost); dev_priv 2238 drivers/gpu/drm/i915/display/intel_ddi.c _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); dev_priv 2244 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2250 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); dev_priv 2252 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); dev_priv 2254 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); dev_priv 2261 drivers/gpu/drm/i915/display/intel_ddi.c bxt_ddi_phy_set_signal_level(dev_priv, port, dev_priv 2270 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2273 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, port); dev_priv 2276 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11) { dev_priv 2277 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_phy_is_combo(dev_priv, phy)) dev_priv 2278 drivers/gpu/drm/i915/display/intel_ddi.c icl_get_combo_buf_trans(dev_priv, encoder->type, dev_priv 2282 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_CANNONLAKE(dev_priv)) { dev_priv 2284 drivers/gpu/drm/i915/display/intel_ddi.c cnl_get_buf_trans_edp(dev_priv, &n_entries); dev_priv 2286 drivers/gpu/drm/i915/display/intel_ddi.c cnl_get_buf_trans_dp(dev_priv, &n_entries); dev_priv 2287 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_GEN9_LP(dev_priv)) { dev_priv 2289 drivers/gpu/drm/i915/display/intel_ddi.c bxt_get_buf_trans_edp(dev_priv, &n_entries); dev_priv 2291 drivers/gpu/drm/i915/display/intel_ddi.c bxt_get_buf_trans_dp(dev_priv, &n_entries); dev_priv 2294 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); dev_priv 2296 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); dev_priv 2331 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2338 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); dev_priv 2340 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); dev_priv 2342 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); dev_priv 2395 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2459 drivers/gpu/drm/i915/display/intel_ddi.c static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, dev_priv 2467 drivers/gpu/drm/i915/display/intel_ddi.c ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, dev_priv 2519 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2520 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, encoder->port); dev_priv 2577 drivers/gpu/drm/i915/display/intel_ddi.c icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); dev_priv 2589 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2709 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2710 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, encoder->port); dev_priv 2712 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_phy_is_combo(dev_priv, phy)) dev_priv 2745 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); dev_priv 2749 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 2752 drivers/gpu/drm/i915/display/intel_ddi.c else if (IS_CANNONLAKE(dev_priv)) dev_priv 2763 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); dev_priv 2767 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_GEN9_BC(dev_priv)) dev_priv 2774 drivers/gpu/drm/i915/display/intel_ddi.c u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, dev_priv 2777 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_phy_is_combo(dev_priv, phy)) { dev_priv 2779 drivers/gpu/drm/i915/display/intel_ddi.c } else if (intel_phy_is_tc(dev_priv, phy)) { dev_priv 2780 drivers/gpu/drm/i915/display/intel_ddi.c enum tc_port tc_port = intel_port_to_tc(dev_priv, dev_priv 2792 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2794 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, encoder->port); dev_priv 2797 drivers/gpu/drm/i915/display/intel_ddi.c mutex_lock(&dev_priv->dpll_lock); dev_priv 2800 drivers/gpu/drm/i915/display/intel_ddi.c WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); dev_priv 2802 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_phy_is_combo(dev_priv, phy)) { dev_priv 2819 drivers/gpu/drm/i915/display/intel_ddi.c val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); dev_priv 2822 drivers/gpu/drm/i915/display/intel_ddi.c mutex_unlock(&dev_priv->dpll_lock); dev_priv 2827 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2828 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, encoder->port); dev_priv 2831 drivers/gpu/drm/i915/display/intel_ddi.c mutex_lock(&dev_priv->dpll_lock); dev_priv 2834 drivers/gpu/drm/i915/display/intel_ddi.c val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); dev_priv 2837 drivers/gpu/drm/i915/display/intel_ddi.c mutex_unlock(&dev_priv->dpll_lock); dev_priv 2842 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2879 drivers/gpu/drm/i915/display/intel_ddi.c for_each_intel_encoder(&dev_priv->drm, other_encoder) { dev_priv 2895 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, port); dev_priv 2898 drivers/gpu/drm/i915/display/intel_ddi.c icl_dpclka_cfgcr0_clk_off(dev_priv, dev_priv 2913 drivers/gpu/drm/i915/display/intel_ddi.c val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); dev_priv 2921 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2923 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, port); dev_priv 2930 drivers/gpu/drm/i915/display/intel_ddi.c mutex_lock(&dev_priv->dpll_lock); dev_priv 2932 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11) { dev_priv 2933 drivers/gpu/drm/i915/display/intel_ddi.c if (!intel_phy_is_combo(dev_priv, phy)) dev_priv 2936 drivers/gpu/drm/i915/display/intel_ddi.c else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) dev_priv 2942 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_CANNONLAKE(dev_priv)) { dev_priv 2957 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_GEN9_BC(dev_priv)) { dev_priv 2968 drivers/gpu/drm/i915/display/intel_ddi.c } else if (INTEL_GEN(dev_priv) < 9) { dev_priv 2972 drivers/gpu/drm/i915/display/intel_ddi.c mutex_unlock(&dev_priv->dpll_lock); dev_priv 2977 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2979 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, port); dev_priv 2981 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11) { dev_priv 2982 drivers/gpu/drm/i915/display/intel_ddi.c if (!intel_phy_is_combo(dev_priv, phy) || dev_priv 2983 drivers/gpu/drm/i915/display/intel_ddi.c (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) dev_priv 2985 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_CANNONLAKE(dev_priv)) { dev_priv 2988 drivers/gpu/drm/i915/display/intel_ddi.c } else if (IS_GEN9_BC(dev_priv)) { dev_priv 2991 drivers/gpu/drm/i915/display/intel_ddi.c } else if (INTEL_GEN(dev_priv) < 9) { dev_priv 2998 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); dev_priv 3000 drivers/gpu/drm/i915/display/intel_ddi.c enum tc_port tc_port = intel_port_to_tc(dev_priv, port); dev_priv 3030 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); dev_priv 3032 drivers/gpu/drm/i915/display/intel_ddi.c enum tc_port tc_port = intel_port_to_tc(dev_priv, port); dev_priv 3062 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); dev_priv 3135 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3146 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port), dev_priv 3154 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3172 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3174 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, port); dev_priv 3188 drivers/gpu/drm/i915/display/intel_ddi.c if (!intel_phy_is_tc(dev_priv, phy) || dev_priv 3190 drivers/gpu/drm/i915/display/intel_ddi.c intel_display_power_get(dev_priv, dev_priv 3196 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 3199 drivers/gpu/drm/i915/display/intel_ddi.c else if (IS_CANNONLAKE(dev_priv)) dev_priv 3201 drivers/gpu/drm/i915/display/intel_ddi.c else if (IS_GEN9_LP(dev_priv)) dev_priv 3206 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_phy_is_combo(dev_priv, phy)) { dev_priv 3210 drivers/gpu/drm/i915/display/intel_ddi.c intel_combo_phy_power_up_lanes(dev_priv, phy, false, dev_priv 3222 drivers/gpu/drm/i915/display/intel_ddi.c if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) dev_priv 3241 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3243 drivers/gpu/drm/i915/display/intel_ddi.c int level = intel_ddi_hdmi_level(dev_priv, port); dev_priv 3249 drivers/gpu/drm/i915/display/intel_ddi.c intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); dev_priv 3254 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 3257 drivers/gpu/drm/i915/display/intel_ddi.c else if (IS_CANNONLAKE(dev_priv)) dev_priv 3259 drivers/gpu/drm/i915/display/intel_ddi.c else if (IS_GEN9_LP(dev_priv)) dev_priv 3266 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_GEN9_BC(dev_priv)) dev_priv 3281 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 3299 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 3302 drivers/gpu/drm/i915/display/intel_ddi.c intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); dev_priv 3325 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3346 drivers/gpu/drm/i915/display/intel_ddi.c intel_wait_ddi_buf_idle(dev_priv, port); dev_priv 3353 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3358 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, encoder->port); dev_priv 3374 drivers/gpu/drm/i915/display/intel_ddi.c if (!intel_phy_is_tc(dev_priv, phy) || dev_priv 3376 drivers/gpu/drm/i915/display/intel_ddi.c intel_display_power_put_unchecked(dev_priv, dev_priv 3386 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3397 drivers/gpu/drm/i915/display/intel_ddi.c intel_display_power_put_unchecked(dev_priv, dev_priv 3409 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3431 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 3439 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3473 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3477 drivers/gpu/drm/i915/display/intel_ddi.c if (port == PORT_A && INTEL_GEN(dev_priv) < 9) dev_priv 3490 drivers/gpu/drm/i915/display/intel_ddi.c gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, dev_priv 3501 drivers/gpu/drm/i915/display/intel_ddi.c WARN_ON(INTEL_GEN(dev_priv) < 9); dev_priv 3513 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3525 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_GEN9_BC(dev_priv)) { dev_priv 3532 drivers/gpu/drm/i915/display/intel_ddi.c i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); dev_priv 3718 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3720 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, encoder->port); dev_priv 3721 drivers/gpu/drm/i915/display/intel_ddi.c bool is_tc_port = intel_phy_is_tc(dev_priv, phy); dev_priv 3727 drivers/gpu/drm/i915/display/intel_ddi.c intel_display_power_get(dev_priv, dev_priv 3736 drivers/gpu/drm/i915/display/intel_ddi.c else if (IS_GEN9_LP(dev_priv)) dev_priv 3746 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3748 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, encoder->port); dev_priv 3749 drivers/gpu/drm/i915/display/intel_ddi.c bool is_tc_port = intel_phy_is_tc(dev_priv, phy); dev_priv 3752 drivers/gpu/drm/i915/display/intel_ddi.c intel_display_power_put_unchecked(dev_priv, dev_priv 3762 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = dev_priv 3783 drivers/gpu/drm/i915/display/intel_ddi.c intel_wait_ddi_buf_idle(dev_priv, port); dev_priv 3805 drivers/gpu/drm/i915/display/intel_ddi.c static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, dev_priv 3811 drivers/gpu/drm/i915/display/intel_ddi.c if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) dev_priv 3818 drivers/gpu/drm/i915/display/intel_ddi.c void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, dev_priv 3821 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) dev_priv 3823 drivers/gpu/drm/i915/display/intel_ddi.c else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) dev_priv 3830 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3910 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); dev_priv 3912 drivers/gpu/drm/i915/display/intel_ddi.c if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && dev_priv 3913 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { dev_priv 3928 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); dev_priv 3929 drivers/gpu/drm/i915/display/intel_ddi.c dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; dev_priv 3934 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_GEN9_LP(dev_priv)) dev_priv 3938 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); dev_priv 3979 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3983 drivers/gpu/drm/i915/display/intel_ddi.c if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) dev_priv 3993 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && dev_priv 3999 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_GEN9_LP(dev_priv)) dev_priv 4003 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); dev_priv 4076 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 4080 drivers/gpu/drm/i915/display/intel_ddi.c intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); dev_priv 4090 drivers/gpu/drm/i915/display/intel_ddi.c ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, dev_priv 4217 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); dev_priv 4228 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_GEN9_LP(dev_priv)) dev_priv 4236 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_CANNONLAKE(dev_priv) && dev_priv 4237 drivers/gpu/drm/i915/display/intel_ddi.c !intel_bios_is_port_present(dev_priv, PORT_E)) dev_priv 4246 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); dev_priv 4250 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 4275 drivers/gpu/drm/i915/display/intel_ddi.c void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) dev_priv 4278 drivers/gpu/drm/i915/display/intel_ddi.c &dev_priv->vbt.ddi_port_info[port]; dev_priv 4284 drivers/gpu/drm/i915/display/intel_ddi.c enum phy phy = intel_port_to_phy(dev_priv, port); dev_priv 4289 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_bios_is_lspcon_present(dev_priv, port)) { dev_priv 4314 drivers/gpu/drm/i915/display/intel_ddi.c drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs, dev_priv 4335 drivers/gpu/drm/i915/display/intel_ddi.c for_each_pipe(dev_priv, pipe) dev_priv 4338 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 4346 drivers/gpu/drm/i915/display/intel_ddi.c intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); dev_priv 4348 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_phy_is_tc(dev_priv, phy)) { dev_priv 27 drivers/gpu/drm/i915/display/intel_ddi.h void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); dev_priv 39 drivers/gpu/drm/i915/display/intel_ddi.h void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, dev_priv 49 drivers/gpu/drm/i915/display/intel_ddi.h int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, dev_priv 161 drivers/gpu/drm/i915/display/intel_display.c int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) dev_priv 166 drivers/gpu/drm/i915/display/intel_display.c hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & dev_priv 172 drivers/gpu/drm/i915/display/intel_display.c int vlv_get_cck_clock(struct drm_i915_private *dev_priv, dev_priv 178 drivers/gpu/drm/i915/display/intel_display.c val = vlv_cck_read(dev_priv, reg); dev_priv 188 drivers/gpu/drm/i915/display/intel_display.c int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, dev_priv 193 drivers/gpu/drm/i915/display/intel_display.c vlv_cck_get(dev_priv); dev_priv 195 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->hpll_freq == 0) dev_priv 196 drivers/gpu/drm/i915/display/intel_display.c dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); dev_priv 198 drivers/gpu/drm/i915/display/intel_display.c hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); dev_priv 200 drivers/gpu/drm/i915/display/intel_display.c vlv_cck_put(dev_priv); dev_priv 205 drivers/gpu/drm/i915/display/intel_display.c static void intel_update_czclk(struct drm_i915_private *dev_priv) dev_priv 207 drivers/gpu/drm/i915/display/intel_display.c if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) dev_priv 210 drivers/gpu/drm/i915/display/intel_display.c dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", dev_priv 213 drivers/gpu/drm/i915/display/intel_display.c DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); dev_priv 217 drivers/gpu/drm/i915/display/intel_display.c intel_fdi_link_freq(struct drm_i915_private *dev_priv, dev_priv 220 drivers/gpu/drm/i915/display/intel_display.c if (HAS_DDI(dev_priv)) dev_priv 223 drivers/gpu/drm/i915/display/intel_display.c return dev_priv->fdi_pll_freq; dev_priv 493 drivers/gpu/drm/i915/display/intel_display.c skl_wa_827(struct drm_i915_private *dev_priv, int pipe, bool enable) dev_priv 507 drivers/gpu/drm/i915/display/intel_display.c icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, dev_priv 593 drivers/gpu/drm/i915/display/intel_display.c static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, dev_priv 606 drivers/gpu/drm/i915/display/intel_display.c if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && dev_priv 607 drivers/gpu/drm/i915/display/intel_display.c !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) dev_priv 611 drivers/gpu/drm/i915/display/intel_display.c if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && dev_priv 612 drivers/gpu/drm/i915/display/intel_display.c !IS_GEN9_LP(dev_priv)) { dev_priv 635 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 643 drivers/gpu/drm/i915/display/intel_display.c if (intel_is_dual_link_lvds(dev_priv)) dev_priv 1021 drivers/gpu/drm/i915/display/intel_display.c enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, dev_priv 1024 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 1029 drivers/gpu/drm/i915/display/intel_display.c static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, dev_priv 1036 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 2)) dev_priv 1050 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1054 drivers/gpu/drm/i915/display/intel_display.c if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) dev_priv 1073 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1075 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) { dev_priv 1080 drivers/gpu/drm/i915/display/intel_display.c if (intel_de_wait_for_clear(dev_priv, reg, dev_priv 1089 drivers/gpu/drm/i915/display/intel_display.c void assert_pll(struct drm_i915_private *dev_priv, dev_priv 1103 drivers/gpu/drm/i915/display/intel_display.c void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) dev_priv 1108 drivers/gpu/drm/i915/display/intel_display.c vlv_cck_get(dev_priv); dev_priv 1109 drivers/gpu/drm/i915/display/intel_display.c val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); dev_priv 1110 drivers/gpu/drm/i915/display/intel_display.c vlv_cck_put(dev_priv); dev_priv 1118 drivers/gpu/drm/i915/display/intel_display.c static void assert_fdi_tx(struct drm_i915_private *dev_priv, dev_priv 1122 drivers/gpu/drm/i915/display/intel_display.c enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, dev_priv 1125 drivers/gpu/drm/i915/display/intel_display.c if (HAS_DDI(dev_priv)) { dev_priv 1140 drivers/gpu/drm/i915/display/intel_display.c static void assert_fdi_rx(struct drm_i915_private *dev_priv, dev_priv 1155 drivers/gpu/drm/i915/display/intel_display.c static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, dev_priv 1161 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 5)) dev_priv 1165 drivers/gpu/drm/i915/display/intel_display.c if (HAS_DDI(dev_priv)) dev_priv 1172 drivers/gpu/drm/i915/display/intel_display.c void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, dev_priv 1185 drivers/gpu/drm/i915/display/intel_display.c void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv 1192 drivers/gpu/drm/i915/display/intel_display.c if (WARN_ON(HAS_DDI(dev_priv))) dev_priv 1195 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 1203 drivers/gpu/drm/i915/display/intel_display.c intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe); dev_priv 1206 drivers/gpu/drm/i915/display/intel_display.c intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe); dev_priv 1209 drivers/gpu/drm/i915/display/intel_display.c intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe); dev_priv 1212 drivers/gpu/drm/i915/display/intel_display.c intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe); dev_priv 1218 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 1229 drivers/gpu/drm/i915/display/intel_display.c intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe); dev_priv 1242 drivers/gpu/drm/i915/display/intel_display.c void assert_pipe(struct drm_i915_private *dev_priv, dev_priv 1246 drivers/gpu/drm/i915/display/intel_display.c enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, dev_priv 1252 drivers/gpu/drm/i915/display/intel_display.c if (IS_I830(dev_priv)) dev_priv 1256 drivers/gpu/drm/i915/display/intel_display.c wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 1261 drivers/gpu/drm/i915/display/intel_display.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 1288 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1291 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) dev_priv 1301 drivers/gpu/drm/i915/display/intel_display.c void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, dev_priv 1314 drivers/gpu/drm/i915/display/intel_display.c static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, dev_priv 1321 drivers/gpu/drm/i915/display/intel_display.c state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe); dev_priv 1327 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, dev_priv 1332 drivers/gpu/drm/i915/display/intel_display.c static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, dev_priv 1339 drivers/gpu/drm/i915/display/intel_display.c state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe); dev_priv 1345 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, dev_priv 1350 drivers/gpu/drm/i915/display/intel_display.c static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, dev_priv 1355 drivers/gpu/drm/i915/display/intel_display.c assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); dev_priv 1356 drivers/gpu/drm/i915/display/intel_display.c assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C); dev_priv 1357 drivers/gpu/drm/i915/display/intel_display.c assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D); dev_priv 1359 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && dev_priv 1364 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && dev_priv 1370 drivers/gpu/drm/i915/display/intel_display.c assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); dev_priv 1371 drivers/gpu/drm/i915/display/intel_display.c assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC); dev_priv 1372 drivers/gpu/drm/i915/display/intel_display.c assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID); dev_priv 1378 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1385 drivers/gpu/drm/i915/display/intel_display.c if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) dev_priv 1392 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1395 drivers/gpu/drm/i915/display/intel_display.c assert_pipe_disabled(dev_priv, pipe); dev_priv 1398 drivers/gpu/drm/i915/display/intel_display.c assert_panel_unlocked(dev_priv, pipe); dev_priv 1411 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1416 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_get(dev_priv); dev_priv 1419 drivers/gpu/drm/i915/display/intel_display.c tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); dev_priv 1421 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); dev_priv 1423 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_put(dev_priv); dev_priv 1434 drivers/gpu/drm/i915/display/intel_display.c if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) dev_priv 1441 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1444 drivers/gpu/drm/i915/display/intel_display.c assert_pipe_disabled(dev_priv, pipe); dev_priv 1447 drivers/gpu/drm/i915/display/intel_display.c assert_panel_unlocked(dev_priv, pipe); dev_priv 1462 drivers/gpu/drm/i915/display/intel_display.c dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; dev_priv 1475 drivers/gpu/drm/i915/display/intel_display.c static bool i9xx_has_pps(struct drm_i915_private *dev_priv) dev_priv 1477 drivers/gpu/drm/i915/display/intel_display.c if (IS_I830(dev_priv)) dev_priv 1480 drivers/gpu/drm/i915/display/intel_display.c return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); dev_priv 1486 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1491 drivers/gpu/drm/i915/display/intel_display.c assert_pipe_disabled(dev_priv, crtc->pipe); dev_priv 1494 drivers/gpu/drm/i915/display/intel_display.c if (i9xx_has_pps(dev_priv)) dev_priv 1495 drivers/gpu/drm/i915/display/intel_display.c assert_panel_unlocked(dev_priv, crtc->pipe); dev_priv 1509 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) { dev_priv 1532 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1536 drivers/gpu/drm/i915/display/intel_display.c if (IS_I830(dev_priv)) dev_priv 1540 drivers/gpu/drm/i915/display/intel_display.c assert_pipe_disabled(dev_priv, pipe); dev_priv 1546 drivers/gpu/drm/i915/display/intel_display.c static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv 1551 drivers/gpu/drm/i915/display/intel_display.c assert_pipe_disabled(dev_priv, pipe); dev_priv 1562 drivers/gpu/drm/i915/display/intel_display.c static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv 1568 drivers/gpu/drm/i915/display/intel_display.c assert_pipe_disabled(dev_priv, pipe); dev_priv 1578 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_get(dev_priv); dev_priv 1581 drivers/gpu/drm/i915/display/intel_display.c val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); dev_priv 1583 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); dev_priv 1585 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_put(dev_priv); dev_priv 1588 drivers/gpu/drm/i915/display/intel_display.c void vlv_wait_port_ready(struct drm_i915_private *dev_priv, dev_priv 1613 drivers/gpu/drm/i915/display/intel_display.c if (intel_de_wait_for_register(dev_priv, dpll_reg, dev_priv 1623 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1629 drivers/gpu/drm/i915/display/intel_display.c assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); dev_priv 1632 drivers/gpu/drm/i915/display/intel_display.c assert_fdi_tx_enabled(dev_priv, pipe); dev_priv 1633 drivers/gpu/drm/i915/display/intel_display.c assert_fdi_rx_enabled(dev_priv, pipe); dev_priv 1635 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_CPT(dev_priv)) { dev_priv 1648 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_IBX(dev_priv)) { dev_priv 1663 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_IBX(dev_priv) && dev_priv 1673 drivers/gpu/drm/i915/display/intel_display.c if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100)) dev_priv 1677 drivers/gpu/drm/i915/display/intel_display.c static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, dev_priv 1683 drivers/gpu/drm/i915/display/intel_display.c assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); dev_priv 1684 drivers/gpu/drm/i915/display/intel_display.c assert_fdi_rx_enabled(dev_priv, PIPE_A); dev_priv 1701 drivers/gpu/drm/i915/display/intel_display.c if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF, dev_priv 1706 drivers/gpu/drm/i915/display/intel_display.c static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, dev_priv 1713 drivers/gpu/drm/i915/display/intel_display.c assert_fdi_tx_disabled(dev_priv, pipe); dev_priv 1714 drivers/gpu/drm/i915/display/intel_display.c assert_fdi_rx_disabled(dev_priv, pipe); dev_priv 1717 drivers/gpu/drm/i915/display/intel_display.c assert_pch_ports_disabled(dev_priv, pipe); dev_priv 1724 drivers/gpu/drm/i915/display/intel_display.c if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50)) dev_priv 1727 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_CPT(dev_priv)) { dev_priv 1736 drivers/gpu/drm/i915/display/intel_display.c void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) dev_priv 1744 drivers/gpu/drm/i915/display/intel_display.c if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF, dev_priv 1756 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1758 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_LPT(dev_priv)) dev_priv 1766 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 1772 drivers/gpu/drm/i915/display/intel_display.c if (IS_I965GM(dev_priv) && dev_priv 1776 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) dev_priv 1778 drivers/gpu/drm/i915/display/intel_display.c else if (INTEL_GEN(dev_priv) >= 3) dev_priv 1796 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1811 drivers/gpu/drm/i915/display/intel_display.c if (HAS_GMCH(dev_priv)) { dev_priv 1813 drivers/gpu/drm/i915/display/intel_display.c assert_dsi_pll_enabled(dev_priv); dev_priv 1815 drivers/gpu/drm/i915/display/intel_display.c assert_pll_enabled(dev_priv, pipe); dev_priv 1819 drivers/gpu/drm/i915/display/intel_display.c assert_fdi_rx_pll_enabled(dev_priv, dev_priv 1821 drivers/gpu/drm/i915/display/intel_display.c assert_fdi_tx_pll_enabled(dev_priv, dev_priv 1833 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(!IS_I830(dev_priv)); dev_priv 1854 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1883 drivers/gpu/drm/i915/display/intel_display.c if (!IS_I830(dev_priv)) dev_priv 1891 drivers/gpu/drm/i915/display/intel_display.c static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) dev_priv 1893 drivers/gpu/drm/i915/display/intel_display.c return IS_GEN(dev_priv, 2) ? 2048 : 4096; dev_priv 1899 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(fb->dev); dev_priv 1904 drivers/gpu/drm/i915/display/intel_display.c return intel_tile_size(dev_priv); dev_priv 1906 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 2)) dev_priv 1915 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv)) dev_priv 2006 drivers/gpu/drm/i915/display/intel_display.c static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv) dev_priv 2008 drivers/gpu/drm/i915/display/intel_display.c if (IS_I830(dev_priv)) dev_priv 2010 drivers/gpu/drm/i915/display/intel_display.c else if (IS_I85X(dev_priv)) dev_priv 2012 drivers/gpu/drm/i915/display/intel_display.c else if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) dev_priv 2018 drivers/gpu/drm/i915/display/intel_display.c static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) dev_priv 2020 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 2022 drivers/gpu/drm/i915/display/intel_display.c else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || dev_priv 2023 drivers/gpu/drm/i915/display/intel_display.c IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 2025 drivers/gpu/drm/i915/display/intel_display.c else if (INTEL_GEN(dev_priv) >= 4) dev_priv 2034 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(fb->dev); dev_priv 2042 drivers/gpu/drm/i915/display/intel_display.c return intel_linear_alignment(dev_priv); dev_priv 2044 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 2061 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 2063 drivers/gpu/drm/i915/display/intel_display.c return INTEL_GEN(dev_priv) < 4 || dev_priv 2075 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 2091 drivers/gpu/drm/i915/display/intel_display.c if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) dev_priv 2101 drivers/gpu/drm/i915/display/intel_display.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 2104 drivers/gpu/drm/i915/display/intel_display.c atomic_inc(&dev_priv->gpu_error.pending_fb_pin); dev_priv 2115 drivers/gpu/drm/i915/display/intel_display.c if (HAS_GMCH(dev_priv)) dev_priv 2143 drivers/gpu/drm/i915/display/intel_display.c if (ret != 0 && INTEL_GEN(dev_priv) < 4) { dev_priv 2155 drivers/gpu/drm/i915/display/intel_display.c atomic_dec(&dev_priv->gpu_error.pending_fb_pin); dev_priv 2158 drivers/gpu/drm/i915/display/intel_display.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 2254 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(fb->dev); dev_priv 2263 drivers/gpu/drm/i915/display/intel_display.c tile_size = intel_tile_size(dev_priv); dev_priv 2315 drivers/gpu/drm/i915/display/intel_display.c static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv, dev_priv 2333 drivers/gpu/drm/i915/display/intel_display.c tile_size = intel_tile_size(dev_priv); dev_priv 2371 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); dev_priv 2378 drivers/gpu/drm/i915/display/intel_display.c alignment = intel_cursor_alignment(dev_priv); dev_priv 2382 drivers/gpu/drm/i915/display/intel_display.c return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane, dev_priv 2391 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(fb->dev); dev_priv 2395 drivers/gpu/drm/i915/display/intel_display.c fb->offsets[color_plane] % intel_tile_size(dev_priv)) { dev_priv 2496 drivers/gpu/drm/i915/display/intel_display.c u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, dev_priv 2506 drivers/gpu/drm/i915/display/intel_display.c crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); dev_priv 2517 drivers/gpu/drm/i915/display/intel_display.c u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, dev_priv 2527 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 7) dev_priv 2529 drivers/gpu/drm/i915/display/intel_display.c else if (INTEL_GEN(dev_priv) >= 4) dev_priv 2533 drivers/gpu/drm/i915/display/intel_display.c return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier); dev_priv 2539 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(fb->dev); dev_priv 2542 drivers/gpu/drm/i915/display/intel_display.c u32 max_stride = intel_plane_fb_max_stride(dev_priv, dev_priv 2551 drivers/gpu/drm/i915/display/intel_display.c return intel_tile_size(dev_priv); dev_priv 2562 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 2576 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 4) dev_priv 2588 drivers/gpu/drm/i915/display/intel_display.c unsigned int alignment = intel_tile_size(dev_priv) - 1; dev_priv 2628 drivers/gpu/drm/i915/display/intel_display.c intel_fill_fb_info(struct drm_i915_private *dev_priv, dev_priv 2637 drivers/gpu/drm/i915/display/intel_display.c unsigned int tile_size = intel_tile_size(dev_priv); dev_priv 2711 drivers/gpu/drm/i915/display/intel_display.c offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i, dev_priv 2795 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = dev_priv 2802 drivers/gpu/drm/i915/display/intel_display.c unsigned int tile_size = intel_tile_size(dev_priv); dev_priv 2852 drivers/gpu/drm/i915/display/intel_display.c offset = intel_compute_aligned_offset(dev_priv, &x, &y, dev_priv 3038 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 3055 drivers/gpu/drm/i915/display/intel_display.c if (size_aligned * 2 > dev_priv->stolen_usable_size) dev_priv 3070 drivers/gpu/drm/i915/display/intel_display.c obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, dev_priv 3127 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 3137 drivers/gpu/drm/i915/display/intel_display.c drm_for_each_plane_mask(plane, &dev_priv->drm, dev_priv 3175 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 3268 drivers/gpu/drm/i915/display/intel_display.c dev_priv->preserve_bios_swizzle = true; dev_priv 3390 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); dev_priv 3401 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 3403 drivers/gpu/drm/i915/display/intel_display.c else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 3573 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 3575 drivers/gpu/drm/i915/display/intel_display.c if (!HAS_GMCH(dev_priv)) { dev_priv 3577 drivers/gpu/drm/i915/display/intel_display.c } else if (INTEL_GEN(dev_priv) >= 4) { dev_priv 3582 drivers/gpu/drm/i915/display/intel_display.c } else if (INTEL_GEN(dev_priv) >= 3) { dev_priv 3598 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 3607 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 5) dev_priv 3616 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = dev_priv 3624 drivers/gpu/drm/i915/display/intel_display.c if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) || dev_priv 3625 drivers/gpu/drm/i915/display/intel_display.c IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) dev_priv 3655 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4 && dev_priv 3670 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = dev_priv 3688 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 3703 drivers/gpu/drm/i915/display/intel_display.c if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { dev_priv 3725 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 3728 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 3730 drivers/gpu/drm/i915/display/intel_display.c else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) dev_priv 3732 drivers/gpu/drm/i915/display/intel_display.c else if (IS_GEN(dev_priv, 4)) dev_priv 3779 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 3796 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 3801 drivers/gpu/drm/i915/display/intel_display.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 3805 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 4) { dev_priv 3814 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { dev_priv 3821 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { dev_priv 3823 drivers/gpu/drm/i915/display/intel_display.c } else if (INTEL_GEN(dev_priv) >= 4) { dev_priv 3834 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 3843 drivers/gpu/drm/i915/display/intel_display.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 3849 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 3866 drivers/gpu/drm/i915/display/intel_display.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 3869 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 3874 drivers/gpu/drm/i915/display/intel_display.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 3880 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 3893 drivers/gpu/drm/i915/display/intel_display.c wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 3901 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 5) dev_priv 3907 drivers/gpu/drm/i915/display/intel_display.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 3915 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 4122 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 4125 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 4140 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = dev_priv 4149 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) { dev_priv 4164 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 10) dev_priv 4178 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 4181 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 4196 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = dev_priv 4205 drivers/gpu/drm/i915/display/intel_display.c if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { dev_priv 4259 drivers/gpu/drm/i915/display/intel_display.c static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) dev_priv 4261 drivers/gpu/drm/i915/display/intel_display.c return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && dev_priv 4262 drivers/gpu/drm/i915/display/intel_display.c intel_has_gpu_reset(dev_priv)); dev_priv 4265 drivers/gpu/drm/i915/display/intel_display.c void intel_prepare_reset(struct drm_i915_private *dev_priv) dev_priv 4267 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = &dev_priv->drm; dev_priv 4268 drivers/gpu/drm/i915/display/intel_display.c struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; dev_priv 4274 drivers/gpu/drm/i915/display/intel_display.c !gpu_reset_clobbers_display(dev_priv)) dev_priv 4278 drivers/gpu/drm/i915/display/intel_display.c set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags); dev_priv 4280 drivers/gpu/drm/i915/display/intel_display.c wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET); dev_priv 4282 drivers/gpu/drm/i915/display/intel_display.c if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { dev_priv 4284 drivers/gpu/drm/i915/display/intel_display.c intel_gt_set_wedged(&dev_priv->gt); dev_priv 4318 drivers/gpu/drm/i915/display/intel_display.c dev_priv->modeset_restore_state = state; dev_priv 4322 drivers/gpu/drm/i915/display/intel_display.c void intel_finish_reset(struct drm_i915_private *dev_priv) dev_priv 4324 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = &dev_priv->drm; dev_priv 4325 drivers/gpu/drm/i915/display/intel_display.c struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; dev_priv 4330 drivers/gpu/drm/i915/display/intel_display.c if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags)) dev_priv 4333 drivers/gpu/drm/i915/display/intel_display.c state = fetch_and_zero(&dev_priv->modeset_restore_state); dev_priv 4338 drivers/gpu/drm/i915/display/intel_display.c if (!gpu_reset_clobbers_display(dev_priv)) { dev_priv 4348 drivers/gpu/drm/i915/display/intel_display.c intel_pps_unlock_regs_wa(dev_priv); dev_priv 4350 drivers/gpu/drm/i915/display/intel_display.c intel_init_clock_gating(dev_priv); dev_priv 4352 drivers/gpu/drm/i915/display/intel_display.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 4353 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->display.hpd_irq_setup) dev_priv 4354 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.hpd_irq_setup(dev_priv); dev_priv 4355 drivers/gpu/drm/i915/display/intel_display.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 4361 drivers/gpu/drm/i915/display/intel_display.c intel_hpd_init(dev_priv); dev_priv 4370 drivers/gpu/drm/i915/display/intel_display.c clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags); dev_priv 4375 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 4401 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 4420 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 4425 drivers/gpu/drm/i915/display/intel_display.c } else if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 4432 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 4439 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 4447 drivers/gpu/drm/i915/display/intel_display.c if (IS_IVYBRIDGE(dev_priv)) { dev_priv 4458 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_CPT(dev_priv)) { dev_priv 4472 drivers/gpu/drm/i915/display/intel_display.c if (IS_IVYBRIDGE(dev_priv)) dev_priv 4482 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 4488 drivers/gpu/drm/i915/display/intel_display.c assert_pipe_enabled(dev_priv, pipe); dev_priv 4583 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 4616 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_CPT(dev_priv)) { dev_priv 4660 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 6)) { dev_priv 4669 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_CPT(dev_priv)) { dev_priv 4716 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 4834 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); dev_priv 4871 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 4901 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 4923 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_IBX(dev_priv)) dev_priv 4935 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_CPT(dev_priv)) { dev_priv 4951 drivers/gpu/drm/i915/display/intel_display.c bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) dev_priv 4956 drivers/gpu/drm/i915/display/intel_display.c drm_for_each_crtc(crtc, &dev_priv->drm) { dev_priv 4976 drivers/gpu/drm/i915/display/intel_display.c void lpt_disable_iclkip(struct drm_i915_private *dev_priv) dev_priv 4982 drivers/gpu/drm/i915/display/intel_display.c mutex_lock(&dev_priv->sb_lock); dev_priv 4984 drivers/gpu/drm/i915/display/intel_display.c temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); dev_priv 4986 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); dev_priv 4988 drivers/gpu/drm/i915/display/intel_display.c mutex_unlock(&dev_priv->sb_lock); dev_priv 4995 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 5000 drivers/gpu/drm/i915/display/intel_display.c lpt_disable_iclkip(dev_priv); dev_priv 5039 drivers/gpu/drm/i915/display/intel_display.c mutex_lock(&dev_priv->sb_lock); dev_priv 5042 drivers/gpu/drm/i915/display/intel_display.c temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); dev_priv 5049 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); dev_priv 5052 drivers/gpu/drm/i915/display/intel_display.c temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); dev_priv 5055 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); dev_priv 5058 drivers/gpu/drm/i915/display/intel_display.c temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); dev_priv 5060 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); dev_priv 5062 drivers/gpu/drm/i915/display/intel_display.c mutex_unlock(&dev_priv->sb_lock); dev_priv 5070 drivers/gpu/drm/i915/display/intel_display.c int lpt_get_iclkip(struct drm_i915_private *dev_priv) dev_priv 5081 drivers/gpu/drm/i915/display/intel_display.c mutex_lock(&dev_priv->sb_lock); dev_priv 5083 drivers/gpu/drm/i915/display/intel_display.c temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); dev_priv 5085 drivers/gpu/drm/i915/display/intel_display.c mutex_unlock(&dev_priv->sb_lock); dev_priv 5089 drivers/gpu/drm/i915/display/intel_display.c temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); dev_priv 5095 drivers/gpu/drm/i915/display/intel_display.c temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); dev_priv 5099 drivers/gpu/drm/i915/display/intel_display.c mutex_unlock(&dev_priv->sb_lock); dev_priv 5111 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 5131 drivers/gpu/drm/i915/display/intel_display.c static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable) dev_priv 5154 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 5161 drivers/gpu/drm/i915/display/intel_display.c cpt_set_fdi_bc_bifurcation(dev_priv, false); dev_priv 5163 drivers/gpu/drm/i915/display/intel_display.c cpt_set_fdi_bc_bifurcation(dev_priv, true); dev_priv 5167 drivers/gpu/drm/i915/display/intel_display.c cpt_set_fdi_bc_bifurcation(dev_priv, true); dev_priv 5217 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 5221 drivers/gpu/drm/i915/display/intel_display.c assert_pch_transcoder_disabled(dev_priv, pipe); dev_priv 5223 drivers/gpu/drm/i915/display/intel_display.c if (IS_IVYBRIDGE(dev_priv)) dev_priv 5232 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.fdi_link_train(crtc, crtc_state); dev_priv 5236 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_CPT(dev_priv)) { dev_priv 5243 drivers/gpu/drm/i915/display/intel_display.c intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) dev_priv 5260 drivers/gpu/drm/i915/display/intel_display.c assert_panel_unlocked(dev_priv, pipe); dev_priv 5266 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_CPT(dev_priv) && dev_priv 5300 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 5303 drivers/gpu/drm/i915/display/intel_display.c assert_pch_transcoder_disabled(dev_priv, PIPE_A); dev_priv 5310 drivers/gpu/drm/i915/display/intel_display.c lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); dev_priv 5315 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 5417 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); dev_priv 5435 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && dev_priv 5474 drivers/gpu/drm/i915/display/intel_display.c (INTEL_GEN(dev_priv) >= 11 && dev_priv 5477 drivers/gpu/drm/i915/display/intel_display.c (INTEL_GEN(dev_priv) < 11 && dev_priv 5534 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); dev_priv 5541 drivers/gpu/drm/i915/display/intel_display.c if (!icl_is_hdr_plane(dev_priv, intel_plane->id) && dev_priv 5614 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 5651 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 5659 drivers/gpu/drm/i915/display/intel_display.c if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) dev_priv 5673 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 5685 drivers/gpu/drm/i915/display/intel_display.c if (IS_BROADWELL(dev_priv)) { dev_priv 5686 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, dev_priv 5700 drivers/gpu/drm/i915/display/intel_display.c if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50)) dev_priv 5709 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 5714 drivers/gpu/drm/i915/display/intel_display.c if (IS_BROADWELL(dev_priv)) { dev_priv 5715 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); dev_priv 5721 drivers/gpu/drm/i915/display/intel_display.c if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100)) dev_priv 5729 drivers/gpu/drm/i915/display/intel_display.c intel_wait_for_vblank(dev_priv, crtc->pipe); dev_priv 5763 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 5774 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 2)) dev_priv 5775 drivers/gpu/drm/i915/display/intel_display.c intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); dev_priv 5778 drivers/gpu/drm/i915/display/intel_display.c intel_check_cpu_fifo_underruns(dev_priv); dev_priv 5779 drivers/gpu/drm/i915/display/intel_display.c intel_check_pch_fifo_underruns(dev_priv); dev_priv 5787 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 5795 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 2)) dev_priv 5796 drivers/gpu/drm/i915/display/intel_display.c intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); dev_priv 5809 drivers/gpu/drm/i915/display/intel_display.c if (HAS_GMCH(dev_priv) && dev_priv 5810 drivers/gpu/drm/i915/display/intel_display.c intel_set_memory_cxsr(dev_priv, false)) dev_priv 5811 drivers/gpu/drm/i915/display/intel_display.c intel_wait_for_vblank(dev_priv, pipe); dev_priv 5818 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 5832 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv) && dev_priv 5845 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 5859 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv) && dev_priv 5876 drivers/gpu/drm/i915/display/intel_display.c static bool needs_nv12_wa(struct drm_i915_private *dev_priv, dev_priv 5883 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) dev_priv 5889 drivers/gpu/drm/i915/display/intel_display.c static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv, dev_priv 5893 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv)) dev_priv 5903 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 5932 drivers/gpu/drm/i915/display/intel_display.c if (needs_nv12_wa(dev_priv, old_crtc_state) && dev_priv 5933 drivers/gpu/drm/i915/display/intel_display.c !needs_nv12_wa(dev_priv, pipe_config)) dev_priv 5934 drivers/gpu/drm/i915/display/intel_display.c skl_wa_827(dev_priv, crtc->pipe, false); dev_priv 5936 drivers/gpu/drm/i915/display/intel_display.c if (needs_scalerclk_wa(dev_priv, old_crtc_state) && dev_priv 5937 drivers/gpu/drm/i915/display/intel_display.c !needs_scalerclk_wa(dev_priv, pipe_config)) dev_priv 5938 drivers/gpu/drm/i915/display/intel_display.c icl_wa_scalerclkgating(dev_priv, crtc->pipe, false); dev_priv 5946 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 5968 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 2) && old_primary_state->visible && dev_priv 5970 drivers/gpu/drm/i915/display/intel_display.c intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); dev_priv 5974 drivers/gpu/drm/i915/display/intel_display.c if (!needs_nv12_wa(dev_priv, old_crtc_state) && dev_priv 5975 drivers/gpu/drm/i915/display/intel_display.c needs_nv12_wa(dev_priv, pipe_config)) dev_priv 5976 drivers/gpu/drm/i915/display/intel_display.c skl_wa_827(dev_priv, crtc->pipe, true); dev_priv 5979 drivers/gpu/drm/i915/display/intel_display.c if (!needs_scalerclk_wa(dev_priv, old_crtc_state) && dev_priv 5980 drivers/gpu/drm/i915/display/intel_display.c needs_scalerclk_wa(dev_priv, pipe_config)) dev_priv 5981 drivers/gpu/drm/i915/display/intel_display.c icl_wa_scalerclkgating(dev_priv, crtc->pipe, true); dev_priv 5992 drivers/gpu/drm/i915/display/intel_display.c if (HAS_GMCH(dev_priv) && old_crtc_state->base.active && dev_priv 5993 drivers/gpu/drm/i915/display/intel_display.c pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) dev_priv 5994 drivers/gpu/drm/i915/display/intel_display.c intel_wait_for_vblank(dev_priv, crtc->pipe); dev_priv 6005 drivers/gpu/drm/i915/display/intel_display.c intel_wait_for_vblank(dev_priv, crtc->pipe); dev_priv 6028 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->display.initial_watermarks != NULL) dev_priv 6029 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.initial_watermarks(intel_state, dev_priv 6038 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 6060 drivers/gpu/drm/i915/display/intel_display.c intel_frontbuffer_flip(dev_priv, fb_bits); dev_priv 6310 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 6327 drivers/gpu/drm/i915/display/intel_display.c intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); dev_priv 6328 drivers/gpu/drm/i915/display/intel_display.c intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); dev_priv 6356 drivers/gpu/drm/i915/display/intel_display.c assert_fdi_tx_disabled(dev_priv, pipe); dev_priv 6357 drivers/gpu/drm/i915/display/intel_display.c assert_fdi_rx_disabled(dev_priv, pipe); dev_priv 6371 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->display.initial_watermarks != NULL) dev_priv 6372 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.initial_watermarks(state, pipe_config); dev_priv 6383 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_CPT(dev_priv)) dev_priv 6393 drivers/gpu/drm/i915/display/intel_display.c intel_wait_for_vblank(dev_priv, pipe); dev_priv 6394 drivers/gpu/drm/i915/display/intel_display.c intel_wait_for_vblank(dev_priv, pipe); dev_priv 6396 drivers/gpu/drm/i915/display/intel_display.c intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); dev_priv 6397 drivers/gpu/drm/i915/display/intel_display.c intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); dev_priv 6406 drivers/gpu/drm/i915/display/intel_display.c static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, dev_priv 6422 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 6428 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 12) { dev_priv 6443 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 6481 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) dev_priv 6487 drivers/gpu/drm/i915/display/intel_display.c psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) && dev_priv 6490 drivers/gpu/drm/i915/display/intel_display.c glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); dev_priv 6492 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 6504 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 9) dev_priv 6507 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 6514 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->display.initial_watermarks != NULL) dev_priv 6515 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.initial_watermarks(state, pipe_config); dev_priv 6517 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 6536 drivers/gpu/drm/i915/display/intel_display.c intel_wait_for_vblank(dev_priv, pipe); dev_priv 6537 drivers/gpu/drm/i915/display/intel_display.c glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); dev_priv 6543 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { dev_priv 6544 drivers/gpu/drm/i915/display/intel_display.c intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); dev_priv 6545 drivers/gpu/drm/i915/display/intel_display.c intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); dev_priv 6552 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 6569 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 6578 drivers/gpu/drm/i915/display/intel_display.c intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); dev_priv 6579 drivers/gpu/drm/i915/display/intel_display.c intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); dev_priv 6596 drivers/gpu/drm/i915/display/intel_display.c ironlake_disable_pch_transcoder(dev_priv, pipe); dev_priv 6598 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_CPT(dev_priv)) { dev_priv 6619 drivers/gpu/drm/i915/display/intel_display.c intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); dev_priv 6620 drivers/gpu/drm/i915/display/intel_display.c intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); dev_priv 6627 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 6648 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 6661 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 6671 drivers/gpu/drm/i915/display/intel_display.c assert_pipe_disabled(dev_priv, crtc->pipe); dev_priv 6681 drivers/gpu/drm/i915/display/intel_display.c bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) dev_priv 6686 drivers/gpu/drm/i915/display/intel_display.c if (IS_ELKHARTLAKE(dev_priv)) dev_priv 6689 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 6695 drivers/gpu/drm/i915/display/intel_display.c bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) dev_priv 6697 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 12) dev_priv 6700 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv)) dev_priv 6714 drivers/gpu/drm/i915/display/intel_display.c enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) dev_priv 6716 drivers/gpu/drm/i915/display/intel_display.c if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) dev_priv 6719 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 12) dev_priv 6749 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); dev_priv 6750 drivers/gpu/drm/i915/display/intel_display.c enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); dev_priv 6752 drivers/gpu/drm/i915/display/intel_display.c if (intel_phy_is_tc(dev_priv, phy) && dev_priv 6791 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 6806 drivers/gpu/drm/i915/display/intel_display.c drm_for_each_encoder_mask(encoder, &dev_priv->drm, dev_priv 6813 drivers/gpu/drm/i915/display/intel_display.c if (HAS_DDI(dev_priv) && crtc_state->has_audio) dev_priv 6826 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 6837 drivers/gpu/drm/i915/display/intel_display.c intel_display_power_get(dev_priv, domain); dev_priv 6842 drivers/gpu/drm/i915/display/intel_display.c static void modeset_put_power_domains(struct drm_i915_private *dev_priv, dev_priv 6848 drivers/gpu/drm/i915/display/intel_display.c intel_display_power_put_unchecked(dev_priv, domain); dev_priv 6856 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 6869 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { dev_priv 6878 drivers/gpu/drm/i915/display/intel_display.c intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); dev_priv 6882 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 6899 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.initial_watermarks(state, pipe_config); dev_priv 6911 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 6922 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 6941 drivers/gpu/drm/i915/display/intel_display.c if (!IS_GEN(dev_priv, 2)) dev_priv 6942 drivers/gpu/drm/i915/display/intel_display.c intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); dev_priv 6955 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->display.initial_watermarks != NULL) dev_priv 6956 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.initial_watermarks(state, dev_priv 6971 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 6976 drivers/gpu/drm/i915/display/intel_display.c assert_pipe_disabled(dev_priv, crtc->pipe); dev_priv 6988 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 6996 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 2)) dev_priv 6997 drivers/gpu/drm/i915/display/intel_display.c intel_wait_for_vblank(dev_priv, pipe); dev_priv 7011 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 7012 drivers/gpu/drm/i915/display/intel_display.c chv_disable_pll(dev_priv, pipe); dev_priv 7013 drivers/gpu/drm/i915/display/intel_display.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 7014 drivers/gpu/drm/i915/display/intel_display.c vlv_disable_pll(dev_priv, pipe); dev_priv 7021 drivers/gpu/drm/i915/display/intel_display.c if (!IS_GEN(dev_priv, 2)) dev_priv 7022 drivers/gpu/drm/i915/display/intel_display.c intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); dev_priv 7024 drivers/gpu/drm/i915/display/intel_display.c if (!dev_priv->display.initial_watermarks) dev_priv 7028 drivers/gpu/drm/i915/display/intel_display.c if (IS_I830(dev_priv)) dev_priv 7029 drivers/gpu/drm/i915/display/intel_display.c i830_enable_pipe(dev_priv, pipe); dev_priv 7037 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 7039 drivers/gpu/drm/i915/display/intel_display.c to_intel_bw_state(dev_priv->bw_obj.state); dev_priv 7050 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) { dev_priv 7073 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_disable(crtc_state, to_intel_atomic_state(state)); dev_priv 7096 drivers/gpu/drm/i915/display/intel_display.c intel_display_power_put_unchecked(dev_priv, domain); dev_priv 7099 drivers/gpu/drm/i915/display/intel_display.c dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); dev_priv 7100 drivers/gpu/drm/i915/display/intel_display.c dev_priv->min_cdclk[intel_crtc->pipe] = 0; dev_priv 7101 drivers/gpu/drm/i915/display/intel_display.c dev_priv->min_voltage_level[intel_crtc->pipe] = 0; dev_priv 7113 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 7122 drivers/gpu/drm/i915/display/intel_display.c dev_priv->modeset_restore_state = state; dev_priv 7184 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 7197 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { dev_priv 7207 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_INFO(dev_priv)->num_pipes == 2) dev_priv 7218 drivers/gpu/drm/i915/display/intel_display.c other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); dev_priv 7237 drivers/gpu/drm/i915/display/intel_display.c other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); dev_priv 7305 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 7324 drivers/gpu/drm/i915/display/intel_display.c if (IS_BROADWELL(dev_priv) && dev_priv 7325 drivers/gpu/drm/i915/display/intel_display.c crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100) dev_priv 7333 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = dev_priv 7355 drivers/gpu/drm/i915/display/intel_display.c if (IS_BROADWELL(dev_priv) && dev_priv 7364 drivers/gpu/drm/i915/display/intel_display.c const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 7367 drivers/gpu/drm/i915/display/intel_display.c return INTEL_GEN(dev_priv) < 4 && dev_priv 7368 drivers/gpu/drm/i915/display/intel_display.c (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); dev_priv 7408 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 7410 drivers/gpu/drm/i915/display/intel_display.c if (HAS_GMCH(dev_priv)) dev_priv 7422 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 7424 drivers/gpu/drm/i915/display/intel_display.c int clock_limit = dev_priv->max_dotclk_freq; dev_priv 7426 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 4) { dev_priv 7427 drivers/gpu/drm/i915/display/intel_display.c clock_limit = dev_priv->max_cdclk_freq * 9 / 10; dev_priv 7435 drivers/gpu/drm/i915/display/intel_display.c clock_limit = dev_priv->max_dotclk_freq; dev_priv 7472 drivers/gpu/drm/i915/display/intel_display.c intel_is_dual_link_lvds(dev_priv)) { dev_priv 7481 drivers/gpu/drm/i915/display/intel_display.c if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && dev_priv 7545 drivers/gpu/drm/i915/display/intel_display.c static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) dev_priv 7549 drivers/gpu/drm/i915/display/intel_display.c return dev_priv->vbt.lvds_use_ssc dev_priv 7550 drivers/gpu/drm/i915/display/intel_display.c && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); dev_priv 7567 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 7570 drivers/gpu/drm/i915/display/intel_display.c if (IS_PINEVIEW(dev_priv)) { dev_priv 7590 drivers/gpu/drm/i915/display/intel_display.c static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe dev_priv 7599 drivers/gpu/drm/i915/display/intel_display.c reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); dev_priv 7602 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); dev_priv 7604 drivers/gpu/drm/i915/display/intel_display.c reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); dev_priv 7607 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); dev_priv 7609 drivers/gpu/drm/i915/display/intel_display.c reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); dev_priv 7611 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); dev_priv 7613 drivers/gpu/drm/i915/display/intel_display.c reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); dev_priv 7616 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); dev_priv 7623 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 7632 drivers/gpu/drm/i915/display/intel_display.c static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv, dev_priv 7635 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv)) dev_priv 7642 drivers/gpu/drm/i915/display/intel_display.c return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv); dev_priv 7650 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 7654 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 5) { dev_priv 7664 drivers/gpu/drm/i915/display/intel_display.c transcoder_has_m2_n2(dev_priv, transcoder)) { dev_priv 7741 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 7756 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_get(dev_priv); dev_priv 7768 drivers/gpu/drm/i915/display/intel_display.c vlv_pllb_recal_opamp(dev_priv, pipe); dev_priv 7771 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); dev_priv 7774 drivers/gpu/drm/i915/display/intel_display.c reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); dev_priv 7776 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); dev_priv 7779 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); dev_priv 7793 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); dev_priv 7796 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); dev_priv 7802 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), dev_priv 7805 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), dev_priv 7811 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), dev_priv 7814 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), dev_priv 7819 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), dev_priv 7822 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), dev_priv 7826 drivers/gpu/drm/i915/display/intel_display.c coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); dev_priv 7830 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); dev_priv 7832 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); dev_priv 7834 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_put(dev_priv); dev_priv 7841 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 7867 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_get(dev_priv); dev_priv 7870 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), dev_priv 7877 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); dev_priv 7880 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), dev_priv 7885 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); dev_priv 7888 drivers/gpu/drm/i915/display/intel_display.c dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); dev_priv 7893 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); dev_priv 7896 drivers/gpu/drm/i915/display/intel_display.c dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); dev_priv 7902 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); dev_priv 7927 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); dev_priv 7929 drivers/gpu/drm/i915/display/intel_display.c dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); dev_priv 7932 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); dev_priv 7935 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), dev_priv 7936 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | dev_priv 7939 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_put(dev_priv); dev_priv 7952 drivers/gpu/drm/i915/display/intel_display.c int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, dev_priv 7955 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 7966 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 7989 drivers/gpu/drm/i915/display/intel_display.c void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv 7991 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 7992 drivers/gpu/drm/i915/display/intel_display.c chv_disable_pll(dev_priv, pipe); dev_priv 7994 drivers/gpu/drm/i915/display/intel_display.c vlv_disable_pll(dev_priv, pipe); dev_priv 8001 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 8014 drivers/gpu/drm/i915/display/intel_display.c if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || dev_priv 8015 drivers/gpu/drm/i915/display/intel_display.c IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { dev_priv 8028 drivers/gpu/drm/i915/display/intel_display.c if (IS_PINEVIEW(dev_priv)) dev_priv 8032 drivers/gpu/drm/i915/display/intel_display.c if (IS_G4X(dev_priv) && reduced_clock) dev_priv 8049 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 8055 drivers/gpu/drm/i915/display/intel_display.c intel_panel_use_ssc(dev_priv)) dev_priv 8063 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) { dev_priv 8075 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 8106 drivers/gpu/drm/i915/display/intel_display.c if (IS_I830(dev_priv) || dev_priv 8111 drivers/gpu/drm/i915/display/intel_display.c intel_panel_use_ssc(dev_priv)) dev_priv 8123 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 8149 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) > 3) dev_priv 8176 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && dev_priv 8185 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 8200 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 8245 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 8282 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 8288 drivers/gpu/drm/i915/display/intel_display.c if (IS_I830(dev_priv)) dev_priv 8295 drivers/gpu/drm/i915/display/intel_display.c if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || dev_priv 8296 drivers/gpu/drm/i915/display/intel_display.c IS_CHERRYVIEW(dev_priv)) { dev_priv 8319 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 4 || dev_priv 8328 drivers/gpu/drm/i915/display/intel_display.c if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && dev_priv 8342 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 8350 drivers/gpu/drm/i915/display/intel_display.c if (intel_panel_use_ssc(dev_priv)) { dev_priv 8351 drivers/gpu/drm/i915/display/intel_display.c refclk = dev_priv->vbt.lvds_ssc_freq; dev_priv 8377 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 8385 drivers/gpu/drm/i915/display/intel_display.c if (intel_panel_use_ssc(dev_priv)) { dev_priv 8386 drivers/gpu/drm/i915/display/intel_display.c refclk = dev_priv->vbt.lvds_ssc_freq; dev_priv 8390 drivers/gpu/drm/i915/display/intel_display.c if (intel_is_dual_link_lvds(dev_priv)) dev_priv 8420 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 8428 drivers/gpu/drm/i915/display/intel_display.c if (intel_panel_use_ssc(dev_priv)) { dev_priv 8429 drivers/gpu/drm/i915/display/intel_display.c refclk = dev_priv->vbt.lvds_ssc_freq; dev_priv 8454 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 8462 drivers/gpu/drm/i915/display/intel_display.c if (intel_panel_use_ssc(dev_priv)) { dev_priv 8463 drivers/gpu/drm/i915/display/intel_display.c refclk = dev_priv->vbt.lvds_ssc_freq; dev_priv 8526 drivers/gpu/drm/i915/display/intel_display.c static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) dev_priv 8528 drivers/gpu/drm/i915/display/intel_display.c if (IS_I830(dev_priv)) dev_priv 8531 drivers/gpu/drm/i915/display/intel_display.c return INTEL_GEN(dev_priv) >= 4 || dev_priv 8532 drivers/gpu/drm/i915/display/intel_display.c IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); dev_priv 8538 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 8541 drivers/gpu/drm/i915/display/intel_display.c if (!i9xx_has_pfit(dev_priv)) dev_priv 8549 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 4) { dev_priv 8565 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 8575 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_get(dev_priv); dev_priv 8576 drivers/gpu/drm/i915/display/intel_display.c mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); dev_priv 8577 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_put(dev_priv); dev_priv 8593 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 8620 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) { dev_priv 8630 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && dev_priv 8638 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { dev_priv 8641 drivers/gpu/drm/i915/display/intel_display.c } else if (INTEL_GEN(dev_priv) >= 4) { dev_priv 8675 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 8686 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_get(dev_priv); dev_priv 8687 drivers/gpu/drm/i915/display/intel_display.c cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); dev_priv 8688 drivers/gpu/drm/i915/display/intel_display.c pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); dev_priv 8689 drivers/gpu/drm/i915/display/intel_display.c pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); dev_priv 8690 drivers/gpu/drm/i915/display/intel_display.c pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); dev_priv 8691 drivers/gpu/drm/i915/display/intel_display.c pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); dev_priv 8692 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_put(dev_priv); dev_priv 8708 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 8713 drivers/gpu/drm/i915/display/intel_display.c if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) { dev_priv 8724 drivers/gpu/drm/i915/display/intel_display.c else if (!(IS_GEMINILAKE(dev_priv) || dev_priv 8725 drivers/gpu/drm/i915/display/intel_display.c INTEL_GEN(dev_priv) >= 10)) dev_priv 8752 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 8761 drivers/gpu/drm/i915/display/intel_display.c if (!HAS_GMCH(dev_priv) && dev_priv 8769 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 8776 drivers/gpu/drm/i915/display/intel_display.c wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 8790 drivers/gpu/drm/i915/display/intel_display.c if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || dev_priv 8791 drivers/gpu/drm/i915/display/intel_display.c IS_CHERRYVIEW(dev_priv)) { dev_priv 8807 drivers/gpu/drm/i915/display/intel_display.c if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && dev_priv 8814 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 8820 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 4) dev_priv 8828 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) { dev_priv 8830 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) dev_priv 8831 drivers/gpu/drm/i915/display/intel_display.c tmp = dev_priv->chv_dpll_md[crtc->pipe]; dev_priv 8838 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || dev_priv 8839 drivers/gpu/drm/i915/display/intel_display.c IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { dev_priv 8851 drivers/gpu/drm/i915/display/intel_display.c if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { dev_priv 8861 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 8863 drivers/gpu/drm/i915/display/intel_display.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 8879 drivers/gpu/drm/i915/display/intel_display.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 8884 drivers/gpu/drm/i915/display/intel_display.c static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) dev_priv 8897 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_encoder(&dev_priv->drm, encoder) { dev_priv 8913 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_IBX(dev_priv)) { dev_priv 8914 drivers/gpu/drm/i915/display/intel_display.c has_ck505 = dev_priv->vbt.display_clock_mode; dev_priv 8922 drivers/gpu/drm/i915/display/intel_display.c for (i = 0; i < dev_priv->num_shared_dpll; i++) { dev_priv 8963 drivers/gpu/drm/i915/display/intel_display.c if (intel_panel_use_ssc(dev_priv) && can_ssc) dev_priv 8967 drivers/gpu/drm/i915/display/intel_display.c if (intel_panel_use_ssc(dev_priv) && can_ssc) dev_priv 8994 drivers/gpu/drm/i915/display/intel_display.c if (intel_panel_use_ssc(dev_priv) && can_ssc) { dev_priv 9009 drivers/gpu/drm/i915/display/intel_display.c if (intel_panel_use_ssc(dev_priv) && can_ssc) { dev_priv 9051 drivers/gpu/drm/i915/display/intel_display.c static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) dev_priv 9073 drivers/gpu/drm/i915/display/intel_display.c static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) dev_priv 9077 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); dev_priv 9080 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); dev_priv 9082 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); dev_priv 9084 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); dev_priv 9086 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); dev_priv 9088 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); dev_priv 9090 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); dev_priv 9092 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); dev_priv 9094 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); dev_priv 9096 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); dev_priv 9098 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); dev_priv 9101 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); dev_priv 9103 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); dev_priv 9106 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); dev_priv 9108 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); dev_priv 9111 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); dev_priv 9113 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); dev_priv 9116 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); dev_priv 9118 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); dev_priv 9121 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); dev_priv 9123 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); dev_priv 9126 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); dev_priv 9128 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); dev_priv 9130 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); dev_priv 9132 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); dev_priv 9134 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); dev_priv 9136 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); dev_priv 9139 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); dev_priv 9141 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); dev_priv 9144 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); dev_priv 9153 drivers/gpu/drm/i915/display/intel_display.c static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, dev_priv 9160 drivers/gpu/drm/i915/display/intel_display.c if (WARN(HAS_PCH_LPT_LP(dev_priv) && dev_priv 9164 drivers/gpu/drm/i915/display/intel_display.c mutex_lock(&dev_priv->sb_lock); dev_priv 9166 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); dev_priv 9169 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); dev_priv 9174 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); dev_priv 9176 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); dev_priv 9179 drivers/gpu/drm/i915/display/intel_display.c lpt_reset_fdi_mphy(dev_priv); dev_priv 9180 drivers/gpu/drm/i915/display/intel_display.c lpt_program_fdi_mphy(dev_priv); dev_priv 9184 drivers/gpu/drm/i915/display/intel_display.c reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; dev_priv 9185 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); dev_priv 9187 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); dev_priv 9189 drivers/gpu/drm/i915/display/intel_display.c mutex_unlock(&dev_priv->sb_lock); dev_priv 9193 drivers/gpu/drm/i915/display/intel_display.c void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) dev_priv 9197 drivers/gpu/drm/i915/display/intel_display.c mutex_lock(&dev_priv->sb_lock); dev_priv 9199 drivers/gpu/drm/i915/display/intel_display.c reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; dev_priv 9200 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); dev_priv 9202 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); dev_priv 9204 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); dev_priv 9208 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); dev_priv 9212 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); dev_priv 9215 drivers/gpu/drm/i915/display/intel_display.c mutex_unlock(&dev_priv->sb_lock); dev_priv 9250 drivers/gpu/drm/i915/display/intel_display.c static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) dev_priv 9261 drivers/gpu/drm/i915/display/intel_display.c mutex_lock(&dev_priv->sb_lock); dev_priv 9267 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); dev_priv 9269 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); dev_priv 9272 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); dev_priv 9274 drivers/gpu/drm/i915/display/intel_display.c mutex_unlock(&dev_priv->sb_lock); dev_priv 9279 drivers/gpu/drm/i915/display/intel_display.c static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv) dev_priv 9291 drivers/gpu/drm/i915/display/intel_display.c if (IS_BROADWELL(dev_priv) && dev_priv 9298 drivers/gpu/drm/i915/display/intel_display.c static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv, dev_priv 9310 drivers/gpu/drm/i915/display/intel_display.c if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) && dev_priv 9318 drivers/gpu/drm/i915/display/intel_display.c static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) dev_priv 9323 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_encoder(&dev_priv->drm, encoder) { dev_priv 9348 drivers/gpu/drm/i915/display/intel_display.c dev_priv->pch_ssc_use = 0; dev_priv 9350 drivers/gpu/drm/i915/display/intel_display.c if (spll_uses_pch_ssc(dev_priv)) { dev_priv 9352 drivers/gpu/drm/i915/display/intel_display.c dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL); dev_priv 9355 drivers/gpu/drm/i915/display/intel_display.c if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) { dev_priv 9357 drivers/gpu/drm/i915/display/intel_display.c dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1); dev_priv 9360 drivers/gpu/drm/i915/display/intel_display.c if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) { dev_priv 9362 drivers/gpu/drm/i915/display/intel_display.c dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2); dev_priv 9365 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->pch_ssc_use) dev_priv 9369 drivers/gpu/drm/i915/display/intel_display.c lpt_bend_clkout_dp(dev_priv, 0); dev_priv 9370 drivers/gpu/drm/i915/display/intel_display.c lpt_enable_clkout_dp(dev_priv, true, true); dev_priv 9372 drivers/gpu/drm/i915/display/intel_display.c lpt_disable_clkout_dp(dev_priv); dev_priv 9379 drivers/gpu/drm/i915/display/intel_display.c void intel_init_pch_refclk(struct drm_i915_private *dev_priv) dev_priv 9381 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) dev_priv 9382 drivers/gpu/drm/i915/display/intel_display.c ironlake_init_pch_refclk(dev_priv); dev_priv 9383 drivers/gpu/drm/i915/display/intel_display.c else if (HAS_PCH_LPT(dev_priv)) dev_priv 9384 drivers/gpu/drm/i915/display/intel_display.c lpt_init_pch_refclk(dev_priv); dev_priv 9390 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 9434 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 9438 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv) && crtc_state->dither) dev_priv 9453 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 9485 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11 && dev_priv 9495 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 9535 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 9542 drivers/gpu/drm/i915/display/intel_display.c if ((intel_panel_use_ssc(dev_priv) && dev_priv 9543 drivers/gpu/drm/i915/display/intel_display.c dev_priv->vbt.lvds_ssc_freq == 100000) || dev_priv 9544 drivers/gpu/drm/i915/display/intel_display.c (HAS_PCH_IBX(dev_priv) && dev_priv 9545 drivers/gpu/drm/i915/display/intel_display.c intel_is_dual_link_lvds(dev_priv))) dev_priv 9596 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_INFO(dev_priv)->num_pipes == 3 && dev_priv 9621 drivers/gpu/drm/i915/display/intel_display.c intel_panel_use_ssc(dev_priv)) dev_priv 9636 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 9650 drivers/gpu/drm/i915/display/intel_display.c if (intel_panel_use_ssc(dev_priv)) { dev_priv 9652 drivers/gpu/drm/i915/display/intel_display.c dev_priv->vbt.lvds_ssc_freq); dev_priv 9653 drivers/gpu/drm/i915/display/intel_display.c refclk = dev_priv->vbt.lvds_ssc_freq; dev_priv 9656 drivers/gpu/drm/i915/display/intel_display.c if (intel_is_dual_link_lvds(dev_priv)) { dev_priv 9693 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 9710 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 9713 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 5) { dev_priv 9722 drivers/gpu/drm/i915/display/intel_display.c if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) { dev_priv 9764 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 9796 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 9823 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 9828 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { dev_priv 9885 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 10 && dev_priv 9922 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 9935 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 7)) { dev_priv 9946 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 9953 drivers/gpu/drm/i915/display/intel_display.c wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 10006 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_IBX(dev_priv)) { dev_priv 10021 drivers/gpu/drm/i915/display/intel_display.c intel_get_shared_dpll_by_id(dev_priv, pll_id); dev_priv 10024 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll, dev_priv 10045 drivers/gpu/drm/i915/display/intel_display.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 10052 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 10057 drivers/gpu/drm/i915/display/intel_display.c INTEL_GEN(dev_priv) >= 11) { dev_priv 10071 drivers/gpu/drm/i915/display/intel_display.c static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv, dev_priv 10084 drivers/gpu/drm/i915/display/intel_display.c pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); dev_priv 10087 drivers/gpu/drm/i915/display/intel_display.c static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv, dev_priv 10091 drivers/gpu/drm/i915/display/intel_display.c enum phy phy = intel_port_to_phy(dev_priv, port); dev_priv 10096 drivers/gpu/drm/i915/display/intel_display.c if (intel_phy_is_combo(dev_priv, phy)) { dev_priv 10101 drivers/gpu/drm/i915/display/intel_display.c } else if (intel_phy_is_tc(dev_priv, phy)) { dev_priv 10105 drivers/gpu/drm/i915/display/intel_display.c id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, dev_priv 10119 drivers/gpu/drm/i915/display/intel_display.c intel_get_shared_dpll_by_id(dev_priv, id); dev_priv 10124 drivers/gpu/drm/i915/display/intel_display.c static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, dev_priv 10145 drivers/gpu/drm/i915/display/intel_display.c pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); dev_priv 10148 drivers/gpu/drm/i915/display/intel_display.c static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, dev_priv 10161 drivers/gpu/drm/i915/display/intel_display.c pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); dev_priv 10164 drivers/gpu/drm/i915/display/intel_display.c static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, dev_priv 10197 drivers/gpu/drm/i915/display/intel_display.c pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); dev_priv 10206 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 10214 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 10218 drivers/gpu/drm/i915/display/intel_display.c if (HAS_TRANSCODER_EDP(dev_priv)) dev_priv 10233 drivers/gpu/drm/i915/display/intel_display.c ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) { dev_priv 10284 drivers/gpu/drm/i915/display/intel_display.c wf = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 10302 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 10318 drivers/gpu/drm/i915/display/intel_display.c wf = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 10332 drivers/gpu/drm/i915/display/intel_display.c if (!bxt_dsi_pll_is_enabled(dev_priv)) dev_priv 10354 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 10361 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 12) dev_priv 10366 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 10367 drivers/gpu/drm/i915/display/intel_display.c icelake_get_ddi_pll(dev_priv, port, pipe_config); dev_priv 10368 drivers/gpu/drm/i915/display/intel_display.c else if (IS_CANNONLAKE(dev_priv)) dev_priv 10369 drivers/gpu/drm/i915/display/intel_display.c cannonlake_get_ddi_pll(dev_priv, port, pipe_config); dev_priv 10370 drivers/gpu/drm/i915/display/intel_display.c else if (IS_GEN9_BC(dev_priv)) dev_priv 10371 drivers/gpu/drm/i915/display/intel_display.c skylake_get_ddi_pll(dev_priv, port, pipe_config); dev_priv 10372 drivers/gpu/drm/i915/display/intel_display.c else if (IS_GEN9_LP(dev_priv)) dev_priv 10373 drivers/gpu/drm/i915/display/intel_display.c bxt_get_ddi_pll(dev_priv, port, pipe_config); dev_priv 10375 drivers/gpu/drm/i915/display/intel_display.c haswell_get_ddi_pll(dev_priv, port, pipe_config); dev_priv 10379 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll, dev_priv 10388 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 9 && dev_priv 10403 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 10412 drivers/gpu/drm/i915/display/intel_display.c wf = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 10424 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN9_LP(dev_priv) && dev_priv 10435 drivers/gpu/drm/i915/display/intel_display.c INTEL_GEN(dev_priv) >= 11) { dev_priv 10447 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 10464 drivers/gpu/drm/i915/display/intel_display.c wf = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 10469 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 10476 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv)) dev_priv 10498 drivers/gpu/drm/i915/display/intel_display.c intel_display_power_put(dev_priv, dev_priv 10506 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = dev_priv 10512 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_INFO(dev_priv)->display.cursor_needs_physical) dev_priv 10520 drivers/gpu/drm/i915/display/intel_display.c if (HAS_GMCH(dev_priv) && dev_priv 10706 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 10723 drivers/gpu/drm/i915/display/intel_display.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 10744 drivers/gpu/drm/i915/display/intel_display.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 10756 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 10762 drivers/gpu/drm/i915/display/intel_display.c wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 10770 drivers/gpu/drm/i915/display/intel_display.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 10786 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 10789 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 10798 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) dev_priv 10807 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = dev_priv 10811 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) dev_priv 10837 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = dev_priv 10861 drivers/gpu/drm/i915/display/intel_display.c if (HAS_CUR_FBC(dev_priv) && dev_priv 10877 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 10917 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && dev_priv 10932 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 10948 drivers/gpu/drm/i915/display/intel_display.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 10970 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 10976 drivers/gpu/drm/i915/display/intel_display.c if (HAS_CUR_FBC(dev_priv)) dev_priv 10990 drivers/gpu/drm/i915/display/intel_display.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 11002 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 11014 drivers/gpu/drm/i915/display/intel_display.c wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 11022 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) dev_priv 11028 drivers/gpu/drm/i915/display/intel_display.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 11098 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 11225 drivers/gpu/drm/i915/display/intel_display.c intel_wait_for_vblank(dev_priv, intel_crtc->pipe); dev_priv 11270 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 11274 drivers/gpu/drm/i915/display/intel_display.c return dev_priv->vbt.lvds_ssc_freq; dev_priv 11275 drivers/gpu/drm/i915/display/intel_display.c else if (HAS_PCH_SPLIT(dev_priv)) dev_priv 11277 drivers/gpu/drm/i915/display/intel_display.c else if (!IS_GEN(dev_priv, 2)) dev_priv 11288 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 11302 drivers/gpu/drm/i915/display/intel_display.c if (IS_PINEVIEW(dev_priv)) { dev_priv 11310 drivers/gpu/drm/i915/display/intel_display.c if (!IS_GEN(dev_priv, 2)) { dev_priv 11311 drivers/gpu/drm/i915/display/intel_display.c if (IS_PINEVIEW(dev_priv)) dev_priv 11333 drivers/gpu/drm/i915/display/intel_display.c if (IS_PINEVIEW(dev_priv)) dev_priv 11338 drivers/gpu/drm/i915/display/intel_display.c u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); dev_priv 11395 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 11406 drivers/gpu/drm/i915/display/intel_display.c intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), dev_priv 11414 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 11423 drivers/gpu/drm/i915/display/intel_display.c crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 11437 drivers/gpu/drm/i915/display/intel_display.c if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) { dev_priv 11508 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 11516 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { dev_priv 11564 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) dev_priv 11571 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) dev_priv 11578 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { dev_priv 11622 drivers/gpu/drm/i915/display/intel_display.c (IS_GEN_RANGE(dev_priv, 5, 6) || dev_priv 11623 drivers/gpu/drm/i915/display/intel_display.c IS_IVYBRIDGE(dev_priv)) && dev_priv 11687 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 11693 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 11) dev_priv 11723 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { dev_priv 11770 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 11777 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) && dev_priv 11782 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_compute_clock && dev_priv 11784 drivers/gpu/drm/i915/display/intel_display.c ret = dev_priv->display.crtc_compute_clock(intel_crtc, dev_priv 11805 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->display.compute_pipe_wm) { dev_priv 11806 drivers/gpu/drm/i915/display/intel_display.c ret = dev_priv->display.compute_pipe_wm(pipe_config); dev_priv 11813 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->display.compute_intermediate_wm) { dev_priv 11814 drivers/gpu/drm/i915/display/intel_display.c if (WARN_ON(!dev_priv->display.compute_pipe_wm)) dev_priv 11822 drivers/gpu/drm/i915/display/intel_display.c ret = dev_priv->display.compute_intermediate_wm(pipe_config); dev_priv 11829 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 11839 drivers/gpu/drm/i915/display/intel_display.c ret = intel_atomic_setup_scalers(dev_priv, intel_crtc, dev_priv 11843 drivers/gpu/drm/i915/display/intel_display.c if (HAS_IPS(dev_priv)) dev_priv 11920 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 11926 drivers/gpu/drm/i915/display/intel_display.c if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || dev_priv 11927 drivers/gpu/drm/i915/display/intel_display.c IS_CHERRYVIEW(dev_priv))) dev_priv 11929 drivers/gpu/drm/i915/display/intel_display.c else if (INTEL_GEN(dev_priv) >= 5) dev_priv 11975 drivers/gpu/drm/i915/display/intel_display.c intel_dump_infoframe(struct drm_i915_private *dev_priv, dev_priv 11981 drivers/gpu/drm/i915/display/intel_display.c hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); dev_priv 12075 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 12121 drivers/gpu/drm/i915/display/intel_display.c intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); dev_priv 12124 drivers/gpu/drm/i915/display/intel_display.c intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); dev_priv 12127 drivers/gpu/drm/i915/display/intel_display.c intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); dev_priv 12139 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 12145 drivers/gpu/drm/i915/display/intel_display.c if (HAS_GMCH(dev_priv)) dev_priv 12160 drivers/gpu/drm/i915/display/intel_display.c intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); dev_priv 12241 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = dev_priv 12260 drivers/gpu/drm/i915/display/intel_display.c if (IS_G4X(dev_priv) || dev_priv 12261 drivers/gpu/drm/i915/display/intel_display.c IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 12479 drivers/gpu/drm/i915/display/intel_display.c pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, dev_priv 12490 drivers/gpu/drm/i915/display/intel_display.c hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); dev_priv 12492 drivers/gpu/drm/i915/display/intel_display.c hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); dev_priv 12496 drivers/gpu/drm/i915/display/intel_display.c hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); dev_priv 12498 drivers/gpu/drm/i915/display/intel_display.c hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); dev_priv 12520 drivers/gpu/drm/i915/display/intel_display.c static bool fastboot_enabled(struct drm_i915_private *dev_priv) dev_priv 12526 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 12530 drivers/gpu/drm/i915/display/intel_display.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 12542 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(current_config->base.crtc->dev); dev_priv 12548 drivers/gpu/drm/i915/display/intel_display.c if (fixup_inherited && !fastboot_enabled(dev_priv)) { dev_priv 12688 drivers/gpu/drm/i915/display/intel_display.c pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ dev_priv 12707 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 8) { dev_priv 12734 drivers/gpu/drm/i915/display/intel_display.c if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || dev_priv 12735 drivers/gpu/drm/i915/display/intel_display.c IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 12760 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 4) dev_priv 12784 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 12830 drivers/gpu/drm/i915/display/intel_display.c if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) dev_priv 12857 drivers/gpu/drm/i915/display/intel_display.c static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, dev_priv 12861 drivers/gpu/drm/i915/display/intel_display.c int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), dev_priv 12878 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 12889 drivers/gpu/drm/i915/display/intel_display.c int plane, level, max_level = ilk_wm_max_level(dev_priv); dev_priv 12891 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active) dev_priv 12903 drivers/gpu/drm/i915/display/intel_display.c skl_ddb_get_hw_state(dev_priv, &hw->ddb); dev_priv 12904 drivers/gpu/drm/i915/display/intel_display.c sw_ddb = &dev_priv->wm.skl_hw.ddb; dev_priv 12906 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11 && dev_priv 12913 drivers/gpu/drm/i915/display/intel_display.c for_each_universal_plane(dev_priv, pipe, plane) { dev_priv 13040 drivers/gpu/drm/i915/display/intel_display.c verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state) dev_priv 13047 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_encoder(&dev_priv->drm, encoder) { dev_priv 13094 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 13109 drivers/gpu/drm/i915/display/intel_display.c active = dev_priv->display.get_pipe_config(crtc, pipe_config); dev_priv 13112 drivers/gpu/drm/i915/display/intel_display.c if (IS_I830(dev_priv)) dev_priv 13144 drivers/gpu/drm/i915/display/intel_display.c intel_pipe_config_sanity_check(dev_priv, pipe_config); dev_priv 13168 drivers/gpu/drm/i915/display/intel_display.c verify_single_dpll_state(struct drm_i915_private *dev_priv, dev_priv 13181 drivers/gpu/drm/i915/display/intel_display.c active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state); dev_priv 13227 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 13230 drivers/gpu/drm/i915/display/intel_display.c verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); dev_priv 13262 drivers/gpu/drm/i915/display/intel_display.c verify_disabled_dpll_state(struct drm_i915_private *dev_priv) dev_priv 13266 drivers/gpu/drm/i915/display/intel_display.c for (i = 0; i < dev_priv->num_shared_dpll; i++) dev_priv 13267 drivers/gpu/drm/i915/display/intel_display.c verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); dev_priv 13271 drivers/gpu/drm/i915/display/intel_display.c intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, dev_priv 13274 drivers/gpu/drm/i915/display/intel_display.c verify_encoder_state(dev_priv, state); dev_priv 13276 drivers/gpu/drm/i915/display/intel_display.c verify_disabled_dpll_state(dev_priv); dev_priv 13282 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 13311 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 2)) { dev_priv 13320 drivers/gpu/drm/i915/display/intel_display.c } else if (HAS_DDI(dev_priv) && dev_priv 13329 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 13334 drivers/gpu/drm/i915/display/intel_display.c if (!dev_priv->display.crtc_compute_clock) dev_priv 13408 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 13412 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 13425 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 13432 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 13461 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 13473 drivers/gpu/drm/i915/display/intel_display.c state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk; dev_priv 13476 drivers/gpu/drm/i915/display/intel_display.c state->active_crtcs = dev_priv->active_crtcs; dev_priv 13477 drivers/gpu/drm/i915/display/intel_display.c state->cdclk.logical = dev_priv->cdclk.logical; dev_priv 13478 drivers/gpu/drm/i915/display/intel_display.c state->cdclk.actual = dev_priv->cdclk.actual; dev_priv 13499 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->display.modeset_calc_cdclk) { dev_priv 13502 drivers/gpu/drm/i915/display/intel_display.c ret = dev_priv->display.modeset_calc_cdclk(state); dev_priv 13511 drivers/gpu/drm/i915/display/intel_display.c if (intel_cdclk_changed(&dev_priv->cdclk.logical, dev_priv 13523 drivers/gpu/drm/i915/display/intel_display.c crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 13533 drivers/gpu/drm/i915/display/intel_display.c intel_cdclk_needs_cd2x_update(dev_priv, dev_priv 13534 drivers/gpu/drm/i915/display/intel_display.c &dev_priv->cdclk.actual, dev_priv 13541 drivers/gpu/drm/i915/display/intel_display.c } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual, dev_priv 13560 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv)) dev_priv 13574 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 13577 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->display.compute_global_watermarks) dev_priv 13578 drivers/gpu/drm/i915/display/intel_display.c return dev_priv->display.compute_global_watermarks(state); dev_priv 13614 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 13662 drivers/gpu/drm/i915/display/intel_display.c state->cdclk.logical = dev_priv->cdclk.logical; dev_priv 13673 drivers/gpu/drm/i915/display/intel_display.c intel_fbc_choose_crtc(dev_priv, state); dev_priv 13733 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 13741 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_enable(new_crtc_state, state); dev_priv 13764 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 13789 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 13796 drivers/gpu/drm/i915/display/intel_display.c u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; dev_priv 13806 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices) dev_priv 13807 drivers/gpu/drm/i915/display/intel_display.c icl_dbuf_slices_update(dev_priv, required_slices); dev_priv 13829 drivers/gpu/drm/i915/display/intel_display.c INTEL_INFO(dev_priv)->num_pipes, i)) dev_priv 13851 drivers/gpu/drm/i915/display/intel_display.c intel_wait_for_vblank(dev_priv, pipe); dev_priv 13858 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices) dev_priv 13859 drivers/gpu/drm/i915/display/intel_display.c icl_dbuf_slices_update(dev_priv, required_slices); dev_priv 13862 drivers/gpu/drm/i915/display/intel_display.c static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) dev_priv 13867 drivers/gpu/drm/i915/display/intel_display.c freed = llist_del_all(&dev_priv->atomic_helper.free_list); dev_priv 13874 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = dev_priv 13875 drivers/gpu/drm/i915/display/intel_display.c container_of(work, typeof(*dev_priv), atomic_helper.free_work); dev_priv 13877 drivers/gpu/drm/i915/display/intel_display.c intel_atomic_helper_free_state(dev_priv); dev_priv 13883 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); dev_priv 13890 drivers/gpu/drm/i915/display/intel_display.c prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags, dev_priv 13896 drivers/gpu/drm/i915/display/intel_display.c test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags)) dev_priv 13902 drivers/gpu/drm/i915/display/intel_display.c finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags, dev_priv 13923 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 13935 drivers/gpu/drm/i915/display/intel_display.c wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); dev_priv 13959 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_disable(old_crtc_state, state); dev_priv 13968 drivers/gpu/drm/i915/display/intel_display.c intel_check_cpu_fifo_underruns(dev_priv); dev_priv 13969 drivers/gpu/drm/i915/display/intel_display.c intel_check_pch_fifo_underruns(dev_priv); dev_priv 13973 drivers/gpu/drm/i915/display/intel_display.c !HAS_GMCH(dev_priv) && dev_priv 13974 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.initial_watermarks) dev_priv 13975 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.initial_watermarks(state, dev_priv 13987 drivers/gpu/drm/i915/display/intel_display.c intel_set_cdclk_pre_plane_update(dev_priv, dev_priv 13989 drivers/gpu/drm/i915/display/intel_display.c &dev_priv->cdclk.actual, dev_priv 13997 drivers/gpu/drm/i915/display/intel_display.c intel_disable_sagv(dev_priv); dev_priv 13999 drivers/gpu/drm/i915/display/intel_display.c intel_modeset_verify_disabled(dev_priv, state); dev_priv 14020 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.update_crtcs(state); dev_priv 14025 drivers/gpu/drm/i915/display/intel_display.c intel_set_cdclk_post_plane_update(dev_priv, dev_priv 14027 drivers/gpu/drm/i915/display/intel_display.c &dev_priv->cdclk.actual, dev_priv 14059 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->display.optimize_watermarks) dev_priv 14060 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.optimize_watermarks(state, dev_priv 14068 drivers/gpu/drm/i915/display/intel_display.c modeset_put_power_domains(dev_priv, put_domains[i]); dev_priv 14077 drivers/gpu/drm/i915/display/intel_display.c intel_enable_sagv(dev_priv); dev_priv 14088 drivers/gpu/drm/i915/display/intel_display.c intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); dev_priv 14089 drivers/gpu/drm/i915/display/intel_display.c intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); dev_priv 14091 drivers/gpu/drm/i915/display/intel_display.c intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); dev_priv 14156 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 14159 drivers/gpu/drm/i915/display/intel_display.c state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 14182 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) { dev_priv 14197 drivers/gpu/drm/i915/display/intel_display.c intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); dev_priv 14209 drivers/gpu/drm/i915/display/intel_display.c intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); dev_priv 14212 drivers/gpu/drm/i915/display/intel_display.c dev_priv->wm.distrust_bios_wm = false; dev_priv 14217 drivers/gpu/drm/i915/display/intel_display.c memcpy(dev_priv->min_cdclk, state->min_cdclk, dev_priv 14219 drivers/gpu/drm/i915/display/intel_display.c memcpy(dev_priv->min_voltage_level, state->min_voltage_level, dev_priv 14221 drivers/gpu/drm/i915/display/intel_display.c dev_priv->active_crtcs = state->active_crtcs; dev_priv 14222 drivers/gpu/drm/i915/display/intel_display.c dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk; dev_priv 14232 drivers/gpu/drm/i915/display/intel_display.c queue_work(dev_priv->modeset_wq, &state->base.commit_work); dev_priv 14237 drivers/gpu/drm/i915/display/intel_display.c flush_workqueue(dev_priv->modeset_wq); dev_priv 14305 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 14310 drivers/gpu/drm/i915/display/intel_display.c INTEL_INFO(dev_priv)->display.cursor_needs_physical) { dev_priv 14312 drivers/gpu/drm/i915/display/intel_display.c const int align = intel_cursor_alignment(dev_priv); dev_priv 14370 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->dev); dev_priv 14418 drivers/gpu/drm/i915/display/intel_display.c ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); dev_priv 14426 drivers/gpu/drm/i915/display/intel_display.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 14462 drivers/gpu/drm/i915/display/intel_display.c intel_rps_mark_interactive(dev_priv, true); dev_priv 14484 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->dev); dev_priv 14487 drivers/gpu/drm/i915/display/intel_display.c intel_rps_mark_interactive(dev_priv, false); dev_priv 14492 drivers/gpu/drm/i915/display/intel_display.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 14494 drivers/gpu/drm/i915/display/intel_display.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 14502 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 14512 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) dev_priv 14535 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 14554 drivers/gpu/drm/i915/display/intel_display.c else if (INTEL_GEN(dev_priv) >= 9) dev_priv 14557 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) dev_priv 14561 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->display.atomic_update_watermarks) dev_priv 14562 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.atomic_update_watermarks(state, dev_priv 14569 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 14571 drivers/gpu/drm/i915/display/intel_display.c if (!IS_GEN(dev_priv, 2)) dev_priv 14572 drivers/gpu/drm/i915/display/intel_display.c intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); dev_priv 14578 drivers/gpu/drm/i915/display/intel_display.c intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); dev_priv 14694 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 14760 drivers/gpu/drm/i915/display/intel_display.c ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); dev_priv 14797 drivers/gpu/drm/i915/display/intel_display.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 14822 drivers/gpu/drm/i915/display/intel_display.c static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, dev_priv 14825 drivers/gpu/drm/i915/display/intel_display.c if (!HAS_FBC(dev_priv)) dev_priv 14828 drivers/gpu/drm/i915/display/intel_display.c if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) dev_priv 14830 drivers/gpu/drm/i915/display/intel_display.c else if (IS_IVYBRIDGE(dev_priv)) dev_priv 14833 drivers/gpu/drm/i915/display/intel_display.c else if (INTEL_GEN(dev_priv) >= 4) dev_priv 14840 drivers/gpu/drm/i915/display/intel_display.c intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv 14851 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 14852 drivers/gpu/drm/i915/display/intel_display.c return skl_universal_plane_create(dev_priv, pipe, dev_priv 14864 drivers/gpu/drm/i915/display/intel_display.c if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) dev_priv 14871 drivers/gpu/drm/i915/display/intel_display.c plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane); dev_priv 14873 drivers/gpu/drm/i915/display/intel_display.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 14878 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) { dev_priv 14906 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) dev_priv 14907 drivers/gpu/drm/i915/display/intel_display.c ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, dev_priv 14913 drivers/gpu/drm/i915/display/intel_display.c ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, dev_priv 14922 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { dev_priv 14926 drivers/gpu/drm/i915/display/intel_display.c } else if (INTEL_GEN(dev_priv) >= 4) { dev_priv 14933 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 14949 drivers/gpu/drm/i915/display/intel_display.c intel_cursor_plane_create(struct drm_i915_private *dev_priv, dev_priv 14965 drivers/gpu/drm/i915/display/intel_display.c if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { dev_priv 14982 drivers/gpu/drm/i915/display/intel_display.c if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) dev_priv 14987 drivers/gpu/drm/i915/display/intel_display.c ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, dev_priv 14997 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 15018 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 15021 drivers/gpu/drm/i915/display/intel_display.c crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe]; dev_priv 15102 drivers/gpu/drm/i915/display/intel_display.c static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv 15123 drivers/gpu/drm/i915/display/intel_display.c primary = intel_primary_plane_create(dev_priv, pipe); dev_priv 15130 drivers/gpu/drm/i915/display/intel_display.c for_each_sprite(dev_priv, pipe, sprite) { dev_priv 15133 drivers/gpu/drm/i915/display/intel_display.c plane = intel_sprite_plane_create(dev_priv, pipe, sprite); dev_priv 15141 drivers/gpu/drm/i915/display/intel_display.c cursor = intel_cursor_plane_create(dev_priv, pipe); dev_priv 15148 drivers/gpu/drm/i915/display/intel_display.c if (HAS_GMCH(dev_priv)) { dev_priv 15149 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv) || dev_priv 15150 drivers/gpu/drm/i915/display/intel_display.c IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv)) dev_priv 15152 drivers/gpu/drm/i915/display/intel_display.c else if (IS_GEN(dev_priv, 4)) dev_priv 15154 drivers/gpu/drm/i915/display/intel_display.c else if (IS_I945GM(dev_priv)) dev_priv 15156 drivers/gpu/drm/i915/display/intel_display.c else if (IS_GEN(dev_priv, 3)) dev_priv 15161 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 15167 drivers/gpu/drm/i915/display/intel_display.c ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, dev_priv 15178 drivers/gpu/drm/i915/display/intel_display.c BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) || dev_priv 15179 drivers/gpu/drm/i915/display/intel_display.c dev_priv->pipe_to_crtc_mapping[pipe] != NULL); dev_priv 15180 drivers/gpu/drm/i915/display/intel_display.c dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc; dev_priv 15182 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 9) { dev_priv 15185 drivers/gpu/drm/i915/display/intel_display.c BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || dev_priv 15186 drivers/gpu/drm/i915/display/intel_display.c dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL); dev_priv 15187 drivers/gpu/drm/i915/display/intel_display.c dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc; dev_priv 15243 drivers/gpu/drm/i915/display/intel_display.c static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) dev_priv 15245 drivers/gpu/drm/i915/display/intel_display.c if (!IS_MOBILE(dev_priv)) dev_priv 15251 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) dev_priv 15257 drivers/gpu/drm/i915/display/intel_display.c static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) dev_priv 15259 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 15262 drivers/gpu/drm/i915/display/intel_display.c if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) dev_priv 15265 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_LPT_H(dev_priv) && dev_priv 15273 drivers/gpu/drm/i915/display/intel_display.c if (!dev_priv->vbt.int_crt_support) dev_priv 15279 drivers/gpu/drm/i915/display/intel_display.c void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) dev_priv 15284 drivers/gpu/drm/i915/display/intel_display.c if (HAS_DDI(dev_priv)) dev_priv 15290 drivers/gpu/drm/i915/display/intel_display.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 15303 drivers/gpu/drm/i915/display/intel_display.c static void intel_pps_init(struct drm_i915_private *dev_priv) dev_priv 15305 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) dev_priv 15306 drivers/gpu/drm/i915/display/intel_display.c dev_priv->pps_mmio_base = PCH_PPS_BASE; dev_priv 15307 drivers/gpu/drm/i915/display/intel_display.c else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 15308 drivers/gpu/drm/i915/display/intel_display.c dev_priv->pps_mmio_base = VLV_PPS_BASE; dev_priv 15310 drivers/gpu/drm/i915/display/intel_display.c dev_priv->pps_mmio_base = PPS_BASE; dev_priv 15312 drivers/gpu/drm/i915/display/intel_display.c intel_pps_unlock_regs_wa(dev_priv); dev_priv 15315 drivers/gpu/drm/i915/display/intel_display.c static void intel_setup_outputs(struct drm_i915_private *dev_priv) dev_priv 15320 drivers/gpu/drm/i915/display/intel_display.c intel_pps_init(dev_priv); dev_priv 15322 drivers/gpu/drm/i915/display/intel_display.c if (!HAS_DISPLAY(dev_priv)) dev_priv 15325 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 12) { dev_priv 15327 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_A); dev_priv 15328 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_B); dev_priv 15329 drivers/gpu/drm/i915/display/intel_display.c icl_dsi_init(dev_priv); dev_priv 15330 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_ELKHARTLAKE(dev_priv)) { dev_priv 15331 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_A); dev_priv 15332 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_B); dev_priv 15333 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_C); dev_priv 15334 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_D); dev_priv 15335 drivers/gpu/drm/i915/display/intel_display.c icl_dsi_init(dev_priv); dev_priv 15336 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_GEN(dev_priv, 11)) { dev_priv 15337 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_A); dev_priv 15338 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_B); dev_priv 15339 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_C); dev_priv 15340 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_D); dev_priv 15341 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_E); dev_priv 15347 drivers/gpu/drm/i915/display/intel_display.c if (IS_ICL_WITH_PORT_F(dev_priv) && dev_priv 15348 drivers/gpu/drm/i915/display/intel_display.c intel_bios_is_port_present(dev_priv, PORT_F)) dev_priv 15349 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_F); dev_priv 15351 drivers/gpu/drm/i915/display/intel_display.c icl_dsi_init(dev_priv); dev_priv 15352 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_GEN9_LP(dev_priv)) { dev_priv 15358 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_A); dev_priv 15359 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_B); dev_priv 15360 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_C); dev_priv 15362 drivers/gpu/drm/i915/display/intel_display.c vlv_dsi_init(dev_priv); dev_priv 15363 drivers/gpu/drm/i915/display/intel_display.c } else if (HAS_DDI(dev_priv)) { dev_priv 15366 drivers/gpu/drm/i915/display/intel_display.c if (intel_ddi_crt_present(dev_priv)) dev_priv 15367 drivers/gpu/drm/i915/display/intel_display.c intel_crt_init(dev_priv); dev_priv 15376 drivers/gpu/drm/i915/display/intel_display.c if (found || IS_GEN9_BC(dev_priv)) dev_priv 15377 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_A); dev_priv 15384 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_B); dev_priv 15386 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_C); dev_priv 15388 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_D); dev_priv 15390 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_F); dev_priv 15394 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN9_BC(dev_priv) && dev_priv 15395 drivers/gpu/drm/i915/display/intel_display.c intel_bios_is_port_present(dev_priv, PORT_E)) dev_priv 15396 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_init(dev_priv, PORT_E); dev_priv 15398 drivers/gpu/drm/i915/display/intel_display.c } else if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 15406 drivers/gpu/drm/i915/display/intel_display.c intel_lvds_init(dev_priv); dev_priv 15407 drivers/gpu/drm/i915/display/intel_display.c intel_crt_init(dev_priv); dev_priv 15409 drivers/gpu/drm/i915/display/intel_display.c dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); dev_priv 15411 drivers/gpu/drm/i915/display/intel_display.c if (ilk_has_edp_a(dev_priv)) dev_priv 15412 drivers/gpu/drm/i915/display/intel_display.c intel_dp_init(dev_priv, DP_A, PORT_A); dev_priv 15416 drivers/gpu/drm/i915/display/intel_display.c found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); dev_priv 15418 drivers/gpu/drm/i915/display/intel_display.c intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); dev_priv 15420 drivers/gpu/drm/i915/display/intel_display.c intel_dp_init(dev_priv, PCH_DP_B, PORT_B); dev_priv 15424 drivers/gpu/drm/i915/display/intel_display.c intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); dev_priv 15427 drivers/gpu/drm/i915/display/intel_display.c intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); dev_priv 15430 drivers/gpu/drm/i915/display/intel_display.c intel_dp_init(dev_priv, PCH_DP_C, PORT_C); dev_priv 15433 drivers/gpu/drm/i915/display/intel_display.c intel_dp_init(dev_priv, PCH_DP_D, PORT_D); dev_priv 15434 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 15437 drivers/gpu/drm/i915/display/intel_display.c if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support) dev_priv 15438 drivers/gpu/drm/i915/display/intel_display.c intel_crt_init(dev_priv); dev_priv 15455 drivers/gpu/drm/i915/display/intel_display.c has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); dev_priv 15456 drivers/gpu/drm/i915/display/intel_display.c has_port = intel_bios_is_port_present(dev_priv, PORT_B); dev_priv 15458 drivers/gpu/drm/i915/display/intel_display.c has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); dev_priv 15460 drivers/gpu/drm/i915/display/intel_display.c intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); dev_priv 15462 drivers/gpu/drm/i915/display/intel_display.c has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); dev_priv 15463 drivers/gpu/drm/i915/display/intel_display.c has_port = intel_bios_is_port_present(dev_priv, PORT_C); dev_priv 15465 drivers/gpu/drm/i915/display/intel_display.c has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); dev_priv 15467 drivers/gpu/drm/i915/display/intel_display.c intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); dev_priv 15469 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 15474 drivers/gpu/drm/i915/display/intel_display.c has_port = intel_bios_is_port_present(dev_priv, PORT_D); dev_priv 15476 drivers/gpu/drm/i915/display/intel_display.c intel_dp_init(dev_priv, CHV_DP_D, PORT_D); dev_priv 15478 drivers/gpu/drm/i915/display/intel_display.c intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); dev_priv 15481 drivers/gpu/drm/i915/display/intel_display.c vlv_dsi_init(dev_priv); dev_priv 15482 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_PINEVIEW(dev_priv)) { dev_priv 15483 drivers/gpu/drm/i915/display/intel_display.c intel_lvds_init(dev_priv); dev_priv 15484 drivers/gpu/drm/i915/display/intel_display.c intel_crt_init(dev_priv); dev_priv 15485 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_GEN_RANGE(dev_priv, 3, 4)) { dev_priv 15488 drivers/gpu/drm/i915/display/intel_display.c if (IS_MOBILE(dev_priv)) dev_priv 15489 drivers/gpu/drm/i915/display/intel_display.c intel_lvds_init(dev_priv); dev_priv 15491 drivers/gpu/drm/i915/display/intel_display.c intel_crt_init(dev_priv); dev_priv 15495 drivers/gpu/drm/i915/display/intel_display.c found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); dev_priv 15496 drivers/gpu/drm/i915/display/intel_display.c if (!found && IS_G4X(dev_priv)) { dev_priv 15498 drivers/gpu/drm/i915/display/intel_display.c intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); dev_priv 15501 drivers/gpu/drm/i915/display/intel_display.c if (!found && IS_G4X(dev_priv)) dev_priv 15502 drivers/gpu/drm/i915/display/intel_display.c intel_dp_init(dev_priv, DP_B, PORT_B); dev_priv 15509 drivers/gpu/drm/i915/display/intel_display.c found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); dev_priv 15514 drivers/gpu/drm/i915/display/intel_display.c if (IS_G4X(dev_priv)) { dev_priv 15516 drivers/gpu/drm/i915/display/intel_display.c intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); dev_priv 15518 drivers/gpu/drm/i915/display/intel_display.c if (IS_G4X(dev_priv)) dev_priv 15519 drivers/gpu/drm/i915/display/intel_display.c intel_dp_init(dev_priv, DP_C, PORT_C); dev_priv 15522 drivers/gpu/drm/i915/display/intel_display.c if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) dev_priv 15523 drivers/gpu/drm/i915/display/intel_display.c intel_dp_init(dev_priv, DP_D, PORT_D); dev_priv 15525 drivers/gpu/drm/i915/display/intel_display.c if (SUPPORTS_TV(dev_priv)) dev_priv 15526 drivers/gpu/drm/i915/display/intel_display.c intel_tv_init(dev_priv); dev_priv 15527 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_GEN(dev_priv, 2)) { dev_priv 15528 drivers/gpu/drm/i915/display/intel_display.c if (IS_I85X(dev_priv)) dev_priv 15529 drivers/gpu/drm/i915/display/intel_display.c intel_lvds_init(dev_priv); dev_priv 15531 drivers/gpu/drm/i915/display/intel_display.c intel_crt_init(dev_priv); dev_priv 15532 drivers/gpu/drm/i915/display/intel_display.c intel_dvo_init(dev_priv); dev_priv 15535 drivers/gpu/drm/i915/display/intel_display.c intel_psr_init(dev_priv); dev_priv 15537 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_encoder(&dev_priv->drm, encoder) { dev_priv 15543 drivers/gpu/drm/i915/display/intel_display.c intel_init_pch_refclk(dev_priv); dev_priv 15545 drivers/gpu/drm/i915/display/intel_display.c drm_helper_move_panel_connectors_to_head(&dev_priv->drm); dev_priv 15596 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); dev_priv 15631 drivers/gpu/drm/i915/display/intel_display.c if (!drm_any_plane_has_format(&dev_priv->drm, dev_priv 15647 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 4 && dev_priv 15653 drivers/gpu/drm/i915/display/intel_display.c max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format, dev_priv 15677 drivers/gpu/drm/i915/display/intel_display.c drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); dev_priv 15698 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 && dev_priv 15711 drivers/gpu/drm/i915/display/intel_display.c ret = intel_fill_fb_info(dev_priv, fb); dev_priv 15715 drivers/gpu/drm/i915/display/intel_display.c ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); dev_priv 15762 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 15795 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9 || dev_priv 15796 drivers/gpu/drm/i915/display/intel_display.c IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { dev_priv 15801 drivers/gpu/drm/i915/display/intel_display.c } else if (INTEL_GEN(dev_priv) >= 3) { dev_priv 15844 drivers/gpu/drm/i915/display/intel_display.c void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv 15846 drivers/gpu/drm/i915/display/intel_display.c intel_init_cdclk_hooks(dev_priv); dev_priv 15848 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 15849 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_pipe_config = haswell_get_pipe_config; dev_priv 15850 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_initial_plane_config = dev_priv 15852 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_compute_clock = dev_priv 15854 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_enable = haswell_crtc_enable; dev_priv 15855 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_disable = haswell_crtc_disable; dev_priv 15856 drivers/gpu/drm/i915/display/intel_display.c } else if (HAS_DDI(dev_priv)) { dev_priv 15857 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_pipe_config = haswell_get_pipe_config; dev_priv 15858 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_initial_plane_config = dev_priv 15860 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_compute_clock = dev_priv 15862 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_enable = haswell_crtc_enable; dev_priv 15863 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_disable = haswell_crtc_disable; dev_priv 15864 drivers/gpu/drm/i915/display/intel_display.c } else if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 15865 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_pipe_config = ironlake_get_pipe_config; dev_priv 15866 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_initial_plane_config = dev_priv 15868 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_compute_clock = dev_priv 15870 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_enable = ironlake_crtc_enable; dev_priv 15871 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_disable = ironlake_crtc_disable; dev_priv 15872 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_CHERRYVIEW(dev_priv)) { dev_priv 15873 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_pipe_config = i9xx_get_pipe_config; dev_priv 15874 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_initial_plane_config = dev_priv 15876 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; dev_priv 15877 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_enable = valleyview_crtc_enable; dev_priv 15878 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_disable = i9xx_crtc_disable; dev_priv 15879 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_VALLEYVIEW(dev_priv)) { dev_priv 15880 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_pipe_config = i9xx_get_pipe_config; dev_priv 15881 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_initial_plane_config = dev_priv 15883 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; dev_priv 15884 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_enable = valleyview_crtc_enable; dev_priv 15885 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_disable = i9xx_crtc_disable; dev_priv 15886 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_G4X(dev_priv)) { dev_priv 15887 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_pipe_config = i9xx_get_pipe_config; dev_priv 15888 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_initial_plane_config = dev_priv 15890 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; dev_priv 15891 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_enable = i9xx_crtc_enable; dev_priv 15892 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_disable = i9xx_crtc_disable; dev_priv 15893 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_PINEVIEW(dev_priv)) { dev_priv 15894 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_pipe_config = i9xx_get_pipe_config; dev_priv 15895 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_initial_plane_config = dev_priv 15897 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; dev_priv 15898 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_enable = i9xx_crtc_enable; dev_priv 15899 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_disable = i9xx_crtc_disable; dev_priv 15900 drivers/gpu/drm/i915/display/intel_display.c } else if (!IS_GEN(dev_priv, 2)) { dev_priv 15901 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_pipe_config = i9xx_get_pipe_config; dev_priv 15902 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_initial_plane_config = dev_priv 15904 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; dev_priv 15905 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_enable = i9xx_crtc_enable; dev_priv 15906 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_disable = i9xx_crtc_disable; dev_priv 15908 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_pipe_config = i9xx_get_pipe_config; dev_priv 15909 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_initial_plane_config = dev_priv 15911 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; dev_priv 15912 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_enable = i9xx_crtc_enable; dev_priv 15913 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_disable = i9xx_crtc_disable; dev_priv 15916 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 5)) { dev_priv 15917 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.fdi_link_train = ironlake_fdi_link_train; dev_priv 15918 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_GEN(dev_priv, 6)) { dev_priv 15919 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.fdi_link_train = gen6_fdi_link_train; dev_priv 15920 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_IVYBRIDGE(dev_priv)) { dev_priv 15922 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; dev_priv 15923 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { dev_priv 15924 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.fdi_link_train = hsw_fdi_link_train; dev_priv 15927 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 15928 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.update_crtcs = skl_update_crtcs; dev_priv 15930 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.update_crtcs = intel_update_crtcs; dev_priv 15933 drivers/gpu/drm/i915/display/intel_display.c static i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) dev_priv 15935 drivers/gpu/drm/i915/display/intel_display.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 15937 drivers/gpu/drm/i915/display/intel_display.c else if (INTEL_GEN(dev_priv) >= 5) dev_priv 15944 drivers/gpu/drm/i915/display/intel_display.c static void i915_disable_vga(struct drm_i915_private *dev_priv) dev_priv 15946 drivers/gpu/drm/i915/display/intel_display.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 15948 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); dev_priv 15964 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 15966 drivers/gpu/drm/i915/display/intel_display.c intel_update_cdclk(dev_priv); dev_priv 15967 drivers/gpu/drm/i915/display/intel_display.c intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); dev_priv 15968 drivers/gpu/drm/i915/display/intel_display.c dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw; dev_priv 15983 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 15993 drivers/gpu/drm/i915/display/intel_display.c if (!dev_priv->display.optimize_watermarks) dev_priv 16021 drivers/gpu/drm/i915/display/intel_display.c if (!HAS_GMCH(dev_priv)) dev_priv 16044 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.optimize_watermarks(intel_state, crtc_state); dev_priv 16056 drivers/gpu/drm/i915/display/intel_display.c static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv) dev_priv 16058 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 5)) { dev_priv 16062 drivers/gpu/drm/i915/display/intel_display.c dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000; dev_priv 16063 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) { dev_priv 16064 drivers/gpu/drm/i915/display/intel_display.c dev_priv->fdi_pll_freq = 270000; dev_priv 16069 drivers/gpu/drm/i915/display/intel_display.c DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq); dev_priv 16130 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 16135 drivers/gpu/drm/i915/display/intel_display.c dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); dev_priv 16139 drivers/gpu/drm/i915/display/intel_display.c ret = intel_bw_init(dev_priv); dev_priv 16153 drivers/gpu/drm/i915/display/intel_display.c init_llist_head(&dev_priv->atomic_helper.free_list); dev_priv 16154 drivers/gpu/drm/i915/display/intel_display.c INIT_WORK(&dev_priv->atomic_helper.free_work, dev_priv 16157 drivers/gpu/drm/i915/display/intel_display.c intel_init_quirks(dev_priv); dev_priv 16159 drivers/gpu/drm/i915/display/intel_display.c intel_fbc_init(dev_priv); dev_priv 16161 drivers/gpu/drm/i915/display/intel_display.c intel_init_pm(dev_priv); dev_priv 16169 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { dev_priv 16173 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { dev_priv 16176 drivers/gpu/drm/i915/display/intel_display.c dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); dev_priv 16177 drivers/gpu/drm/i915/display/intel_display.c dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; dev_priv 16185 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 7) { dev_priv 16188 drivers/gpu/drm/i915/display/intel_display.c } else if (INTEL_GEN(dev_priv) >= 4) { dev_priv 16191 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_GEN(dev_priv, 3)) { dev_priv 16199 drivers/gpu/drm/i915/display/intel_display.c if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { dev_priv 16200 drivers/gpu/drm/i915/display/intel_display.c dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; dev_priv 16202 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_GEN(dev_priv, 2)) { dev_priv 16211 drivers/gpu/drm/i915/display/intel_display.c INTEL_INFO(dev_priv)->num_pipes, dev_priv 16212 drivers/gpu/drm/i915/display/intel_display.c INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); dev_priv 16214 drivers/gpu/drm/i915/display/intel_display.c for_each_pipe(dev_priv, pipe) { dev_priv 16215 drivers/gpu/drm/i915/display/intel_display.c ret = intel_crtc_init(dev_priv, pipe); dev_priv 16223 drivers/gpu/drm/i915/display/intel_display.c intel_update_fdi_pll_freq(dev_priv); dev_priv 16225 drivers/gpu/drm/i915/display/intel_display.c intel_update_czclk(dev_priv); dev_priv 16228 drivers/gpu/drm/i915/display/intel_display.c intel_hdcp_component_init(dev_priv); dev_priv 16230 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->max_cdclk_freq == 0) dev_priv 16231 drivers/gpu/drm/i915/display/intel_display.c intel_update_max_cdclk(dev_priv); dev_priv 16234 drivers/gpu/drm/i915/display/intel_display.c i915_disable_vga(dev_priv); dev_priv 16235 drivers/gpu/drm/i915/display/intel_display.c intel_setup_outputs(dev_priv); dev_priv 16254 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_initial_plane_config(crtc, dev_priv 16269 drivers/gpu/drm/i915/display/intel_display.c if (!HAS_GMCH(dev_priv)) dev_priv 16285 drivers/gpu/drm/i915/display/intel_display.c void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv 16287 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 16355 drivers/gpu/drm/i915/display/intel_display.c void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv 16357 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 16378 drivers/gpu/drm/i915/display/intel_display.c intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) dev_priv 16382 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 16385 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 16400 drivers/gpu/drm/i915/display/intel_display.c plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 16427 drivers/gpu/drm/i915/display/intel_display.c static bool has_pch_trancoder(struct drm_i915_private *dev_priv, dev_priv 16430 drivers/gpu/drm/i915/display/intel_display.c return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || dev_priv 16431 drivers/gpu/drm/i915/display/intel_display.c (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A); dev_priv 16438 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 16467 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 16478 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active || HAS_GMCH(dev_priv)) { dev_priv 16502 drivers/gpu/drm/i915/display/intel_display.c if (has_pch_trancoder(dev_priv, crtc->pipe)) dev_priv 16509 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 16521 drivers/gpu/drm/i915/display/intel_display.c return IS_GEN(dev_priv, 6) && dev_priv 16529 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 16590 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 16594 drivers/gpu/drm/i915/display/intel_display.c void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) dev_priv 16596 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); dev_priv 16600 drivers/gpu/drm/i915/display/intel_display.c i915_disable_vga(dev_priv); dev_priv 16604 drivers/gpu/drm/i915/display/intel_display.c void i915_redisable_vga(struct drm_i915_private *dev_priv) dev_priv 16617 drivers/gpu/drm/i915/display/intel_display.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 16622 drivers/gpu/drm/i915/display/intel_display.c i915_redisable_vga_power_on(dev_priv); dev_priv 16624 drivers/gpu/drm/i915/display/intel_display.c intel_display_power_put(dev_priv, POWER_DOMAIN_VGA, wakeref); dev_priv 16628 drivers/gpu/drm/i915/display/intel_display.c static void readout_plane_state(struct drm_i915_private *dev_priv) dev_priv 16633 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_plane(&dev_priv->drm, plane) { dev_priv 16642 drivers/gpu/drm/i915/display/intel_display.c crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 16652 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 16662 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 16670 drivers/gpu/drm/i915/display/intel_display.c dev_priv->active_crtcs = 0; dev_priv 16681 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_pipe_config(crtc, crtc_state); dev_priv 16687 drivers/gpu/drm/i915/display/intel_display.c dev_priv->active_crtcs |= 1 << crtc->pipe; dev_priv 16694 drivers/gpu/drm/i915/display/intel_display.c readout_plane_state(dev_priv); dev_priv 16696 drivers/gpu/drm/i915/display/intel_display.c for (i = 0; i < dev_priv->num_shared_dpll; i++) { dev_priv 16697 drivers/gpu/drm/i915/display/intel_display.c struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; dev_priv 16699 drivers/gpu/drm/i915/display/intel_display.c pll->on = pll->info->funcs->get_hw_state(dev_priv, pll, dev_priv 16702 drivers/gpu/drm/i915/display/intel_display.c if (IS_ELKHARTLAKE(dev_priv) && pll->on && dev_priv 16704 drivers/gpu/drm/i915/display/intel_display.c pll->wakeref = intel_display_power_get(dev_priv, dev_priv 16729 drivers/gpu/drm/i915/display/intel_display.c crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 16777 drivers/gpu/drm/i915/display/intel_display.c to_intel_bw_state(dev_priv->bw_obj.state); dev_priv 16804 drivers/gpu/drm/i915/display/intel_display.c if (dev_priv->display.modeset_calc_cdclk) { dev_priv 16815 drivers/gpu/drm/i915/display/intel_display.c dev_priv->min_cdclk[crtc->pipe] = min_cdclk; dev_priv 16816 drivers/gpu/drm/i915/display/intel_display.c dev_priv->min_voltage_level[crtc->pipe] = dev_priv 16819 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { dev_priv 16834 drivers/gpu/drm/i915/display/intel_display.c intel_pipe_config_sanity_check(dev_priv, crtc_state); dev_priv 16839 drivers/gpu/drm/i915/display/intel_display.c get_encoder_power_domains(struct drm_i915_private *dev_priv) dev_priv 16843 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_encoder(&dev_priv->drm, encoder) { dev_priv 16861 drivers/gpu/drm/i915/display/intel_display.c static void intel_early_display_was(struct drm_i915_private *dev_priv) dev_priv 16867 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv)) dev_priv 16871 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv)) { dev_priv 16881 drivers/gpu/drm/i915/display/intel_display.c static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv, dev_priv 16899 drivers/gpu/drm/i915/display/intel_display.c static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv, dev_priv 16917 drivers/gpu/drm/i915/display/intel_display.c static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv) dev_priv 16930 drivers/gpu/drm/i915/display/intel_display.c ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B); dev_priv 16931 drivers/gpu/drm/i915/display/intel_display.c ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C); dev_priv 16932 drivers/gpu/drm/i915/display/intel_display.c ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D); dev_priv 16935 drivers/gpu/drm/i915/display/intel_display.c ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB); dev_priv 16936 drivers/gpu/drm/i915/display/intel_display.c ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC); dev_priv 16937 drivers/gpu/drm/i915/display/intel_display.c ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID); dev_priv 16947 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 16954 drivers/gpu/drm/i915/display/intel_display.c wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); dev_priv 16956 drivers/gpu/drm/i915/display/intel_display.c intel_early_display_was(dev_priv); dev_priv 16963 drivers/gpu/drm/i915/display/intel_display.c enum phy phy = intel_port_to_phy(dev_priv, encoder->port); dev_priv 16967 drivers/gpu/drm/i915/display/intel_display.c intel_phy_is_tc(dev_priv, phy)) dev_priv 16971 drivers/gpu/drm/i915/display/intel_display.c get_encoder_power_domains(dev_priv); dev_priv 16973 drivers/gpu/drm/i915/display/intel_display.c if (HAS_PCH_IBX(dev_priv)) dev_priv 16974 drivers/gpu/drm/i915/display/intel_display.c ibx_sanitize_pch_ports(dev_priv); dev_priv 16980 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 16989 drivers/gpu/drm/i915/display/intel_display.c intel_sanitize_plane_mapping(dev_priv); dev_priv 16994 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 17002 drivers/gpu/drm/i915/display/intel_display.c for (i = 0; i < dev_priv->num_shared_dpll; i++) { dev_priv 17003 drivers/gpu/drm/i915/display/intel_display.c struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; dev_priv 17011 drivers/gpu/drm/i915/display/intel_display.c pll->info->funcs->disable(dev_priv, pll); dev_priv 17015 drivers/gpu/drm/i915/display/intel_display.c if (IS_G4X(dev_priv)) { dev_priv 17016 drivers/gpu/drm/i915/display/intel_display.c g4x_wm_get_hw_state(dev_priv); dev_priv 17017 drivers/gpu/drm/i915/display/intel_display.c g4x_wm_sanitize(dev_priv); dev_priv 17018 drivers/gpu/drm/i915/display/intel_display.c } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 17019 drivers/gpu/drm/i915/display/intel_display.c vlv_wm_get_hw_state(dev_priv); dev_priv 17020 drivers/gpu/drm/i915/display/intel_display.c vlv_wm_sanitize(dev_priv); dev_priv 17021 drivers/gpu/drm/i915/display/intel_display.c } else if (INTEL_GEN(dev_priv) >= 9) { dev_priv 17022 drivers/gpu/drm/i915/display/intel_display.c skl_wm_get_hw_state(dev_priv); dev_priv 17023 drivers/gpu/drm/i915/display/intel_display.c } else if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 17024 drivers/gpu/drm/i915/display/intel_display.c ilk_wm_get_hw_state(dev_priv); dev_priv 17033 drivers/gpu/drm/i915/display/intel_display.c modeset_put_power_domains(dev_priv, put_domains); dev_priv 17036 drivers/gpu/drm/i915/display/intel_display.c intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); dev_priv 17038 drivers/gpu/drm/i915/display/intel_display.c intel_fbc_init_pipe_state(dev_priv); dev_priv 17043 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 17044 drivers/gpu/drm/i915/display/intel_display.c struct drm_atomic_state *state = dev_priv->modeset_restore_state; dev_priv 17048 drivers/gpu/drm/i915/display/intel_display.c dev_priv->modeset_restore_state = NULL; dev_priv 17065 drivers/gpu/drm/i915/display/intel_display.c intel_enable_ipc(dev_priv); dev_priv 17095 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 17097 drivers/gpu/drm/i915/display/intel_display.c flush_workqueue(dev_priv->modeset_wq); dev_priv 17099 drivers/gpu/drm/i915/display/intel_display.c flush_work(&dev_priv->atomic_helper.free_work); dev_priv 17100 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); dev_priv 17107 drivers/gpu/drm/i915/display/intel_display.c intel_irq_uninstall(dev_priv); dev_priv 17116 drivers/gpu/drm/i915/display/intel_display.c intel_fbdev_fini(dev_priv); dev_priv 17120 drivers/gpu/drm/i915/display/intel_display.c intel_fbc_global_disable(dev_priv); dev_priv 17125 drivers/gpu/drm/i915/display/intel_display.c intel_hdcp_component_fini(dev_priv); dev_priv 17129 drivers/gpu/drm/i915/display/intel_display.c intel_overlay_cleanup(dev_priv); dev_priv 17131 drivers/gpu/drm/i915/display/intel_display.c intel_gmbus_teardown(dev_priv); dev_priv 17133 drivers/gpu/drm/i915/display/intel_display.c destroy_workqueue(dev_priv->modeset_wq); dev_priv 17135 drivers/gpu/drm/i915/display/intel_display.c intel_fbc_cleanup_cfb(dev_priv); dev_priv 17141 drivers/gpu/drm/i915/display/intel_display.c int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) dev_priv 17143 drivers/gpu/drm/i915/display/intel_display.c unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; dev_priv 17146 drivers/gpu/drm/i915/display/intel_display.c if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { dev_priv 17159 drivers/gpu/drm/i915/display/intel_display.c if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { dev_priv 17213 drivers/gpu/drm/i915/display/intel_display.c intel_display_capture_error_state(struct drm_i915_private *dev_priv) dev_priv 17227 drivers/gpu/drm/i915/display/intel_display.c if (!HAS_DISPLAY(dev_priv)) dev_priv 17234 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 17237 drivers/gpu/drm/i915/display/intel_display.c for_each_pipe(dev_priv, i) { dev_priv 17239 drivers/gpu/drm/i915/display/intel_display.c __intel_display_power_is_enabled(dev_priv, dev_priv 17250 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) <= 3) { dev_priv 17254 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) dev_priv 17256 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) { dev_priv 17263 drivers/gpu/drm/i915/display/intel_display.c if (HAS_GMCH(dev_priv)) dev_priv 17270 drivers/gpu/drm/i915/display/intel_display.c if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder]) dev_priv 17275 drivers/gpu/drm/i915/display/intel_display.c __intel_display_power_is_enabled(dev_priv, dev_priv 17300 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = m->i915; dev_priv 17306 drivers/gpu/drm/i915/display/intel_display.c err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); dev_priv 17307 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 17310 drivers/gpu/drm/i915/display/intel_display.c for_each_pipe(dev_priv, i) { dev_priv 17320 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) <= 3) { dev_priv 17324 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) dev_priv 17326 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 4) { dev_priv 156 drivers/gpu/drm/i915/display/intel_display.h #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') dev_priv 419 drivers/gpu/drm/i915/display/intel_display.h void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); dev_priv 420 drivers/gpu/drm/i915/display/intel_display.h u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, dev_priv 426 drivers/gpu/drm/i915/display/intel_display.h void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); dev_priv 427 drivers/gpu/drm/i915/display/intel_display.h void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); dev_priv 429 drivers/gpu/drm/i915/display/intel_display.h int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); dev_priv 430 drivers/gpu/drm/i915/display/intel_display.h int vlv_get_cck_clock(struct drm_i915_private *dev_priv, dev_priv 432 drivers/gpu/drm/i915/display/intel_display.h int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, dev_priv 434 drivers/gpu/drm/i915/display/intel_display.h void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); dev_priv 435 drivers/gpu/drm/i915/display/intel_display.h void lpt_disable_iclkip(struct drm_i915_private *dev_priv); dev_priv 436 drivers/gpu/drm/i915/display/intel_display.h void intel_init_display_hooks(struct drm_i915_private *dev_priv); dev_priv 446 drivers/gpu/drm/i915/display/intel_display.h bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); dev_priv 448 drivers/gpu/drm/i915/display/intel_display.h void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); dev_priv 452 drivers/gpu/drm/i915/display/intel_display.h bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); dev_priv 453 drivers/gpu/drm/i915/display/intel_display.h bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); dev_priv 454 drivers/gpu/drm/i915/display/intel_display.h enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, dev_priv 458 drivers/gpu/drm/i915/display/intel_display.h enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, dev_priv 463 drivers/gpu/drm/i915/display/intel_display.h void vlv_wait_port_ready(struct drm_i915_private *dev_priv, dev_priv 487 drivers/gpu/drm/i915/display/intel_display.h void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, dev_priv 490 drivers/gpu/drm/i915/display/intel_display.h int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, dev_priv 492 drivers/gpu/drm/i915/display/intel_display.h void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); dev_priv 493 drivers/gpu/drm/i915/display/intel_display.h int lpt_get_iclkip(struct drm_i915_private *dev_priv); dev_priv 496 drivers/gpu/drm/i915/display/intel_display.h void intel_prepare_reset(struct drm_i915_private *dev_priv); dev_priv 497 drivers/gpu/drm/i915/display/intel_display.h void intel_finish_reset(struct drm_i915_private *dev_priv); dev_priv 542 drivers/gpu/drm/i915/display/intel_display.h intel_display_capture_error_state(struct drm_i915_private *dev_priv); dev_priv 550 drivers/gpu/drm/i915/display/intel_display.h int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state); dev_priv 552 drivers/gpu/drm/i915/display/intel_display.h void i915_redisable_vga(struct drm_i915_private *dev_priv); dev_priv 553 drivers/gpu/drm/i915/display/intel_display.h void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv); dev_priv 554 drivers/gpu/drm/i915/display/intel_display.h void intel_init_pch_refclk(struct drm_i915_private *dev_priv); dev_priv 557 drivers/gpu/drm/i915/display/intel_display.h void assert_panel_unlocked(struct drm_i915_private *dev_priv, dev_priv 559 drivers/gpu/drm/i915/display/intel_display.h void assert_pll(struct drm_i915_private *dev_priv, dev_priv 563 drivers/gpu/drm/i915/display/intel_display.h void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); dev_priv 566 drivers/gpu/drm/i915/display/intel_display.h void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, dev_priv 570 drivers/gpu/drm/i915/display/intel_display.h void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); dev_priv 23 drivers/gpu/drm/i915/display/intel_display_power.c bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, dev_priv 176 drivers/gpu/drm/i915/display/intel_display_power.c static void intel_power_well_enable(struct drm_i915_private *dev_priv, dev_priv 180 drivers/gpu/drm/i915/display/intel_display_power.c power_well->desc->ops->enable(dev_priv, power_well); dev_priv 184 drivers/gpu/drm/i915/display/intel_display_power.c static void intel_power_well_disable(struct drm_i915_private *dev_priv, dev_priv 189 drivers/gpu/drm/i915/display/intel_display_power.c power_well->desc->ops->disable(dev_priv, power_well); dev_priv 192 drivers/gpu/drm/i915/display/intel_display_power.c static void intel_power_well_get(struct drm_i915_private *dev_priv, dev_priv 196 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_well_enable(dev_priv, power_well); dev_priv 199 drivers/gpu/drm/i915/display/intel_display_power.c static void intel_power_well_put(struct drm_i915_private *dev_priv, dev_priv 206 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_well_disable(dev_priv, power_well); dev_priv 221 drivers/gpu/drm/i915/display/intel_display_power.c bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, dev_priv 227 drivers/gpu/drm/i915/display/intel_display_power.c if (dev_priv->runtime_pm.suspended) dev_priv 232 drivers/gpu/drm/i915/display/intel_display_power.c for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) { dev_priv 262 drivers/gpu/drm/i915/display/intel_display_power.c bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, dev_priv 268 drivers/gpu/drm/i915/display/intel_display_power.c power_domains = &dev_priv->power_domains; dev_priv 271 drivers/gpu/drm/i915/display/intel_display_power.c ret = __intel_display_power_is_enabled(dev_priv, domain); dev_priv 283 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, dev_priv 286 drivers/gpu/drm/i915/display/intel_display_power.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 305 drivers/gpu/drm/i915/display/intel_display_power.c gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); dev_priv 308 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, dev_priv 312 drivers/gpu/drm/i915/display/intel_display_power.c gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); dev_priv 315 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, dev_priv 322 drivers/gpu/drm/i915/display/intel_display_power.c if (intel_de_wait_for_set(dev_priv, regs->driver, dev_priv 332 drivers/gpu/drm/i915/display/intel_display_power.c static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, dev_priv 348 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, dev_priv 367 drivers/gpu/drm/i915/display/intel_display_power.c (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1); dev_priv 376 drivers/gpu/drm/i915/display/intel_display_power.c static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, dev_priv 380 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ON(intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS, dev_priv 384 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_power_well_enable(struct drm_i915_private *dev_priv, dev_priv 394 drivers/gpu/drm/i915/display/intel_display_power.c pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : dev_priv 404 drivers/gpu/drm/i915/display/intel_display_power.c gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); dev_priv 409 drivers/gpu/drm/i915/display/intel_display_power.c hsw_wait_for_power_well_enable(dev_priv, power_well); dev_priv 412 drivers/gpu/drm/i915/display/intel_display_power.c if (IS_CANNONLAKE(dev_priv) && dev_priv 421 drivers/gpu/drm/i915/display/intel_display_power.c gen9_wait_for_power_well_fuses(dev_priv, pg); dev_priv 423 drivers/gpu/drm/i915/display/intel_display_power.c hsw_power_well_post_enable(dev_priv, dev_priv 428 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_power_well_disable(struct drm_i915_private *dev_priv, dev_priv 435 drivers/gpu/drm/i915/display/intel_display_power.c hsw_power_well_pre_disable(dev_priv, dev_priv 440 drivers/gpu/drm/i915/display/intel_display_power.c hsw_wait_for_power_well_disable(dev_priv, power_well); dev_priv 446 drivers/gpu/drm/i915/display/intel_display_power.c icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, dev_priv 458 drivers/gpu/drm/i915/display/intel_display_power.c if (INTEL_GEN(dev_priv) < 12) { dev_priv 463 drivers/gpu/drm/i915/display/intel_display_power.c hsw_wait_for_power_well_enable(dev_priv, power_well); dev_priv 466 drivers/gpu/drm/i915/display/intel_display_power.c if (IS_TIGERLAKE(dev_priv)) dev_priv 471 drivers/gpu/drm/i915/display/intel_display_power.c if (!IS_ELKHARTLAKE(dev_priv) && dev_priv 473 drivers/gpu/drm/i915/display/intel_display_power.c !intel_bios_is_port_edp(dev_priv, (enum port)phy)) { dev_priv 481 drivers/gpu/drm/i915/display/intel_display_power.c icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, dev_priv 489 drivers/gpu/drm/i915/display/intel_display_power.c if (INTEL_GEN(dev_priv) < 12) { dev_priv 497 drivers/gpu/drm/i915/display/intel_display_power.c hsw_wait_for_power_well_disable(dev_priv, power_well); dev_priv 506 drivers/gpu/drm/i915/display/intel_display_power.c static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv, dev_priv 519 drivers/gpu/drm/i915/display/intel_display_power.c static int power_well_async_ref_count(struct drm_i915_private *dev_priv, dev_priv 523 drivers/gpu/drm/i915/display/intel_display_power.c async_put_domains_mask(&dev_priv->power_domains)); dev_priv 530 drivers/gpu/drm/i915/display/intel_display_power.c static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, dev_priv 533 drivers/gpu/drm/i915/display/intel_display_power.c enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well); dev_priv 538 drivers/gpu/drm/i915/display/intel_display_power.c if (power_well_async_ref_count(dev_priv, power_well) == dev_priv 542 drivers/gpu/drm/i915/display/intel_display_power.c aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well); dev_priv 544 drivers/gpu/drm/i915/display/intel_display_power.c for_each_intel_encoder(&dev_priv->drm, encoder) { dev_priv 545 drivers/gpu/drm/i915/display/intel_display_power.c enum phy phy = intel_port_to_phy(dev_priv, encoder->port); dev_priv 547 drivers/gpu/drm/i915/display/intel_display_power.c if (!intel_phy_is_tc(dev_priv, phy)) dev_priv 574 drivers/gpu/drm/i915/display/intel_display_power.c static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, dev_priv 582 drivers/gpu/drm/i915/display/intel_display_power.c icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, dev_priv 585 drivers/gpu/drm/i915/display/intel_display_power.c enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well); dev_priv 588 drivers/gpu/drm/i915/display/intel_display_power.c icl_tc_port_assert_ref_held(dev_priv, power_well); dev_priv 596 drivers/gpu/drm/i915/display/intel_display_power.c hsw_power_well_enable(dev_priv, power_well); dev_priv 600 drivers/gpu/drm/i915/display/intel_display_power.c icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, dev_priv 603 drivers/gpu/drm/i915/display/intel_display_power.c icl_tc_port_assert_ref_held(dev_priv, power_well); dev_priv 605 drivers/gpu/drm/i915/display/intel_display_power.c hsw_power_well_disable(dev_priv, power_well); dev_priv 613 drivers/gpu/drm/i915/display/intel_display_power.c static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, dev_priv 631 drivers/gpu/drm/i915/display/intel_display_power.c if (IS_GEN(dev_priv, 9) && !IS_GEN9_LP(dev_priv) && dev_priv 638 drivers/gpu/drm/i915/display/intel_display_power.c static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) dev_priv 647 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE(intel_irqs_enabled(dev_priv), dev_priv 659 drivers/gpu/drm/i915/display/intel_display_power.c static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) dev_priv 661 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE(intel_irqs_enabled(dev_priv), dev_priv 675 drivers/gpu/drm/i915/display/intel_display_power.c static void gen9_write_dc_state(struct drm_i915_private *dev_priv, dev_priv 712 drivers/gpu/drm/i915/display/intel_display_power.c static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) dev_priv 717 drivers/gpu/drm/i915/display/intel_display_power.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 719 drivers/gpu/drm/i915/display/intel_display_power.c else if (IS_GEN9_LP(dev_priv)) dev_priv 727 drivers/gpu/drm/i915/display/intel_display_power.c static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) dev_priv 731 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); dev_priv 734 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->csr.dc_state, val); dev_priv 735 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->csr.dc_state = val; dev_priv 761 drivers/gpu/drm/i915/display/intel_display_power.c static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) dev_priv 766 drivers/gpu/drm/i915/display/intel_display_power.c if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) dev_priv 767 drivers/gpu/drm/i915/display/intel_display_power.c state &= dev_priv->csr.allowed_dc_mask; dev_priv 770 drivers/gpu/drm/i915/display/intel_display_power.c mask = gen9_dc_mask(dev_priv); dev_priv 775 drivers/gpu/drm/i915/display/intel_display_power.c if ((val & mask) != dev_priv->csr.dc_state) dev_priv 777 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->csr.dc_state, val & mask); dev_priv 782 drivers/gpu/drm/i915/display/intel_display_power.c gen9_write_dc_state(dev_priv, val); dev_priv 784 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->csr.dc_state = val & mask; dev_priv 787 drivers/gpu/drm/i915/display/intel_display_power.c static void bxt_enable_dc9(struct drm_i915_private *dev_priv) dev_priv 789 drivers/gpu/drm/i915/display/intel_display_power.c assert_can_enable_dc9(dev_priv); dev_priv 797 drivers/gpu/drm/i915/display/intel_display_power.c if (!HAS_PCH_SPLIT(dev_priv)) dev_priv 798 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_sequencer_reset(dev_priv); dev_priv 799 drivers/gpu/drm/i915/display/intel_display_power.c gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); dev_priv 802 drivers/gpu/drm/i915/display/intel_display_power.c static void bxt_disable_dc9(struct drm_i915_private *dev_priv) dev_priv 804 drivers/gpu/drm/i915/display/intel_display_power.c assert_can_disable_dc9(dev_priv); dev_priv 808 drivers/gpu/drm/i915/display/intel_display_power.c gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); dev_priv 810 drivers/gpu/drm/i915/display/intel_display_power.c intel_pps_unlock_regs_wa(dev_priv); dev_priv 813 drivers/gpu/drm/i915/display/intel_display_power.c static void assert_csr_loaded(struct drm_i915_private *dev_priv) dev_priv 822 drivers/gpu/drm/i915/display/intel_display_power.c lookup_power_well(struct drm_i915_private *dev_priv, dev_priv 827 drivers/gpu/drm/i915/display/intel_display_power.c for_each_power_well(dev_priv, power_well) dev_priv 839 drivers/gpu/drm/i915/display/intel_display_power.c return &dev_priv->power_domains.power_wells[0]; dev_priv 842 drivers/gpu/drm/i915/display/intel_display_power.c static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) dev_priv 844 drivers/gpu/drm/i915/display/intel_display_power.c bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, dev_priv 851 drivers/gpu/drm/i915/display/intel_display_power.c assert_rpm_wakelock_held(&dev_priv->runtime_pm); dev_priv 853 drivers/gpu/drm/i915/display/intel_display_power.c assert_csr_loaded(dev_priv); dev_priv 856 drivers/gpu/drm/i915/display/intel_display_power.c static void gen9_enable_dc5(struct drm_i915_private *dev_priv) dev_priv 858 drivers/gpu/drm/i915/display/intel_display_power.c assert_can_enable_dc5(dev_priv); dev_priv 863 drivers/gpu/drm/i915/display/intel_display_power.c if (IS_GEN9_BC(dev_priv)) dev_priv 867 drivers/gpu/drm/i915/display/intel_display_power.c gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); dev_priv 870 drivers/gpu/drm/i915/display/intel_display_power.c static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) dev_priv 877 drivers/gpu/drm/i915/display/intel_display_power.c assert_csr_loaded(dev_priv); dev_priv 880 drivers/gpu/drm/i915/display/intel_display_power.c static void skl_enable_dc6(struct drm_i915_private *dev_priv) dev_priv 882 drivers/gpu/drm/i915/display/intel_display_power.c assert_can_enable_dc6(dev_priv); dev_priv 887 drivers/gpu/drm/i915/display/intel_display_power.c if (IS_GEN9_BC(dev_priv)) dev_priv 891 drivers/gpu/drm/i915/display/intel_display_power.c gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); dev_priv 894 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, dev_priv 912 drivers/gpu/drm/i915/display/intel_display_power.c static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, dev_priv 915 drivers/gpu/drm/i915/display/intel_display_power.c bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy); dev_priv 918 drivers/gpu/drm/i915/display/intel_display_power.c static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, dev_priv 921 drivers/gpu/drm/i915/display/intel_display_power.c bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy); dev_priv 924 drivers/gpu/drm/i915/display/intel_display_power.c static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, dev_priv 927 drivers/gpu/drm/i915/display/intel_display_power.c return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc->bxt.phy); dev_priv 930 drivers/gpu/drm/i915/display/intel_display_power.c static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) dev_priv 934 drivers/gpu/drm/i915/display/intel_display_power.c power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A); dev_priv 936 drivers/gpu/drm/i915/display/intel_display_power.c bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy); dev_priv 938 drivers/gpu/drm/i915/display/intel_display_power.c power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); dev_priv 940 drivers/gpu/drm/i915/display/intel_display_power.c bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy); dev_priv 942 drivers/gpu/drm/i915/display/intel_display_power.c if (IS_GEMINILAKE(dev_priv)) { dev_priv 943 drivers/gpu/drm/i915/display/intel_display_power.c power_well = lookup_power_well(dev_priv, dev_priv 946 drivers/gpu/drm/i915/display/intel_display_power.c bxt_ddi_phy_verify_state(dev_priv, dev_priv 951 drivers/gpu/drm/i915/display/intel_display_power.c static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, dev_priv 957 drivers/gpu/drm/i915/display/intel_display_power.c static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) dev_priv 966 drivers/gpu/drm/i915/display/intel_display_power.c static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) dev_priv 970 drivers/gpu/drm/i915/display/intel_display_power.c gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); dev_priv 972 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->display.get_cdclk(dev_priv, &cdclk_state); dev_priv 974 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); dev_priv 976 drivers/gpu/drm/i915/display/intel_display_power.c gen9_assert_dbuf_enabled(dev_priv); dev_priv 978 drivers/gpu/drm/i915/display/intel_display_power.c if (IS_GEN9_LP(dev_priv)) dev_priv 979 drivers/gpu/drm/i915/display/intel_display_power.c bxt_verify_ddi_phy_power_wells(dev_priv); dev_priv 981 drivers/gpu/drm/i915/display/intel_display_power.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 987 drivers/gpu/drm/i915/display/intel_display_power.c intel_combo_phy_init(dev_priv); dev_priv 990 drivers/gpu/drm/i915/display/intel_display_power.c static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, dev_priv 993 drivers/gpu/drm/i915/display/intel_display_power.c gen9_disable_dc_states(dev_priv); dev_priv 996 drivers/gpu/drm/i915/display/intel_display_power.c static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, dev_priv 999 drivers/gpu/drm/i915/display/intel_display_power.c if (!dev_priv->csr.dmc_payload) dev_priv 1002 drivers/gpu/drm/i915/display/intel_display_power.c if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) dev_priv 1003 drivers/gpu/drm/i915/display/intel_display_power.c skl_enable_dc6(dev_priv); dev_priv 1004 drivers/gpu/drm/i915/display/intel_display_power.c else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) dev_priv 1005 drivers/gpu/drm/i915/display/intel_display_power.c gen9_enable_dc5(dev_priv); dev_priv 1008 drivers/gpu/drm/i915/display/intel_display_power.c static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, dev_priv 1013 drivers/gpu/drm/i915/display/intel_display_power.c static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, dev_priv 1018 drivers/gpu/drm/i915/display/intel_display_power.c static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, dev_priv 1024 drivers/gpu/drm/i915/display/intel_display_power.c static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, dev_priv 1028 drivers/gpu/drm/i915/display/intel_display_power.c i830_enable_pipe(dev_priv, PIPE_A); dev_priv 1030 drivers/gpu/drm/i915/display/intel_display_power.c i830_enable_pipe(dev_priv, PIPE_B); dev_priv 1033 drivers/gpu/drm/i915/display/intel_display_power.c static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, dev_priv 1036 drivers/gpu/drm/i915/display/intel_display_power.c i830_disable_pipe(dev_priv, PIPE_B); dev_priv 1037 drivers/gpu/drm/i915/display/intel_display_power.c i830_disable_pipe(dev_priv, PIPE_A); dev_priv 1040 drivers/gpu/drm/i915/display/intel_display_power.c static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, dev_priv 1047 drivers/gpu/drm/i915/display/intel_display_power.c static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, dev_priv 1051 drivers/gpu/drm/i915/display/intel_display_power.c i830_pipes_power_well_enable(dev_priv, power_well); dev_priv 1053 drivers/gpu/drm/i915/display/intel_display_power.c i830_pipes_power_well_disable(dev_priv, power_well); dev_priv 1056 drivers/gpu/drm/i915/display/intel_display_power.c static void vlv_set_power_well(struct drm_i915_private *dev_priv, dev_priv 1068 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_get(dev_priv); dev_priv 1071 drivers/gpu/drm/i915/display/intel_display_power.c ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) dev_priv 1076 drivers/gpu/drm/i915/display/intel_display_power.c ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); dev_priv 1079 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); dev_priv 1084 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); dev_priv 1089 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_put(dev_priv); dev_priv 1092 drivers/gpu/drm/i915/display/intel_display_power.c static void vlv_power_well_enable(struct drm_i915_private *dev_priv, dev_priv 1095 drivers/gpu/drm/i915/display/intel_display_power.c vlv_set_power_well(dev_priv, power_well, true); dev_priv 1098 drivers/gpu/drm/i915/display/intel_display_power.c static void vlv_power_well_disable(struct drm_i915_private *dev_priv, dev_priv 1101 drivers/gpu/drm/i915/display/intel_display_power.c vlv_set_power_well(dev_priv, power_well, false); dev_priv 1104 drivers/gpu/drm/i915/display/intel_display_power.c static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, dev_priv 1116 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_get(dev_priv); dev_priv 1118 drivers/gpu/drm/i915/display/intel_display_power.c state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; dev_priv 1132 drivers/gpu/drm/i915/display/intel_display_power.c ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; dev_priv 1135 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_put(dev_priv); dev_priv 1140 drivers/gpu/drm/i915/display/intel_display_power.c static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) dev_priv 1161 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ON(dev_priv->rawclk_freq == 0); dev_priv 1164 drivers/gpu/drm/i915/display/intel_display_power.c DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000)); dev_priv 1167 drivers/gpu/drm/i915/display/intel_display_power.c static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) dev_priv 1180 drivers/gpu/drm/i915/display/intel_display_power.c for_each_pipe(dev_priv, pipe) { dev_priv 1190 drivers/gpu/drm/i915/display/intel_display_power.c vlv_init_display_clock_gating(dev_priv); dev_priv 1192 drivers/gpu/drm/i915/display/intel_display_power.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 1193 drivers/gpu/drm/i915/display/intel_display_power.c valleyview_enable_display_irqs(dev_priv); dev_priv 1194 drivers/gpu/drm/i915/display/intel_display_power.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 1200 drivers/gpu/drm/i915/display/intel_display_power.c if (dev_priv->power_domains.initializing) dev_priv 1203 drivers/gpu/drm/i915/display/intel_display_power.c intel_hpd_init(dev_priv); dev_priv 1206 drivers/gpu/drm/i915/display/intel_display_power.c for_each_intel_encoder(&dev_priv->drm, encoder) { dev_priv 1211 drivers/gpu/drm/i915/display/intel_display_power.c i915_redisable_vga_power_on(dev_priv); dev_priv 1213 drivers/gpu/drm/i915/display/intel_display_power.c intel_pps_unlock_regs_wa(dev_priv); dev_priv 1216 drivers/gpu/drm/i915/display/intel_display_power.c static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) dev_priv 1218 drivers/gpu/drm/i915/display/intel_display_power.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 1219 drivers/gpu/drm/i915/display/intel_display_power.c valleyview_disable_display_irqs(dev_priv); dev_priv 1220 drivers/gpu/drm/i915/display/intel_display_power.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 1223 drivers/gpu/drm/i915/display/intel_display_power.c intel_synchronize_irq(dev_priv); dev_priv 1225 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_sequencer_reset(dev_priv); dev_priv 1228 drivers/gpu/drm/i915/display/intel_display_power.c if (!dev_priv->drm.dev->power.is_suspended) dev_priv 1229 drivers/gpu/drm/i915/display/intel_display_power.c intel_hpd_poll_init(dev_priv); dev_priv 1232 drivers/gpu/drm/i915/display/intel_display_power.c static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, dev_priv 1235 drivers/gpu/drm/i915/display/intel_display_power.c vlv_set_power_well(dev_priv, power_well, true); dev_priv 1237 drivers/gpu/drm/i915/display/intel_display_power.c vlv_display_power_well_init(dev_priv); dev_priv 1240 drivers/gpu/drm/i915/display/intel_display_power.c static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, dev_priv 1243 drivers/gpu/drm/i915/display/intel_display_power.c vlv_display_power_well_deinit(dev_priv); dev_priv 1245 drivers/gpu/drm/i915/display/intel_display_power.c vlv_set_power_well(dev_priv, power_well, false); dev_priv 1248 drivers/gpu/drm/i915/display/intel_display_power.c static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, dev_priv 1254 drivers/gpu/drm/i915/display/intel_display_power.c vlv_set_power_well(dev_priv, power_well, true); dev_priv 1270 drivers/gpu/drm/i915/display/intel_display_power.c static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, dev_priv 1275 drivers/gpu/drm/i915/display/intel_display_power.c for_each_pipe(dev_priv, pipe) dev_priv 1276 drivers/gpu/drm/i915/display/intel_display_power.c assert_pll_disabled(dev_priv, pipe); dev_priv 1281 drivers/gpu/drm/i915/display/intel_display_power.c vlv_set_power_well(dev_priv, power_well, false); dev_priv 1288 drivers/gpu/drm/i915/display/intel_display_power.c static void assert_chv_phy_status(struct drm_i915_private *dev_priv) dev_priv 1291 drivers/gpu/drm/i915/display/intel_display_power.c lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); dev_priv 1293 drivers/gpu/drm/i915/display/intel_display_power.c lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D); dev_priv 1294 drivers/gpu/drm/i915/display/intel_display_power.c u32 phy_control = dev_priv->chv_phy_control; dev_priv 1305 drivers/gpu/drm/i915/display/intel_display_power.c if (!dev_priv->chv_phy_assert[DPIO_PHY0]) dev_priv 1313 drivers/gpu/drm/i915/display/intel_display_power.c if (!dev_priv->chv_phy_assert[DPIO_PHY1]) dev_priv 1318 drivers/gpu/drm/i915/display/intel_display_power.c if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) { dev_priv 1359 drivers/gpu/drm/i915/display/intel_display_power.c if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) { dev_priv 1384 drivers/gpu/drm/i915/display/intel_display_power.c if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS, dev_priv 1388 drivers/gpu/drm/i915/display/intel_display_power.c phy_status, dev_priv->chv_phy_control); dev_priv 1393 drivers/gpu/drm/i915/display/intel_display_power.c static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, dev_priv 1413 drivers/gpu/drm/i915/display/intel_display_power.c vlv_set_power_well(dev_priv, power_well, true); dev_priv 1416 drivers/gpu/drm/i915/display/intel_display_power.c if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS, dev_priv 1420 drivers/gpu/drm/i915/display/intel_display_power.c vlv_dpio_get(dev_priv); dev_priv 1423 drivers/gpu/drm/i915/display/intel_display_power.c tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); dev_priv 1426 drivers/gpu/drm/i915/display/intel_display_power.c vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); dev_priv 1429 drivers/gpu/drm/i915/display/intel_display_power.c tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); dev_priv 1431 drivers/gpu/drm/i915/display/intel_display_power.c vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); dev_priv 1438 drivers/gpu/drm/i915/display/intel_display_power.c tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); dev_priv 1440 drivers/gpu/drm/i915/display/intel_display_power.c vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); dev_priv 1443 drivers/gpu/drm/i915/display/intel_display_power.c vlv_dpio_put(dev_priv); dev_priv 1445 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); dev_priv 1446 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); dev_priv 1449 drivers/gpu/drm/i915/display/intel_display_power.c phy, dev_priv->chv_phy_control); dev_priv 1451 drivers/gpu/drm/i915/display/intel_display_power.c assert_chv_phy_status(dev_priv); dev_priv 1454 drivers/gpu/drm/i915/display/intel_display_power.c static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, dev_priv 1464 drivers/gpu/drm/i915/display/intel_display_power.c assert_pll_disabled(dev_priv, PIPE_A); dev_priv 1465 drivers/gpu/drm/i915/display/intel_display_power.c assert_pll_disabled(dev_priv, PIPE_B); dev_priv 1468 drivers/gpu/drm/i915/display/intel_display_power.c assert_pll_disabled(dev_priv, PIPE_C); dev_priv 1471 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); dev_priv 1472 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); dev_priv 1474 drivers/gpu/drm/i915/display/intel_display_power.c vlv_set_power_well(dev_priv, power_well, false); dev_priv 1477 drivers/gpu/drm/i915/display/intel_display_power.c phy, dev_priv->chv_phy_control); dev_priv 1480 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_assert[phy] = true; dev_priv 1482 drivers/gpu/drm/i915/display/intel_display_power.c assert_chv_phy_status(dev_priv); dev_priv 1485 drivers/gpu/drm/i915/display/intel_display_power.c static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, dev_priv 1498 drivers/gpu/drm/i915/display/intel_display_power.c if (!dev_priv->chv_phy_assert[phy]) dev_priv 1506 drivers/gpu/drm/i915/display/intel_display_power.c vlv_dpio_get(dev_priv); dev_priv 1507 drivers/gpu/drm/i915/display/intel_display_power.c val = vlv_dpio_read(dev_priv, pipe, reg); dev_priv 1508 drivers/gpu/drm/i915/display/intel_display_power.c vlv_dpio_put(dev_priv); dev_priv 1547 drivers/gpu/drm/i915/display/intel_display_power.c bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, dev_priv 1550 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 1555 drivers/gpu/drm/i915/display/intel_display_power.c was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); dev_priv 1561 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); dev_priv 1563 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); dev_priv 1565 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); dev_priv 1568 drivers/gpu/drm/i915/display/intel_display_power.c phy, ch, dev_priv->chv_phy_control); dev_priv 1570 drivers/gpu/drm/i915/display/intel_display_power.c assert_chv_phy_status(dev_priv); dev_priv 1581 drivers/gpu/drm/i915/display/intel_display_power.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1582 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 1588 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); dev_priv 1589 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); dev_priv 1592 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); dev_priv 1594 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); dev_priv 1596 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); dev_priv 1599 drivers/gpu/drm/i915/display/intel_display_power.c phy, ch, mask, dev_priv->chv_phy_control); dev_priv 1601 drivers/gpu/drm/i915/display/intel_display_power.c assert_chv_phy_status(dev_priv); dev_priv 1603 drivers/gpu/drm/i915/display/intel_display_power.c assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); dev_priv 1608 drivers/gpu/drm/i915/display/intel_display_power.c static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, dev_priv 1615 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_get(dev_priv); dev_priv 1617 drivers/gpu/drm/i915/display/intel_display_power.c state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); dev_priv 1629 drivers/gpu/drm/i915/display/intel_display_power.c ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); dev_priv 1632 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_put(dev_priv); dev_priv 1637 drivers/gpu/drm/i915/display/intel_display_power.c static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, dev_priv 1647 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_get(dev_priv); dev_priv 1650 drivers/gpu/drm/i915/display/intel_display_power.c ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) dev_priv 1655 drivers/gpu/drm/i915/display/intel_display_power.c ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); dev_priv 1658 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl); dev_priv 1663 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); dev_priv 1668 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_put(dev_priv); dev_priv 1671 drivers/gpu/drm/i915/display/intel_display_power.c static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, dev_priv 1674 drivers/gpu/drm/i915/display/intel_display_power.c chv_set_pipe_power_well(dev_priv, power_well, true); dev_priv 1676 drivers/gpu/drm/i915/display/intel_display_power.c vlv_display_power_well_init(dev_priv); dev_priv 1679 drivers/gpu/drm/i915/display/intel_display_power.c static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, dev_priv 1682 drivers/gpu/drm/i915/display/intel_display_power.c vlv_display_power_well_deinit(dev_priv); dev_priv 1684 drivers/gpu/drm/i915/display/intel_display_power.c chv_set_pipe_power_well(dev_priv, power_well, false); dev_priv 1784 drivers/gpu/drm/i915/display/intel_display_power.c intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv, dev_priv 1787 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 1801 drivers/gpu/drm/i915/display/intel_display_power.c intel_runtime_pm_put_raw(&dev_priv->runtime_pm, dev_priv 1810 drivers/gpu/drm/i915/display/intel_display_power.c __intel_display_power_get_domain(struct drm_i915_private *dev_priv, dev_priv 1813 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 1816 drivers/gpu/drm/i915/display/intel_display_power.c if (intel_display_power_grab_async_put_ref(dev_priv, domain)) dev_priv 1819 drivers/gpu/drm/i915/display/intel_display_power.c for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) dev_priv 1820 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_well_get(dev_priv, power_well); dev_priv 1837 drivers/gpu/drm/i915/display/intel_display_power.c intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, dev_priv 1840 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 1841 drivers/gpu/drm/i915/display/intel_display_power.c intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 1844 drivers/gpu/drm/i915/display/intel_display_power.c __intel_display_power_get_domain(dev_priv, domain); dev_priv 1863 drivers/gpu/drm/i915/display/intel_display_power.c intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, dev_priv 1866 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 1870 drivers/gpu/drm/i915/display/intel_display_power.c wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm); dev_priv 1876 drivers/gpu/drm/i915/display/intel_display_power.c if (__intel_display_power_is_enabled(dev_priv, domain)) { dev_priv 1877 drivers/gpu/drm/i915/display/intel_display_power.c __intel_display_power_get_domain(dev_priv, domain); dev_priv 1886 drivers/gpu/drm/i915/display/intel_display_power.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 1894 drivers/gpu/drm/i915/display/intel_display_power.c __intel_display_power_put_domain(struct drm_i915_private *dev_priv, dev_priv 1899 drivers/gpu/drm/i915/display/intel_display_power.c const char *name = intel_display_power_domain_str(dev_priv, domain); dev_priv 1901 drivers/gpu/drm/i915/display/intel_display_power.c power_domains = &dev_priv->power_domains; dev_priv 1912 drivers/gpu/drm/i915/display/intel_display_power.c for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) dev_priv 1913 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_well_put(dev_priv, power_well); dev_priv 1916 drivers/gpu/drm/i915/display/intel_display_power.c static void __intel_display_power_put(struct drm_i915_private *dev_priv, dev_priv 1919 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 1922 drivers/gpu/drm/i915/display/intel_display_power.c __intel_display_power_put_domain(dev_priv, domain); dev_priv 1939 drivers/gpu/drm/i915/display/intel_display_power.c void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, dev_priv 1942 drivers/gpu/drm/i915/display/intel_display_power.c __intel_display_power_put(dev_priv, domain); dev_priv 1943 drivers/gpu/drm/i915/display/intel_display_power.c intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); dev_priv 1960 drivers/gpu/drm/i915/display/intel_display_power.c struct drm_i915_private *dev_priv = dev_priv 1963 drivers/gpu/drm/i915/display/intel_display_power.c struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; dev_priv 1978 drivers/gpu/drm/i915/display/intel_display_power.c __intel_display_power_put_domain(dev_priv, domain); dev_priv 1987 drivers/gpu/drm/i915/display/intel_display_power.c struct drm_i915_private *dev_priv = dev_priv 1990 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 1991 drivers/gpu/drm/i915/display/intel_display_power.c struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; dev_priv 2142 drivers/gpu/drm/i915/display/intel_display_power.c void intel_display_power_put(struct drm_i915_private *dev_priv, dev_priv 2146 drivers/gpu/drm/i915/display/intel_display_power.c __intel_display_power_put(dev_priv, domain); dev_priv 2147 drivers/gpu/drm/i915/display/intel_display_power.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 2892 drivers/gpu/drm/i915/display/intel_display_power.c bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, dev_priv 2898 drivers/gpu/drm/i915/display/intel_display_power.c power_well = lookup_power_well(dev_priv, power_well_id); dev_priv 2899 drivers/gpu/drm/i915/display/intel_display_power.c ret = power_well->desc->ops->is_enabled(dev_priv, power_well); dev_priv 3918 drivers/gpu/drm/i915/display/intel_display_power.c sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, dev_priv 3927 drivers/gpu/drm/i915/display/intel_display_power.c static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, dev_priv 3934 drivers/gpu/drm/i915/display/intel_display_power.c if (INTEL_GEN(dev_priv) >= 11) { dev_priv 3942 drivers/gpu/drm/i915/display/intel_display_power.c } else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) { dev_priv 3945 drivers/gpu/drm/i915/display/intel_display_power.c } else if (IS_GEN9_LP(dev_priv)) { dev_priv 4022 drivers/gpu/drm/i915/display/intel_display_power.c int intel_power_domains_init(struct drm_i915_private *dev_priv) dev_priv 4024 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 4028 drivers/gpu/drm/i915/display/intel_display_power.c sanitize_disable_power_well_option(dev_priv, dev_priv 4030 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->csr.allowed_dc_mask = dev_priv 4031 drivers/gpu/drm/i915/display/intel_display_power.c get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc); dev_priv 4044 drivers/gpu/drm/i915/display/intel_display_power.c if (IS_GEN(dev_priv, 12)) { dev_priv 4046 drivers/gpu/drm/i915/display/intel_display_power.c } else if (IS_GEN(dev_priv, 11)) { dev_priv 4048 drivers/gpu/drm/i915/display/intel_display_power.c } else if (IS_CANNONLAKE(dev_priv)) { dev_priv 4057 drivers/gpu/drm/i915/display/intel_display_power.c if (!IS_CNL_WITH_PORT_F(dev_priv)) dev_priv 4059 drivers/gpu/drm/i915/display/intel_display_power.c } else if (IS_GEMINILAKE(dev_priv)) { dev_priv 4061 drivers/gpu/drm/i915/display/intel_display_power.c } else if (IS_BROXTON(dev_priv)) { dev_priv 4063 drivers/gpu/drm/i915/display/intel_display_power.c } else if (IS_GEN9_BC(dev_priv)) { dev_priv 4065 drivers/gpu/drm/i915/display/intel_display_power.c } else if (IS_CHERRYVIEW(dev_priv)) { dev_priv 4067 drivers/gpu/drm/i915/display/intel_display_power.c } else if (IS_BROADWELL(dev_priv)) { dev_priv 4069 drivers/gpu/drm/i915/display/intel_display_power.c } else if (IS_HASWELL(dev_priv)) { dev_priv 4071 drivers/gpu/drm/i915/display/intel_display_power.c } else if (IS_VALLEYVIEW(dev_priv)) { dev_priv 4073 drivers/gpu/drm/i915/display/intel_display_power.c } else if (IS_I830(dev_priv)) { dev_priv 4088 drivers/gpu/drm/i915/display/intel_display_power.c void intel_power_domains_cleanup(struct drm_i915_private *dev_priv) dev_priv 4090 drivers/gpu/drm/i915/display/intel_display_power.c kfree(dev_priv->power_domains.power_wells); dev_priv 4093 drivers/gpu/drm/i915/display/intel_display_power.c static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) dev_priv 4095 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 4099 drivers/gpu/drm/i915/display/intel_display_power.c for_each_power_well(dev_priv, power_well) { dev_priv 4100 drivers/gpu/drm/i915/display/intel_display_power.c power_well->desc->ops->sync_hw(dev_priv, power_well); dev_priv 4102 drivers/gpu/drm/i915/display/intel_display_power.c power_well->desc->ops->is_enabled(dev_priv, power_well); dev_priv 4108 drivers/gpu/drm/i915/display/intel_display_power.c bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv, dev_priv 4128 drivers/gpu/drm/i915/display/intel_display_power.c static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) dev_priv 4130 drivers/gpu/drm/i915/display/intel_display_power.c intel_dbuf_slice_set(dev_priv, DBUF_CTL, true); dev_priv 4133 drivers/gpu/drm/i915/display/intel_display_power.c static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) dev_priv 4135 drivers/gpu/drm/i915/display/intel_display_power.c intel_dbuf_slice_set(dev_priv, DBUF_CTL, false); dev_priv 4138 drivers/gpu/drm/i915/display/intel_display_power.c static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv) dev_priv 4140 drivers/gpu/drm/i915/display/intel_display_power.c if (INTEL_GEN(dev_priv) < 11) dev_priv 4145 drivers/gpu/drm/i915/display/intel_display_power.c void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, dev_priv 4148 drivers/gpu/drm/i915/display/intel_display_power.c const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; dev_priv 4151 drivers/gpu/drm/i915/display/intel_display_power.c if (req_slices > intel_dbuf_max_slices(dev_priv)) { dev_priv 4160 drivers/gpu/drm/i915/display/intel_display_power.c ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true); dev_priv 4162 drivers/gpu/drm/i915/display/intel_display_power.c ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false); dev_priv 4165 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices; dev_priv 4168 drivers/gpu/drm/i915/display/intel_display_power.c static void icl_dbuf_enable(struct drm_i915_private *dev_priv) dev_priv 4184 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->wm.skl_hw.ddb.enabled_slices = 1; dev_priv 4187 drivers/gpu/drm/i915/display/intel_display_power.c static void icl_dbuf_disable(struct drm_i915_private *dev_priv) dev_priv 4203 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->wm.skl_hw.ddb.enabled_slices = 1; dev_priv 4206 drivers/gpu/drm/i915/display/intel_display_power.c static void icl_mbus_init(struct drm_i915_private *dev_priv) dev_priv 4224 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) dev_priv 4244 drivers/gpu/drm/i915/display/intel_display_power.c static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) dev_priv 4246 drivers/gpu/drm/i915/display/intel_display_power.c struct drm_device *dev = &dev_priv->drm; dev_priv 4265 drivers/gpu/drm/i915/display/intel_display_power.c if (IS_HASWELL(dev_priv)) dev_priv 4281 drivers/gpu/drm/i915/display/intel_display_power.c I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); dev_priv 4284 drivers/gpu/drm/i915/display/intel_display_power.c static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv) dev_priv 4286 drivers/gpu/drm/i915/display/intel_display_power.c if (IS_HASWELL(dev_priv)) dev_priv 4292 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val) dev_priv 4294 drivers/gpu/drm/i915/display/intel_display_power.c if (IS_HASWELL(dev_priv)) { dev_priv 4295 drivers/gpu/drm/i915/display/intel_display_power.c if (sandybridge_pcode_write(dev_priv, dev_priv 4312 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, dev_priv 4317 drivers/gpu/drm/i915/display/intel_display_power.c assert_can_disable_lcpll(dev_priv); dev_priv 4336 drivers/gpu/drm/i915/display/intel_display_power.c if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) dev_priv 4339 drivers/gpu/drm/i915/display/intel_display_power.c val = hsw_read_dcomp(dev_priv); dev_priv 4341 drivers/gpu/drm/i915/display/intel_display_power.c hsw_write_dcomp(dev_priv, val); dev_priv 4344 drivers/gpu/drm/i915/display/intel_display_power.c if (wait_for((hsw_read_dcomp(dev_priv) & dev_priv 4360 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) dev_priv 4374 drivers/gpu/drm/i915/display/intel_display_power.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 4382 drivers/gpu/drm/i915/display/intel_display_power.c val = hsw_read_dcomp(dev_priv); dev_priv 4385 drivers/gpu/drm/i915/display/intel_display_power.c hsw_write_dcomp(dev_priv, val); dev_priv 4391 drivers/gpu/drm/i915/display/intel_display_power.c if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) dev_priv 4404 drivers/gpu/drm/i915/display/intel_display_power.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 4406 drivers/gpu/drm/i915/display/intel_display_power.c intel_update_cdclk(dev_priv); dev_priv 4407 drivers/gpu/drm/i915/display/intel_display_power.c intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); dev_priv 4433 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_enable_pc8(struct drm_i915_private *dev_priv) dev_priv 4439 drivers/gpu/drm/i915/display/intel_display_power.c if (HAS_PCH_LPT_LP(dev_priv)) { dev_priv 4445 drivers/gpu/drm/i915/display/intel_display_power.c lpt_disable_clkout_dp(dev_priv); dev_priv 4446 drivers/gpu/drm/i915/display/intel_display_power.c hsw_disable_lcpll(dev_priv, true, true); dev_priv 4449 drivers/gpu/drm/i915/display/intel_display_power.c static void hsw_disable_pc8(struct drm_i915_private *dev_priv) dev_priv 4455 drivers/gpu/drm/i915/display/intel_display_power.c hsw_restore_lcpll(dev_priv); dev_priv 4456 drivers/gpu/drm/i915/display/intel_display_power.c intel_init_pch_refclk(dev_priv); dev_priv 4458 drivers/gpu/drm/i915/display/intel_display_power.c if (HAS_PCH_LPT_LP(dev_priv)) { dev_priv 4465 drivers/gpu/drm/i915/display/intel_display_power.c static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, dev_priv 4471 drivers/gpu/drm/i915/display/intel_display_power.c if (IS_IVYBRIDGE(dev_priv)) { dev_priv 4489 drivers/gpu/drm/i915/display/intel_display_power.c static void skl_display_core_init(struct drm_i915_private *dev_priv, dev_priv 4492 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 4495 drivers/gpu/drm/i915/display/intel_display_power.c gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); dev_priv 4498 drivers/gpu/drm/i915/display/intel_display_power.c intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); dev_priv 4503 drivers/gpu/drm/i915/display/intel_display_power.c well = lookup_power_well(dev_priv, SKL_DISP_PW_1); dev_priv 4504 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_well_enable(dev_priv, well); dev_priv 4506 drivers/gpu/drm/i915/display/intel_display_power.c well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); dev_priv 4507 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_well_enable(dev_priv, well); dev_priv 4511 drivers/gpu/drm/i915/display/intel_display_power.c intel_cdclk_init(dev_priv); dev_priv 4513 drivers/gpu/drm/i915/display/intel_display_power.c gen9_dbuf_enable(dev_priv); dev_priv 4515 drivers/gpu/drm/i915/display/intel_display_power.c if (resume && dev_priv->csr.dmc_payload) dev_priv 4516 drivers/gpu/drm/i915/display/intel_display_power.c intel_csr_load_program(dev_priv); dev_priv 4519 drivers/gpu/drm/i915/display/intel_display_power.c static void skl_display_core_uninit(struct drm_i915_private *dev_priv) dev_priv 4521 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 4524 drivers/gpu/drm/i915/display/intel_display_power.c gen9_disable_dc_states(dev_priv); dev_priv 4526 drivers/gpu/drm/i915/display/intel_display_power.c gen9_dbuf_disable(dev_priv); dev_priv 4528 drivers/gpu/drm/i915/display/intel_display_power.c intel_cdclk_uninit(dev_priv); dev_priv 4541 drivers/gpu/drm/i915/display/intel_display_power.c well = lookup_power_well(dev_priv, SKL_DISP_PW_1); dev_priv 4542 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_well_disable(dev_priv, well); dev_priv 4549 drivers/gpu/drm/i915/display/intel_display_power.c static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume) dev_priv 4551 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 4554 drivers/gpu/drm/i915/display/intel_display_power.c gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); dev_priv 4562 drivers/gpu/drm/i915/display/intel_display_power.c intel_pch_reset_handshake(dev_priv, false); dev_priv 4567 drivers/gpu/drm/i915/display/intel_display_power.c well = lookup_power_well(dev_priv, SKL_DISP_PW_1); dev_priv 4568 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_well_enable(dev_priv, well); dev_priv 4572 drivers/gpu/drm/i915/display/intel_display_power.c intel_cdclk_init(dev_priv); dev_priv 4574 drivers/gpu/drm/i915/display/intel_display_power.c gen9_dbuf_enable(dev_priv); dev_priv 4576 drivers/gpu/drm/i915/display/intel_display_power.c if (resume && dev_priv->csr.dmc_payload) dev_priv 4577 drivers/gpu/drm/i915/display/intel_display_power.c intel_csr_load_program(dev_priv); dev_priv 4580 drivers/gpu/drm/i915/display/intel_display_power.c static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) dev_priv 4582 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 4585 drivers/gpu/drm/i915/display/intel_display_power.c gen9_disable_dc_states(dev_priv); dev_priv 4587 drivers/gpu/drm/i915/display/intel_display_power.c gen9_dbuf_disable(dev_priv); dev_priv 4589 drivers/gpu/drm/i915/display/intel_display_power.c intel_cdclk_uninit(dev_priv); dev_priv 4600 drivers/gpu/drm/i915/display/intel_display_power.c well = lookup_power_well(dev_priv, SKL_DISP_PW_1); dev_priv 4601 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_well_disable(dev_priv, well); dev_priv 4608 drivers/gpu/drm/i915/display/intel_display_power.c static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume) dev_priv 4610 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 4613 drivers/gpu/drm/i915/display/intel_display_power.c gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); dev_priv 4616 drivers/gpu/drm/i915/display/intel_display_power.c intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); dev_priv 4619 drivers/gpu/drm/i915/display/intel_display_power.c intel_combo_phy_init(dev_priv); dev_priv 4626 drivers/gpu/drm/i915/display/intel_display_power.c well = lookup_power_well(dev_priv, SKL_DISP_PW_1); dev_priv 4627 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_well_enable(dev_priv, well); dev_priv 4631 drivers/gpu/drm/i915/display/intel_display_power.c intel_cdclk_init(dev_priv); dev_priv 4634 drivers/gpu/drm/i915/display/intel_display_power.c gen9_dbuf_enable(dev_priv); dev_priv 4636 drivers/gpu/drm/i915/display/intel_display_power.c if (resume && dev_priv->csr.dmc_payload) dev_priv 4637 drivers/gpu/drm/i915/display/intel_display_power.c intel_csr_load_program(dev_priv); dev_priv 4640 drivers/gpu/drm/i915/display/intel_display_power.c static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) dev_priv 4642 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 4645 drivers/gpu/drm/i915/display/intel_display_power.c gen9_disable_dc_states(dev_priv); dev_priv 4650 drivers/gpu/drm/i915/display/intel_display_power.c gen9_dbuf_disable(dev_priv); dev_priv 4653 drivers/gpu/drm/i915/display/intel_display_power.c intel_cdclk_uninit(dev_priv); dev_priv 4661 drivers/gpu/drm/i915/display/intel_display_power.c well = lookup_power_well(dev_priv, SKL_DISP_PW_1); dev_priv 4662 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_well_disable(dev_priv, well); dev_priv 4668 drivers/gpu/drm/i915/display/intel_display_power.c intel_combo_phy_uninit(dev_priv); dev_priv 4671 drivers/gpu/drm/i915/display/intel_display_power.c static void icl_display_core_init(struct drm_i915_private *dev_priv, dev_priv 4674 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 4677 drivers/gpu/drm/i915/display/intel_display_power.c gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); dev_priv 4680 drivers/gpu/drm/i915/display/intel_display_power.c intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); dev_priv 4683 drivers/gpu/drm/i915/display/intel_display_power.c intel_combo_phy_init(dev_priv); dev_priv 4690 drivers/gpu/drm/i915/display/intel_display_power.c well = lookup_power_well(dev_priv, SKL_DISP_PW_1); dev_priv 4691 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_well_enable(dev_priv, well); dev_priv 4695 drivers/gpu/drm/i915/display/intel_display_power.c intel_cdclk_init(dev_priv); dev_priv 4698 drivers/gpu/drm/i915/display/intel_display_power.c icl_dbuf_enable(dev_priv); dev_priv 4701 drivers/gpu/drm/i915/display/intel_display_power.c icl_mbus_init(dev_priv); dev_priv 4703 drivers/gpu/drm/i915/display/intel_display_power.c if (resume && dev_priv->csr.dmc_payload) dev_priv 4704 drivers/gpu/drm/i915/display/intel_display_power.c intel_csr_load_program(dev_priv); dev_priv 4707 drivers/gpu/drm/i915/display/intel_display_power.c static void icl_display_core_uninit(struct drm_i915_private *dev_priv) dev_priv 4709 drivers/gpu/drm/i915/display/intel_display_power.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 4712 drivers/gpu/drm/i915/display/intel_display_power.c gen9_disable_dc_states(dev_priv); dev_priv 4717 drivers/gpu/drm/i915/display/intel_display_power.c icl_dbuf_disable(dev_priv); dev_priv 4720 drivers/gpu/drm/i915/display/intel_display_power.c intel_cdclk_uninit(dev_priv); dev_priv 4728 drivers/gpu/drm/i915/display/intel_display_power.c well = lookup_power_well(dev_priv, SKL_DISP_PW_1); dev_priv 4729 drivers/gpu/drm/i915/display/intel_display_power.c intel_power_well_disable(dev_priv, well); dev_priv 4733 drivers/gpu/drm/i915/display/intel_display_power.c intel_combo_phy_uninit(dev_priv); dev_priv 4736 drivers/gpu/drm/i915/display/intel_display_power.c static void chv_phy_control_init(struct drm_i915_private *dev_priv) dev_priv 4739 drivers/gpu/drm/i915/display/intel_display_power.c lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); dev_priv 4741 drivers/gpu/drm/i915/display/intel_display_power.c lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D); dev_priv 4750 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control = dev_priv 4764 drivers/gpu/drm/i915/display/intel_display_power.c if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) { dev_priv 4772 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= dev_priv 4775 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= dev_priv 4782 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= dev_priv 4785 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= dev_priv 4788 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); dev_priv 4790 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_assert[DPIO_PHY0] = false; dev_priv 4792 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_assert[DPIO_PHY0] = true; dev_priv 4795 drivers/gpu/drm/i915/display/intel_display_power.c if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) { dev_priv 4804 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= dev_priv 4807 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= dev_priv 4810 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); dev_priv 4812 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_assert[DPIO_PHY1] = false; dev_priv 4814 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_assert[DPIO_PHY1] = true; dev_priv 4817 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); dev_priv 4820 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control); dev_priv 4823 drivers/gpu/drm/i915/display/intel_display_power.c static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) dev_priv 4826 drivers/gpu/drm/i915/display/intel_display_power.c lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); dev_priv 4828 drivers/gpu/drm/i915/display/intel_display_power.c lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D); dev_priv 4831 drivers/gpu/drm/i915/display/intel_display_power.c if (cmn->desc->ops->is_enabled(dev_priv, cmn) && dev_priv 4832 drivers/gpu/drm/i915/display/intel_display_power.c disp2d->desc->ops->is_enabled(dev_priv, disp2d) && dev_priv 4839 drivers/gpu/drm/i915/display/intel_display_power.c disp2d->desc->ops->enable(dev_priv, disp2d); dev_priv 4848 drivers/gpu/drm/i915/display/intel_display_power.c cmn->desc->ops->disable(dev_priv, cmn); dev_priv 4851 drivers/gpu/drm/i915/display/intel_display_power.c static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0) dev_priv 4855 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_get(dev_priv); dev_priv 4856 drivers/gpu/drm/i915/display/intel_display_power.c ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; dev_priv 4857 drivers/gpu/drm/i915/display/intel_display_power.c vlv_punit_put(dev_priv); dev_priv 4862 drivers/gpu/drm/i915/display/intel_display_power.c static void assert_ved_power_gated(struct drm_i915_private *dev_priv) dev_priv 4864 drivers/gpu/drm/i915/display/intel_display_power.c WARN(!vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0), dev_priv 4868 drivers/gpu/drm/i915/display/intel_display_power.c static void assert_isp_power_gated(struct drm_i915_private *dev_priv) dev_priv 4877 drivers/gpu/drm/i915/display/intel_display_power.c !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0), dev_priv 4881 drivers/gpu/drm/i915/display/intel_display_power.c static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv); dev_priv 132 drivers/gpu/drm/i915/display/intel_display_power.h void (*sync_hw)(struct drm_i915_private *dev_priv, dev_priv 139 drivers/gpu/drm/i915/display/intel_display_power.h void (*enable)(struct drm_i915_private *dev_priv, dev_priv 145 drivers/gpu/drm/i915/display/intel_display_power.h void (*disable)(struct drm_i915_private *dev_priv, dev_priv 148 drivers/gpu/drm/i915/display/intel_display_power.h bool (*is_enabled)(struct drm_i915_private *dev_priv, dev_priv 256 drivers/gpu/drm/i915/display/intel_display_power.h int intel_power_domains_init(struct drm_i915_private *dev_priv); dev_priv 257 drivers/gpu/drm/i915/display/intel_display_power.h void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); dev_priv 258 drivers/gpu/drm/i915/display/intel_display_power.h void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); dev_priv 259 drivers/gpu/drm/i915/display/intel_display_power.h void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); dev_priv 260 drivers/gpu/drm/i915/display/intel_display_power.h void intel_power_domains_enable(struct drm_i915_private *dev_priv); dev_priv 261 drivers/gpu/drm/i915/display/intel_display_power.h void intel_power_domains_disable(struct drm_i915_private *dev_priv); dev_priv 262 drivers/gpu/drm/i915/display/intel_display_power.h void intel_power_domains_suspend(struct drm_i915_private *dev_priv, dev_priv 264 drivers/gpu/drm/i915/display/intel_display_power.h void intel_power_domains_resume(struct drm_i915_private *dev_priv); dev_priv 275 drivers/gpu/drm/i915/display/intel_display_power.h bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, dev_priv 277 drivers/gpu/drm/i915/display/intel_display_power.h bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, dev_priv 279 drivers/gpu/drm/i915/display/intel_display_power.h intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, dev_priv 282 drivers/gpu/drm/i915/display/intel_display_power.h intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, dev_priv 284 drivers/gpu/drm/i915/display/intel_display_power.h void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, dev_priv 291 drivers/gpu/drm/i915/display/intel_display_power.h void intel_display_power_put(struct drm_i915_private *dev_priv, dev_priv 323 drivers/gpu/drm/i915/display/intel_display_power.h void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, dev_priv 328 drivers/gpu/drm/i915/display/intel_display_power.h bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, dev_priv 1340 drivers/gpu/drm/i915/display/intel_display_types.h intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv 1342 drivers/gpu/drm/i915/display/intel_display_types.h return dev_priv->pipe_to_crtc_mapping[pipe]; dev_priv 1346 drivers/gpu/drm/i915/display/intel_display_types.h intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane) dev_priv 1348 drivers/gpu/drm/i915/display/intel_display_types.h return dev_priv->plane_to_crtc_mapping[plane]; dev_priv 1508 drivers/gpu/drm/i915/display/intel_display_types.h intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv 1510 drivers/gpu/drm/i915/display/intel_display_types.h drm_wait_one_vblank(&dev_priv->drm, pipe); dev_priv 1513 drivers/gpu/drm/i915/display/intel_display_types.h intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe) dev_priv 1515 drivers/gpu/drm/i915/display/intel_display_types.h const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 1518 drivers/gpu/drm/i915/display/intel_display_types.h intel_wait_for_vblank(dev_priv, pipe); dev_priv 165 drivers/gpu/drm/i915/display/intel_dp.c static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, dev_priv 256 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 257 drivers/gpu/drm/i915/display/intel_dp.c int max_dotclk = dev_priv->max_dotclk_freq; dev_priv 277 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); dev_priv 287 drivers/gpu/drm/i915/display/intel_dp.c if (IS_CNL_WITH_PORT_F(dev_priv)) dev_priv 300 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); dev_priv 301 drivers/gpu/drm/i915/display/intel_dp.c enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); dev_priv 303 drivers/gpu/drm/i915/display/intel_dp.c if (intel_phy_is_combo(dev_priv, phy) && dev_priv 304 drivers/gpu/drm/i915/display/intel_dp.c !IS_ELKHARTLAKE(dev_priv) && dev_priv 331 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); dev_priv 333 drivers/gpu/drm/i915/display/intel_dp.c &dev_priv->vbt.ddi_port_info[dig_port->base.port]; dev_priv 340 drivers/gpu/drm/i915/display/intel_dp.c if (INTEL_GEN(dev_priv) >= 10) { dev_priv 343 drivers/gpu/drm/i915/display/intel_dp.c if (IS_GEN(dev_priv, 10)) dev_priv 347 drivers/gpu/drm/i915/display/intel_dp.c } else if (IS_GEN9_LP(dev_priv)) { dev_priv 350 drivers/gpu/drm/i915/display/intel_dp.c } else if (IS_GEN9_BC(dev_priv)) { dev_priv 353 drivers/gpu/drm/i915/display/intel_dp.c } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || dev_priv 354 drivers/gpu/drm/i915/display/intel_dp.c IS_BROADWELL(dev_priv)) { dev_priv 595 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 627 drivers/gpu/drm/i915/display/intel_dp.c if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) && dev_priv 693 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 700 drivers/gpu/drm/i915/display/intel_dp.c wakeref = intel_display_power_get(dev_priv, dev_priv 703 drivers/gpu/drm/i915/display/intel_dp.c mutex_lock(&dev_priv->pps_mutex); dev_priv 711 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 713 drivers/gpu/drm/i915/display/intel_dp.c mutex_unlock(&dev_priv->pps_mutex); dev_priv 714 drivers/gpu/drm/i915/display/intel_dp.c intel_display_power_put(dev_priv, dev_priv 726 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 750 drivers/gpu/drm/i915/display/intel_dp.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 762 drivers/gpu/drm/i915/display/intel_dp.c release_cl_override = IS_CHERRYVIEW(dev_priv) && dev_priv 763 drivers/gpu/drm/i915/display/intel_dp.c !chv_phy_powergate_ch(dev_priv, phy, ch, true); dev_priv 765 drivers/gpu/drm/i915/display/intel_dp.c if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? dev_priv 789 drivers/gpu/drm/i915/display/intel_dp.c vlv_force_pll_off(dev_priv, pipe); dev_priv 792 drivers/gpu/drm/i915/display/intel_dp.c chv_phy_powergate_ch(dev_priv, phy, ch, false); dev_priv 796 drivers/gpu/drm/i915/display/intel_dp.c static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) dev_priv 805 drivers/gpu/drm/i915/display/intel_dp.c for_each_intel_dp(&dev_priv->drm, encoder) { dev_priv 831 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 835 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 846 drivers/gpu/drm/i915/display/intel_dp.c pipe = vlv_find_free_pps(dev_priv); dev_priv 855 drivers/gpu/drm/i915/display/intel_dp.c vlv_steal_power_sequencer(dev_priv, pipe); dev_priv 878 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 879 drivers/gpu/drm/i915/display/intel_dp.c int backlight_controller = dev_priv->vbt.backlight.controller; dev_priv 881 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 900 drivers/gpu/drm/i915/display/intel_dp.c typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, dev_priv 903 drivers/gpu/drm/i915/display/intel_dp.c static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, dev_priv 909 drivers/gpu/drm/i915/display/intel_dp.c static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, dev_priv 915 drivers/gpu/drm/i915/display/intel_dp.c static bool vlv_pipe_any(struct drm_i915_private *dev_priv, dev_priv 922 drivers/gpu/drm/i915/display/intel_dp.c vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, dev_priv 935 drivers/gpu/drm/i915/display/intel_dp.c if (!pipe_check(dev_priv, pipe)) dev_priv 947 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 951 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 955 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, dev_priv 959 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, dev_priv 963 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, dev_priv 980 drivers/gpu/drm/i915/display/intel_dp.c void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) dev_priv 984 drivers/gpu/drm/i915/display/intel_dp.c if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && dev_priv 985 drivers/gpu/drm/i915/display/intel_dp.c !IS_GEN9_LP(dev_priv))) dev_priv 998 drivers/gpu/drm/i915/display/intel_dp.c for_each_intel_dp(&dev_priv->drm, encoder) { dev_priv 1006 drivers/gpu/drm/i915/display/intel_dp.c if (IS_GEN9_LP(dev_priv)) dev_priv 1024 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1029 drivers/gpu/drm/i915/display/intel_dp.c if (IS_GEN9_LP(dev_priv)) dev_priv 1031 drivers/gpu/drm/i915/display/intel_dp.c else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 1040 drivers/gpu/drm/i915/display/intel_dp.c if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) dev_priv 1073 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1080 drivers/gpu/drm/i915/display/intel_dp.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 1102 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1104 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 1106 drivers/gpu/drm/i915/display/intel_dp.c if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && dev_priv 1115 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1117 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 1119 drivers/gpu/drm/i915/display/intel_dp.c if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && dev_priv 1129 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1166 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1175 drivers/gpu/drm/i915/display/intel_dp.c return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); dev_priv 1180 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1192 drivers/gpu/drm/i915/display/intel_dp.c return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000); dev_priv 1194 drivers/gpu/drm/i915/display/intel_dp.c return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); dev_priv 1199 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1202 drivers/gpu/drm/i915/display/intel_dp.c if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { dev_priv 1229 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dev_priv 1233 drivers/gpu/drm/i915/display/intel_dp.c if (IS_GEN(dev_priv, 6)) dev_priv 1238 drivers/gpu/drm/i915/display/intel_dp.c if (IS_BROADWELL(dev_priv)) dev_priv 1556 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1573 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1590 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1609 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1628 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1648 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1675 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1679 drivers/gpu/drm/i915/display/intel_dp.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 1682 drivers/gpu/drm/i915/display/intel_dp.c } else if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 1690 drivers/gpu/drm/i915/display/intel_dp.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 1692 drivers/gpu/drm/i915/display/intel_dp.c else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) dev_priv 1694 drivers/gpu/drm/i915/display/intel_dp.c else if (HAS_PCH_SPLIT(dev_priv)) dev_priv 1699 drivers/gpu/drm/i915/display/intel_dp.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 1730 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1734 drivers/gpu/drm/i915/display/intel_dp.c if (IS_G4X(dev_priv)) { dev_priv 1737 drivers/gpu/drm/i915/display/intel_dp.c } else if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 1740 drivers/gpu/drm/i915/display/intel_dp.c } else if (IS_CHERRYVIEW(dev_priv)) { dev_priv 1743 drivers/gpu/drm/i915/display/intel_dp.c } else if (IS_VALLEYVIEW(dev_priv)) { dev_priv 1835 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1837 drivers/gpu/drm/i915/display/intel_dp.c return INTEL_GEN(dev_priv) >= 11 && dev_priv 1851 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1853 drivers/gpu/drm/i915/display/intel_dp.c return INTEL_GEN(dev_priv) >= 10 && dev_priv 1870 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1883 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) { dev_priv 1885 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->vbt.edp.bpp); dev_priv 1886 drivers/gpu/drm/i915/display/intel_dp.c bpp = dev_priv->vbt.edp.bpp; dev_priv 2001 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); dev_priv 2065 drivers/gpu/drm/i915/display/intel_dp.c if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { dev_priv 2245 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2258 drivers/gpu/drm/i915/display/intel_dp.c if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) dev_priv 2272 drivers/gpu/drm/i915/display/intel_dp.c if (IS_G4X(dev_priv) || port == PORT_A) dev_priv 2283 drivers/gpu/drm/i915/display/intel_dp.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 2289 drivers/gpu/drm/i915/display/intel_dp.c if (HAS_GMCH(dev_priv)) dev_priv 2300 drivers/gpu/drm/i915/display/intel_dp.c if (HAS_GMCH(dev_priv) && dev_priv 2327 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { dev_priv 2337 drivers/gpu/drm/i915/display/intel_dp.c if (!HAS_DDI(dev_priv)) dev_priv 2358 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2397 drivers/gpu/drm/i915/display/intel_dp.c if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { dev_priv 2408 drivers/gpu/drm/i915/display/intel_dp.c } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { dev_priv 2420 drivers/gpu/drm/i915/display/intel_dp.c if (IS_G4X(dev_priv) && pipe_config->limited_color_range) dev_priv 2432 drivers/gpu/drm/i915/display/intel_dp.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 2454 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 2457 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 2469 drivers/gpu/drm/i915/display/intel_dp.c if (intel_de_wait_for_register(dev_priv, pp_stat_reg, dev_priv 2529 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 2532 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 2535 drivers/gpu/drm/i915/display/intel_dp.c if (WARN_ON(!HAS_DDI(dev_priv) && dev_priv 2550 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 2556 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 2567 drivers/gpu/drm/i915/display/intel_dp.c intel_display_power_get(dev_priv, dev_priv 2622 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 2628 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 2654 drivers/gpu/drm/i915/display/intel_dp.c intel_display_power_put_unchecked(dev_priv, dev_priv 2691 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 2693 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 2711 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 2715 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 2732 drivers/gpu/drm/i915/display/intel_dp.c if (IS_GEN(dev_priv, 5)) { dev_priv 2740 drivers/gpu/drm/i915/display/intel_dp.c if (!IS_GEN(dev_priv, 5)) dev_priv 2749 drivers/gpu/drm/i915/display/intel_dp.c if (IS_GEN(dev_priv, 5)) { dev_priv 2770 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 2775 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 2803 drivers/gpu/drm/i915/display/intel_dp.c intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port)); dev_priv 2820 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 2861 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 2925 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); dev_priv 2935 drivers/gpu/drm/i915/display/intel_dp.c static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) dev_priv 2950 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 2952 drivers/gpu/drm/i915/display/intel_dp.c assert_pipe_disabled(dev_priv, crtc->pipe); dev_priv 2954 drivers/gpu/drm/i915/display/intel_dp.c assert_edp_pll_disabled(dev_priv); dev_priv 2976 drivers/gpu/drm/i915/display/intel_dp.c if (IS_GEN(dev_priv, 5)) dev_priv 2977 drivers/gpu/drm/i915/display/intel_dp.c intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); dev_priv 2990 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 2992 drivers/gpu/drm/i915/display/intel_dp.c assert_pipe_disabled(dev_priv, crtc->pipe); dev_priv 2994 drivers/gpu/drm/i915/display/intel_dp.c assert_edp_pll_enabled(dev_priv); dev_priv 3075 drivers/gpu/drm/i915/display/intel_dp.c static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, dev_priv 3080 drivers/gpu/drm/i915/display/intel_dp.c for_each_pipe(dev_priv, p) { dev_priv 3097 drivers/gpu/drm/i915/display/intel_dp.c bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, dev_priv 3109 drivers/gpu/drm/i915/display/intel_dp.c if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) dev_priv 3111 drivers/gpu/drm/i915/display/intel_dp.c else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) dev_priv 3112 drivers/gpu/drm/i915/display/intel_dp.c ret &= cpt_dp_port_selected(dev_priv, port, pipe); dev_priv 3113 drivers/gpu/drm/i915/display/intel_dp.c else if (IS_CHERRYVIEW(dev_priv)) dev_priv 3124 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3129 drivers/gpu/drm/i915/display/intel_dp.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 3134 drivers/gpu/drm/i915/display/intel_dp.c ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg, dev_priv 3137 drivers/gpu/drm/i915/display/intel_dp.c intel_display_power_put(dev_priv, encoder->power_domain, wakeref); dev_priv 3145 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3160 drivers/gpu/drm/i915/display/intel_dp.c if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { dev_priv 3186 drivers/gpu/drm/i915/display/intel_dp.c if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) dev_priv 3205 drivers/gpu/drm/i915/display/intel_dp.c if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp && dev_priv 3206 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { dev_priv 3221 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); dev_priv 3222 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; dev_priv 3291 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3295 drivers/gpu/drm/i915/display/intel_dp.c vlv_dpio_get(dev_priv); dev_priv 3300 drivers/gpu/drm/i915/display/intel_dp.c vlv_dpio_put(dev_priv); dev_priv 3308 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 3317 drivers/gpu/drm/i915/display/intel_dp.c if (HAS_DDI(dev_priv)) { dev_priv 3346 drivers/gpu/drm/i915/display/intel_dp.c } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || dev_priv 3347 drivers/gpu/drm/i915/display/intel_dp.c (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { dev_priv 3390 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 3414 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3425 drivers/gpu/drm/i915/display/intel_dp.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 3435 drivers/gpu/drm/i915/display/intel_dp.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 3438 drivers/gpu/drm/i915/display/intel_dp.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 3441 drivers/gpu/drm/i915/display/intel_dp.c vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), dev_priv 3488 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); dev_priv 3516 drivers/gpu/drm/i915/display/intel_dp.c static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, dev_priv 3521 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 3523 drivers/gpu/drm/i915/display/intel_dp.c for_each_intel_dp(&dev_priv->drm, encoder) { dev_priv 3545 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3549 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 3567 drivers/gpu/drm/i915/display/intel_dp.c vlv_steal_power_sequencer(dev_priv, crtc->pipe); dev_priv 3646 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 3650 drivers/gpu/drm/i915/display/intel_dp.c if (HAS_DDI(dev_priv)) dev_priv 3652 drivers/gpu/drm/i915/display/intel_dp.c else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 3654 drivers/gpu/drm/i915/display/intel_dp.c else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) dev_priv 3656 drivers/gpu/drm/i915/display/intel_dp.c else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) dev_priv 3665 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 3669 drivers/gpu/drm/i915/display/intel_dp.c if (HAS_DDI(dev_priv)) { dev_priv 3671 drivers/gpu/drm/i915/display/intel_dp.c } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 3683 drivers/gpu/drm/i915/display/intel_dp.c } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { dev_priv 3977 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 3983 drivers/gpu/drm/i915/display/intel_dp.c if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) { dev_priv 3985 drivers/gpu/drm/i915/display/intel_dp.c } else if (HAS_DDI(dev_priv)) { dev_priv 3988 drivers/gpu/drm/i915/display/intel_dp.c } else if (IS_CHERRYVIEW(dev_priv)) { dev_priv 3990 drivers/gpu/drm/i915/display/intel_dp.c } else if (IS_VALLEYVIEW(dev_priv)) { dev_priv 3992 drivers/gpu/drm/i915/display/intel_dp.c } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { dev_priv 3995 drivers/gpu/drm/i915/display/intel_dp.c } else if (IS_GEN(dev_priv, 6) && port == PORT_A) { dev_priv 4023 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dev_priv 4034 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 4039 drivers/gpu/drm/i915/display/intel_dp.c if (!HAS_DDI(dev_priv)) dev_priv 4057 drivers/gpu/drm/i915/display/intel_dp.c if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port), dev_priv 4066 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 4077 drivers/gpu/drm/i915/display/intel_dp.c if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || dev_priv 4078 drivers/gpu/drm/i915/display/intel_dp.c (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { dev_priv 4097 drivers/gpu/drm/i915/display/intel_dp.c if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { dev_priv 4102 drivers/gpu/drm/i915/display/intel_dp.c intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); dev_priv 4103 drivers/gpu/drm/i915/display/intel_dp.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); dev_priv 4116 drivers/gpu/drm/i915/display/intel_dp.c intel_wait_for_vblank_if_active(dev_priv, PIPE_A); dev_priv 4117 drivers/gpu/drm/i915/display/intel_dp.c intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); dev_priv 4118 drivers/gpu/drm/i915/display/intel_dp.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); dev_priv 4125 drivers/gpu/drm/i915/display/intel_dp.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 4230 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dev_priv 4300 drivers/gpu/drm/i915/display/intel_dp.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 4796 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 4809 drivers/gpu/drm/i915/display/intel_dp.c ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, dev_priv 4839 drivers/gpu/drm/i915/display/intel_dp.c intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); dev_priv 4841 drivers/gpu/drm/i915/display/intel_dp.c intel_set_pch_fifo_underrun_reporting(dev_priv, dev_priv 4848 drivers/gpu/drm/i915/display/intel_dp.c intel_wait_for_vblank(dev_priv, crtc->pipe); dev_priv 4850 drivers/gpu/drm/i915/display/intel_dp.c intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); dev_priv 4852 drivers/gpu/drm/i915/display/intel_dp.c intel_set_pch_fifo_underrun_reporting(dev_priv, dev_priv 4947 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 4984 drivers/gpu/drm/i915/display/intel_dp.c drm_kms_helper_hotplug_event(&dev_priv->drm); dev_priv 5053 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 5076 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 5099 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 5118 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 5141 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 5164 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 5174 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 5184 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 5194 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 5204 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 5225 drivers/gpu/drm/i915/display/intel_dp.c static bool icl_combo_port_connected(struct drm_i915_private *dev_priv, dev_priv 5235 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 5237 drivers/gpu/drm/i915/display/intel_dp.c enum phy phy = intel_port_to_phy(dev_priv, encoder->port); dev_priv 5239 drivers/gpu/drm/i915/display/intel_dp.c if (intel_phy_is_combo(dev_priv, phy)) dev_priv 5240 drivers/gpu/drm/i915/display/intel_dp.c return icl_combo_port_connected(dev_priv, dig_port); dev_priv 5241 drivers/gpu/drm/i915/display/intel_dp.c else if (intel_phy_is_tc(dev_priv, phy)) dev_priv 5262 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 5264 drivers/gpu/drm/i915/display/intel_dp.c if (HAS_GMCH(dev_priv)) { dev_priv 5265 drivers/gpu/drm/i915/display/intel_dp.c if (IS_GM45(dev_priv)) dev_priv 5271 drivers/gpu/drm/i915/display/intel_dp.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 5273 drivers/gpu/drm/i915/display/intel_dp.c else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) dev_priv 5275 drivers/gpu/drm/i915/display/intel_dp.c else if (IS_GEN9_LP(dev_priv)) dev_priv 5277 drivers/gpu/drm/i915/display/intel_dp.c else if (IS_GEN(dev_priv, 8)) dev_priv 5279 drivers/gpu/drm/i915/display/intel_dp.c else if (IS_GEN(dev_priv, 7)) dev_priv 5281 drivers/gpu/drm/i915/display/intel_dp.c else if (IS_GEN(dev_priv, 6)) dev_priv 5283 drivers/gpu/drm/i915/display/intel_dp.c else if (IS_GEN(dev_priv, 5)) dev_priv 5286 drivers/gpu/drm/i915/display/intel_dp.c MISSING_CASE(INTEL_GEN(dev_priv)); dev_priv 5292 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 5296 drivers/gpu/drm/i915/display/intel_dp.c with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) dev_priv 5350 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 5358 drivers/gpu/drm/i915/display/intel_dp.c WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); dev_priv 5397 drivers/gpu/drm/i915/display/intel_dp.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 5447 drivers/gpu/drm/i915/display/intel_dp.c intel_display_power_flush_work(dev_priv); dev_priv 5458 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); dev_priv 5470 drivers/gpu/drm/i915/display/intel_dp.c wakeref = intel_display_power_get(dev_priv, aux_domain); dev_priv 5474 drivers/gpu/drm/i915/display/intel_dp.c intel_display_power_put(dev_priv, aux_domain, wakeref); dev_priv 6180 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 6183 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 6195 drivers/gpu/drm/i915/display/intel_dp.c intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port)); dev_priv 6202 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 6206 drivers/gpu/drm/i915/display/intel_dp.c if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg, dev_priv 6215 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->dev); dev_priv 6220 drivers/gpu/drm/i915/display/intel_dp.c if (!HAS_DDI(dev_priv)) dev_priv 6228 drivers/gpu/drm/i915/display/intel_dp.c if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && dev_priv 6233 drivers/gpu/drm/i915/display/intel_dp.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 6326 drivers/gpu/drm/i915/display/intel_dp.c bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port) dev_priv 6332 drivers/gpu/drm/i915/display/intel_dp.c if (INTEL_GEN(dev_priv) < 5) dev_priv 6335 drivers/gpu/drm/i915/display/intel_dp.c if (INTEL_GEN(dev_priv) < 9 && port == PORT_A) dev_priv 6338 drivers/gpu/drm/i915/display/intel_dp.c return intel_bios_is_port_edp(dev_priv, port); dev_priv 6344 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 6347 drivers/gpu/drm/i915/display/intel_dp.c if (!IS_G4X(dev_priv) && port != PORT_A) dev_priv 6351 drivers/gpu/drm/i915/display/intel_dp.c if (HAS_GMCH(dev_priv)) dev_priv 6353 drivers/gpu/drm/i915/display/intel_dp.c else if (INTEL_GEN(dev_priv) >= 5) dev_priv 6360 drivers/gpu/drm/i915/display/intel_dp.c if (!HAS_GMCH(dev_priv)) dev_priv 6380 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 6389 drivers/gpu/drm/i915/display/intel_dp.c if (!HAS_DDI(dev_priv)) dev_priv 6439 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 6443 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 6453 drivers/gpu/drm/i915/display/intel_dp.c vbt = dev_priv->vbt.edp.pps; dev_priv 6459 drivers/gpu/drm/i915/display/intel_dp.c if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) { dev_priv 6532 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 6534 drivers/gpu/drm/i915/display/intel_dp.c int div = dev_priv->rawclk_freq / 1000; dev_priv 6539 drivers/gpu/drm/i915/display/intel_dp.c lockdep_assert_held(&dev_priv->pps_mutex); dev_priv 6575 drivers/gpu/drm/i915/display/intel_dp.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 6577 drivers/gpu/drm/i915/display/intel_dp.c } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { dev_priv 6625 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 6627 drivers/gpu/drm/i915/display/intel_dp.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 6648 drivers/gpu/drm/i915/display/intel_dp.c static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, dev_priv 6652 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = dev_priv->drrs.dp; dev_priv 6671 drivers/gpu/drm/i915/display/intel_dp.c if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { dev_priv 6680 drivers/gpu/drm/i915/display/intel_dp.c if (index == dev_priv->drrs.refresh_rate_type) { dev_priv 6691 drivers/gpu/drm/i915/display/intel_dp.c if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { dev_priv 6703 drivers/gpu/drm/i915/display/intel_dp.c } else if (INTEL_GEN(dev_priv) > 6) { dev_priv 6709 drivers/gpu/drm/i915/display/intel_dp.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 6714 drivers/gpu/drm/i915/display/intel_dp.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 6722 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->drrs.refresh_rate_type = index; dev_priv 6737 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 6744 drivers/gpu/drm/i915/display/intel_dp.c if (dev_priv->psr.enabled) { dev_priv 6749 drivers/gpu/drm/i915/display/intel_dp.c mutex_lock(&dev_priv->drrs.mutex); dev_priv 6750 drivers/gpu/drm/i915/display/intel_dp.c if (dev_priv->drrs.dp) { dev_priv 6755 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->drrs.busy_frontbuffer_bits = 0; dev_priv 6757 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->drrs.dp = intel_dp; dev_priv 6760 drivers/gpu/drm/i915/display/intel_dp.c mutex_unlock(&dev_priv->drrs.mutex); dev_priv 6772 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 6777 drivers/gpu/drm/i915/display/intel_dp.c mutex_lock(&dev_priv->drrs.mutex); dev_priv 6778 drivers/gpu/drm/i915/display/intel_dp.c if (!dev_priv->drrs.dp) { dev_priv 6779 drivers/gpu/drm/i915/display/intel_dp.c mutex_unlock(&dev_priv->drrs.mutex); dev_priv 6783 drivers/gpu/drm/i915/display/intel_dp.c if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) dev_priv 6784 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_set_drrs_state(dev_priv, old_crtc_state, dev_priv 6787 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->drrs.dp = NULL; dev_priv 6788 drivers/gpu/drm/i915/display/intel_dp.c mutex_unlock(&dev_priv->drrs.mutex); dev_priv 6790 drivers/gpu/drm/i915/display/intel_dp.c cancel_delayed_work_sync(&dev_priv->drrs.work); dev_priv 6795 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dev_priv 6796 drivers/gpu/drm/i915/display/intel_dp.c container_of(work, typeof(*dev_priv), drrs.work.work); dev_priv 6799 drivers/gpu/drm/i915/display/intel_dp.c mutex_lock(&dev_priv->drrs.mutex); dev_priv 6801 drivers/gpu/drm/i915/display/intel_dp.c intel_dp = dev_priv->drrs.dp; dev_priv 6811 drivers/gpu/drm/i915/display/intel_dp.c if (dev_priv->drrs.busy_frontbuffer_bits) dev_priv 6814 drivers/gpu/drm/i915/display/intel_dp.c if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { dev_priv 6817 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, dev_priv 6822 drivers/gpu/drm/i915/display/intel_dp.c mutex_unlock(&dev_priv->drrs.mutex); dev_priv 6835 drivers/gpu/drm/i915/display/intel_dp.c void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, dev_priv 6841 drivers/gpu/drm/i915/display/intel_dp.c if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) dev_priv 6844 drivers/gpu/drm/i915/display/intel_dp.c cancel_delayed_work(&dev_priv->drrs.work); dev_priv 6846 drivers/gpu/drm/i915/display/intel_dp.c mutex_lock(&dev_priv->drrs.mutex); dev_priv 6847 drivers/gpu/drm/i915/display/intel_dp.c if (!dev_priv->drrs.dp) { dev_priv 6848 drivers/gpu/drm/i915/display/intel_dp.c mutex_unlock(&dev_priv->drrs.mutex); dev_priv 6852 drivers/gpu/drm/i915/display/intel_dp.c crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; dev_priv 6856 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; dev_priv 6859 drivers/gpu/drm/i915/display/intel_dp.c if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) dev_priv 6860 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, dev_priv 6861 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); dev_priv 6863 drivers/gpu/drm/i915/display/intel_dp.c mutex_unlock(&dev_priv->drrs.mutex); dev_priv 6878 drivers/gpu/drm/i915/display/intel_dp.c void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, dev_priv 6884 drivers/gpu/drm/i915/display/intel_dp.c if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) dev_priv 6887 drivers/gpu/drm/i915/display/intel_dp.c cancel_delayed_work(&dev_priv->drrs.work); dev_priv 6889 drivers/gpu/drm/i915/display/intel_dp.c mutex_lock(&dev_priv->drrs.mutex); dev_priv 6890 drivers/gpu/drm/i915/display/intel_dp.c if (!dev_priv->drrs.dp) { dev_priv 6891 drivers/gpu/drm/i915/display/intel_dp.c mutex_unlock(&dev_priv->drrs.mutex); dev_priv 6895 drivers/gpu/drm/i915/display/intel_dp.c crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; dev_priv 6899 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; dev_priv 6902 drivers/gpu/drm/i915/display/intel_dp.c if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) dev_priv 6903 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, dev_priv 6904 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); dev_priv 6910 drivers/gpu/drm/i915/display/intel_dp.c if (!dev_priv->drrs.busy_frontbuffer_bits) dev_priv 6911 drivers/gpu/drm/i915/display/intel_dp.c schedule_delayed_work(&dev_priv->drrs.work, dev_priv 6913 drivers/gpu/drm/i915/display/intel_dp.c mutex_unlock(&dev_priv->drrs.mutex); dev_priv 6970 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 6973 drivers/gpu/drm/i915/display/intel_dp.c INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); dev_priv 6974 drivers/gpu/drm/i915/display/intel_dp.c mutex_init(&dev_priv->drrs.mutex); dev_priv 6976 drivers/gpu/drm/i915/display/intel_dp.c if (INTEL_GEN(dev_priv) <= 6) { dev_priv 6981 drivers/gpu/drm/i915/display/intel_dp.c if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { dev_priv 6992 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->drrs.type = dev_priv->vbt.drrs_type; dev_priv 6994 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; dev_priv 7002 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 7003 drivers/gpu/drm/i915/display/intel_dp.c struct drm_device *dev = &dev_priv->drm; dev_priv 7023 drivers/gpu/drm/i915/display/intel_dp.c if (intel_get_lvds_encoder(dev_priv)) { dev_priv 7024 drivers/gpu/drm/i915/display/intel_dp.c WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); dev_priv 7069 drivers/gpu/drm/i915/display/intel_dp.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 7143 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 7145 drivers/gpu/drm/i915/display/intel_dp.c enum phy phy = intel_port_to_phy(dev_priv, port); dev_priv 7167 drivers/gpu/drm/i915/display/intel_dp.c if (intel_dp_is_port_edp(dev_priv, port)) { dev_priv 7172 drivers/gpu/drm/i915/display/intel_dp.c WARN_ON(intel_phy_is_tc(dev_priv, phy)); dev_priv 7178 drivers/gpu/drm/i915/display/intel_dp.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 7190 drivers/gpu/drm/i915/display/intel_dp.c if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && dev_priv 7202 drivers/gpu/drm/i915/display/intel_dp.c if (!HAS_GMCH(dev_priv)) dev_priv 7206 drivers/gpu/drm/i915/display/intel_dp.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 7209 drivers/gpu/drm/i915/display/intel_dp.c intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); dev_priv 7215 drivers/gpu/drm/i915/display/intel_dp.c if (HAS_DDI(dev_priv)) dev_priv 7232 drivers/gpu/drm/i915/display/intel_dp.c if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { dev_priv 7242 drivers/gpu/drm/i915/display/intel_dp.c if (IS_G45(dev_priv)) { dev_priv 7255 drivers/gpu/drm/i915/display/intel_dp.c bool intel_dp_init(struct drm_i915_private *dev_priv, dev_priv 7275 drivers/gpu/drm/i915/display/intel_dp.c if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, dev_priv 7286 drivers/gpu/drm/i915/display/intel_dp.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 7293 drivers/gpu/drm/i915/display/intel_dp.c } else if (IS_VALLEYVIEW(dev_priv)) { dev_priv 7311 drivers/gpu/drm/i915/display/intel_dp.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 7327 drivers/gpu/drm/i915/display/intel_dp.c intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); dev_priv 7342 drivers/gpu/drm/i915/display/intel_dp.c void intel_dp_mst_suspend(struct drm_i915_private *dev_priv) dev_priv 7346 drivers/gpu/drm/i915/display/intel_dp.c for_each_intel_encoder(&dev_priv->drm, encoder) { dev_priv 7362 drivers/gpu/drm/i915/display/intel_dp.c void intel_dp_mst_resume(struct drm_i915_private *dev_priv) dev_priv 7366 drivers/gpu/drm/i915/display/intel_dp.c for_each_intel_encoder(&dev_priv->drm, encoder) { dev_priv 38 drivers/gpu/drm/i915/display/intel_dp.h bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, dev_priv 41 drivers/gpu/drm/i915/display/intel_dp.h bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, dev_priv 63 drivers/gpu/drm/i915/display/intel_dp.h bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); dev_priv 72 drivers/gpu/drm/i915/display/intel_dp.h void intel_dp_mst_suspend(struct drm_i915_private *dev_priv); dev_priv 73 drivers/gpu/drm/i915/display/intel_dp.h void intel_dp_mst_resume(struct drm_i915_private *dev_priv); dev_priv 77 drivers/gpu/drm/i915/display/intel_dp.h void intel_power_sequencer_reset(struct drm_i915_private *dev_priv); dev_priv 84 drivers/gpu/drm/i915/display/intel_dp.h void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, dev_priv 86 drivers/gpu/drm/i915/display/intel_dp.h void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, dev_priv 112 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 121 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c freq = dev_priv->vbt.backlight.pwm_freq_hz; dev_priv 267 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c struct drm_i915_private *dev_priv = to_i915(intel_connector->base.dev); dev_priv 271 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c dev_priv->vbt.backlight.type != INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE)) dev_priv 94 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 151 drivers/gpu/drm/i915/display/intel_dp_mst.c if (IS_GEN9_LP(dev_priv)) dev_priv 155 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); dev_priv 297 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 344 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 349 drivers/gpu/drm/i915/display/intel_dp_mst.c if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port), dev_priv 504 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 529 drivers/gpu/drm/i915/display/intel_dp_mst.c for_each_pipe(dev_priv, pipe) { dev_priv 566 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 568 drivers/gpu/drm/i915/display/intel_dp_mst.c if (dev_priv->fbdev) dev_priv 569 drivers/gpu/drm/i915/display/intel_dp_mst.c drm_fb_helper_add_one_connector(&dev_priv->fbdev->helper, dev_priv 578 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 583 drivers/gpu/drm/i915/display/intel_dp_mst.c if (dev_priv->fbdev) dev_priv 584 drivers/gpu/drm/i915/display/intel_dp_mst.c drm_fb_helper_remove_one_connector(&dev_priv->fbdev->helper, dev_priv 639 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); dev_priv 642 drivers/gpu/drm/i915/display/intel_dp_mst.c for_each_pipe(dev_priv, pipe) dev_priv 216 drivers/gpu/drm/i915/display/intel_dpio_phy.c bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count) dev_priv 218 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (IS_GEMINILAKE(dev_priv)) { dev_priv 228 drivers/gpu/drm/i915/display/intel_dpio_phy.c bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy) dev_priv 232 drivers/gpu/drm/i915/display/intel_dpio_phy.c bxt_get_phy_list(dev_priv, &count); dev_priv 237 drivers/gpu/drm/i915/display/intel_dpio_phy.c void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, dev_priv 243 drivers/gpu/drm/i915/display/intel_dpio_phy.c phys = bxt_get_phy_list(dev_priv, &count); dev_priv 267 drivers/gpu/drm/i915/display/intel_dpio_phy.c void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, dev_priv 275 drivers/gpu/drm/i915/display/intel_dpio_phy.c bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); dev_priv 310 drivers/gpu/drm/i915/display/intel_dpio_phy.c bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, dev_priv 315 drivers/gpu/drm/i915/display/intel_dpio_phy.c phy_info = bxt_get_phy_info(dev_priv, phy); dev_priv 338 drivers/gpu/drm/i915/display/intel_dpio_phy.c static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy) dev_priv 345 drivers/gpu/drm/i915/display/intel_dpio_phy.c static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv, dev_priv 348 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy), dev_priv 353 drivers/gpu/drm/i915/display/intel_dpio_phy.c static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, dev_priv 359 drivers/gpu/drm/i915/display/intel_dpio_phy.c phy_info = bxt_get_phy_info(dev_priv, phy); dev_priv 361 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (bxt_ddi_phy_is_enabled(dev_priv, phy)) { dev_priv 364 drivers/gpu/drm/i915/display/intel_dpio_phy.c dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy); dev_priv 366 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (bxt_ddi_phy_verify_state(dev_priv, phy)) { dev_priv 388 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (intel_wait_for_register_fw(&dev_priv->uncore, dev_priv 421 drivers/gpu/drm/i915/display/intel_dpio_phy.c bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy); dev_priv 428 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, dev_priv 448 drivers/gpu/drm/i915/display/intel_dpio_phy.c void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) dev_priv 453 drivers/gpu/drm/i915/display/intel_dpio_phy.c phy_info = bxt_get_phy_info(dev_priv, phy); dev_priv 464 drivers/gpu/drm/i915/display/intel_dpio_phy.c void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) dev_priv 467 drivers/gpu/drm/i915/display/intel_dpio_phy.c bxt_get_phy_info(dev_priv, phy); dev_priv 471 drivers/gpu/drm/i915/display/intel_dpio_phy.c lockdep_assert_held(&dev_priv->power_domains.lock); dev_priv 475 drivers/gpu/drm/i915/display/intel_dpio_phy.c was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy); dev_priv 482 drivers/gpu/drm/i915/display/intel_dpio_phy.c _bxt_ddi_phy_init(dev_priv, rcomp_phy); dev_priv 484 drivers/gpu/drm/i915/display/intel_dpio_phy.c _bxt_ddi_phy_init(dev_priv, phy); dev_priv 487 drivers/gpu/drm/i915/display/intel_dpio_phy.c bxt_ddi_phy_uninit(dev_priv, rcomp_phy); dev_priv 491 drivers/gpu/drm/i915/display/intel_dpio_phy.c __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, dev_priv 517 drivers/gpu/drm/i915/display/intel_dpio_phy.c bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, dev_priv 524 drivers/gpu/drm/i915/display/intel_dpio_phy.c phy_info = bxt_get_phy_info(dev_priv, phy); dev_priv 527 drivers/gpu/drm/i915/display/intel_dpio_phy.c __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \ dev_priv 530 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (!bxt_ddi_phy_is_enabled(dev_priv, phy)) dev_priv 554 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 grc_code = dev_priv->bxt_phy_grc; dev_priv 593 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 599 drivers/gpu/drm/i915/display/intel_dpio_phy.c bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); dev_priv 619 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 626 drivers/gpu/drm/i915/display/intel_dpio_phy.c bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); dev_priv 644 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 652 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_get(dev_priv); dev_priv 655 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); dev_priv 659 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); dev_priv 662 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); dev_priv 666 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); dev_priv 669 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); dev_priv 672 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); dev_priv 675 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); dev_priv 678 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); dev_priv 683 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); dev_priv 686 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); dev_priv 691 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); dev_priv 704 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); dev_priv 714 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); dev_priv 719 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); dev_priv 723 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); dev_priv 725 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); dev_priv 728 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); dev_priv 730 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); dev_priv 733 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_put(dev_priv); dev_priv 740 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 746 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); dev_priv 751 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); dev_priv 754 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); dev_priv 759 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); dev_priv 762 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); dev_priv 768 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); dev_priv 771 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); dev_priv 777 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); dev_priv 785 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 799 drivers/gpu/drm/i915/display/intel_dpio_phy.c !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); dev_priv 803 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_get(dev_priv); dev_priv 810 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); dev_priv 816 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); dev_priv 818 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); dev_priv 824 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); dev_priv 828 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); dev_priv 834 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); dev_priv 837 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); dev_priv 843 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); dev_priv 851 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); dev_priv 856 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); dev_priv 858 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_put(dev_priv); dev_priv 866 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 873 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_get(dev_priv); dev_priv 876 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); dev_priv 878 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); dev_priv 881 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); dev_priv 883 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); dev_priv 893 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), dev_priv 909 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); dev_priv 911 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); dev_priv 914 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); dev_priv 916 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); dev_priv 919 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), dev_priv 927 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), dev_priv 938 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_put(dev_priv); dev_priv 944 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 947 drivers/gpu/drm/i915/display/intel_dpio_phy.c chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); dev_priv 955 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 959 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_get(dev_priv); dev_priv 963 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); dev_priv 965 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); dev_priv 967 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); dev_priv 969 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); dev_priv 972 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_put(dev_priv); dev_priv 990 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 996 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_get(dev_priv); dev_priv 998 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); dev_priv 999 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); dev_priv 1000 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), dev_priv 1002 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); dev_priv 1005 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph); dev_priv 1007 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); dev_priv 1008 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); dev_priv 1009 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); dev_priv 1011 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_put(dev_priv); dev_priv 1018 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1024 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_get(dev_priv); dev_priv 1026 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), dev_priv 1029 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), dev_priv 1036 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); dev_priv 1037 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); dev_priv 1038 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); dev_priv 1040 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_put(dev_priv); dev_priv 1048 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1054 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_get(dev_priv); dev_priv 1057 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); dev_priv 1064 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); dev_priv 1067 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); dev_priv 1068 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); dev_priv 1070 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_put(dev_priv); dev_priv 1077 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1082 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_get(dev_priv); dev_priv 1083 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); dev_priv 1084 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); dev_priv 1085 drivers/gpu/drm/i915/display/intel_dpio_phy.c vlv_dpio_put(dev_priv); dev_priv 18 drivers/gpu/drm/i915/display/intel_dpio_phy.h void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, dev_priv 20 drivers/gpu/drm/i915/display/intel_dpio_phy.h void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, dev_priv 23 drivers/gpu/drm/i915/display/intel_dpio_phy.h void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); dev_priv 24 drivers/gpu/drm/i915/display/intel_dpio_phy.h void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); dev_priv 25 drivers/gpu/drm/i915/display/intel_dpio_phy.h bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, dev_priv 27 drivers/gpu/drm/i915/display/intel_dpio_phy.h bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, dev_priv 49 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv, dev_priv 55 drivers/gpu/drm/i915/display/intel_dpll_mgr.c for (i = 0; i < dev_priv->num_shared_dpll; i++) { dev_priv 56 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; dev_priv 88 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, dev_priv 91 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return &dev_priv->shared_dplls[id]; dev_priv 103 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, dev_priv 106 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (WARN_ON(pll < dev_priv->shared_dplls|| dev_priv 107 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll])) dev_priv 110 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return (enum intel_dpll_id) (pll - dev_priv->shared_dplls); dev_priv 114 drivers/gpu/drm/i915/display/intel_dpll_mgr.c void assert_shared_dpll(struct drm_i915_private *dev_priv, dev_priv 124 drivers/gpu/drm/i915/display/intel_dpll_mgr.c cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state); dev_priv 140 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 146 drivers/gpu/drm/i915/display/intel_dpll_mgr.c mutex_lock(&dev_priv->dpll_lock); dev_priv 151 drivers/gpu/drm/i915/display/intel_dpll_mgr.c assert_shared_dpll_disabled(dev_priv, pll); dev_priv 153 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->funcs->prepare(dev_priv, pll); dev_priv 155 drivers/gpu/drm/i915/display/intel_dpll_mgr.c mutex_unlock(&dev_priv->dpll_lock); dev_priv 167 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 175 drivers/gpu/drm/i915/display/intel_dpll_mgr.c mutex_lock(&dev_priv->dpll_lock); dev_priv 190 drivers/gpu/drm/i915/display/intel_dpll_mgr.c assert_shared_dpll_enabled(dev_priv, pll); dev_priv 196 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->funcs->enable(dev_priv, pll); dev_priv 200 drivers/gpu/drm/i915/display/intel_dpll_mgr.c mutex_unlock(&dev_priv->dpll_lock); dev_priv 212 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 217 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (INTEL_GEN(dev_priv) < 5) dev_priv 223 drivers/gpu/drm/i915/display/intel_dpll_mgr.c mutex_lock(&dev_priv->dpll_lock); dev_priv 231 drivers/gpu/drm/i915/display/intel_dpll_mgr.c assert_shared_dpll_enabled(dev_priv, pll); dev_priv 239 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->funcs->disable(dev_priv, pll); dev_priv 243 drivers/gpu/drm/i915/display/intel_dpll_mgr.c mutex_unlock(&dev_priv->dpll_lock); dev_priv 253 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 261 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = &dev_priv->shared_dplls[i]; dev_priv 352 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 359 drivers/gpu/drm/i915/display/intel_dpll_mgr.c for (i = 0; i < dev_priv->num_shared_dpll; i++) { dev_priv 361 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &dev_priv->shared_dplls[i]; dev_priv 367 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 375 drivers/gpu/drm/i915/display/intel_dpll_mgr.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 385 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); dev_priv 390 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv, dev_priv 399 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) dev_priv 404 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); dev_priv 412 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, dev_priv 418 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ibx_assert_pch_refclk_enabled(dev_priv); dev_priv 436 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, dev_priv 452 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 456 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (HAS_PCH_IBX(dev_priv)) { dev_priv 459 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = &dev_priv->shared_dplls[i]; dev_priv 483 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void ibx_dump_hw_state(struct drm_i915_private *dev_priv, dev_priv 501 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, dev_priv 511 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, dev_priv 519 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, dev_priv 533 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (dev_priv->pch_ssc_use & BIT(id)) dev_priv 534 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_init_pch_refclk(dev_priv); dev_priv 537 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, dev_priv 551 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (dev_priv->pch_ssc_use & BIT(id)) dev_priv 552 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_init_pch_refclk(dev_priv); dev_priv 555 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 563 drivers/gpu/drm/i915/display/intel_dpll_mgr.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 571 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); dev_priv 576 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 583 drivers/gpu/drm/i915/display/intel_dpll_mgr.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 591 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); dev_priv 843 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 863 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = intel_get_shared_dpll_by_id(dev_priv, pll_id); dev_priv 911 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void hsw_dump_hw_state(struct drm_i915_private *dev_priv, dev_priv 930 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv, dev_priv 935 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv, dev_priv 940 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 984 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv, dev_priv 1001 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, dev_priv 1007 drivers/gpu/drm/i915/display/intel_dpll_mgr.c skl_ddi_pll_write_ctrl1(dev_priv, pll); dev_priv 1018 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_de_wait_for_set(dev_priv, DPLL_STATUS, DPLL_LOCK(id), 5)) dev_priv 1022 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv, dev_priv 1025 drivers/gpu/drm/i915/display/intel_dpll_mgr.c skl_ddi_pll_write_ctrl1(dev_priv, pll); dev_priv 1028 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, dev_priv 1040 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv, dev_priv 1045 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 1055 drivers/gpu/drm/i915/display/intel_dpll_mgr.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 1077 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); dev_priv 1082 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 1092 drivers/gpu/drm/i915/display/intel_dpll_mgr.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 1110 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); dev_priv 1483 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void skl_dump_hw_state(struct drm_i915_private *dev_priv, dev_priv 1505 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, dev_priv 1513 drivers/gpu/drm/i915/display/intel_dpll_mgr.c bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); dev_priv 1520 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (IS_GEMINILAKE(dev_priv)) { dev_priv 1608 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (IS_GEMINILAKE(dev_priv)) { dev_priv 1625 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, dev_priv 1636 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (IS_GEMINILAKE(dev_priv)) { dev_priv 1647 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 1658 drivers/gpu/drm/i915/display/intel_dpll_mgr.c bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); dev_priv 1660 drivers/gpu/drm/i915/display/intel_dpll_mgr.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 1719 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); dev_priv 1892 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1906 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = intel_get_shared_dpll_by_id(dev_priv, id); dev_priv 1919 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void bxt_dump_hw_state(struct drm_i915_private *dev_priv, dev_priv 1955 drivers/gpu/drm/i915/display/intel_dpll_mgr.c void (*dump_hw_state)(struct drm_i915_private *dev_priv, dev_priv 2018 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv, dev_priv 2030 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), dev_priv 2068 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5)) dev_priv 2086 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv, dev_priv 2112 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5)) dev_priv 2130 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), dev_priv 2135 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 2144 drivers/gpu/drm/i915/display/intel_dpll_mgr.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 2165 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); dev_priv 2257 drivers/gpu/drm/i915/display/intel_dpll_mgr.c int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv) dev_priv 2259 drivers/gpu/drm/i915/display/intel_dpll_mgr.c int ref_clock = dev_priv->cdclk.hw.ref; dev_priv 2265 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400) dev_priv 2275 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 2310 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ref_clock = cnl_hdmi_pll_ref_clock(dev_priv); dev_priv 2434 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void cnl_dump_hw_state(struct drm_i915_private *dev_priv, dev_priv 2541 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 2543 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dev_priv->cdclk.hw.ref == 24000 ? dev_priv 2563 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 2565 drivers/gpu/drm/i915/display/intel_dpll_mgr.c *pll_params = dev_priv->cdclk.hw.ref == 24000 ? dev_priv 2574 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 2579 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, dev_priv 2599 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (INTEL_GEN(dev_priv) >= 12) dev_priv 2700 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 2701 drivers/gpu/drm/i915/display/intel_dpll_mgr.c int refclk_khz = dev_priv->cdclk.hw.ref; dev_priv 2909 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 2919 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) dev_priv 2945 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 2975 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, dev_priv 3003 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 3004 drivers/gpu/drm/i915/display/intel_dpll_mgr.c enum phy phy = intel_port_to_phy(dev_priv, encoder->port); dev_priv 3006 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_phy_is_combo(dev_priv, phy)) dev_priv 3008 drivers/gpu/drm/i915/display/intel_dpll_mgr.c else if (intel_phy_is_tc(dev_priv, phy)) dev_priv 3042 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 3052 drivers/gpu/drm/i915/display/intel_dpll_mgr.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 3087 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (dev_priv->cdclk.hw.ref == 38400) { dev_priv 3100 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); dev_priv 3104 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 3114 drivers/gpu/drm/i915/display/intel_dpll_mgr.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 3123 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (INTEL_GEN(dev_priv) >= 12) { dev_priv 3127 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) { dev_priv 3138 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); dev_priv 3142 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 3148 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (IS_ELKHARTLAKE(dev_priv) && dev_priv 3153 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg); dev_priv 3156 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 3160 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return icl_pll_get_hw_state(dev_priv, pll, hw_state, TBT_PLL_ENABLE); dev_priv 3163 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void icl_dpll_write(struct drm_i915_private *dev_priv, dev_priv 3170 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (INTEL_GEN(dev_priv) >= 12) { dev_priv 3174 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) { dev_priv 3188 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void icl_mg_pll_write(struct drm_i915_private *dev_priv, dev_priv 3238 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void icl_pll_power_enable(struct drm_i915_private *dev_priv, dev_priv 3252 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_POWER_STATE, 1)) dev_priv 3256 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void icl_pll_enable(struct drm_i915_private *dev_priv, dev_priv 3267 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 1)) dev_priv 3271 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void combo_pll_enable(struct drm_i915_private *dev_priv, dev_priv 3276 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (IS_ELKHARTLAKE(dev_priv) && dev_priv 3285 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->wakeref = intel_display_power_get(dev_priv, dev_priv 3289 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_power_enable(dev_priv, pll, enable_reg); dev_priv 3291 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_dpll_write(dev_priv, pll); dev_priv 3299 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_enable(dev_priv, pll, enable_reg); dev_priv 3304 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void tbt_pll_enable(struct drm_i915_private *dev_priv, dev_priv 3307 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_power_enable(dev_priv, pll, TBT_PLL_ENABLE); dev_priv 3309 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_dpll_write(dev_priv, pll); dev_priv 3317 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_enable(dev_priv, pll, TBT_PLL_ENABLE); dev_priv 3322 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void mg_pll_enable(struct drm_i915_private *dev_priv, dev_priv 3328 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_power_enable(dev_priv, pll, enable_reg); dev_priv 3330 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_mg_pll_write(dev_priv, pll); dev_priv 3338 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_enable(dev_priv, pll, enable_reg); dev_priv 3343 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void icl_pll_disable(struct drm_i915_private *dev_priv, dev_priv 3362 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 1)) dev_priv 3375 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_POWER_STATE, 1)) dev_priv 3379 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void combo_pll_disable(struct drm_i915_private *dev_priv, dev_priv 3384 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (IS_ELKHARTLAKE(dev_priv) && dev_priv 3387 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_disable(dev_priv, pll, enable_reg); dev_priv 3389 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF, dev_priv 3394 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_disable(dev_priv, pll, enable_reg); dev_priv 3397 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void tbt_pll_disable(struct drm_i915_private *dev_priv, dev_priv 3400 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_disable(dev_priv, pll, TBT_PLL_ENABLE); dev_priv 3403 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void mg_pll_disable(struct drm_i915_private *dev_priv, dev_priv 3409 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_disable(dev_priv, pll, enable_reg); dev_priv 3412 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void icl_dump_hw_state(struct drm_i915_private *dev_priv, dev_priv 3508 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 3513 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (INTEL_GEN(dev_priv) >= 12) dev_priv 3515 drivers/gpu/drm/i915/display/intel_dpll_mgr.c else if (IS_ELKHARTLAKE(dev_priv)) dev_priv 3517 drivers/gpu/drm/i915/display/intel_dpll_mgr.c else if (INTEL_GEN(dev_priv) >= 11) dev_priv 3519 drivers/gpu/drm/i915/display/intel_dpll_mgr.c else if (IS_CANNONLAKE(dev_priv)) dev_priv 3521 drivers/gpu/drm/i915/display/intel_dpll_mgr.c else if (IS_GEN9_BC(dev_priv)) dev_priv 3523 drivers/gpu/drm/i915/display/intel_dpll_mgr.c else if (IS_GEN9_LP(dev_priv)) dev_priv 3525 drivers/gpu/drm/i915/display/intel_dpll_mgr.c else if (HAS_DDI(dev_priv)) dev_priv 3527 drivers/gpu/drm/i915/display/intel_dpll_mgr.c else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) dev_priv 3531 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dev_priv->num_shared_dpll = 0; dev_priv 3539 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dev_priv->shared_dplls[i].info = &dpll_info[i]; dev_priv 3542 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dev_priv->dpll_mgr = dpll_mgr; dev_priv 3543 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dev_priv->num_shared_dpll = i; dev_priv 3544 drivers/gpu/drm/i915/display/intel_dpll_mgr.c mutex_init(&dev_priv->dpll_lock); dev_priv 3546 drivers/gpu/drm/i915/display/intel_dpll_mgr.c BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); dev_priv 3572 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 3573 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr; dev_priv 3595 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 3596 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr; dev_priv 3624 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 3625 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr; dev_priv 3640 drivers/gpu/drm/i915/display/intel_dpll_mgr.c void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, dev_priv 3643 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (dev_priv->dpll_mgr) { dev_priv 3644 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dev_priv->dpll_mgr->dump_hw_state(dev_priv, hw_state); dev_priv 249 drivers/gpu/drm/i915/display/intel_dpll_mgr.h void (*prepare)(struct drm_i915_private *dev_priv, dev_priv 258 drivers/gpu/drm/i915/display/intel_dpll_mgr.h void (*enable)(struct drm_i915_private *dev_priv, dev_priv 268 drivers/gpu/drm/i915/display/intel_dpll_mgr.h void (*disable)(struct drm_i915_private *dev_priv, dev_priv 278 drivers/gpu/drm/i915/display/intel_dpll_mgr.h bool (*get_hw_state)(struct drm_i915_private *dev_priv, dev_priv 350 drivers/gpu/drm/i915/display/intel_dpll_mgr.h intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, dev_priv 353 drivers/gpu/drm/i915/display/intel_dpll_mgr.h intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, dev_priv 355 drivers/gpu/drm/i915/display/intel_dpll_mgr.h void assert_shared_dpll(struct drm_i915_private *dev_priv, dev_priv 376 drivers/gpu/drm/i915/display/intel_dpll_mgr.h void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, dev_priv 378 drivers/gpu/drm/i915/display/intel_dpll_mgr.h int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv); dev_priv 116 drivers/gpu/drm/i915/display/intel_dsi.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 119 drivers/gpu/drm/i915/display/intel_dsi.c orientation = dev_priv->vbt.dsi.orientation; dev_priv 123 drivers/gpu/drm/i915/display/intel_dsi.c orientation = dev_priv->vbt.orientation; dev_priv 165 drivers/gpu/drm/i915/display/intel_dsi.h void icl_dsi_init(struct drm_i915_private *dev_priv); dev_priv 182 drivers/gpu/drm/i915/display/intel_dsi.h void vlv_dsi_init(struct drm_i915_private *dev_priv); dev_priv 194 drivers/gpu/drm/i915/display/intel_dsi.h bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv); dev_priv 162 drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 166 drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c if (dev_priv->vbt.backlight.type != INTEL_BACKLIGHT_DSI_DCS) dev_priv 124 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); dev_priv 195 drivers/gpu/drm/i915/display/intel_dsi_vbt.c if (INTEL_GEN(dev_priv) < 11) dev_priv 216 drivers/gpu/drm/i915/display/intel_dsi_vbt.c static void vlv_exec_gpio(struct drm_i915_private *dev_priv, dev_priv 231 drivers/gpu/drm/i915/display/intel_dsi_vbt.c if (dev_priv->vbt.dsi.seq_version >= 3) { dev_priv 249 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); dev_priv 252 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); dev_priv 257 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_write(dev_priv, port, padval, tmp); dev_priv 258 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); dev_priv 261 drivers/gpu/drm/i915/display/intel_dsi_vbt.c static void chv_exec_gpio(struct drm_i915_private *dev_priv, dev_priv 268 drivers/gpu/drm/i915/display/intel_dsi_vbt.c if (dev_priv->vbt.dsi.seq_version >= 3) { dev_priv 304 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); dev_priv 305 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_write(dev_priv, port, cfg1, 0); dev_priv 306 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_write(dev_priv, port, cfg0, dev_priv 309 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); dev_priv 312 drivers/gpu/drm/i915/display/intel_dsi_vbt.c static void bxt_exec_gpio(struct drm_i915_private *dev_priv, dev_priv 320 drivers/gpu/drm/i915/display/intel_dsi_vbt.c gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, dev_priv 337 drivers/gpu/drm/i915/display/intel_dsi_vbt.c static void icl_exec_gpio(struct drm_i915_private *dev_priv, dev_priv 346 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 352 drivers/gpu/drm/i915/display/intel_dsi_vbt.c if (dev_priv->vbt.dsi.seq_version >= 3) dev_priv 358 drivers/gpu/drm/i915/display/intel_dsi_vbt.c if (dev_priv->vbt.dsi.seq_version == 2) dev_priv 366 drivers/gpu/drm/i915/display/intel_dsi_vbt.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 367 drivers/gpu/drm/i915/display/intel_dsi_vbt.c icl_exec_gpio(dev_priv, gpio_source, gpio_index, value); dev_priv 368 drivers/gpu/drm/i915/display/intel_dsi_vbt.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 369 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value); dev_priv 370 drivers/gpu/drm/i915/display/intel_dsi_vbt.c else if (IS_CHERRYVIEW(dev_priv)) dev_priv 371 drivers/gpu/drm/i915/display/intel_dsi_vbt.c chv_exec_gpio(dev_priv, gpio_source, gpio_number, value); dev_priv 373 drivers/gpu/drm/i915/display/intel_dsi_vbt.c bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value); dev_priv 459 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); dev_priv 463 drivers/gpu/drm/i915/display/intel_dsi_vbt.c if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) dev_priv 466 drivers/gpu/drm/i915/display/intel_dsi_vbt.c data = dev_priv->vbt.dsi.sequence[seq_id]; dev_priv 479 drivers/gpu/drm/i915/display/intel_dsi_vbt.c if (dev_priv->vbt.dsi.seq_version >= 3) dev_priv 495 drivers/gpu/drm/i915/display/intel_dsi_vbt.c if (dev_priv->vbt.dsi.seq_version >= 3) dev_priv 524 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); dev_priv 527 drivers/gpu/drm/i915/display/intel_dsi_vbt.c if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3) dev_priv 574 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 575 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; dev_priv 576 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; dev_priv 577 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; dev_priv 136 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 151 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 165 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 190 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 204 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 279 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 322 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 333 drivers/gpu/drm/i915/display/intel_dvo.c intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC)); dev_priv 409 drivers/gpu/drm/i915/display/intel_dvo.c void intel_dvo_init(struct drm_i915_private *dev_priv) dev_priv 455 drivers/gpu/drm/i915/display/intel_dvo.c if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio)) dev_priv 467 drivers/gpu/drm/i915/display/intel_dvo.c i2c = intel_gmbus_get_adapter(dev_priv, gpio); dev_priv 483 drivers/gpu/drm/i915/display/intel_dvo.c for_each_pipe(dev_priv, pipe) { dev_priv 491 drivers/gpu/drm/i915/display/intel_dvo.c for_each_pipe(dev_priv, pipe) { dev_priv 501 drivers/gpu/drm/i915/display/intel_dvo.c drm_encoder_init(&dev_priv->drm, &intel_encoder->base, dev_priv 514 drivers/gpu/drm/i915/display/intel_dvo.c drm_connector_init(&dev_priv->drm, connector, dev_priv 521 drivers/gpu/drm/i915/display/intel_dvo.c drm_connector_init(&dev_priv->drm, connector, dev_priv 11 drivers/gpu/drm/i915/display/intel_dvo.h void intel_dvo_init(struct drm_i915_private *dev_priv); dev_priv 43 drivers/gpu/drm/i915/display/intel_dvo_dev.h void *dev_priv; dev_priv 48 drivers/gpu/drm/i915/display/intel_fbc.c static inline bool fbc_supported(struct drm_i915_private *dev_priv) dev_priv 50 drivers/gpu/drm/i915/display/intel_fbc.c return HAS_FBC(dev_priv); dev_priv 53 drivers/gpu/drm/i915/display/intel_fbc.c static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv) dev_priv 55 drivers/gpu/drm/i915/display/intel_fbc.c return INTEL_GEN(dev_priv) <= 3; dev_priv 85 drivers/gpu/drm/i915/display/intel_fbc.c static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, dev_priv 91 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_GEN(dev_priv, 7)) dev_priv 93 drivers/gpu/drm/i915/display/intel_fbc.c else if (INTEL_GEN(dev_priv) >= 8) dev_priv 100 drivers/gpu/drm/i915/display/intel_fbc.c static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) dev_priv 113 drivers/gpu/drm/i915/display/intel_fbc.c if (intel_de_wait_for_clear(dev_priv, FBC_STATUS, dev_priv 120 drivers/gpu/drm/i915/display/intel_fbc.c static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) dev_priv 122 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc_reg_params *params = &dev_priv->fbc.params; dev_priv 133 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_GEN(dev_priv, 2)) dev_priv 142 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_GEN(dev_priv, 4)) { dev_priv 156 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_I945GM(dev_priv)) dev_priv 163 drivers/gpu/drm/i915/display/intel_fbc.c static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) dev_priv 168 drivers/gpu/drm/i915/display/intel_fbc.c static void g4x_fbc_activate(struct drm_i915_private *dev_priv) dev_priv 170 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc_reg_params *params = &dev_priv->fbc.params; dev_priv 190 drivers/gpu/drm/i915/display/intel_fbc.c static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) dev_priv 202 drivers/gpu/drm/i915/display/intel_fbc.c static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) dev_priv 208 drivers/gpu/drm/i915/display/intel_fbc.c static void intel_fbc_recompress(struct drm_i915_private *dev_priv) dev_priv 214 drivers/gpu/drm/i915/display/intel_fbc.c static void ilk_fbc_activate(struct drm_i915_private *dev_priv) dev_priv 216 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc_reg_params *params = &dev_priv->fbc.params; dev_priv 218 drivers/gpu/drm/i915/display/intel_fbc.c int threshold = dev_priv->fbc.threshold; dev_priv 239 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_GEN(dev_priv, 5)) dev_priv 241 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_GEN(dev_priv, 6)) { dev_priv 249 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_GEN(dev_priv, 6)) { dev_priv 261 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_recompress(dev_priv); dev_priv 264 drivers/gpu/drm/i915/display/intel_fbc.c static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) dev_priv 276 drivers/gpu/drm/i915/display/intel_fbc.c static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) dev_priv 281 drivers/gpu/drm/i915/display/intel_fbc.c static void gen7_fbc_activate(struct drm_i915_private *dev_priv) dev_priv 283 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc_reg_params *params = &dev_priv->fbc.params; dev_priv 285 drivers/gpu/drm/i915/display/intel_fbc.c int threshold = dev_priv->fbc.threshold; dev_priv 288 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) { dev_priv 301 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_IVYBRIDGE(dev_priv)) dev_priv 331 drivers/gpu/drm/i915/display/intel_fbc.c if (dev_priv->fbc.false_color) dev_priv 334 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_IVYBRIDGE(dev_priv)) { dev_priv 339 drivers/gpu/drm/i915/display/intel_fbc.c } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { dev_priv 346 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_GEN(dev_priv, 11)) dev_priv 352 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_recompress(dev_priv); dev_priv 355 drivers/gpu/drm/i915/display/intel_fbc.c static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) dev_priv 357 drivers/gpu/drm/i915/display/intel_fbc.c if (INTEL_GEN(dev_priv) >= 5) dev_priv 358 drivers/gpu/drm/i915/display/intel_fbc.c return ilk_fbc_is_active(dev_priv); dev_priv 359 drivers/gpu/drm/i915/display/intel_fbc.c else if (IS_GM45(dev_priv)) dev_priv 360 drivers/gpu/drm/i915/display/intel_fbc.c return g4x_fbc_is_active(dev_priv); dev_priv 362 drivers/gpu/drm/i915/display/intel_fbc.c return i8xx_fbc_is_active(dev_priv); dev_priv 365 drivers/gpu/drm/i915/display/intel_fbc.c static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) dev_priv 367 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 371 drivers/gpu/drm/i915/display/intel_fbc.c if (INTEL_GEN(dev_priv) >= 7) dev_priv 372 drivers/gpu/drm/i915/display/intel_fbc.c gen7_fbc_activate(dev_priv); dev_priv 373 drivers/gpu/drm/i915/display/intel_fbc.c else if (INTEL_GEN(dev_priv) >= 5) dev_priv 374 drivers/gpu/drm/i915/display/intel_fbc.c ilk_fbc_activate(dev_priv); dev_priv 375 drivers/gpu/drm/i915/display/intel_fbc.c else if (IS_GM45(dev_priv)) dev_priv 376 drivers/gpu/drm/i915/display/intel_fbc.c g4x_fbc_activate(dev_priv); dev_priv 378 drivers/gpu/drm/i915/display/intel_fbc.c i8xx_fbc_activate(dev_priv); dev_priv 381 drivers/gpu/drm/i915/display/intel_fbc.c static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv) dev_priv 383 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 387 drivers/gpu/drm/i915/display/intel_fbc.c if (INTEL_GEN(dev_priv) >= 5) dev_priv 388 drivers/gpu/drm/i915/display/intel_fbc.c ilk_fbc_deactivate(dev_priv); dev_priv 389 drivers/gpu/drm/i915/display/intel_fbc.c else if (IS_GM45(dev_priv)) dev_priv 390 drivers/gpu/drm/i915/display/intel_fbc.c g4x_fbc_deactivate(dev_priv); dev_priv 392 drivers/gpu/drm/i915/display/intel_fbc.c i8xx_fbc_deactivate(dev_priv); dev_priv 404 drivers/gpu/drm/i915/display/intel_fbc.c bool intel_fbc_is_active(struct drm_i915_private *dev_priv) dev_priv 406 drivers/gpu/drm/i915/display/intel_fbc.c return dev_priv->fbc.active; dev_priv 409 drivers/gpu/drm/i915/display/intel_fbc.c static void intel_fbc_deactivate(struct drm_i915_private *dev_priv, dev_priv 412 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 417 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_hw_deactivate(dev_priv); dev_priv 425 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 426 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 430 drivers/gpu/drm/i915/display/intel_fbc.c if (!no_fbc_on_multiple_pipes(dev_priv)) dev_priv 441 drivers/gpu/drm/i915/display/intel_fbc.c static int find_compression_threshold(struct drm_i915_private *dev_priv, dev_priv 454 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv)) dev_priv 455 drivers/gpu/drm/i915/display/intel_fbc.c end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024; dev_priv 467 drivers/gpu/drm/i915/display/intel_fbc.c ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, dev_priv 478 drivers/gpu/drm/i915/display/intel_fbc.c ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, dev_priv 480 drivers/gpu/drm/i915/display/intel_fbc.c if (ret && INTEL_GEN(dev_priv) <= 4) { dev_priv 492 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 493 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 499 drivers/gpu/drm/i915/display/intel_fbc.c size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache); dev_priv 502 drivers/gpu/drm/i915/display/intel_fbc.c ret = find_compression_threshold(dev_priv, &fbc->compressed_fb, dev_priv 512 drivers/gpu/drm/i915/display/intel_fbc.c if (INTEL_GEN(dev_priv) >= 5) dev_priv 514 drivers/gpu/drm/i915/display/intel_fbc.c else if (IS_GM45(dev_priv)) { dev_priv 521 drivers/gpu/drm/i915/display/intel_fbc.c ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, dev_priv 528 drivers/gpu/drm/i915/display/intel_fbc.c GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start, dev_priv 531 drivers/gpu/drm/i915/display/intel_fbc.c GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start, dev_priv 535 drivers/gpu/drm/i915/display/intel_fbc.c dev_priv->dsm.start + fbc->compressed_fb.start); dev_priv 537 drivers/gpu/drm/i915/display/intel_fbc.c dev_priv->dsm.start + compressed_llb->start); dev_priv 547 drivers/gpu/drm/i915/display/intel_fbc.c i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); dev_priv 549 drivers/gpu/drm/i915/display/intel_fbc.c if (drm_mm_initialized(&dev_priv->mm.stolen)) dev_priv 554 drivers/gpu/drm/i915/display/intel_fbc.c static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) dev_priv 556 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 559 drivers/gpu/drm/i915/display/intel_fbc.c i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); dev_priv 562 drivers/gpu/drm/i915/display/intel_fbc.c i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb); dev_priv 567 drivers/gpu/drm/i915/display/intel_fbc.c void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) dev_priv 569 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 571 drivers/gpu/drm/i915/display/intel_fbc.c if (!fbc_supported(dev_priv)) dev_priv 575 drivers/gpu/drm/i915/display/intel_fbc.c __intel_fbc_cleanup_cfb(dev_priv); dev_priv 579 drivers/gpu/drm/i915/display/intel_fbc.c static bool stride_is_valid(struct drm_i915_private *dev_priv, dev_priv 590 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3)) dev_priv 593 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048) dev_priv 602 drivers/gpu/drm/i915/display/intel_fbc.c static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, dev_priv 612 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_GEN(dev_priv, 2)) dev_priv 615 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_G4X(dev_priv)) dev_priv 631 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 632 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 635 drivers/gpu/drm/i915/display/intel_fbc.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { dev_priv 638 drivers/gpu/drm/i915/display/intel_fbc.c } else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) { dev_priv 641 drivers/gpu/drm/i915/display/intel_fbc.c } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { dev_priv 661 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 662 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 670 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 702 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 703 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 746 drivers/gpu/drm/i915/display/intel_fbc.c if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) && dev_priv 752 drivers/gpu/drm/i915/display/intel_fbc.c if (!stride_is_valid(dev_priv, cache->fb.stride)) { dev_priv 757 drivers/gpu/drm/i915/display/intel_fbc.c if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) { dev_priv 769 drivers/gpu/drm/i915/display/intel_fbc.c if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && dev_priv 770 drivers/gpu/drm/i915/display/intel_fbc.c cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) { dev_priv 785 drivers/gpu/drm/i915/display/intel_fbc.c if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) > dev_priv 796 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_GEN_RANGE(dev_priv, 9, 10) && dev_priv 805 drivers/gpu/drm/i915/display/intel_fbc.c static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) dev_priv 807 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 809 drivers/gpu/drm/i915/display/intel_fbc.c if (intel_vgpu_active(dev_priv)) { dev_priv 830 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 831 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 849 drivers/gpu/drm/i915/display/intel_fbc.c params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); dev_priv 851 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) dev_priv 860 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 861 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 864 drivers/gpu/drm/i915/display/intel_fbc.c if (!fbc_supported(dev_priv)) dev_priv 881 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_deactivate(dev_priv, reason); dev_priv 893 drivers/gpu/drm/i915/display/intel_fbc.c static void __intel_fbc_disable(struct drm_i915_private *dev_priv) dev_priv 895 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 904 drivers/gpu/drm/i915/display/intel_fbc.c __intel_fbc_cleanup_cfb(dev_priv); dev_priv 912 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 913 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 924 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_deactivate(dev_priv, "disabled at runtime per module param"); dev_priv 925 drivers/gpu/drm/i915/display/intel_fbc.c __intel_fbc_disable(dev_priv); dev_priv 936 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_deactivate(dev_priv, "FBC enabled (active or scheduled)"); dev_priv 937 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_hw_activate(dev_priv); dev_priv 939 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_deactivate(dev_priv, "frontbuffer write"); dev_priv 944 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 945 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 947 drivers/gpu/drm/i915/display/intel_fbc.c if (!fbc_supported(dev_priv)) dev_priv 963 drivers/gpu/drm/i915/display/intel_fbc.c void intel_fbc_invalidate(struct drm_i915_private *dev_priv, dev_priv 967 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 969 drivers/gpu/drm/i915/display/intel_fbc.c if (!fbc_supported(dev_priv)) dev_priv 980 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_deactivate(dev_priv, "frontbuffer write"); dev_priv 985 drivers/gpu/drm/i915/display/intel_fbc.c void intel_fbc_flush(struct drm_i915_private *dev_priv, dev_priv 988 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 990 drivers/gpu/drm/i915/display/intel_fbc.c if (!fbc_supported(dev_priv)) dev_priv 1003 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_recompress(dev_priv); dev_priv 1024 drivers/gpu/drm/i915/display/intel_fbc.c void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, dev_priv 1027 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 1040 drivers/gpu/drm/i915/display/intel_fbc.c if (!intel_fbc_can_enable(dev_priv)) dev_priv 1086 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1087 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 1089 drivers/gpu/drm/i915/display/intel_fbc.c if (!fbc_supported(dev_priv)) dev_priv 1132 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1133 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 1135 drivers/gpu/drm/i915/display/intel_fbc.c if (!fbc_supported(dev_priv)) dev_priv 1140 drivers/gpu/drm/i915/display/intel_fbc.c __intel_fbc_disable(dev_priv); dev_priv 1150 drivers/gpu/drm/i915/display/intel_fbc.c void intel_fbc_global_disable(struct drm_i915_private *dev_priv) dev_priv 1152 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 1154 drivers/gpu/drm/i915/display/intel_fbc.c if (!fbc_supported(dev_priv)) dev_priv 1160 drivers/gpu/drm/i915/display/intel_fbc.c __intel_fbc_disable(dev_priv); dev_priv 1167 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = dev_priv 1169 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 1180 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_deactivate(dev_priv, "FIFO underrun"); dev_priv 1192 drivers/gpu/drm/i915/display/intel_fbc.c int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv) dev_priv 1196 drivers/gpu/drm/i915/display/intel_fbc.c cancel_work_sync(&dev_priv->fbc.underrun_work); dev_priv 1198 drivers/gpu/drm/i915/display/intel_fbc.c ret = mutex_lock_interruptible(&dev_priv->fbc.lock); dev_priv 1202 drivers/gpu/drm/i915/display/intel_fbc.c if (dev_priv->fbc.underrun_detected) { dev_priv 1204 drivers/gpu/drm/i915/display/intel_fbc.c dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared"; dev_priv 1207 drivers/gpu/drm/i915/display/intel_fbc.c dev_priv->fbc.underrun_detected = false; dev_priv 1208 drivers/gpu/drm/i915/display/intel_fbc.c mutex_unlock(&dev_priv->fbc.lock); dev_priv 1227 drivers/gpu/drm/i915/display/intel_fbc.c void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv) dev_priv 1229 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 1231 drivers/gpu/drm/i915/display/intel_fbc.c if (!fbc_supported(dev_priv)) dev_priv 1254 drivers/gpu/drm/i915/display/intel_fbc.c void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv) dev_priv 1259 drivers/gpu/drm/i915/display/intel_fbc.c if (!no_fbc_on_multiple_pipes(dev_priv)) dev_priv 1262 drivers/gpu/drm/i915/display/intel_fbc.c for_each_intel_crtc(&dev_priv->drm, crtc) dev_priv 1265 drivers/gpu/drm/i915/display/intel_fbc.c dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe); dev_priv 1277 drivers/gpu/drm/i915/display/intel_fbc.c static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) dev_priv 1282 drivers/gpu/drm/i915/display/intel_fbc.c if (!HAS_FBC(dev_priv)) dev_priv 1286 drivers/gpu/drm/i915/display/intel_fbc.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 1289 drivers/gpu/drm/i915/display/intel_fbc.c if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) dev_priv 1295 drivers/gpu/drm/i915/display/intel_fbc.c static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv) dev_priv 1299 drivers/gpu/drm/i915/display/intel_fbc.c (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) { dev_priv 1313 drivers/gpu/drm/i915/display/intel_fbc.c void intel_fbc_init(struct drm_i915_private *dev_priv) dev_priv 1315 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 1322 drivers/gpu/drm/i915/display/intel_fbc.c if (need_fbc_vtd_wa(dev_priv)) dev_priv 1323 drivers/gpu/drm/i915/display/intel_fbc.c mkwrite_device_info(dev_priv)->display.has_fbc = false; dev_priv 1325 drivers/gpu/drm/i915/display/intel_fbc.c i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv); dev_priv 1329 drivers/gpu/drm/i915/display/intel_fbc.c if (!HAS_FBC(dev_priv)) { dev_priv 1335 drivers/gpu/drm/i915/display/intel_fbc.c if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv)) dev_priv 1341 drivers/gpu/drm/i915/display/intel_fbc.c if (intel_fbc_hw_is_active(dev_priv)) dev_priv 1342 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_hw_deactivate(dev_priv); dev_priv 19 drivers/gpu/drm/i915/display/intel_fbc.h void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, dev_priv 21 drivers/gpu/drm/i915/display/intel_fbc.h bool intel_fbc_is_active(struct drm_i915_private *dev_priv); dev_priv 26 drivers/gpu/drm/i915/display/intel_fbc.h void intel_fbc_init(struct drm_i915_private *dev_priv); dev_priv 27 drivers/gpu/drm/i915/display/intel_fbc.h void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv); dev_priv 32 drivers/gpu/drm/i915/display/intel_fbc.h void intel_fbc_global_disable(struct drm_i915_private *dev_priv); dev_priv 33 drivers/gpu/drm/i915/display/intel_fbc.h void intel_fbc_invalidate(struct drm_i915_private *dev_priv, dev_priv 36 drivers/gpu/drm/i915/display/intel_fbc.h void intel_fbc_flush(struct drm_i915_private *dev_priv, dev_priv 38 drivers/gpu/drm/i915/display/intel_fbc.h void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); dev_priv 39 drivers/gpu/drm/i915/display/intel_fbc.h void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv); dev_priv 40 drivers/gpu/drm/i915/display/intel_fbc.h int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv); dev_priv 121 drivers/gpu/drm/i915/display/intel_fbdev.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 145 drivers/gpu/drm/i915/display/intel_fbdev.c if (size * 2 < dev_priv->stolen_usable_size) dev_priv 146 drivers/gpu/drm/i915/display/intel_fbdev.c obj = i915_gem_object_create_stolen(dev_priv, size); dev_priv 148 drivers/gpu/drm/i915/display/intel_fbdev.c obj = i915_gem_object_create_shmem(dev_priv, size); dev_priv 170 drivers/gpu/drm/i915/display/intel_fbdev.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 171 drivers/gpu/drm/i915/display/intel_fbdev.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 172 drivers/gpu/drm/i915/display/intel_fbdev.c struct i915_ggtt *ggtt = &dev_priv->ggtt; dev_priv 208 drivers/gpu/drm/i915/display/intel_fbdev.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 269 drivers/gpu/drm/i915/display/intel_fbdev.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 277 drivers/gpu/drm/i915/display/intel_fbdev.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 444 drivers/gpu/drm/i915/display/intel_fbdev.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 448 drivers/gpu/drm/i915/display/intel_fbdev.c if (WARN_ON(!HAS_DISPLAY(dev_priv))) dev_priv 467 drivers/gpu/drm/i915/display/intel_fbdev.c dev_priv->fbdev = ifbdev; dev_priv 468 drivers/gpu/drm/i915/display/intel_fbdev.c INIT_WORK(&dev_priv->fbdev_suspend_work, intel_fbdev_suspend_worker); dev_priv 505 drivers/gpu/drm/i915/display/intel_fbdev.c void intel_fbdev_unregister(struct drm_i915_private *dev_priv) dev_priv 507 drivers/gpu/drm/i915/display/intel_fbdev.c struct intel_fbdev *ifbdev = dev_priv->fbdev; dev_priv 512 drivers/gpu/drm/i915/display/intel_fbdev.c cancel_work_sync(&dev_priv->fbdev_suspend_work); dev_priv 519 drivers/gpu/drm/i915/display/intel_fbdev.c void intel_fbdev_fini(struct drm_i915_private *dev_priv) dev_priv 521 drivers/gpu/drm/i915/display/intel_fbdev.c struct intel_fbdev *ifbdev = fetch_and_zero(&dev_priv->fbdev); dev_priv 551 drivers/gpu/drm/i915/display/intel_fbdev.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 552 drivers/gpu/drm/i915/display/intel_fbdev.c struct intel_fbdev *ifbdev = dev_priv->fbdev; dev_priv 569 drivers/gpu/drm/i915/display/intel_fbdev.c flush_work(&dev_priv->fbdev_suspend_work); dev_priv 583 drivers/gpu/drm/i915/display/intel_fbdev.c schedule_work(&dev_priv->fbdev_suspend_work); dev_priv 17 drivers/gpu/drm/i915/display/intel_fbdev.h void intel_fbdev_unregister(struct drm_i915_private *dev_priv); dev_priv 18 drivers/gpu/drm/i915/display/intel_fbdev.h void intel_fbdev_fini(struct drm_i915_private *dev_priv); dev_priv 32 drivers/gpu/drm/i915/display/intel_fbdev.h static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv) dev_priv 36 drivers/gpu/drm/i915/display/intel_fbdev.h static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv) dev_priv 56 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 60 drivers/gpu/drm/i915/display/intel_fifo_underrun.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 62 drivers/gpu/drm/i915/display/intel_fifo_underrun.c for_each_pipe(dev_priv, pipe) { dev_priv 63 drivers/gpu/drm/i915/display/intel_fifo_underrun.c crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 74 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 78 drivers/gpu/drm/i915/display/intel_fifo_underrun.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 80 drivers/gpu/drm/i915/display/intel_fifo_underrun.c for_each_pipe(dev_priv, pipe) { dev_priv 81 drivers/gpu/drm/i915/display/intel_fifo_underrun.c crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 92 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 96 drivers/gpu/drm/i915/display/intel_fifo_underrun.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 101 drivers/gpu/drm/i915/display/intel_fifo_underrun.c enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); dev_priv 105 drivers/gpu/drm/i915/display/intel_fifo_underrun.c trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); dev_priv 113 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 116 drivers/gpu/drm/i915/display/intel_fifo_underrun.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 119 drivers/gpu/drm/i915/display/intel_fifo_underrun.c u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); dev_priv 132 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 137 drivers/gpu/drm/i915/display/intel_fifo_underrun.c ilk_enable_display_irq(dev_priv, bit); dev_priv 139 drivers/gpu/drm/i915/display/intel_fifo_underrun.c ilk_disable_display_irq(dev_priv, bit); dev_priv 144 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 148 drivers/gpu/drm/i915/display/intel_fifo_underrun.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 156 drivers/gpu/drm/i915/display/intel_fifo_underrun.c trace_intel_cpu_fifo_underrun(dev_priv, pipe); dev_priv 164 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 171 drivers/gpu/drm/i915/display/intel_fifo_underrun.c ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB); dev_priv 173 drivers/gpu/drm/i915/display/intel_fifo_underrun.c ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB); dev_priv 186 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 189 drivers/gpu/drm/i915/display/intel_fifo_underrun.c bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); dev_priv 191 drivers/gpu/drm/i915/display/intel_fifo_underrun.c bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); dev_priv 198 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 203 drivers/gpu/drm/i915/display/intel_fifo_underrun.c ibx_enable_display_interrupt(dev_priv, bit); dev_priv 205 drivers/gpu/drm/i915/display/intel_fifo_underrun.c ibx_disable_display_interrupt(dev_priv, bit); dev_priv 210 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 214 drivers/gpu/drm/i915/display/intel_fifo_underrun.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 222 drivers/gpu/drm/i915/display/intel_fifo_underrun.c trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); dev_priv 231 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 240 drivers/gpu/drm/i915/display/intel_fifo_underrun.c ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); dev_priv 242 drivers/gpu/drm/i915/display/intel_fifo_underrun.c ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); dev_priv 255 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 256 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 259 drivers/gpu/drm/i915/display/intel_fifo_underrun.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 264 drivers/gpu/drm/i915/display/intel_fifo_underrun.c if (HAS_GMCH(dev_priv)) dev_priv 266 drivers/gpu/drm/i915/display/intel_fifo_underrun.c else if (IS_GEN_RANGE(dev_priv, 5, 6)) dev_priv 268 drivers/gpu/drm/i915/display/intel_fifo_underrun.c else if (IS_GEN(dev_priv, 7)) dev_priv 270 drivers/gpu/drm/i915/display/intel_fifo_underrun.c else if (INTEL_GEN(dev_priv) >= 8) dev_priv 292 drivers/gpu/drm/i915/display/intel_fifo_underrun.c bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, dev_priv 298 drivers/gpu/drm/i915/display/intel_fifo_underrun.c spin_lock_irqsave(&dev_priv->irq_lock, flags); dev_priv 299 drivers/gpu/drm/i915/display/intel_fifo_underrun.c ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe, dev_priv 301 drivers/gpu/drm/i915/display/intel_fifo_underrun.c spin_unlock_irqrestore(&dev_priv->irq_lock, flags); dev_priv 320 drivers/gpu/drm/i915/display/intel_fifo_underrun.c bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, dev_priv 325 drivers/gpu/drm/i915/display/intel_fifo_underrun.c intel_get_crtc_for_pipe(dev_priv, pch_transcoder); dev_priv 338 drivers/gpu/drm/i915/display/intel_fifo_underrun.c spin_lock_irqsave(&dev_priv->irq_lock, flags); dev_priv 343 drivers/gpu/drm/i915/display/intel_fifo_underrun.c if (HAS_PCH_IBX(dev_priv)) dev_priv 344 drivers/gpu/drm/i915/display/intel_fifo_underrun.c ibx_set_fifo_underrun_reporting(&dev_priv->drm, dev_priv 348 drivers/gpu/drm/i915/display/intel_fifo_underrun.c cpt_set_fifo_underrun_reporting(&dev_priv->drm, dev_priv 352 drivers/gpu/drm/i915/display/intel_fifo_underrun.c spin_unlock_irqrestore(&dev_priv->irq_lock, flags); dev_priv 365 drivers/gpu/drm/i915/display/intel_fifo_underrun.c void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, dev_priv 368 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 375 drivers/gpu/drm/i915/display/intel_fifo_underrun.c if (HAS_GMCH(dev_priv) && dev_priv 379 drivers/gpu/drm/i915/display/intel_fifo_underrun.c if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) { dev_priv 380 drivers/gpu/drm/i915/display/intel_fifo_underrun.c trace_intel_cpu_fifo_underrun(dev_priv, pipe); dev_priv 385 drivers/gpu/drm/i915/display/intel_fifo_underrun.c intel_fbc_handle_fifo_underrun_irq(dev_priv); dev_priv 397 drivers/gpu/drm/i915/display/intel_fifo_underrun.c void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, dev_priv 400 drivers/gpu/drm/i915/display/intel_fifo_underrun.c if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, dev_priv 402 drivers/gpu/drm/i915/display/intel_fifo_underrun.c trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); dev_priv 417 drivers/gpu/drm/i915/display/intel_fifo_underrun.c void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) dev_priv 421 drivers/gpu/drm/i915/display/intel_fifo_underrun.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 423 drivers/gpu/drm/i915/display/intel_fifo_underrun.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 427 drivers/gpu/drm/i915/display/intel_fifo_underrun.c if (HAS_GMCH(dev_priv)) dev_priv 429 drivers/gpu/drm/i915/display/intel_fifo_underrun.c else if (IS_GEN(dev_priv, 7)) dev_priv 433 drivers/gpu/drm/i915/display/intel_fifo_underrun.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 444 drivers/gpu/drm/i915/display/intel_fifo_underrun.c void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv) dev_priv 448 drivers/gpu/drm/i915/display/intel_fifo_underrun.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 450 drivers/gpu/drm/i915/display/intel_fifo_underrun.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 454 drivers/gpu/drm/i915/display/intel_fifo_underrun.c if (HAS_PCH_CPT(dev_priv)) dev_priv 458 drivers/gpu/drm/i915/display/intel_fifo_underrun.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 15 drivers/gpu/drm/i915/display/intel_fifo_underrun.h bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, dev_priv 17 drivers/gpu/drm/i915/display/intel_fifo_underrun.h bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, dev_priv 20 drivers/gpu/drm/i915/display/intel_fifo_underrun.h void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, dev_priv 22 drivers/gpu/drm/i915/display/intel_fifo_underrun.h void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, dev_priv 24 drivers/gpu/drm/i915/display/intel_fifo_underrun.h void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); dev_priv 25 drivers/gpu/drm/i915/display/intel_fifo_underrun.h void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); dev_priv 95 drivers/gpu/drm/i915/display/intel_gmbus.c static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, dev_priv 98 drivers/gpu/drm/i915/display/intel_gmbus.c if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) dev_priv 100 drivers/gpu/drm/i915/display/intel_gmbus.c else if (HAS_PCH_CNP(dev_priv)) dev_priv 102 drivers/gpu/drm/i915/display/intel_gmbus.c else if (IS_GEN9_LP(dev_priv)) dev_priv 104 drivers/gpu/drm/i915/display/intel_gmbus.c else if (IS_GEN9_BC(dev_priv)) dev_priv 106 drivers/gpu/drm/i915/display/intel_gmbus.c else if (IS_BROADWELL(dev_priv)) dev_priv 112 drivers/gpu/drm/i915/display/intel_gmbus.c bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, dev_priv 117 drivers/gpu/drm/i915/display/intel_gmbus.c if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) dev_priv 119 drivers/gpu/drm/i915/display/intel_gmbus.c else if (HAS_PCH_CNP(dev_priv)) dev_priv 121 drivers/gpu/drm/i915/display/intel_gmbus.c else if (IS_GEN9_LP(dev_priv)) dev_priv 123 drivers/gpu/drm/i915/display/intel_gmbus.c else if (IS_GEN9_BC(dev_priv)) dev_priv 125 drivers/gpu/drm/i915/display/intel_gmbus.c else if (IS_BROADWELL(dev_priv)) dev_priv 130 drivers/gpu/drm/i915/display/intel_gmbus.c return pin < size && get_gmbus_pin(dev_priv, pin)->name; dev_priv 144 drivers/gpu/drm/i915/display/intel_gmbus.c intel_gmbus_reset(struct drm_i915_private *dev_priv) dev_priv 150 drivers/gpu/drm/i915/display/intel_gmbus.c static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, dev_priv 164 drivers/gpu/drm/i915/display/intel_gmbus.c static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, dev_priv 177 drivers/gpu/drm/i915/display/intel_gmbus.c static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, dev_priv 192 drivers/gpu/drm/i915/display/intel_gmbus.c struct drm_i915_private *i915 = bus->dev_priv; dev_priv 208 drivers/gpu/drm/i915/display/intel_gmbus.c struct intel_uncore *uncore = &bus->dev_priv->uncore; dev_priv 223 drivers/gpu/drm/i915/display/intel_gmbus.c struct intel_uncore *uncore = &bus->dev_priv->uncore; dev_priv 238 drivers/gpu/drm/i915/display/intel_gmbus.c struct intel_uncore *uncore = &bus->dev_priv->uncore; dev_priv 257 drivers/gpu/drm/i915/display/intel_gmbus.c struct intel_uncore *uncore = &bus->dev_priv->uncore; dev_priv 277 drivers/gpu/drm/i915/display/intel_gmbus.c struct drm_i915_private *dev_priv = bus->dev_priv; dev_priv 279 drivers/gpu/drm/i915/display/intel_gmbus.c intel_gmbus_reset(dev_priv); dev_priv 281 drivers/gpu/drm/i915/display/intel_gmbus.c if (IS_PINEVIEW(dev_priv)) dev_priv 282 drivers/gpu/drm/i915/display/intel_gmbus.c pnv_gmbus_clock_gating(dev_priv, false); dev_priv 296 drivers/gpu/drm/i915/display/intel_gmbus.c struct drm_i915_private *dev_priv = bus->dev_priv; dev_priv 301 drivers/gpu/drm/i915/display/intel_gmbus.c if (IS_PINEVIEW(dev_priv)) dev_priv 302 drivers/gpu/drm/i915/display/intel_gmbus.c pnv_gmbus_clock_gating(dev_priv, true); dev_priv 308 drivers/gpu/drm/i915/display/intel_gmbus.c struct drm_i915_private *dev_priv = bus->dev_priv; dev_priv 313 drivers/gpu/drm/i915/display/intel_gmbus.c bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); dev_priv 326 drivers/gpu/drm/i915/display/intel_gmbus.c static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) dev_priv 336 drivers/gpu/drm/i915/display/intel_gmbus.c if (!HAS_GMBUS_IRQ(dev_priv)) dev_priv 339 drivers/gpu/drm/i915/display/intel_gmbus.c add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); dev_priv 348 drivers/gpu/drm/i915/display/intel_gmbus.c remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); dev_priv 357 drivers/gpu/drm/i915/display/intel_gmbus.c gmbus_wait_idle(struct drm_i915_private *dev_priv) dev_priv 365 drivers/gpu/drm/i915/display/intel_gmbus.c if (HAS_GMBUS_IRQ(dev_priv)) dev_priv 368 drivers/gpu/drm/i915/display/intel_gmbus.c add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); dev_priv 371 drivers/gpu/drm/i915/display/intel_gmbus.c ret = intel_wait_for_register_fw(&dev_priv->uncore, dev_priv 376 drivers/gpu/drm/i915/display/intel_gmbus.c remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); dev_priv 382 drivers/gpu/drm/i915/display/intel_gmbus.c unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) dev_priv 384 drivers/gpu/drm/i915/display/intel_gmbus.c return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : dev_priv 389 drivers/gpu/drm/i915/display/intel_gmbus.c gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, dev_priv 394 drivers/gpu/drm/i915/display/intel_gmbus.c bool burst_read = len > gmbus_max_xfer_size(dev_priv); dev_priv 420 drivers/gpu/drm/i915/display/intel_gmbus.c ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); dev_priv 452 drivers/gpu/drm/i915/display/intel_gmbus.c gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, dev_priv 461 drivers/gpu/drm/i915/display/intel_gmbus.c if (HAS_GMBUS_BURST_READ(dev_priv)) dev_priv 464 drivers/gpu/drm/i915/display/intel_gmbus.c len = min(rx_size, gmbus_max_xfer_size(dev_priv)); dev_priv 466 drivers/gpu/drm/i915/display/intel_gmbus.c ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len, dev_priv 479 drivers/gpu/drm/i915/display/intel_gmbus.c gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, dev_priv 508 drivers/gpu/drm/i915/display/intel_gmbus.c ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); dev_priv 517 drivers/gpu/drm/i915/display/intel_gmbus.c gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, dev_priv 526 drivers/gpu/drm/i915/display/intel_gmbus.c len = min(tx_size, gmbus_max_xfer_size(dev_priv)); dev_priv 528 drivers/gpu/drm/i915/display/intel_gmbus.c ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, dev_priv 555 drivers/gpu/drm/i915/display/intel_gmbus.c gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, dev_priv 574 drivers/gpu/drm/i915/display/intel_gmbus.c ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, dev_priv 577 drivers/gpu/drm/i915/display/intel_gmbus.c ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index); dev_priv 593 drivers/gpu/drm/i915/display/intel_gmbus.c struct drm_i915_private *dev_priv = bus->dev_priv; dev_priv 598 drivers/gpu/drm/i915/display/intel_gmbus.c if (IS_GEN9_LP(dev_priv)) dev_priv 599 drivers/gpu/drm/i915/display/intel_gmbus.c bxt_gmbus_clock_gating(dev_priv, false); dev_priv 600 drivers/gpu/drm/i915/display/intel_gmbus.c else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) dev_priv 601 drivers/gpu/drm/i915/display/intel_gmbus.c pch_gmbus_clock_gating(dev_priv, false); dev_priv 609 drivers/gpu/drm/i915/display/intel_gmbus.c ret = gmbus_index_xfer(dev_priv, &msgs[i], dev_priv 613 drivers/gpu/drm/i915/display/intel_gmbus.c ret = gmbus_xfer_read(dev_priv, &msgs[i], dev_priv 616 drivers/gpu/drm/i915/display/intel_gmbus.c ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); dev_priv 620 drivers/gpu/drm/i915/display/intel_gmbus.c ret = gmbus_wait(dev_priv, dev_priv 638 drivers/gpu/drm/i915/display/intel_gmbus.c if (gmbus_wait_idle(dev_priv)) { dev_priv 662 drivers/gpu/drm/i915/display/intel_gmbus.c if (gmbus_wait_idle(dev_priv)) { dev_priv 707 drivers/gpu/drm/i915/display/intel_gmbus.c if (IS_GEN9_LP(dev_priv)) dev_priv 708 drivers/gpu/drm/i915/display/intel_gmbus.c bxt_gmbus_clock_gating(dev_priv, true); dev_priv 709 drivers/gpu/drm/i915/display/intel_gmbus.c else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) dev_priv 710 drivers/gpu/drm/i915/display/intel_gmbus.c pch_gmbus_clock_gating(dev_priv, true); dev_priv 720 drivers/gpu/drm/i915/display/intel_gmbus.c struct drm_i915_private *dev_priv = bus->dev_priv; dev_priv 724 drivers/gpu/drm/i915/display/intel_gmbus.c wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); dev_priv 736 drivers/gpu/drm/i915/display/intel_gmbus.c intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); dev_priv 745 drivers/gpu/drm/i915/display/intel_gmbus.c struct drm_i915_private *dev_priv = bus->dev_priv; dev_priv 765 drivers/gpu/drm/i915/display/intel_gmbus.c wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); dev_priv 766 drivers/gpu/drm/i915/display/intel_gmbus.c mutex_lock(&dev_priv->gmbus_mutex); dev_priv 775 drivers/gpu/drm/i915/display/intel_gmbus.c mutex_unlock(&dev_priv->gmbus_mutex); dev_priv 776 drivers/gpu/drm/i915/display/intel_gmbus.c intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); dev_priv 799 drivers/gpu/drm/i915/display/intel_gmbus.c struct drm_i915_private *dev_priv = bus->dev_priv; dev_priv 801 drivers/gpu/drm/i915/display/intel_gmbus.c mutex_lock(&dev_priv->gmbus_mutex); dev_priv 808 drivers/gpu/drm/i915/display/intel_gmbus.c struct drm_i915_private *dev_priv = bus->dev_priv; dev_priv 810 drivers/gpu/drm/i915/display/intel_gmbus.c return mutex_trylock(&dev_priv->gmbus_mutex); dev_priv 817 drivers/gpu/drm/i915/display/intel_gmbus.c struct drm_i915_private *dev_priv = bus->dev_priv; dev_priv 819 drivers/gpu/drm/i915/display/intel_gmbus.c mutex_unlock(&dev_priv->gmbus_mutex); dev_priv 832 drivers/gpu/drm/i915/display/intel_gmbus.c int intel_gmbus_setup(struct drm_i915_private *dev_priv) dev_priv 834 drivers/gpu/drm/i915/display/intel_gmbus.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 839 drivers/gpu/drm/i915/display/intel_gmbus.c if (!HAS_DISPLAY(dev_priv)) dev_priv 842 drivers/gpu/drm/i915/display/intel_gmbus.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 843 drivers/gpu/drm/i915/display/intel_gmbus.c dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; dev_priv 844 drivers/gpu/drm/i915/display/intel_gmbus.c else if (!HAS_GMCH(dev_priv)) dev_priv 849 drivers/gpu/drm/i915/display/intel_gmbus.c dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE; dev_priv 851 drivers/gpu/drm/i915/display/intel_gmbus.c mutex_init(&dev_priv->gmbus_mutex); dev_priv 852 drivers/gpu/drm/i915/display/intel_gmbus.c init_waitqueue_head(&dev_priv->gmbus_wait_queue); dev_priv 854 drivers/gpu/drm/i915/display/intel_gmbus.c for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { dev_priv 855 drivers/gpu/drm/i915/display/intel_gmbus.c if (!intel_gmbus_is_valid_pin(dev_priv, pin)) dev_priv 858 drivers/gpu/drm/i915/display/intel_gmbus.c bus = &dev_priv->gmbus[pin]; dev_priv 865 drivers/gpu/drm/i915/display/intel_gmbus.c get_gmbus_pin(dev_priv, pin)->name); dev_priv 868 drivers/gpu/drm/i915/display/intel_gmbus.c bus->dev_priv = dev_priv; dev_priv 883 drivers/gpu/drm/i915/display/intel_gmbus.c if (IS_I830(dev_priv)) dev_priv 893 drivers/gpu/drm/i915/display/intel_gmbus.c intel_gmbus_reset(dev_priv); dev_priv 899 drivers/gpu/drm/i915/display/intel_gmbus.c if (!intel_gmbus_is_valid_pin(dev_priv, pin)) dev_priv 902 drivers/gpu/drm/i915/display/intel_gmbus.c bus = &dev_priv->gmbus[pin]; dev_priv 908 drivers/gpu/drm/i915/display/intel_gmbus.c struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, dev_priv 911 drivers/gpu/drm/i915/display/intel_gmbus.c if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) dev_priv 914 drivers/gpu/drm/i915/display/intel_gmbus.c return &dev_priv->gmbus[pin].adapter; dev_priv 927 drivers/gpu/drm/i915/display/intel_gmbus.c struct drm_i915_private *dev_priv = bus->dev_priv; dev_priv 929 drivers/gpu/drm/i915/display/intel_gmbus.c mutex_lock(&dev_priv->gmbus_mutex); dev_priv 936 drivers/gpu/drm/i915/display/intel_gmbus.c mutex_unlock(&dev_priv->gmbus_mutex); dev_priv 946 drivers/gpu/drm/i915/display/intel_gmbus.c void intel_gmbus_teardown(struct drm_i915_private *dev_priv) dev_priv 951 drivers/gpu/drm/i915/display/intel_gmbus.c for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { dev_priv 952 drivers/gpu/drm/i915/display/intel_gmbus.c if (!intel_gmbus_is_valid_pin(dev_priv, pin)) dev_priv 955 drivers/gpu/drm/i915/display/intel_gmbus.c bus = &dev_priv->gmbus[pin]; dev_priv 36 drivers/gpu/drm/i915/display/intel_gmbus.h int intel_gmbus_setup(struct drm_i915_private *dev_priv); dev_priv 37 drivers/gpu/drm/i915/display/intel_gmbus.h void intel_gmbus_teardown(struct drm_i915_private *dev_priv); dev_priv 38 drivers/gpu/drm/i915/display/intel_gmbus.h bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, dev_priv 43 drivers/gpu/drm/i915/display/intel_gmbus.h intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); dev_priv 47 drivers/gpu/drm/i915/display/intel_gmbus.h void intel_gmbus_reset(struct drm_i915_private *dev_priv); dev_priv 85 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 95 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 96 drivers/gpu/drm/i915/display/intel_hdcp.c if (!dev_priv->hdcp_comp_added || !dev_priv->hdcp_master) { dev_priv 97 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 100 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 110 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 120 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 149 drivers/gpu/drm/i915/display/intel_hdcp.c static bool hdcp_key_loadable(struct drm_i915_private *dev_priv) dev_priv 151 drivers/gpu/drm/i915/display/intel_hdcp.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 160 drivers/gpu/drm/i915/display/intel_hdcp.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 168 drivers/gpu/drm/i915/display/intel_hdcp.c for_each_power_well(dev_priv, power_well) { dev_priv 170 drivers/gpu/drm/i915/display/intel_hdcp.c enabled = power_well->desc->ops->is_enabled(dev_priv, dev_priv 186 drivers/gpu/drm/i915/display/intel_hdcp.c static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv) dev_priv 193 drivers/gpu/drm/i915/display/intel_hdcp.c static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) dev_priv 206 drivers/gpu/drm/i915/display/intel_hdcp.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 217 drivers/gpu/drm/i915/display/intel_hdcp.c if (IS_GEN9_BC(dev_priv)) { dev_priv 218 drivers/gpu/drm/i915/display/intel_hdcp.c ret = sandybridge_pcode_write(dev_priv, dev_priv 230 drivers/gpu/drm/i915/display/intel_hdcp.c ret = __intel_wait_for_register(&dev_priv->uncore, HDCP_KEY_STATUS, dev_priv 245 drivers/gpu/drm/i915/display/intel_hdcp.c static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text) dev_priv 248 drivers/gpu/drm/i915/display/intel_hdcp.c if (intel_de_wait_for_set(dev_priv, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { dev_priv 282 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv; dev_priv 286 drivers/gpu/drm/i915/display/intel_hdcp.c dev_priv = intel_dig_port->base.base.dev->dev_private; dev_priv 320 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, sha_text); dev_priv 343 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, sha_text); dev_priv 360 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, dev_priv 368 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, 0); dev_priv 375 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, 0); dev_priv 386 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, sha_text); dev_priv 393 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, 0); dev_priv 400 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, 0); dev_priv 409 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, sha_text); dev_priv 417 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, 0); dev_priv 426 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, sha_text); dev_priv 433 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, bstatus[1]); dev_priv 440 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, 0); dev_priv 447 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, 0); dev_priv 460 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, 0); dev_priv 472 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_write_sha_text(dev_priv, sha_text); dev_priv 478 drivers/gpu/drm/i915/display/intel_hdcp.c if (intel_de_wait_for_set(dev_priv, HDCP_REP_CTL, dev_priv 578 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv; dev_priv 596 drivers/gpu/drm/i915/display/intel_hdcp.c dev_priv = intel_dig_port->base.base.dev->dev_private; dev_priv 622 drivers/gpu/drm/i915/display/intel_hdcp.c if (intel_de_wait_for_set(dev_priv, PORT_HDCP_STATUS(port), dev_priv 707 drivers/gpu/drm/i915/display/intel_hdcp.c if (intel_de_wait_for_set(dev_priv, PORT_HDCP_STATUS(port), dev_priv 729 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = connector->base.dev->dev_private; dev_priv 739 drivers/gpu/drm/i915/display/intel_hdcp.c if (intel_de_wait_for_clear(dev_priv, PORT_HDCP_STATUS(port), ~0, dev_priv 758 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = connector->base.dev->dev_private; dev_priv 764 drivers/gpu/drm/i915/display/intel_hdcp.c if (!hdcp_key_loadable(dev_priv)) { dev_priv 770 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_hdcp_load_keys(dev_priv); dev_priv 773 drivers/gpu/drm/i915/display/intel_hdcp.c intel_hdcp_clear_keys(dev_priv); dev_priv 808 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = connector->base.dev->dev_private; dev_priv 887 drivers/gpu/drm/i915/display/intel_hdcp.c bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port) dev_priv 890 drivers/gpu/drm/i915/display/intel_hdcp.c return INTEL_GEN(dev_priv) >= 9 && port < PORT_E; dev_priv 898 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 902 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 903 drivers/gpu/drm/i915/display/intel_hdcp.c comp = dev_priv->hdcp_master; dev_priv 906 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 913 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 926 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 930 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 931 drivers/gpu/drm/i915/display/intel_hdcp.c comp = dev_priv->hdcp_master; dev_priv 934 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 943 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 952 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 956 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 957 drivers/gpu/drm/i915/display/intel_hdcp.c comp = dev_priv->hdcp_master; dev_priv 960 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 967 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 977 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 981 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 982 drivers/gpu/drm/i915/display/intel_hdcp.c comp = dev_priv->hdcp_master; dev_priv 985 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 992 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1002 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1006 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 1007 drivers/gpu/drm/i915/display/intel_hdcp.c comp = dev_priv->hdcp_master; dev_priv 1010 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1017 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1027 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1031 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 1032 drivers/gpu/drm/i915/display/intel_hdcp.c comp = dev_priv->hdcp_master; dev_priv 1035 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1042 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1051 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1055 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 1056 drivers/gpu/drm/i915/display/intel_hdcp.c comp = dev_priv->hdcp_master; dev_priv 1059 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1066 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1078 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1082 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 1083 drivers/gpu/drm/i915/display/intel_hdcp.c comp = dev_priv->hdcp_master; dev_priv 1086 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1095 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1105 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1109 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 1110 drivers/gpu/drm/i915/display/intel_hdcp.c comp = dev_priv->hdcp_master; dev_priv 1113 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1120 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1128 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1132 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 1133 drivers/gpu/drm/i915/display/intel_hdcp.c comp = dev_priv->hdcp_master; dev_priv 1136 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1143 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1150 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1154 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 1155 drivers/gpu/drm/i915/display/intel_hdcp.c comp = dev_priv->hdcp_master; dev_priv 1158 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1164 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1493 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1516 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_de_wait_for_set(dev_priv, HDCP2_STATUS_DDI(port), dev_priv 1526 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1536 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_de_wait_for_clear(dev_priv, HDCP2_STATUS_DDI(port), dev_priv 1632 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1725 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); dev_priv 1728 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 1729 drivers/gpu/drm/i915/display/intel_hdcp.c dev_priv->hdcp_master = (struct i915_hdcp_comp_master *)data; dev_priv 1730 drivers/gpu/drm/i915/display/intel_hdcp.c dev_priv->hdcp_master->mei_dev = mei_kdev; dev_priv 1731 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1739 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); dev_priv 1742 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 1743 drivers/gpu/drm/i915/display/intel_hdcp.c dev_priv->hdcp_master = NULL; dev_priv 1744 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1778 drivers/gpu/drm/i915/display/intel_hdcp.c static bool is_hdcp2_supported(struct drm_i915_private *dev_priv) dev_priv 1783 drivers/gpu/drm/i915/display/intel_hdcp.c return (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || dev_priv 1784 drivers/gpu/drm/i915/display/intel_hdcp.c IS_KABYLAKE(dev_priv)); dev_priv 1787 drivers/gpu/drm/i915/display/intel_hdcp.c void intel_hdcp_component_init(struct drm_i915_private *dev_priv) dev_priv 1791 drivers/gpu/drm/i915/display/intel_hdcp.c if (!is_hdcp2_supported(dev_priv)) dev_priv 1794 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 1795 drivers/gpu/drm/i915/display/intel_hdcp.c WARN_ON(dev_priv->hdcp_comp_added); dev_priv 1797 drivers/gpu/drm/i915/display/intel_hdcp.c dev_priv->hdcp_comp_added = true; dev_priv 1798 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1799 drivers/gpu/drm/i915/display/intel_hdcp.c ret = component_add_typed(dev_priv->drm.dev, &i915_hdcp_component_ops, dev_priv 1803 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 1804 drivers/gpu/drm/i915/display/intel_hdcp.c dev_priv->hdcp_comp_added = false; dev_priv 1805 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1828 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1835 drivers/gpu/drm/i915/display/intel_hdcp.c if (is_hdcp2_supported(dev_priv)) dev_priv 1921 drivers/gpu/drm/i915/display/intel_hdcp.c void intel_hdcp_component_fini(struct drm_i915_private *dev_priv) dev_priv 1923 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv 1924 drivers/gpu/drm/i915/display/intel_hdcp.c if (!dev_priv->hdcp_comp_added) { dev_priv 1925 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1929 drivers/gpu/drm/i915/display/intel_hdcp.c dev_priv->hdcp_comp_added = false; dev_priv 1930 drivers/gpu/drm/i915/display/intel_hdcp.c mutex_unlock(&dev_priv->hdcp_comp_mutex); dev_priv 1932 drivers/gpu/drm/i915/display/intel_hdcp.c component_del(dev_priv->drm.dev, &i915_hdcp_component_ops); dev_priv 26 drivers/gpu/drm/i915/display/intel_hdcp.h bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port); dev_priv 29 drivers/gpu/drm/i915/display/intel_hdcp.h void intel_hdcp_component_init(struct drm_i915_private *dev_priv); dev_priv 30 drivers/gpu/drm/i915/display/intel_hdcp.h void intel_hdcp_component_fini(struct drm_i915_private *dev_priv); dev_priv 70 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 73 drivers/gpu/drm/i915/display/intel_hdmi.c enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; dev_priv 80 drivers/gpu/drm/i915/display/intel_hdmi.c assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, dev_priv 166 drivers/gpu/drm/i915/display/intel_hdmi.c hsw_dip_data_reg(struct drm_i915_private *dev_priv, dev_priv 210 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 244 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 262 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 281 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 317 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 336 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 358 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 397 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 416 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 434 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 470 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 489 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 510 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 523 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, dev_priv 529 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, dev_priv 542 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 550 drivers/gpu/drm/i915/display/intel_hdmi.c *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder, dev_priv 557 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 565 drivers/gpu/drm/i915/display/intel_hdmi.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 596 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 607 drivers/gpu/drm/i915/display/intel_hdmi.c if (HAS_DDI(dev_priv)) { dev_priv 807 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 810 drivers/gpu/drm/i915/display/intel_hdmi.c if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))) dev_priv 840 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 950 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 958 drivers/gpu/drm/i915/display/intel_hdmi.c if (HAS_DDI(dev_priv)) dev_priv 960 drivers/gpu/drm/i915/display/intel_hdmi.c else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 962 drivers/gpu/drm/i915/display/intel_hdmi.c else if (HAS_PCH_SPLIT(dev_priv)) dev_priv 975 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 983 drivers/gpu/drm/i915/display/intel_hdmi.c if (HAS_DDI(dev_priv)) dev_priv 985 drivers/gpu/drm/i915/display/intel_hdmi.c else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 987 drivers/gpu/drm/i915/display/intel_hdmi.c else if (HAS_PCH_SPLIT(dev_priv)) dev_priv 999 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1001 drivers/gpu/drm/i915/display/intel_hdmi.c if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) dev_priv 1022 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1081 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1130 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1188 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1192 drivers/gpu/drm/i915/display/intel_hdmi.c assert_hdmi_transcoder_func_disabled(dev_priv, dev_priv 1228 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); dev_priv 1230 drivers/gpu/drm/i915/display/intel_hdmi.c intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); dev_priv 1246 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = dev_priv 1248 drivers/gpu/drm/i915/display/intel_hdmi.c struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, dev_priv 1276 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = dev_priv 1278 drivers/gpu/drm/i915/display/intel_hdmi.c struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, dev_priv 1311 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = dev_priv 1313 drivers/gpu/drm/i915/display/intel_hdmi.c struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, dev_priv 1431 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1466 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1483 drivers/gpu/drm/i915/display/intel_hdmi.c if (IS_KABYLAKE(dev_priv) && enable) dev_priv 1492 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = dev_priv 1722 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1731 drivers/gpu/drm/i915/display/intel_hdmi.c if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) dev_priv 1746 drivers/gpu/drm/i915/display/intel_hdmi.c if (HAS_PCH_CPT(dev_priv)) dev_priv 1748 drivers/gpu/drm/i915/display/intel_hdmi.c else if (IS_CHERRYVIEW(dev_priv)) dev_priv 1760 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1765 drivers/gpu/drm/i915/display/intel_hdmi.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 1770 drivers/gpu/drm/i915/display/intel_hdmi.c ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); dev_priv 1772 drivers/gpu/drm/i915/display/intel_hdmi.c intel_display_power_put(dev_priv, encoder->power_domain, wakeref); dev_priv 1782 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1812 drivers/gpu/drm/i915/display/intel_hdmi.c if (!HAS_PCH_SPLIT(dev_priv) && dev_priv 1860 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1882 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1932 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1993 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 2011 drivers/gpu/drm/i915/display/intel_hdmi.c if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { dev_priv 2016 drivers/gpu/drm/i915/display/intel_hdmi.c intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); dev_priv 2017 drivers/gpu/drm/i915/display/intel_hdmi.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); dev_priv 2034 drivers/gpu/drm/i915/display/intel_hdmi.c intel_wait_for_vblank_if_active(dev_priv, PIPE_A); dev_priv 2035 drivers/gpu/drm/i915/display/intel_hdmi.c intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); dev_priv 2036 drivers/gpu/drm/i915/display/intel_hdmi.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); dev_priv 2075 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2077 drivers/gpu/drm/i915/display/intel_hdmi.c &dev_priv->vbt.ddi_port_info[encoder->port]; dev_priv 2080 drivers/gpu/drm/i915/display/intel_hdmi.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 2082 drivers/gpu/drm/i915/display/intel_hdmi.c else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) dev_priv 2084 drivers/gpu/drm/i915/display/intel_hdmi.c else if (INTEL_GEN(dev_priv) >= 5) dev_priv 2125 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); dev_priv 2133 drivers/gpu/drm/i915/display/intel_hdmi.c if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) dev_priv 2137 drivers/gpu/drm/i915/display/intel_hdmi.c if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) dev_priv 2149 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 2178 drivers/gpu/drm/i915/display/intel_hdmi.c if (status != MODE_OK && !HAS_GMCH(dev_priv)) dev_priv 2183 drivers/gpu/drm/i915/display/intel_hdmi.c if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) dev_priv 2194 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = dev_priv 2203 drivers/gpu/drm/i915/display/intel_hdmi.c if (HAS_GMCH(dev_priv)) dev_priv 2206 drivers/gpu/drm/i915/display/intel_hdmi.c if (bpc == 10 && INTEL_GEN(dev_priv) < 11) dev_priv 2248 drivers/gpu/drm/i915/display/intel_hdmi.c if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && dev_priv 2254 drivers/gpu/drm/i915/display/intel_hdmi.c bpc == 10 && INTEL_GEN(dev_priv) >= 11 && dev_priv 2299 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2347 drivers/gpu/drm/i915/display/intel_hdmi.c if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) dev_priv 2401 drivers/gpu/drm/i915/display/intel_hdmi.c if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || dev_priv 2402 drivers/gpu/drm/i915/display/intel_hdmi.c IS_GEMINILAKE(dev_priv))) { dev_priv 2455 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 2459 drivers/gpu/drm/i915/display/intel_hdmi.c intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); dev_priv 2479 drivers/gpu/drm/i915/display/intel_hdmi.c intel_bios_is_port_dp_dual_mode(dev_priv, port)) { dev_priv 2502 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 2509 drivers/gpu/drm/i915/display/intel_hdmi.c wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); dev_priv 2511 drivers/gpu/drm/i915/display/intel_hdmi.c i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); dev_priv 2524 drivers/gpu/drm/i915/display/intel_hdmi.c intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); dev_priv 2543 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 2551 drivers/gpu/drm/i915/display/intel_hdmi.c wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); dev_priv 2553 drivers/gpu/drm/i915/display/intel_hdmi.c if (INTEL_GEN(dev_priv) >= 11 && dev_priv 2563 drivers/gpu/drm/i915/display/intel_hdmi.c intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); dev_priv 2572 drivers/gpu/drm/i915/display/intel_hdmi.c intel_display_power_flush_work(dev_priv); dev_priv 2621 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2635 drivers/gpu/drm/i915/display/intel_hdmi.c vlv_wait_port_ready(dev_priv, dport, 0x0); dev_priv 2676 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 2678 drivers/gpu/drm/i915/display/intel_hdmi.c vlv_dpio_get(dev_priv); dev_priv 2683 drivers/gpu/drm/i915/display/intel_hdmi.c vlv_dpio_put(dev_priv); dev_priv 2692 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 2706 drivers/gpu/drm/i915/display/intel_hdmi.c vlv_wait_port_ready(dev_priv, dport, 0x0); dev_priv 2715 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 2718 drivers/gpu/drm/i915/display/intel_hdmi.c return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); dev_priv 2799 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 2818 drivers/gpu/drm/i915/display/intel_hdmi.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 2822 drivers/gpu/drm/i915/display/intel_hdmi.c if (!HAS_GMCH(dev_priv)) dev_priv 2849 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 2854 drivers/gpu/drm/i915/display/intel_hdmi.c intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); dev_priv 2869 drivers/gpu/drm/i915/display/intel_hdmi.c static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) dev_priv 2891 drivers/gpu/drm/i915/display/intel_hdmi.c static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) dev_priv 2910 drivers/gpu/drm/i915/display/intel_hdmi.c static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, dev_priv 2936 drivers/gpu/drm/i915/display/intel_hdmi.c static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) dev_priv 2938 drivers/gpu/drm/i915/display/intel_hdmi.c enum phy phy = intel_port_to_phy(dev_priv, port); dev_priv 2940 drivers/gpu/drm/i915/display/intel_hdmi.c if (intel_phy_is_combo(dev_priv, phy)) dev_priv 2942 drivers/gpu/drm/i915/display/intel_hdmi.c else if (intel_phy_is_tc(dev_priv, phy)) dev_priv 2943 drivers/gpu/drm/i915/display/intel_hdmi.c return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); dev_priv 2949 drivers/gpu/drm/i915/display/intel_hdmi.c static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) dev_priv 2951 drivers/gpu/drm/i915/display/intel_hdmi.c enum phy phy = intel_port_to_phy(dev_priv, port); dev_priv 2972 drivers/gpu/drm/i915/display/intel_hdmi.c static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, dev_priv 2995 drivers/gpu/drm/i915/display/intel_hdmi.c static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, dev_priv 2999 drivers/gpu/drm/i915/display/intel_hdmi.c &dev_priv->vbt.ddi_port_info[port]; dev_priv 3008 drivers/gpu/drm/i915/display/intel_hdmi.c if (HAS_PCH_MCC(dev_priv)) dev_priv 3009 drivers/gpu/drm/i915/display/intel_hdmi.c ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); dev_priv 3010 drivers/gpu/drm/i915/display/intel_hdmi.c else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_ICP(dev_priv)) dev_priv 3011 drivers/gpu/drm/i915/display/intel_hdmi.c ddc_pin = icl_port_to_ddc_pin(dev_priv, port); dev_priv 3012 drivers/gpu/drm/i915/display/intel_hdmi.c else if (HAS_PCH_CNP(dev_priv)) dev_priv 3013 drivers/gpu/drm/i915/display/intel_hdmi.c ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); dev_priv 3014 drivers/gpu/drm/i915/display/intel_hdmi.c else if (IS_GEN9_LP(dev_priv)) dev_priv 3015 drivers/gpu/drm/i915/display/intel_hdmi.c ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); dev_priv 3016 drivers/gpu/drm/i915/display/intel_hdmi.c else if (IS_CHERRYVIEW(dev_priv)) dev_priv 3017 drivers/gpu/drm/i915/display/intel_hdmi.c ddc_pin = chv_port_to_ddc_pin(dev_priv, port); dev_priv 3019 drivers/gpu/drm/i915/display/intel_hdmi.c ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); dev_priv 3029 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = dev_priv 3032 drivers/gpu/drm/i915/display/intel_hdmi.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 3037 drivers/gpu/drm/i915/display/intel_hdmi.c } else if (IS_G4X(dev_priv)) { dev_priv 3042 drivers/gpu/drm/i915/display/intel_hdmi.c } else if (HAS_DDI(dev_priv)) { dev_priv 3054 drivers/gpu/drm/i915/display/intel_hdmi.c } else if (HAS_PCH_IBX(dev_priv)) { dev_priv 3074 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 3093 drivers/gpu/drm/i915/display/intel_hdmi.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 3096 drivers/gpu/drm/i915/display/intel_hdmi.c intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); dev_priv 3100 drivers/gpu/drm/i915/display/intel_hdmi.c intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); dev_priv 3102 drivers/gpu/drm/i915/display/intel_hdmi.c if (HAS_DDI(dev_priv)) dev_priv 3112 drivers/gpu/drm/i915/display/intel_hdmi.c if (is_hdcp_supported(dev_priv, port)) { dev_priv 3123 drivers/gpu/drm/i915/display/intel_hdmi.c if (IS_G45(dev_priv)) { dev_priv 3160 drivers/gpu/drm/i915/display/intel_hdmi.c void intel_hdmi_init(struct drm_i915_private *dev_priv, dev_priv 3179 drivers/gpu/drm/i915/display/intel_hdmi.c drm_encoder_init(&dev_priv->drm, &intel_encoder->base, dev_priv 3185 drivers/gpu/drm/i915/display/intel_hdmi.c if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 3193 drivers/gpu/drm/i915/display/intel_hdmi.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 3199 drivers/gpu/drm/i915/display/intel_hdmi.c } else if (IS_VALLEYVIEW(dev_priv)) { dev_priv 3206 drivers/gpu/drm/i915/display/intel_hdmi.c if (HAS_PCH_CPT(dev_priv)) dev_priv 3208 drivers/gpu/drm/i915/display/intel_hdmi.c else if (HAS_PCH_IBX(dev_priv)) dev_priv 3217 drivers/gpu/drm/i915/display/intel_hdmi.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 3231 drivers/gpu/drm/i915/display/intel_hdmi.c if (IS_G4X(dev_priv)) dev_priv 3240 drivers/gpu/drm/i915/display/intel_hdmi.c intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); dev_priv 27 drivers/gpu/drm/i915/display/intel_hdmi.h void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, dev_priv 89 drivers/gpu/drm/i915/display/intel_hotplug.c enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, dev_priv 104 drivers/gpu/drm/i915/display/intel_hotplug.c if (IS_CNL_WITH_PORT_F(dev_priv)) dev_priv 152 drivers/gpu/drm/i915/display/intel_hotplug.c static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv, dev_priv 155 drivers/gpu/drm/i915/display/intel_hotplug.c struct i915_hotplug *hpd = &dev_priv->hotplug; dev_priv 163 drivers/gpu/drm/i915/display/intel_hotplug.c (!long_hpd && !dev_priv->hotplug.hpd_short_storm_enabled)) dev_priv 185 drivers/gpu/drm/i915/display/intel_hotplug.c intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv) dev_priv 187 drivers/gpu/drm/i915/display/intel_hotplug.c struct drm_device *dev = &dev_priv->drm; dev_priv 195 drivers/gpu/drm/i915/display/intel_hotplug.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 209 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.stats[pin].state != HPD_MARK_DISABLED) dev_priv 216 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.stats[pin].state = HPD_DISABLED; dev_priv 226 drivers/gpu/drm/i915/display/intel_hotplug.c mod_delayed_work(system_wq, &dev_priv->hotplug.reenable_work, dev_priv 233 drivers/gpu/drm/i915/display/intel_hotplug.c struct drm_i915_private *dev_priv = dev_priv 234 drivers/gpu/drm/i915/display/intel_hotplug.c container_of(work, typeof(*dev_priv), dev_priv 236 drivers/gpu/drm/i915/display/intel_hotplug.c struct drm_device *dev = &dev_priv->drm; dev_priv 240 drivers/gpu/drm/i915/display/intel_hotplug.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 242 drivers/gpu/drm/i915/display/intel_hotplug.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 247 drivers/gpu/drm/i915/display/intel_hotplug.c if (dev_priv->hotplug.stats[pin].state != HPD_DISABLED) dev_priv 250 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.stats[pin].state = HPD_ENABLED; dev_priv 269 drivers/gpu/drm/i915/display/intel_hotplug.c if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) dev_priv 270 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->display.hpd_irq_setup(dev_priv); dev_priv 271 drivers/gpu/drm/i915/display/intel_hotplug.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 273 drivers/gpu/drm/i915/display/intel_hotplug.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 310 drivers/gpu/drm/i915/display/intel_hotplug.c struct drm_i915_private *dev_priv = dev_priv 316 drivers/gpu/drm/i915/display/intel_hotplug.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 317 drivers/gpu/drm/i915/display/intel_hotplug.c long_port_mask = dev_priv->hotplug.long_port_mask; dev_priv 318 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.long_port_mask = 0; dev_priv 319 drivers/gpu/drm/i915/display/intel_hotplug.c short_port_mask = dev_priv->hotplug.short_port_mask; dev_priv 320 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.short_port_mask = 0; dev_priv 321 drivers/gpu/drm/i915/display/intel_hotplug.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 323 drivers/gpu/drm/i915/display/intel_hotplug.c for_each_intel_encoder(&dev_priv->drm, encoder) { dev_priv 348 drivers/gpu/drm/i915/display/intel_hotplug.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 349 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.event_bits |= old_bits; dev_priv 350 drivers/gpu/drm/i915/display/intel_hotplug.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 351 drivers/gpu/drm/i915/display/intel_hotplug.c queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0); dev_priv 360 drivers/gpu/drm/i915/display/intel_hotplug.c struct drm_i915_private *dev_priv = dev_priv 363 drivers/gpu/drm/i915/display/intel_hotplug.c struct drm_device *dev = &dev_priv->drm; dev_priv 375 drivers/gpu/drm/i915/display/intel_hotplug.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 377 drivers/gpu/drm/i915/display/intel_hotplug.c hpd_event_bits = dev_priv->hotplug.event_bits; dev_priv 378 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.event_bits = 0; dev_priv 379 drivers/gpu/drm/i915/display/intel_hotplug.c hpd_retry_bits = dev_priv->hotplug.retry_bits; dev_priv 380 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.retry_bits = 0; dev_priv 383 drivers/gpu/drm/i915/display/intel_hotplug.c intel_hpd_irq_storm_switch_to_polling(dev_priv); dev_priv 385 drivers/gpu/drm/i915/display/intel_hotplug.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 423 drivers/gpu/drm/i915/display/intel_hotplug.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 424 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.retry_bits |= retry; dev_priv 425 drivers/gpu/drm/i915/display/intel_hotplug.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 427 drivers/gpu/drm/i915/display/intel_hotplug.c mod_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, dev_priv 449 drivers/gpu/drm/i915/display/intel_hotplug.c void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, dev_priv 462 drivers/gpu/drm/i915/display/intel_hotplug.c spin_lock(&dev_priv->irq_lock); dev_priv 470 drivers/gpu/drm/i915/display/intel_hotplug.c for_each_intel_encoder(&dev_priv->drm, encoder) { dev_priv 490 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.long_port_mask |= BIT(port); dev_priv 493 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.short_port_mask |= BIT(port); dev_priv 504 drivers/gpu/drm/i915/display/intel_hotplug.c if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED) { dev_priv 511 drivers/gpu/drm/i915/display/intel_hotplug.c WARN_ONCE(!HAS_GMCH(dev_priv), dev_priv 516 drivers/gpu/drm/i915/display/intel_hotplug.c if (dev_priv->hotplug.stats[pin].state != HPD_ENABLED) dev_priv 527 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.event_bits |= BIT(pin); dev_priv 532 drivers/gpu/drm/i915/display/intel_hotplug.c if (intel_hpd_irq_storm_detect(dev_priv, pin, long_hpd)) { dev_priv 533 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.event_bits &= ~BIT(pin); dev_priv 543 drivers/gpu/drm/i915/display/intel_hotplug.c if (storm_detected && dev_priv->display_irqs_enabled) dev_priv 544 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->display.hpd_irq_setup(dev_priv); dev_priv 545 drivers/gpu/drm/i915/display/intel_hotplug.c spin_unlock(&dev_priv->irq_lock); dev_priv 554 drivers/gpu/drm/i915/display/intel_hotplug.c queue_work(dev_priv->hotplug.dp_wq, &dev_priv->hotplug.dig_port_work); dev_priv 556 drivers/gpu/drm/i915/display/intel_hotplug.c queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0); dev_priv 573 drivers/gpu/drm/i915/display/intel_hotplug.c void intel_hpd_init(struct drm_i915_private *dev_priv) dev_priv 578 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.stats[i].count = 0; dev_priv 579 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.stats[i].state = HPD_ENABLED; dev_priv 582 drivers/gpu/drm/i915/display/intel_hotplug.c WRITE_ONCE(dev_priv->hotplug.poll_enabled, false); dev_priv 583 drivers/gpu/drm/i915/display/intel_hotplug.c schedule_work(&dev_priv->hotplug.poll_init_work); dev_priv 589 drivers/gpu/drm/i915/display/intel_hotplug.c if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) { dev_priv 590 drivers/gpu/drm/i915/display/intel_hotplug.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 591 drivers/gpu/drm/i915/display/intel_hotplug.c if (dev_priv->display_irqs_enabled) dev_priv 592 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->display.hpd_irq_setup(dev_priv); dev_priv 593 drivers/gpu/drm/i915/display/intel_hotplug.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 599 drivers/gpu/drm/i915/display/intel_hotplug.c struct drm_i915_private *dev_priv = dev_priv 602 drivers/gpu/drm/i915/display/intel_hotplug.c struct drm_device *dev = &dev_priv->drm; dev_priv 609 drivers/gpu/drm/i915/display/intel_hotplug.c enabled = READ_ONCE(dev_priv->hotplug.poll_enabled); dev_priv 622 drivers/gpu/drm/i915/display/intel_hotplug.c if (!connector->polled && I915_HAS_HOTPLUG(dev_priv) && dev_priv 661 drivers/gpu/drm/i915/display/intel_hotplug.c void intel_hpd_poll_init(struct drm_i915_private *dev_priv) dev_priv 663 drivers/gpu/drm/i915/display/intel_hotplug.c WRITE_ONCE(dev_priv->hotplug.poll_enabled, true); dev_priv 671 drivers/gpu/drm/i915/display/intel_hotplug.c schedule_work(&dev_priv->hotplug.poll_init_work); dev_priv 674 drivers/gpu/drm/i915/display/intel_hotplug.c void intel_hpd_init_work(struct drm_i915_private *dev_priv) dev_priv 676 drivers/gpu/drm/i915/display/intel_hotplug.c INIT_DELAYED_WORK(&dev_priv->hotplug.hotplug_work, dev_priv 678 drivers/gpu/drm/i915/display/intel_hotplug.c INIT_WORK(&dev_priv->hotplug.dig_port_work, i915_digport_work_func); dev_priv 679 drivers/gpu/drm/i915/display/intel_hotplug.c INIT_WORK(&dev_priv->hotplug.poll_init_work, i915_hpd_poll_init_work); dev_priv 680 drivers/gpu/drm/i915/display/intel_hotplug.c INIT_DELAYED_WORK(&dev_priv->hotplug.reenable_work, dev_priv 684 drivers/gpu/drm/i915/display/intel_hotplug.c void intel_hpd_cancel_work(struct drm_i915_private *dev_priv) dev_priv 686 drivers/gpu/drm/i915/display/intel_hotplug.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 688 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.long_port_mask = 0; dev_priv 689 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.short_port_mask = 0; dev_priv 690 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.event_bits = 0; dev_priv 691 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.retry_bits = 0; dev_priv 693 drivers/gpu/drm/i915/display/intel_hotplug.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 695 drivers/gpu/drm/i915/display/intel_hotplug.c cancel_work_sync(&dev_priv->hotplug.dig_port_work); dev_priv 696 drivers/gpu/drm/i915/display/intel_hotplug.c cancel_delayed_work_sync(&dev_priv->hotplug.hotplug_work); dev_priv 697 drivers/gpu/drm/i915/display/intel_hotplug.c cancel_work_sync(&dev_priv->hotplug.poll_init_work); dev_priv 698 drivers/gpu/drm/i915/display/intel_hotplug.c cancel_delayed_work_sync(&dev_priv->hotplug.reenable_work); dev_priv 701 drivers/gpu/drm/i915/display/intel_hotplug.c bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin) dev_priv 708 drivers/gpu/drm/i915/display/intel_hotplug.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 709 drivers/gpu/drm/i915/display/intel_hotplug.c if (dev_priv->hotplug.stats[pin].state == HPD_ENABLED) { dev_priv 710 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.stats[pin].state = HPD_DISABLED; dev_priv 713 drivers/gpu/drm/i915/display/intel_hotplug.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 718 drivers/gpu/drm/i915/display/intel_hotplug.c void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin) dev_priv 723 drivers/gpu/drm/i915/display/intel_hotplug.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 724 drivers/gpu/drm/i915/display/intel_hotplug.c dev_priv->hotplug.stats[pin].state = HPD_ENABLED; dev_priv 725 drivers/gpu/drm/i915/display/intel_hotplug.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 17 drivers/gpu/drm/i915/display/intel_hotplug.h void intel_hpd_poll_init(struct drm_i915_private *dev_priv); dev_priv 21 drivers/gpu/drm/i915/display/intel_hotplug.h void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, dev_priv 23 drivers/gpu/drm/i915/display/intel_hotplug.h void intel_hpd_init(struct drm_i915_private *dev_priv); dev_priv 24 drivers/gpu/drm/i915/display/intel_hotplug.h void intel_hpd_init_work(struct drm_i915_private *dev_priv); dev_priv 25 drivers/gpu/drm/i915/display/intel_hotplug.h void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); dev_priv 26 drivers/gpu/drm/i915/display/intel_hotplug.h enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, dev_priv 28 drivers/gpu/drm/i915/display/intel_hotplug.h bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); dev_priv 29 drivers/gpu/drm/i915/display/intel_hotplug.h void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); dev_priv 76 drivers/gpu/drm/i915/display/intel_lpe_audio.c #define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->lpe_audio.platdev != NULL) dev_priv 79 drivers/gpu/drm/i915/display/intel_lpe_audio.c lpe_audio_platdev_create(struct drm_i915_private *dev_priv) dev_priv 81 drivers/gpu/drm/i915/display/intel_lpe_audio.c struct drm_device *dev = &dev_priv->drm; dev_priv 97 drivers/gpu/drm/i915/display/intel_lpe_audio.c rsc[0].start = rsc[0].end = dev_priv->lpe_audio.irq; dev_priv 117 drivers/gpu/drm/i915/display/intel_lpe_audio.c pdata->num_pipes = INTEL_INFO(dev_priv)->num_pipes; dev_priv 118 drivers/gpu/drm/i915/display/intel_lpe_audio.c pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */ dev_priv 138 drivers/gpu/drm/i915/display/intel_lpe_audio.c static void lpe_audio_platdev_destroy(struct drm_i915_private *dev_priv) dev_priv 148 drivers/gpu/drm/i915/display/intel_lpe_audio.c platform_device_unregister(dev_priv->lpe_audio.platdev); dev_priv 165 drivers/gpu/drm/i915/display/intel_lpe_audio.c static int lpe_audio_irq_init(struct drm_i915_private *dev_priv) dev_priv 167 drivers/gpu/drm/i915/display/intel_lpe_audio.c int irq = dev_priv->lpe_audio.irq; dev_priv 169 drivers/gpu/drm/i915/display/intel_lpe_audio.c WARN_ON(!intel_irqs_enabled(dev_priv)); dev_priv 175 drivers/gpu/drm/i915/display/intel_lpe_audio.c return irq_set_chip_data(irq, dev_priv); dev_priv 178 drivers/gpu/drm/i915/display/intel_lpe_audio.c static bool lpe_audio_detect(struct drm_i915_private *dev_priv) dev_priv 182 drivers/gpu/drm/i915/display/intel_lpe_audio.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 199 drivers/gpu/drm/i915/display/intel_lpe_audio.c static int lpe_audio_setup(struct drm_i915_private *dev_priv) dev_priv 203 drivers/gpu/drm/i915/display/intel_lpe_audio.c dev_priv->lpe_audio.irq = irq_alloc_desc(0); dev_priv 204 drivers/gpu/drm/i915/display/intel_lpe_audio.c if (dev_priv->lpe_audio.irq < 0) { dev_priv 206 drivers/gpu/drm/i915/display/intel_lpe_audio.c dev_priv->lpe_audio.irq); dev_priv 207 drivers/gpu/drm/i915/display/intel_lpe_audio.c ret = dev_priv->lpe_audio.irq; dev_priv 211 drivers/gpu/drm/i915/display/intel_lpe_audio.c DRM_DEBUG("irq = %d\n", dev_priv->lpe_audio.irq); dev_priv 213 drivers/gpu/drm/i915/display/intel_lpe_audio.c ret = lpe_audio_irq_init(dev_priv); dev_priv 221 drivers/gpu/drm/i915/display/intel_lpe_audio.c dev_priv->lpe_audio.platdev = lpe_audio_platdev_create(dev_priv); dev_priv 223 drivers/gpu/drm/i915/display/intel_lpe_audio.c if (IS_ERR(dev_priv->lpe_audio.platdev)) { dev_priv 224 drivers/gpu/drm/i915/display/intel_lpe_audio.c ret = PTR_ERR(dev_priv->lpe_audio.platdev); dev_priv 237 drivers/gpu/drm/i915/display/intel_lpe_audio.c irq_free_desc(dev_priv->lpe_audio.irq); dev_priv 239 drivers/gpu/drm/i915/display/intel_lpe_audio.c dev_priv->lpe_audio.irq = -1; dev_priv 240 drivers/gpu/drm/i915/display/intel_lpe_audio.c dev_priv->lpe_audio.platdev = NULL; dev_priv 251 drivers/gpu/drm/i915/display/intel_lpe_audio.c void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv) dev_priv 255 drivers/gpu/drm/i915/display/intel_lpe_audio.c if (!HAS_LPE_AUDIO(dev_priv)) dev_priv 258 drivers/gpu/drm/i915/display/intel_lpe_audio.c ret = generic_handle_irq(dev_priv->lpe_audio.irq); dev_priv 272 drivers/gpu/drm/i915/display/intel_lpe_audio.c int intel_lpe_audio_init(struct drm_i915_private *dev_priv) dev_priv 276 drivers/gpu/drm/i915/display/intel_lpe_audio.c if (lpe_audio_detect(dev_priv)) { dev_priv 277 drivers/gpu/drm/i915/display/intel_lpe_audio.c ret = lpe_audio_setup(dev_priv); dev_priv 291 drivers/gpu/drm/i915/display/intel_lpe_audio.c void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv) dev_priv 295 drivers/gpu/drm/i915/display/intel_lpe_audio.c if (!HAS_LPE_AUDIO(dev_priv)) dev_priv 298 drivers/gpu/drm/i915/display/intel_lpe_audio.c desc = irq_to_desc(dev_priv->lpe_audio.irq); dev_priv 300 drivers/gpu/drm/i915/display/intel_lpe_audio.c lpe_audio_platdev_destroy(dev_priv); dev_priv 302 drivers/gpu/drm/i915/display/intel_lpe_audio.c irq_free_desc(dev_priv->lpe_audio.irq); dev_priv 304 drivers/gpu/drm/i915/display/intel_lpe_audio.c dev_priv->lpe_audio.irq = -1; dev_priv 305 drivers/gpu/drm/i915/display/intel_lpe_audio.c dev_priv->lpe_audio.platdev = NULL; dev_priv 320 drivers/gpu/drm/i915/display/intel_lpe_audio.c void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, dev_priv 329 drivers/gpu/drm/i915/display/intel_lpe_audio.c if (!HAS_LPE_AUDIO(dev_priv)) dev_priv 332 drivers/gpu/drm/i915/display/intel_lpe_audio.c pdata = dev_get_platdata(&dev_priv->lpe_audio.platdev->dev); dev_priv 360 drivers/gpu/drm/i915/display/intel_lpe_audio.c pdata->notify_audio_lpe(dev_priv->lpe_audio.platdev, port - PORT_B); dev_priv 15 drivers/gpu/drm/i915/display/intel_lpe_audio.h int intel_lpe_audio_init(struct drm_i915_private *dev_priv); dev_priv 16 drivers/gpu/drm/i915/display/intel_lpe_audio.h void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv); dev_priv 17 drivers/gpu/drm/i915/display/intel_lpe_audio.h void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv); dev_priv 18 drivers/gpu/drm/i915/display/intel_lpe_audio.h void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, dev_priv 558 drivers/gpu/drm/i915/display/intel_lspcon.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 561 drivers/gpu/drm/i915/display/intel_lspcon.c if (!HAS_LSPCON(dev_priv)) { dev_priv 83 drivers/gpu/drm/i915/display/intel_lvds.c bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, dev_priv 91 drivers/gpu/drm/i915/display/intel_lvds.c if (HAS_PCH_CPT(dev_priv)) dev_priv 102 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 107 drivers/gpu/drm/i915/display/intel_lvds.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 112 drivers/gpu/drm/i915/display/intel_lvds.c ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe); dev_priv 114 drivers/gpu/drm/i915/display/intel_lvds.c intel_display_power_put(dev_priv, encoder->power_domain, wakeref); dev_priv 122 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 140 drivers/gpu/drm/i915/display/intel_lvds.c if (INTEL_GEN(dev_priv) < 5) dev_priv 145 drivers/gpu/drm/i915/display/intel_lvds.c if (INTEL_GEN(dev_priv) < 4) { dev_priv 154 drivers/gpu/drm/i915/display/intel_lvds.c static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 183 drivers/gpu/drm/i915/display/intel_lvds.c if (INTEL_GEN(dev_priv) <= 4 && dev_priv 201 drivers/gpu/drm/i915/display/intel_lvds.c static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, dev_priv 232 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 238 drivers/gpu/drm/i915/display/intel_lvds.c if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 239 drivers/gpu/drm/i915/display/intel_lvds.c assert_fdi_rx_pll_disabled(dev_priv, pipe); dev_priv 240 drivers/gpu/drm/i915/display/intel_lvds.c assert_shared_dpll_disabled(dev_priv, dev_priv 243 drivers/gpu/drm/i915/display/intel_lvds.c assert_pll_disabled(dev_priv, pipe); dev_priv 246 drivers/gpu/drm/i915/display/intel_lvds.c intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); dev_priv 251 drivers/gpu/drm/i915/display/intel_lvds.c if (HAS_PCH_CPT(dev_priv)) { dev_priv 286 drivers/gpu/drm/i915/display/intel_lvds.c if (IS_GEN(dev_priv, 4)) { dev_priv 314 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 321 drivers/gpu/drm/i915/display/intel_lvds.c if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) dev_priv 332 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 335 drivers/gpu/drm/i915/display/intel_lvds.c if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) dev_priv 390 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); dev_priv 400 drivers/gpu/drm/i915/display/intel_lvds.c if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { dev_priv 430 drivers/gpu/drm/i915/display/intel_lvds.c if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 752 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv) dev_priv 756 drivers/gpu/drm/i915/display/intel_lvds.c for_each_intel_encoder(&dev_priv->drm, encoder) { dev_priv 764 drivers/gpu/drm/i915/display/intel_lvds.c bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv) dev_priv 766 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_encoder *encoder = intel_get_lvds_encoder(dev_priv); dev_priv 775 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 795 drivers/gpu/drm/i915/display/intel_lvds.c if (HAS_PCH_CPT(dev_priv)) dev_priv 800 drivers/gpu/drm/i915/display/intel_lvds.c val = dev_priv->vbt.bios_lvds_val; dev_priv 812 drivers/gpu/drm/i915/display/intel_lvds.c void intel_lvds_init(struct drm_i915_private *dev_priv) dev_priv 814 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_device *dev = &dev_priv->drm; dev_priv 830 drivers/gpu/drm/i915/display/intel_lvds.c WARN(!dev_priv->vbt.int_lvds_support, dev_priv 835 drivers/gpu/drm/i915/display/intel_lvds.c if (!dev_priv->vbt.int_lvds_support) { dev_priv 840 drivers/gpu/drm/i915/display/intel_lvds.c if (HAS_PCH_SPLIT(dev_priv)) dev_priv 847 drivers/gpu/drm/i915/display/intel_lvds.c if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 853 drivers/gpu/drm/i915/display/intel_lvds.c if (!intel_bios_is_lvds_present(dev_priv, &pin)) { dev_priv 885 drivers/gpu/drm/i915/display/intel_lvds.c if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 902 drivers/gpu/drm/i915/display/intel_lvds.c if (HAS_PCH_SPLIT(dev_priv)) dev_priv 904 drivers/gpu/drm/i915/display/intel_lvds.c else if (IS_GEN(dev_priv, 4)) dev_priv 923 drivers/gpu/drm/i915/display/intel_lvds.c intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); dev_priv 941 drivers/gpu/drm/i915/display/intel_lvds.c intel_gmbus_get_adapter(dev_priv, pin)); dev_priv 944 drivers/gpu/drm/i915/display/intel_lvds.c intel_gmbus_get_adapter(dev_priv, pin)); dev_priv 16 drivers/gpu/drm/i915/display/intel_lvds.h bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, dev_priv 18 drivers/gpu/drm/i915/display/intel_lvds.h void intel_lvds_init(struct drm_i915_private *dev_priv); dev_priv 19 drivers/gpu/drm/i915/display/intel_lvds.h struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv); dev_priv 20 drivers/gpu/drm/i915/display/intel_lvds.h bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv); dev_priv 270 drivers/gpu/drm/i915/display/intel_opregion.c static int swsci(struct drm_i915_private *dev_priv, dev_priv 273 drivers/gpu/drm/i915/display/intel_opregion.c struct opregion_swsci *swsci = dev_priv->opregion.swsci; dev_priv 274 drivers/gpu/drm/i915/display/intel_opregion.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 289 drivers/gpu/drm/i915/display/intel_opregion.c if ((dev_priv->opregion.swsci_sbcb_sub_functions & dev_priv 293 drivers/gpu/drm/i915/display/intel_opregion.c if ((dev_priv->opregion.swsci_gbda_sub_functions & dev_priv 367 drivers/gpu/drm/i915/display/intel_opregion.c struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); dev_priv 373 drivers/gpu/drm/i915/display/intel_opregion.c if (!HAS_DDI(dev_priv)) dev_priv 413 drivers/gpu/drm/i915/display/intel_opregion.c return swsci(dev_priv, SWSCI_SBCB_DISPLAY_POWER_STATE, parm, NULL); dev_priv 427 drivers/gpu/drm/i915/display/intel_opregion.c int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, dev_priv 432 drivers/gpu/drm/i915/display/intel_opregion.c if (!HAS_DDI(dev_priv)) dev_priv 437 drivers/gpu/drm/i915/display/intel_opregion.c return swsci(dev_priv, SWSCI_SBCB_ADAPTER_POWER_STATE, dev_priv 444 drivers/gpu/drm/i915/display/intel_opregion.c static u32 asle_set_backlight(struct drm_i915_private *dev_priv, u32 bclp) dev_priv 448 drivers/gpu/drm/i915/display/intel_opregion.c struct opregion_asle *asle = dev_priv->opregion.asle; dev_priv 449 drivers/gpu/drm/i915/display/intel_opregion.c struct drm_device *dev = &dev_priv->drm; dev_priv 484 drivers/gpu/drm/i915/display/intel_opregion.c static u32 asle_set_als_illum(struct drm_i915_private *dev_priv, u32 alsi) dev_priv 492 drivers/gpu/drm/i915/display/intel_opregion.c static u32 asle_set_pwm_freq(struct drm_i915_private *dev_priv, u32 pfmb) dev_priv 498 drivers/gpu/drm/i915/display/intel_opregion.c static u32 asle_set_pfit(struct drm_i915_private *dev_priv, u32 pfit) dev_priv 506 drivers/gpu/drm/i915/display/intel_opregion.c static u32 asle_set_supported_rotation_angles(struct drm_i915_private *dev_priv, u32 srot) dev_priv 512 drivers/gpu/drm/i915/display/intel_opregion.c static u32 asle_set_button_array(struct drm_i915_private *dev_priv, u32 iuer) dev_priv 530 drivers/gpu/drm/i915/display/intel_opregion.c static u32 asle_set_convertible(struct drm_i915_private *dev_priv, u32 iuer) dev_priv 540 drivers/gpu/drm/i915/display/intel_opregion.c static u32 asle_set_docking(struct drm_i915_private *dev_priv, u32 iuer) dev_priv 550 drivers/gpu/drm/i915/display/intel_opregion.c static u32 asle_isct_state(struct drm_i915_private *dev_priv) dev_priv 560 drivers/gpu/drm/i915/display/intel_opregion.c struct drm_i915_private *dev_priv = dev_priv 562 drivers/gpu/drm/i915/display/intel_opregion.c struct opregion_asle *asle = dev_priv->opregion.asle; dev_priv 578 drivers/gpu/drm/i915/display/intel_opregion.c aslc_stat |= asle_set_als_illum(dev_priv, asle->alsi); dev_priv 581 drivers/gpu/drm/i915/display/intel_opregion.c aslc_stat |= asle_set_backlight(dev_priv, asle->bclp); dev_priv 584 drivers/gpu/drm/i915/display/intel_opregion.c aslc_stat |= asle_set_pfit(dev_priv, asle->pfit); dev_priv 587 drivers/gpu/drm/i915/display/intel_opregion.c aslc_stat |= asle_set_pwm_freq(dev_priv, asle->pfmb); dev_priv 590 drivers/gpu/drm/i915/display/intel_opregion.c aslc_stat |= asle_set_supported_rotation_angles(dev_priv, dev_priv 594 drivers/gpu/drm/i915/display/intel_opregion.c aslc_stat |= asle_set_button_array(dev_priv, asle->iuer); dev_priv 597 drivers/gpu/drm/i915/display/intel_opregion.c aslc_stat |= asle_set_convertible(dev_priv, asle->iuer); dev_priv 600 drivers/gpu/drm/i915/display/intel_opregion.c aslc_stat |= asle_set_docking(dev_priv, asle->iuer); dev_priv 603 drivers/gpu/drm/i915/display/intel_opregion.c aslc_stat |= asle_isct_state(dev_priv); dev_priv 608 drivers/gpu/drm/i915/display/intel_opregion.c void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) dev_priv 610 drivers/gpu/drm/i915/display/intel_opregion.c if (dev_priv->opregion.asle) dev_priv 611 drivers/gpu/drm/i915/display/intel_opregion.c schedule_work(&dev_priv->opregion.asle_work); dev_priv 706 drivers/gpu/drm/i915/display/intel_opregion.c static void intel_didl_outputs(struct drm_i915_private *dev_priv) dev_priv 708 drivers/gpu/drm/i915/display/intel_opregion.c struct intel_opregion *opregion = &dev_priv->opregion; dev_priv 724 drivers/gpu/drm/i915/display/intel_opregion.c drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); dev_priv 753 drivers/gpu/drm/i915/display/intel_opregion.c static void intel_setup_cadls(struct drm_i915_private *dev_priv) dev_priv 755 drivers/gpu/drm/i915/display/intel_opregion.c struct intel_opregion *opregion = &dev_priv->opregion; dev_priv 770 drivers/gpu/drm/i915/display/intel_opregion.c drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); dev_priv 783 drivers/gpu/drm/i915/display/intel_opregion.c static void swsci_setup(struct drm_i915_private *dev_priv) dev_priv 785 drivers/gpu/drm/i915/display/intel_opregion.c struct intel_opregion *opregion = &dev_priv->opregion; dev_priv 794 drivers/gpu/drm/i915/display/intel_opregion.c if (swsci(dev_priv, SWSCI_GBDA_SUPPORTED_CALLS, 0, &tmp) == 0) { dev_priv 805 drivers/gpu/drm/i915/display/intel_opregion.c if (swsci(dev_priv, SWSCI_GBDA_REQUESTED_CALLBACKS, 0, &tmp) == 0) { dev_priv 816 drivers/gpu/drm/i915/display/intel_opregion.c if (swsci(dev_priv, SWSCI_SBCB_SUPPORTED_CALLBACKS, 0, &tmp) == 0) { dev_priv 858 drivers/gpu/drm/i915/display/intel_opregion.c static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv) dev_priv 860 drivers/gpu/drm/i915/display/intel_opregion.c struct intel_opregion *opregion = &dev_priv->opregion; dev_priv 868 drivers/gpu/drm/i915/display/intel_opregion.c ret = request_firmware(&fw, name, &dev_priv->drm.pdev->dev); dev_priv 895 drivers/gpu/drm/i915/display/intel_opregion.c int intel_opregion_setup(struct drm_i915_private *dev_priv) dev_priv 897 drivers/gpu/drm/i915/display/intel_opregion.c struct intel_opregion *opregion = &dev_priv->opregion; dev_priv 898 drivers/gpu/drm/i915/display/intel_opregion.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 949 drivers/gpu/drm/i915/display/intel_opregion.c swsci_setup(dev_priv); dev_priv 962 drivers/gpu/drm/i915/display/intel_opregion.c if (intel_load_vbt_firmware(dev_priv) == 0) dev_priv 1047 drivers/gpu/drm/i915/display/intel_opregion.c intel_opregion_get_panel_type(struct drm_i915_private *dev_priv) dev_priv 1052 drivers/gpu/drm/i915/display/intel_opregion.c ret = swsci(dev_priv, SWSCI_GBDA_PANEL_DETAILS, 0x0, &panel_details); dev_priv 59 drivers/gpu/drm/i915/display/intel_opregion.h int intel_opregion_setup(struct drm_i915_private *dev_priv); dev_priv 61 drivers/gpu/drm/i915/display/intel_opregion.h void intel_opregion_register(struct drm_i915_private *dev_priv); dev_priv 62 drivers/gpu/drm/i915/display/intel_opregion.h void intel_opregion_unregister(struct drm_i915_private *dev_priv); dev_priv 64 drivers/gpu/drm/i915/display/intel_opregion.h void intel_opregion_resume(struct drm_i915_private *dev_priv); dev_priv 65 drivers/gpu/drm/i915/display/intel_opregion.h void intel_opregion_suspend(struct drm_i915_private *dev_priv, dev_priv 68 drivers/gpu/drm/i915/display/intel_opregion.h void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); dev_priv 71 drivers/gpu/drm/i915/display/intel_opregion.h int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, dev_priv 73 drivers/gpu/drm/i915/display/intel_opregion.h int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); dev_priv 77 drivers/gpu/drm/i915/display/intel_opregion.h static inline int intel_opregion_setup(struct drm_i915_private *dev_priv) dev_priv 82 drivers/gpu/drm/i915/display/intel_opregion.h static inline void intel_opregion_register(struct drm_i915_private *dev_priv) dev_priv 86 drivers/gpu/drm/i915/display/intel_opregion.h static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) dev_priv 90 drivers/gpu/drm/i915/display/intel_opregion.h static inline void intel_opregion_resume(struct drm_i915_private *dev_priv) dev_priv 94 drivers/gpu/drm/i915/display/intel_opregion.h static inline void intel_opregion_suspend(struct drm_i915_private *dev_priv, dev_priv 99 drivers/gpu/drm/i915/display/intel_opregion.h static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) dev_priv 198 drivers/gpu/drm/i915/display/intel_overlay.c static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, dev_priv 201 drivers/gpu/drm/i915/display/intel_overlay.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 245 drivers/gpu/drm/i915/display/intel_overlay.c struct drm_i915_private *dev_priv = overlay->i915; dev_priv 263 drivers/gpu/drm/i915/display/intel_overlay.c if (IS_I830(dev_priv)) dev_priv 264 drivers/gpu/drm/i915/display/intel_overlay.c i830_overlay_clock_gating(dev_priv, false); dev_priv 303 drivers/gpu/drm/i915/display/intel_overlay.c struct drm_i915_private *dev_priv = overlay->i915; dev_priv 361 drivers/gpu/drm/i915/display/intel_overlay.c struct drm_i915_private *dev_priv = overlay->i915; dev_priv 369 drivers/gpu/drm/i915/display/intel_overlay.c if (IS_I830(dev_priv)) dev_priv 370 drivers/gpu/drm/i915/display/intel_overlay.c i830_overlay_clock_gating(dev_priv, true); dev_priv 438 drivers/gpu/drm/i915/display/intel_overlay.c struct drm_i915_private *dev_priv = overlay->i915; dev_priv 442 drivers/gpu/drm/i915/display/intel_overlay.c lockdep_assert_held(&dev_priv->drm.struct_mutex); dev_priv 475 drivers/gpu/drm/i915/display/intel_overlay.c void intel_overlay_reset(struct drm_i915_private *dev_priv) dev_priv 477 drivers/gpu/drm/i915/display/intel_overlay.c struct intel_overlay *overlay = dev_priv->overlay; dev_priv 538 drivers/gpu/drm/i915/display/intel_overlay.c static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) dev_priv 542 drivers/gpu/drm/i915/display/intel_overlay.c if (IS_GEN(dev_priv, 2)) dev_priv 747 drivers/gpu/drm/i915/display/intel_overlay.c struct drm_i915_private *dev_priv = overlay->i915; dev_priv 754 drivers/gpu/drm/i915/display/intel_overlay.c lockdep_assert_held(&dev_priv->drm.struct_mutex); dev_priv 755 drivers/gpu/drm/i915/display/intel_overlay.c WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); dev_priv 761 drivers/gpu/drm/i915/display/intel_overlay.c atomic_inc(&dev_priv->gpu_error.pending_fb_pin); dev_priv 777 drivers/gpu/drm/i915/display/intel_overlay.c if (IS_GEN(dev_priv, 4)) dev_priv 798 drivers/gpu/drm/i915/display/intel_overlay.c swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); dev_priv 811 drivers/gpu/drm/i915/display/intel_overlay.c tmp_U = calc_swidthsw(dev_priv, params->offset_U, dev_priv 813 drivers/gpu/drm/i915/display/intel_overlay.c tmp_V = calc_swidthsw(dev_priv, params->offset_V, dev_priv 845 drivers/gpu/drm/i915/display/intel_overlay.c atomic_dec(&dev_priv->gpu_error.pending_fb_pin); dev_priv 852 drivers/gpu/drm/i915/display/intel_overlay.c struct drm_i915_private *dev_priv = overlay->i915; dev_priv 855 drivers/gpu/drm/i915/display/intel_overlay.c lockdep_assert_held(&dev_priv->drm.struct_mutex); dev_priv 856 drivers/gpu/drm/i915/display/intel_overlay.c WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); dev_priv 889 drivers/gpu/drm/i915/display/intel_overlay.c struct drm_i915_private *dev_priv = overlay->i915; dev_priv 896 drivers/gpu/drm/i915/display/intel_overlay.c if (INTEL_GEN(dev_priv) >= 4) { dev_priv 941 drivers/gpu/drm/i915/display/intel_overlay.c static int check_overlay_src(struct drm_i915_private *dev_priv, dev_priv 952 drivers/gpu/drm/i915/display/intel_overlay.c if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { dev_priv 1004 drivers/gpu/drm/i915/display/intel_overlay.c if (IS_I830(dev_priv) || IS_I845G(dev_priv)) dev_priv 1011 drivers/gpu/drm/i915/display/intel_overlay.c if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512) dev_priv 1056 drivers/gpu/drm/i915/display/intel_overlay.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1063 drivers/gpu/drm/i915/display/intel_overlay.c overlay = dev_priv->overlay; dev_priv 1142 drivers/gpu/drm/i915/display/intel_overlay.c ret = check_overlay_src(dev_priv, params, new_bo); dev_priv 1225 drivers/gpu/drm/i915/display/intel_overlay.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1229 drivers/gpu/drm/i915/display/intel_overlay.c overlay = dev_priv->overlay; dev_priv 1245 drivers/gpu/drm/i915/display/intel_overlay.c if (!IS_GEN(dev_priv, 2)) { dev_priv 1269 drivers/gpu/drm/i915/display/intel_overlay.c if (IS_GEN(dev_priv, 2)) dev_priv 1345 drivers/gpu/drm/i915/display/intel_overlay.c void intel_overlay_setup(struct drm_i915_private *dev_priv) dev_priv 1350 drivers/gpu/drm/i915/display/intel_overlay.c if (!HAS_OVERLAY(dev_priv)) dev_priv 1353 drivers/gpu/drm/i915/display/intel_overlay.c if (!HAS_ENGINE(dev_priv, RCS0)) dev_priv 1360 drivers/gpu/drm/i915/display/intel_overlay.c overlay->i915 = dev_priv; dev_priv 1361 drivers/gpu/drm/i915/display/intel_overlay.c overlay->context = dev_priv->engine[RCS0]->kernel_context; dev_priv 1370 drivers/gpu/drm/i915/display/intel_overlay.c i915_active_init(dev_priv, dev_priv 1374 drivers/gpu/drm/i915/display/intel_overlay.c ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); dev_priv 1382 drivers/gpu/drm/i915/display/intel_overlay.c dev_priv->overlay = overlay; dev_priv 1390 drivers/gpu/drm/i915/display/intel_overlay.c void intel_overlay_cleanup(struct drm_i915_private *dev_priv) dev_priv 1394 drivers/gpu/drm/i915/display/intel_overlay.c overlay = fetch_and_zero(&dev_priv->overlay); dev_priv 1421 drivers/gpu/drm/i915/display/intel_overlay.c intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) dev_priv 1423 drivers/gpu/drm/i915/display/intel_overlay.c struct intel_overlay *overlay = dev_priv->overlay; dev_priv 16 drivers/gpu/drm/i915/display/intel_overlay.h void intel_overlay_setup(struct drm_i915_private *dev_priv); dev_priv 17 drivers/gpu/drm/i915/display/intel_overlay.h void intel_overlay_cleanup(struct drm_i915_private *dev_priv); dev_priv 23 drivers/gpu/drm/i915/display/intel_overlay.h void intel_overlay_reset(struct drm_i915_private *dev_priv); dev_priv 25 drivers/gpu/drm/i915/display/intel_overlay.h intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); dev_priv 68 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 95 drivers/gpu/drm/i915/display/intel_panel.c downclock_mode = drm_mode_duplicate(&dev_priv->drm, best_mode); dev_priv 109 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 121 drivers/gpu/drm/i915/display/intel_panel.c fixed_mode = drm_mode_duplicate(&dev_priv->drm, scan); dev_priv 135 drivers/gpu/drm/i915/display/intel_panel.c fixed_mode = drm_mode_duplicate(&dev_priv->drm, scan); dev_priv 151 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 155 drivers/gpu/drm/i915/display/intel_panel.c if (!dev_priv->vbt.lfp_lvds_vbt_mode) dev_priv 158 drivers/gpu/drm/i915/display/intel_panel.c fixed_mode = drm_mode_duplicate(&dev_priv->drm, dev_priv 159 drivers/gpu/drm/i915/display/intel_panel.c dev_priv->vbt.lfp_lvds_vbt_mode); dev_priv 381 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); dev_priv 402 drivers/gpu/drm/i915/display/intel_panel.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 416 drivers/gpu/drm/i915/display/intel_panel.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 432 drivers/gpu/drm/i915/display/intel_panel.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 443 drivers/gpu/drm/i915/display/intel_panel.c if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18) dev_priv 520 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 529 drivers/gpu/drm/i915/display/intel_panel.c dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) { dev_priv 538 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 545 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 552 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 557 drivers/gpu/drm/i915/display/intel_panel.c if (INTEL_GEN(dev_priv) < 4) dev_priv 563 drivers/gpu/drm/i915/display/intel_panel.c pci_read_config_byte(dev_priv->drm.pdev, LBPC, &lbpc); dev_priv 570 drivers/gpu/drm/i915/display/intel_panel.c static u32 _vlv_get_backlight(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv 580 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 583 drivers/gpu/drm/i915/display/intel_panel.c return _vlv_get_backlight(dev_priv, pipe); dev_priv 588 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 606 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 615 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 625 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 636 drivers/gpu/drm/i915/display/intel_panel.c pci_write_config_byte(dev_priv->drm.pdev, LBPC, lbpc); dev_priv 639 drivers/gpu/drm/i915/display/intel_panel.c if (IS_GEN(dev_priv, 4)) { dev_priv 653 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 664 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 697 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 710 drivers/gpu/drm/i915/display/intel_panel.c mutex_lock(&dev_priv->backlight_lock); dev_priv 726 drivers/gpu/drm/i915/display/intel_panel.c mutex_unlock(&dev_priv->backlight_lock); dev_priv 732 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 758 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 777 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(old_conn_state->connector->dev); dev_priv 789 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 802 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 822 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 847 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 859 drivers/gpu/drm/i915/display/intel_panel.c if (dev_priv->drm.switch_power_state == DRM_SWITCH_POWER_CHANGING) { dev_priv 864 drivers/gpu/drm/i915/display/intel_panel.c mutex_lock(&dev_priv->backlight_lock); dev_priv 871 drivers/gpu/drm/i915/display/intel_panel.c mutex_unlock(&dev_priv->backlight_lock); dev_priv 878 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 889 drivers/gpu/drm/i915/display/intel_panel.c if (HAS_PCH_LPT(dev_priv)) { dev_priv 913 drivers/gpu/drm/i915/display/intel_panel.c if (HAS_PCH_LPT(dev_priv)) dev_priv 928 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 974 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 991 drivers/gpu/drm/i915/display/intel_panel.c if (IS_PINEVIEW(dev_priv) && panel->backlight.active_low_pwm) dev_priv 1005 drivers/gpu/drm/i915/display/intel_panel.c if (IS_GEN(dev_priv, 2)) dev_priv 1013 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1048 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1078 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1126 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1190 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1199 drivers/gpu/drm/i915/display/intel_panel.c mutex_lock(&dev_priv->backlight_lock); dev_priv 1203 drivers/gpu/drm/i915/display/intel_panel.c mutex_unlock(&dev_priv->backlight_lock); dev_priv 1209 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1213 drivers/gpu/drm/i915/display/intel_panel.c mutex_lock(&dev_priv->backlight_lock); dev_priv 1220 drivers/gpu/drm/i915/display/intel_panel.c mutex_unlock(&dev_priv->backlight_lock); dev_priv 1231 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1238 drivers/gpu/drm/i915/display/intel_panel.c mutex_lock(&dev_priv->backlight_lock); dev_priv 1248 drivers/gpu/drm/i915/display/intel_panel.c mutex_unlock(&dev_priv->backlight_lock); dev_priv 1287 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1291 drivers/gpu/drm/i915/display/intel_panel.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { dev_priv 1381 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1383 drivers/gpu/drm/i915/display/intel_panel.c return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz); dev_priv 1419 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1428 drivers/gpu/drm/i915/display/intel_panel.c if (HAS_PCH_LPT_H(dev_priv)) dev_priv 1442 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1444 drivers/gpu/drm/i915/display/intel_panel.c return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz * 128); dev_priv 1457 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1460 drivers/gpu/drm/i915/display/intel_panel.c if (IS_PINEVIEW(dev_priv)) dev_priv 1461 drivers/gpu/drm/i915/display/intel_panel.c clock = KHz(dev_priv->rawclk_freq); dev_priv 1463 drivers/gpu/drm/i915/display/intel_panel.c clock = KHz(dev_priv->cdclk.hw.cdclk); dev_priv 1475 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1478 drivers/gpu/drm/i915/display/intel_panel.c if (IS_G4X(dev_priv)) dev_priv 1479 drivers/gpu/drm/i915/display/intel_panel.c clock = KHz(dev_priv->rawclk_freq); dev_priv 1481 drivers/gpu/drm/i915/display/intel_panel.c clock = KHz(dev_priv->cdclk.hw.cdclk); dev_priv 1493 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1497 drivers/gpu/drm/i915/display/intel_panel.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 1503 drivers/gpu/drm/i915/display/intel_panel.c clock = KHz(dev_priv->rawclk_freq); dev_priv 1512 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1514 drivers/gpu/drm/i915/display/intel_panel.c u16 pwm_freq_hz = dev_priv->vbt.backlight.pwm_freq_hz; dev_priv 1545 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1558 drivers/gpu/drm/i915/display/intel_panel.c min = clamp_t(int, dev_priv->vbt.backlight.min_brightness, 0, 64); dev_priv 1559 drivers/gpu/drm/i915/display/intel_panel.c if (min != dev_priv->vbt.backlight.min_brightness) { dev_priv 1561 drivers/gpu/drm/i915/display/intel_panel.c dev_priv->vbt.backlight.min_brightness, min); dev_priv 1570 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1575 drivers/gpu/drm/i915/display/intel_panel.c if (HAS_PCH_LPT(dev_priv)) dev_priv 1599 drivers/gpu/drm/i915/display/intel_panel.c cpu_mode = panel->backlight.enabled && HAS_PCH_LPT(dev_priv) && dev_priv 1625 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1657 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1663 drivers/gpu/drm/i915/display/intel_panel.c if (IS_GEN(dev_priv, 2) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) dev_priv 1666 drivers/gpu/drm/i915/display/intel_panel.c if (IS_PINEVIEW(dev_priv)) dev_priv 1696 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1730 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1751 drivers/gpu/drm/i915/display/intel_panel.c val = _vlv_get_backlight(dev_priv, pipe); dev_priv 1764 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1768 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.controller = dev_priv->vbt.backlight.controller; dev_priv 1804 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1884 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1890 drivers/gpu/drm/i915/display/intel_panel.c mutex_lock(&dev_priv->backlight_lock); dev_priv 1894 drivers/gpu/drm/i915/display/intel_panel.c mutex_unlock(&dev_priv->backlight_lock); dev_priv 1899 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 1904 drivers/gpu/drm/i915/display/intel_panel.c if (!dev_priv->vbt.backlight.present) { dev_priv 1905 drivers/gpu/drm/i915/display/intel_panel.c if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) { dev_priv 1918 drivers/gpu/drm/i915/display/intel_panel.c mutex_lock(&dev_priv->backlight_lock); dev_priv 1920 drivers/gpu/drm/i915/display/intel_panel.c mutex_unlock(&dev_priv->backlight_lock); dev_priv 1953 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1963 drivers/gpu/drm/i915/display/intel_panel.c if (IS_GEN9_LP(dev_priv)) { dev_priv 1970 drivers/gpu/drm/i915/display/intel_panel.c } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) { dev_priv 1977 drivers/gpu/drm/i915/display/intel_panel.c } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_LPT) { dev_priv 1983 drivers/gpu/drm/i915/display/intel_panel.c if (HAS_PCH_LPT(dev_priv)) dev_priv 1987 drivers/gpu/drm/i915/display/intel_panel.c } else if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 1994 drivers/gpu/drm/i915/display/intel_panel.c } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 2009 drivers/gpu/drm/i915/display/intel_panel.c } else if (IS_GEN(dev_priv, 4)) { dev_priv 73 drivers/gpu/drm/i915/display/intel_pipe_crc.c static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, dev_priv 77 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct drm_device *dev = &dev_priv->drm; dev_priv 127 drivers/gpu/drm/i915/display/intel_pipe_crc.c static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, dev_priv 135 drivers/gpu/drm/i915/display/intel_pipe_crc.c int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); dev_priv 153 drivers/gpu/drm/i915/display/intel_pipe_crc.c if (!IS_CHERRYVIEW(dev_priv)) dev_priv 197 drivers/gpu/drm/i915/display/intel_pipe_crc.c static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, dev_priv 203 drivers/gpu/drm/i915/display/intel_pipe_crc.c int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); dev_priv 213 drivers/gpu/drm/i915/display/intel_pipe_crc.c if (!SUPPORTS_TV(dev_priv)) dev_priv 237 drivers/gpu/drm/i915/display/intel_pipe_crc.c static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, dev_priv 289 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 297 drivers/gpu/drm/i915/display/intel_pipe_crc.c state = drm_atomic_state_alloc(&dev_priv->drm); dev_priv 315 drivers/gpu/drm/i915/display/intel_pipe_crc.c if (IS_HASWELL(dev_priv) && dev_priv 336 drivers/gpu/drm/i915/display/intel_pipe_crc.c static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, dev_priv 364 drivers/gpu/drm/i915/display/intel_pipe_crc.c static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, dev_priv 407 drivers/gpu/drm/i915/display/intel_pipe_crc.c static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, dev_priv 411 drivers/gpu/drm/i915/display/intel_pipe_crc.c if (IS_GEN(dev_priv, 2)) dev_priv 413 drivers/gpu/drm/i915/display/intel_pipe_crc.c else if (INTEL_GEN(dev_priv) < 5) dev_priv 414 drivers/gpu/drm/i915/display/intel_pipe_crc.c return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); dev_priv 415 drivers/gpu/drm/i915/display/intel_pipe_crc.c else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 416 drivers/gpu/drm/i915/display/intel_pipe_crc.c return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); dev_priv 417 drivers/gpu/drm/i915/display/intel_pipe_crc.c else if (IS_GEN_RANGE(dev_priv, 5, 6)) dev_priv 419 drivers/gpu/drm/i915/display/intel_pipe_crc.c else if (INTEL_GEN(dev_priv) < 9) dev_priv 420 drivers/gpu/drm/i915/display/intel_pipe_crc.c return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val); dev_priv 422 drivers/gpu/drm/i915/display/intel_pipe_crc.c return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val); dev_priv 443 drivers/gpu/drm/i915/display/intel_pipe_crc.c void intel_display_crc_init(struct drm_i915_private *dev_priv) dev_priv 447 drivers/gpu/drm/i915/display/intel_pipe_crc.c for_each_pipe(dev_priv, pipe) { dev_priv 448 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; dev_priv 454 drivers/gpu/drm/i915/display/intel_pipe_crc.c static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv, dev_priv 466 drivers/gpu/drm/i915/display/intel_pipe_crc.c static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv, dev_priv 479 drivers/gpu/drm/i915/display/intel_pipe_crc.c static int vlv_crc_source_valid(struct drm_i915_private *dev_priv, dev_priv 494 drivers/gpu/drm/i915/display/intel_pipe_crc.c static int ilk_crc_source_valid(struct drm_i915_private *dev_priv, dev_priv 508 drivers/gpu/drm/i915/display/intel_pipe_crc.c static int ivb_crc_source_valid(struct drm_i915_private *dev_priv, dev_priv 522 drivers/gpu/drm/i915/display/intel_pipe_crc.c static int skl_crc_source_valid(struct drm_i915_private *dev_priv, dev_priv 542 drivers/gpu/drm/i915/display/intel_pipe_crc.c intel_is_valid_crc_source(struct drm_i915_private *dev_priv, dev_priv 545 drivers/gpu/drm/i915/display/intel_pipe_crc.c if (IS_GEN(dev_priv, 2)) dev_priv 546 drivers/gpu/drm/i915/display/intel_pipe_crc.c return i8xx_crc_source_valid(dev_priv, source); dev_priv 547 drivers/gpu/drm/i915/display/intel_pipe_crc.c else if (INTEL_GEN(dev_priv) < 5) dev_priv 548 drivers/gpu/drm/i915/display/intel_pipe_crc.c return i9xx_crc_source_valid(dev_priv, source); dev_priv 549 drivers/gpu/drm/i915/display/intel_pipe_crc.c else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 550 drivers/gpu/drm/i915/display/intel_pipe_crc.c return vlv_crc_source_valid(dev_priv, source); dev_priv 551 drivers/gpu/drm/i915/display/intel_pipe_crc.c else if (IS_GEN_RANGE(dev_priv, 5, 6)) dev_priv 552 drivers/gpu/drm/i915/display/intel_pipe_crc.c return ilk_crc_source_valid(dev_priv, source); dev_priv 553 drivers/gpu/drm/i915/display/intel_pipe_crc.c else if (INTEL_GEN(dev_priv) < 9) dev_priv 554 drivers/gpu/drm/i915/display/intel_pipe_crc.c return ivb_crc_source_valid(dev_priv, source); dev_priv 556 drivers/gpu/drm/i915/display/intel_pipe_crc.c return skl_crc_source_valid(dev_priv, source); dev_priv 569 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 578 drivers/gpu/drm/i915/display/intel_pipe_crc.c intel_is_valid_crc_source(dev_priv, source) == 0) { dev_priv 588 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 589 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index]; dev_priv 603 drivers/gpu/drm/i915/display/intel_pipe_crc.c wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 613 drivers/gpu/drm/i915/display/intel_pipe_crc.c ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val); dev_priv 622 drivers/gpu/drm/i915/display/intel_pipe_crc.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 623 drivers/gpu/drm/i915/display/intel_pipe_crc.c vlv_undo_pipe_scramble_reset(dev_priv, crtc->index); dev_priv 632 drivers/gpu/drm/i915/display/intel_pipe_crc.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 640 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 641 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index]; dev_priv 647 drivers/gpu/drm/i915/display/intel_pipe_crc.c if (get_new_crc_ctl_reg(dev_priv, crtc->index, &pipe_crc->source, &val) < 0) dev_priv 660 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 661 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index]; dev_priv 670 drivers/gpu/drm/i915/display/intel_pipe_crc.c intel_synchronize_irq(dev_priv); dev_priv 16 drivers/gpu/drm/i915/display/intel_pipe_crc.h void intel_display_crc_init(struct drm_i915_private *dev_priv); dev_priv 25 drivers/gpu/drm/i915/display/intel_pipe_crc.h static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {} dev_priv 75 drivers/gpu/drm/i915/display/intel_psr.c static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, dev_priv 82 drivers/gpu/drm/i915/display/intel_psr.c switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { dev_priv 108 drivers/gpu/drm/i915/display/intel_psr.c void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug) dev_priv 114 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 121 drivers/gpu/drm/i915/display/intel_psr.c for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { dev_priv 172 drivers/gpu/drm/i915/display/intel_psr.c void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) dev_priv 179 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 184 drivers/gpu/drm/i915/display/intel_psr.c for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { dev_priv 191 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.irq_aux_error = true; dev_priv 205 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.last_entry_attempt = time_ns; dev_priv 211 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.last_exit = time_ns; dev_priv 215 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 217 drivers/gpu/drm/i915/display/intel_psr.c bool psr2_enabled = dev_priv->psr.psr2_enabled; dev_priv 229 drivers/gpu/drm/i915/display/intel_psr.c schedule_work(&dev_priv->psr.work); dev_priv 283 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dev_priv 304 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.sink_support = true; dev_priv 305 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.sink_sync_latency = dev_priv 308 drivers/gpu/drm/i915/display/intel_psr.c WARN_ON(dev_priv->psr.dp); dev_priv 309 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.dp = intel_dp; dev_priv 311 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) >= 9 && dev_priv 328 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.sink_psr2_support = y_req && alpm; dev_priv 330 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.sink_psr2_support ? "" : "not "); dev_priv 332 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->psr.sink_psr2_support) { dev_priv 333 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.colorimetry_support = dev_priv 335 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.su_x_granularity = dev_priv 345 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 348 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->psr.psr2_enabled) { dev_priv 353 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->psr.colorimetry_support) { dev_priv 376 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 409 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 413 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->psr.psr2_enabled) { dev_priv 418 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->psr.link_standby) dev_priv 421 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 432 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 435 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 438 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) dev_priv 440 drivers/gpu/drm/i915/display/intel_psr.c else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) dev_priv 442 drivers/gpu/drm/i915/display/intel_psr.c else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) dev_priv 447 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) dev_priv 449 drivers/gpu/drm/i915/display/intel_psr.c else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) dev_priv 451 drivers/gpu/drm/i915/display/intel_psr.c else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) dev_priv 467 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 474 drivers/gpu/drm/i915/display/intel_psr.c int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); dev_priv 479 drivers/gpu/drm/i915/display/intel_psr.c idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); dev_priv 483 drivers/gpu/drm/i915/display/intel_psr.c if (IS_HASWELL(dev_priv)) dev_priv 486 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->psr.link_standby) dev_priv 491 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 500 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 506 drivers/gpu/drm/i915/display/intel_psr.c int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); dev_priv 508 drivers/gpu/drm/i915/display/intel_psr.c idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); dev_priv 512 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 515 drivers/gpu/drm/i915/display/intel_psr.c val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); dev_priv 517 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && dev_priv 518 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) dev_priv 520 drivers/gpu/drm/i915/display/intel_psr.c else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) dev_priv 522 drivers/gpu/drm/i915/display/intel_psr.c else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) dev_priv 539 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 544 drivers/gpu/drm/i915/display/intel_psr.c if (!dev_priv->psr.sink_psr2_support) dev_priv 557 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { dev_priv 560 drivers/gpu/drm/i915/display/intel_psr.c } else if (IS_GEN(dev_priv, 9)) { dev_priv 578 drivers/gpu/drm/i915/display/intel_psr.c if (crtc_hdisplay % dev_priv->psr.su_x_granularity) { dev_priv 580 drivers/gpu/drm/i915/display/intel_psr.c crtc_hdisplay, dev_priv->psr.su_x_granularity); dev_priv 596 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 601 drivers/gpu/drm/i915/display/intel_psr.c if (!CAN_PSR(dev_priv)) dev_priv 604 drivers/gpu/drm/i915/display/intel_psr.c if (intel_dp != dev_priv->psr.dp) dev_priv 619 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->psr.sink_not_reliable) { dev_priv 649 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 651 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 654 drivers/gpu/drm/i915/display/intel_psr.c WARN_ON(dev_priv->psr.active); dev_priv 655 drivers/gpu/drm/i915/display/intel_psr.c lockdep_assert_held(&dev_priv->psr.lock); dev_priv 658 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->psr.psr2_enabled) dev_priv 663 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.active = true; dev_priv 666 drivers/gpu/drm/i915/display/intel_psr.c static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private *dev_priv, dev_priv 676 drivers/gpu/drm/i915/display/intel_psr.c WARN_ON(INTEL_GEN(dev_priv) < 9); dev_priv 688 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 695 drivers/gpu/drm/i915/display/intel_psr.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 698 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) && dev_priv 699 drivers/gpu/drm/i915/display/intel_psr.c !IS_GEMINILAKE(dev_priv))) { dev_priv 700 drivers/gpu/drm/i915/display/intel_psr.c i915_reg_t reg = gen9_chicken_trans_reg(dev_priv, dev_priv 720 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) < 11) dev_priv 726 drivers/gpu/drm/i915/display/intel_psr.c static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, dev_priv 729 drivers/gpu/drm/i915/display/intel_psr.c struct intel_dp *intel_dp = dev_priv->psr.dp; dev_priv 731 drivers/gpu/drm/i915/display/intel_psr.c WARN_ON(dev_priv->psr.enabled); dev_priv 733 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); dev_priv 734 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.busy_frontbuffer_bits = 0; dev_priv 735 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; dev_priv 738 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.psr2_enabled ? "2" : "1"); dev_priv 742 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.enabled = true; dev_priv 757 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 762 drivers/gpu/drm/i915/display/intel_psr.c if (WARN_ON(!CAN_PSR(dev_priv))) dev_priv 765 drivers/gpu/drm/i915/display/intel_psr.c WARN_ON(dev_priv->drrs.dp); dev_priv 767 drivers/gpu/drm/i915/display/intel_psr.c mutex_lock(&dev_priv->psr.lock); dev_priv 769 drivers/gpu/drm/i915/display/intel_psr.c if (!psr_global_enabled(dev_priv->psr.debug)) { dev_priv 774 drivers/gpu/drm/i915/display/intel_psr.c intel_psr_enable_locked(dev_priv, crtc_state); dev_priv 777 drivers/gpu/drm/i915/display/intel_psr.c mutex_unlock(&dev_priv->psr.lock); dev_priv 780 drivers/gpu/drm/i915/display/intel_psr.c static void intel_psr_exit(struct drm_i915_private *dev_priv) dev_priv 784 drivers/gpu/drm/i915/display/intel_psr.c if (!dev_priv->psr.active) { dev_priv 785 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 791 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->psr.psr2_enabled) { dev_priv 800 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.active = false; dev_priv 805 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 809 drivers/gpu/drm/i915/display/intel_psr.c lockdep_assert_held(&dev_priv->psr.lock); dev_priv 811 drivers/gpu/drm/i915/display/intel_psr.c if (!dev_priv->psr.enabled) dev_priv 815 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.psr2_enabled ? "2" : "1"); dev_priv 817 drivers/gpu/drm/i915/display/intel_psr.c intel_psr_exit(dev_priv); dev_priv 819 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->psr.psr2_enabled) { dev_priv 828 drivers/gpu/drm/i915/display/intel_psr.c if (intel_de_wait_for_clear(dev_priv, psr_status, dev_priv 835 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.enabled = false; dev_priv 848 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 853 drivers/gpu/drm/i915/display/intel_psr.c if (WARN_ON(!CAN_PSR(dev_priv))) dev_priv 856 drivers/gpu/drm/i915/display/intel_psr.c mutex_lock(&dev_priv->psr.lock); dev_priv 860 drivers/gpu/drm/i915/display/intel_psr.c mutex_unlock(&dev_priv->psr.lock); dev_priv 861 drivers/gpu/drm/i915/display/intel_psr.c cancel_work_sync(&dev_priv->psr.work); dev_priv 864 drivers/gpu/drm/i915/display/intel_psr.c static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) dev_priv 866 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 876 drivers/gpu/drm/i915/display/intel_psr.c I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0); dev_priv 882 drivers/gpu/drm/i915/display/intel_psr.c intel_psr_exit(dev_priv); dev_priv 897 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 898 drivers/gpu/drm/i915/display/intel_psr.c struct i915_psr *psr = &dev_priv->psr; dev_priv 901 drivers/gpu/drm/i915/display/intel_psr.c if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp) dev_priv 904 drivers/gpu/drm/i915/display/intel_psr.c mutex_lock(&dev_priv->psr.lock); dev_priv 907 drivers/gpu/drm/i915/display/intel_psr.c psr2_enable = intel_psr2_enabled(dev_priv, crtc_state); dev_priv 912 drivers/gpu/drm/i915/display/intel_psr.c psr_force_hw_tracking_exit(dev_priv); dev_priv 913 drivers/gpu/drm/i915/display/intel_psr.c else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) { dev_priv 918 drivers/gpu/drm/i915/display/intel_psr.c if (!dev_priv->psr.active && dev_priv 919 drivers/gpu/drm/i915/display/intel_psr.c !dev_priv->psr.busy_frontbuffer_bits) dev_priv 920 drivers/gpu/drm/i915/display/intel_psr.c schedule_work(&dev_priv->psr.work); dev_priv 930 drivers/gpu/drm/i915/display/intel_psr.c intel_psr_enable_locked(dev_priv, crtc_state); dev_priv 933 drivers/gpu/drm/i915/display/intel_psr.c mutex_unlock(&dev_priv->psr.lock); dev_priv 950 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 952 drivers/gpu/drm/i915/display/intel_psr.c if (!dev_priv->psr.enabled || !new_crtc_state->has_psr) dev_priv 956 drivers/gpu/drm/i915/display/intel_psr.c if (READ_ONCE(dev_priv->psr.psr2_enabled)) dev_priv 966 drivers/gpu/drm/i915/display/intel_psr.c return __intel_wait_for_register(&dev_priv->uncore, EDP_PSR_STATUS, dev_priv 972 drivers/gpu/drm/i915/display/intel_psr.c static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) dev_priv 978 drivers/gpu/drm/i915/display/intel_psr.c if (!dev_priv->psr.enabled) dev_priv 981 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->psr.psr2_enabled) { dev_priv 989 drivers/gpu/drm/i915/display/intel_psr.c mutex_unlock(&dev_priv->psr.lock); dev_priv 991 drivers/gpu/drm/i915/display/intel_psr.c err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); dev_priv 996 drivers/gpu/drm/i915/display/intel_psr.c mutex_lock(&dev_priv->psr.lock); dev_priv 997 drivers/gpu/drm/i915/display/intel_psr.c return err == 0 && dev_priv->psr.enabled; dev_priv 1000 drivers/gpu/drm/i915/display/intel_psr.c static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) dev_priv 1002 drivers/gpu/drm/i915/display/intel_psr.c struct drm_device *dev = &dev_priv->drm; dev_priv 1052 drivers/gpu/drm/i915/display/intel_psr.c int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val) dev_priv 1064 drivers/gpu/drm/i915/display/intel_psr.c ret = mutex_lock_interruptible(&dev_priv->psr.lock); dev_priv 1068 drivers/gpu/drm/i915/display/intel_psr.c old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK; dev_priv 1069 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.debug = val; dev_priv 1070 drivers/gpu/drm/i915/display/intel_psr.c intel_psr_irq_control(dev_priv, dev_priv->psr.debug); dev_priv 1072 drivers/gpu/drm/i915/display/intel_psr.c mutex_unlock(&dev_priv->psr.lock); dev_priv 1075 drivers/gpu/drm/i915/display/intel_psr.c ret = intel_psr_fastset_force(dev_priv); dev_priv 1080 drivers/gpu/drm/i915/display/intel_psr.c static void intel_psr_handle_irq(struct drm_i915_private *dev_priv) dev_priv 1082 drivers/gpu/drm/i915/display/intel_psr.c struct i915_psr *psr = &dev_priv->psr; dev_priv 1092 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dev_priv 1093 drivers/gpu/drm/i915/display/intel_psr.c container_of(work, typeof(*dev_priv), psr.work); dev_priv 1095 drivers/gpu/drm/i915/display/intel_psr.c mutex_lock(&dev_priv->psr.lock); dev_priv 1097 drivers/gpu/drm/i915/display/intel_psr.c if (!dev_priv->psr.enabled) dev_priv 1100 drivers/gpu/drm/i915/display/intel_psr.c if (READ_ONCE(dev_priv->psr.irq_aux_error)) dev_priv 1101 drivers/gpu/drm/i915/display/intel_psr.c intel_psr_handle_irq(dev_priv); dev_priv 1109 drivers/gpu/drm/i915/display/intel_psr.c if (!__psr_wait_for_idle_locked(dev_priv)) dev_priv 1117 drivers/gpu/drm/i915/display/intel_psr.c if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active) dev_priv 1120 drivers/gpu/drm/i915/display/intel_psr.c intel_psr_activate(dev_priv->psr.dp); dev_priv 1122 drivers/gpu/drm/i915/display/intel_psr.c mutex_unlock(&dev_priv->psr.lock); dev_priv 1138 drivers/gpu/drm/i915/display/intel_psr.c void intel_psr_invalidate(struct drm_i915_private *dev_priv, dev_priv 1141 drivers/gpu/drm/i915/display/intel_psr.c if (!CAN_PSR(dev_priv)) dev_priv 1147 drivers/gpu/drm/i915/display/intel_psr.c mutex_lock(&dev_priv->psr.lock); dev_priv 1148 drivers/gpu/drm/i915/display/intel_psr.c if (!dev_priv->psr.enabled) { dev_priv 1149 drivers/gpu/drm/i915/display/intel_psr.c mutex_unlock(&dev_priv->psr.lock); dev_priv 1153 drivers/gpu/drm/i915/display/intel_psr.c frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); dev_priv 1154 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; dev_priv 1157 drivers/gpu/drm/i915/display/intel_psr.c intel_psr_exit(dev_priv); dev_priv 1159 drivers/gpu/drm/i915/display/intel_psr.c mutex_unlock(&dev_priv->psr.lock); dev_priv 1175 drivers/gpu/drm/i915/display/intel_psr.c void intel_psr_flush(struct drm_i915_private *dev_priv, dev_priv 1178 drivers/gpu/drm/i915/display/intel_psr.c if (!CAN_PSR(dev_priv)) dev_priv 1184 drivers/gpu/drm/i915/display/intel_psr.c mutex_lock(&dev_priv->psr.lock); dev_priv 1185 drivers/gpu/drm/i915/display/intel_psr.c if (!dev_priv->psr.enabled) { dev_priv 1186 drivers/gpu/drm/i915/display/intel_psr.c mutex_unlock(&dev_priv->psr.lock); dev_priv 1190 drivers/gpu/drm/i915/display/intel_psr.c frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); dev_priv 1191 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; dev_priv 1195 drivers/gpu/drm/i915/display/intel_psr.c psr_force_hw_tracking_exit(dev_priv); dev_priv 1197 drivers/gpu/drm/i915/display/intel_psr.c if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) dev_priv 1198 drivers/gpu/drm/i915/display/intel_psr.c schedule_work(&dev_priv->psr.work); dev_priv 1199 drivers/gpu/drm/i915/display/intel_psr.c mutex_unlock(&dev_priv->psr.lock); dev_priv 1209 drivers/gpu/drm/i915/display/intel_psr.c void intel_psr_init(struct drm_i915_private *dev_priv) dev_priv 1213 drivers/gpu/drm/i915/display/intel_psr.c if (!HAS_PSR(dev_priv)) dev_priv 1216 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ? dev_priv 1219 drivers/gpu/drm/i915/display/intel_psr.c if (!dev_priv->psr.sink_support) dev_priv 1223 drivers/gpu/drm/i915/display/intel_psr.c if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) dev_priv 1238 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.sink_not_reliable = true; dev_priv 1242 drivers/gpu/drm/i915/display/intel_psr.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 1244 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.link_standby = false; dev_priv 1247 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; dev_priv 1249 drivers/gpu/drm/i915/display/intel_psr.c INIT_WORK(&dev_priv->psr.work, intel_psr_work); dev_priv 1250 drivers/gpu/drm/i915/display/intel_psr.c mutex_init(&dev_priv->psr.lock); dev_priv 1255 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1256 drivers/gpu/drm/i915/display/intel_psr.c struct i915_psr *psr = &dev_priv->psr; dev_priv 1262 drivers/gpu/drm/i915/display/intel_psr.c if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) dev_priv 1308 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); dev_priv 1311 drivers/gpu/drm/i915/display/intel_psr.c if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) dev_priv 1314 drivers/gpu/drm/i915/display/intel_psr.c mutex_lock(&dev_priv->psr.lock); dev_priv 1315 drivers/gpu/drm/i915/display/intel_psr.c ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled); dev_priv 1316 drivers/gpu/drm/i915/display/intel_psr.c mutex_unlock(&dev_priv->psr.lock); dev_priv 15 drivers/gpu/drm/i915/display/intel_psr.h #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support) dev_priv 23 drivers/gpu/drm/i915/display/intel_psr.h int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value); dev_priv 24 drivers/gpu/drm/i915/display/intel_psr.h void intel_psr_invalidate(struct drm_i915_private *dev_priv, dev_priv 27 drivers/gpu/drm/i915/display/intel_psr.h void intel_psr_flush(struct drm_i915_private *dev_priv, dev_priv 30 drivers/gpu/drm/i915/display/intel_psr.h void intel_psr_init(struct drm_i915_private *dev_priv); dev_priv 33 drivers/gpu/drm/i915/display/intel_psr.h void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug); dev_priv 34 drivers/gpu/drm/i915/display/intel_psr.h void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir); dev_priv 11 drivers/gpu/drm/i915/display/intel_quirks.h void intel_init_quirks(struct drm_i915_private *dev_priv); dev_priv 215 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 219 drivers/gpu/drm/i915/display/intel_sdvo.c if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 226 drivers/gpu/drm/i915/display/intel_sdvo.c if (HAS_PCH_IBX(dev_priv)) { dev_priv 1431 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); dev_priv 1512 drivers/gpu/drm/i915/display/intel_sdvo.c if (INTEL_GEN(dev_priv) >= 4) { dev_priv 1516 drivers/gpu/drm/i915/display/intel_sdvo.c if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) dev_priv 1518 drivers/gpu/drm/i915/display/intel_sdvo.c if (INTEL_GEN(dev_priv) < 5) dev_priv 1529 drivers/gpu/drm/i915/display/intel_sdvo.c if (HAS_PCH_CPT(dev_priv)) dev_priv 1534 drivers/gpu/drm/i915/display/intel_sdvo.c if (INTEL_GEN(dev_priv) >= 4) { dev_priv 1536 drivers/gpu/drm/i915/display/intel_sdvo.c } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || dev_priv 1537 drivers/gpu/drm/i915/display/intel_sdvo.c IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { dev_priv 1545 drivers/gpu/drm/i915/display/intel_sdvo.c INTEL_GEN(dev_priv) < 5) dev_priv 1562 drivers/gpu/drm/i915/display/intel_sdvo.c bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, dev_priv 1570 drivers/gpu/drm/i915/display/intel_sdvo.c if (HAS_PCH_CPT(dev_priv)) dev_priv 1572 drivers/gpu/drm/i915/display/intel_sdvo.c else if (IS_CHERRYVIEW(dev_priv)) dev_priv 1583 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1590 drivers/gpu/drm/i915/display/intel_sdvo.c ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe); dev_priv 1599 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1641 drivers/gpu/drm/i915/display/intel_sdvo.c if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { dev_priv 1724 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1747 drivers/gpu/drm/i915/display/intel_sdvo.c if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { dev_priv 1752 drivers/gpu/drm/i915/display/intel_sdvo.c intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); dev_priv 1753 drivers/gpu/drm/i915/display/intel_sdvo.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); dev_priv 1762 drivers/gpu/drm/i915/display/intel_sdvo.c intel_wait_for_vblank_if_active(dev_priv, PIPE_A); dev_priv 1763 drivers/gpu/drm/i915/display/intel_sdvo.c intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); dev_priv 1764 drivers/gpu/drm/i915/display/intel_sdvo.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); dev_priv 1786 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1799 drivers/gpu/drm/i915/display/intel_sdvo.c intel_wait_for_vblank(dev_priv, intel_crtc->pipe); dev_priv 1896 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); dev_priv 1899 drivers/gpu/drm/i915/display/intel_sdvo.c if (!I915_HAS_HOTPLUG(dev_priv)) dev_priv 1906 drivers/gpu/drm/i915/display/intel_sdvo.c if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) dev_priv 1952 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 1955 drivers/gpu/drm/i915/display/intel_sdvo.c intel_gmbus_get_adapter(dev_priv, dev_priv 1956 drivers/gpu/drm/i915/display/intel_sdvo.c dev_priv->vbt.crt_ddc_pin)); dev_priv 2219 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 2229 drivers/gpu/drm/i915/display/intel_sdvo.c if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { dev_priv 2231 drivers/gpu/drm/i915/display/intel_sdvo.c dev_priv->vbt.sdvo_lvds_vbt_mode); dev_priv 2522 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, dev_priv 2528 drivers/gpu/drm/i915/display/intel_sdvo.c mapping = &dev_priv->vbt.sdvo_mappings[0]; dev_priv 2530 drivers/gpu/drm/i915/display/intel_sdvo.c mapping = &dev_priv->vbt.sdvo_mappings[1]; dev_priv 2539 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, dev_priv 2546 drivers/gpu/drm/i915/display/intel_sdvo.c mapping = &dev_priv->vbt.sdvo_mappings[0]; dev_priv 2548 drivers/gpu/drm/i915/display/intel_sdvo.c mapping = &dev_priv->vbt.sdvo_mappings[1]; dev_priv 2551 drivers/gpu/drm/i915/display/intel_sdvo.c intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) dev_priv 2556 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); dev_priv 2580 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv, dev_priv 2586 drivers/gpu/drm/i915/display/intel_sdvo.c my_mapping = &dev_priv->vbt.sdvo_mappings[0]; dev_priv 2587 drivers/gpu/drm/i915/display/intel_sdvo.c other_mapping = &dev_priv->vbt.sdvo_mappings[1]; dev_priv 2589 drivers/gpu/drm/i915/display/intel_sdvo.c my_mapping = &dev_priv->vbt.sdvo_mappings[1]; dev_priv 2590 drivers/gpu/drm/i915/display/intel_sdvo.c other_mapping = &dev_priv->vbt.sdvo_mappings[0]; dev_priv 2650 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev); dev_priv 2653 drivers/gpu/drm/i915/display/intel_sdvo.c if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) { dev_priv 3214 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv) dev_priv 3216 drivers/gpu/drm/i915/display/intel_sdvo.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 3229 drivers/gpu/drm/i915/display/intel_sdvo.c static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv, dev_priv 3232 drivers/gpu/drm/i915/display/intel_sdvo.c if (HAS_PCH_SPLIT(dev_priv)) dev_priv 3238 drivers/gpu/drm/i915/display/intel_sdvo.c bool intel_sdvo_init(struct drm_i915_private *dev_priv, dev_priv 3245 drivers/gpu/drm/i915/display/intel_sdvo.c assert_sdvo_port_valid(dev_priv, port); dev_priv 3254 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1; dev_priv 3255 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); dev_priv 3256 drivers/gpu/drm/i915/display/intel_sdvo.c if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv)) dev_priv 3264 drivers/gpu/drm/i915/display/intel_sdvo.c drm_encoder_init(&dev_priv->drm, &intel_encoder->base, dev_priv 3280 drivers/gpu/drm/i915/display/intel_sdvo.c if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 3324 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo); dev_priv 18 drivers/gpu/drm/i915/display/intel_sdvo.h bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, dev_priv 20 drivers/gpu/drm/i915/display/intel_sdvo.h bool intel_sdvo_init(struct drm_i915_private *dev_priv, dev_priv 98 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 103 drivers/gpu/drm/i915/display/intel_sprite.c bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && dev_priv 211 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 231 drivers/gpu/drm/i915/display/intel_sprite.c if (intel_vgpu_active(dev_priv)) dev_priv 334 drivers/gpu/drm/i915/display/intel_sprite.c bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) dev_priv 336 drivers/gpu/drm/i915/display/intel_sprite.c return INTEL_GEN(dev_priv) >= 11 && dev_priv 363 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 385 drivers/gpu/drm/i915/display/intel_sprite.c !icl_is_hdr_plane(dev_priv, plane->id)) { dev_priv 425 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 544 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 566 drivers/gpu/drm/i915/display/intel_sprite.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 586 drivers/gpu/drm/i915/display/intel_sprite.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 594 drivers/gpu/drm/i915/display/intel_sprite.c if (icl_is_hdr_plane(dev_priv, plane_id)) { dev_priv 615 drivers/gpu/drm/i915/display/intel_sprite.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 618 drivers/gpu/drm/i915/display/intel_sprite.c if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) dev_priv 629 drivers/gpu/drm/i915/display/intel_sprite.c if (INTEL_GEN(dev_priv) < 11) dev_priv 646 drivers/gpu/drm/i915/display/intel_sprite.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 678 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 683 drivers/gpu/drm/i915/display/intel_sprite.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 685 drivers/gpu/drm/i915/display/intel_sprite.c if (icl_is_hdr_plane(dev_priv, plane_id)) dev_priv 693 drivers/gpu/drm/i915/display/intel_sprite.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 700 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 707 drivers/gpu/drm/i915/display/intel_sprite.c wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 715 drivers/gpu/drm/i915/display/intel_sprite.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 734 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 793 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 908 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 935 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 958 drivers/gpu/drm/i915/display/intel_sprite.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 966 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) dev_priv 990 drivers/gpu/drm/i915/display/intel_sprite.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 997 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1002 drivers/gpu/drm/i915/display/intel_sprite.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 1007 drivers/gpu/drm/i915/display/intel_sprite.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 1014 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1021 drivers/gpu/drm/i915/display/intel_sprite.c wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 1029 drivers/gpu/drm/i915/display/intel_sprite.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 1050 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = dev_priv 1059 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_IVYBRIDGE(dev_priv)) dev_priv 1122 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1152 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1181 drivers/gpu/drm/i915/display/intel_sprite.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 1186 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_IVYBRIDGE(dev_priv)) dev_priv 1197 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { dev_priv 1215 drivers/gpu/drm/i915/display/intel_sprite.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 1222 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1226 drivers/gpu/drm/i915/display/intel_sprite.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 1230 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_IVYBRIDGE(dev_priv)) dev_priv 1234 drivers/gpu/drm/i915/display/intel_sprite.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 1241 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1247 drivers/gpu/drm/i915/display/intel_sprite.c wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 1255 drivers/gpu/drm/i915/display/intel_sprite.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 1284 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = dev_priv 1293 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_GEN(dev_priv, 6)) dev_priv 1343 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1375 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1405 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1434 drivers/gpu/drm/i915/display/intel_sprite.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 1459 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_G4X(dev_priv)) dev_priv 1464 drivers/gpu/drm/i915/display/intel_sprite.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 1471 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1475 drivers/gpu/drm/i915/display/intel_sprite.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 1482 drivers/gpu/drm/i915/display/intel_sprite.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 1489 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1495 drivers/gpu/drm/i915/display/intel_sprite.c wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 1503 drivers/gpu/drm/i915/display/intel_sprite.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 1587 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1593 drivers/gpu/drm/i915/display/intel_sprite.c if (INTEL_GEN(dev_priv) < 7) { dev_priv 1596 drivers/gpu/drm/i915/display/intel_sprite.c } else if (IS_IVYBRIDGE(dev_priv)) { dev_priv 1624 drivers/gpu/drm/i915/display/intel_sprite.c if (INTEL_GEN(dev_priv) >= 7) dev_priv 1635 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1639 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_CHERRYVIEW(dev_priv) && dev_priv 1687 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1721 drivers/gpu/drm/i915/display/intel_sprite.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 1760 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = dev_priv 1775 drivers/gpu/drm/i915/display/intel_sprite.c if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) && dev_priv 1808 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1856 drivers/gpu/drm/i915/display/intel_sprite.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 1863 drivers/gpu/drm/i915/display/intel_sprite.c static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv) dev_priv 1865 drivers/gpu/drm/i915/display/intel_sprite.c return INTEL_GEN(dev_priv) >= 9; dev_priv 1872 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1889 drivers/gpu/drm/i915/display/intel_sprite.c if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && dev_priv 1897 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1915 drivers/gpu/drm/i915/display/intel_sprite.c if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && dev_priv 1928 drivers/gpu/drm/i915/display/intel_sprite.c if (INTEL_GEN(dev_priv) >= 9 && dev_priv 1952 drivers/gpu/drm/i915/display/intel_sprite.c if (!ret && has_dst_key_in_primary_plane(dev_priv)) { dev_priv 1954 drivers/gpu/drm/i915/display/intel_sprite.c intel_get_crtc_for_pipe(dev_priv, dev_priv 2345 drivers/gpu/drm/i915/display/intel_sprite.c static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv, dev_priv 2348 drivers/gpu/drm/i915/display/intel_sprite.c if (!HAS_FBC(dev_priv)) dev_priv 2354 drivers/gpu/drm/i915/display/intel_sprite.c static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, dev_priv 2358 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) dev_priv 2361 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C) dev_priv 2370 drivers/gpu/drm/i915/display/intel_sprite.c static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, dev_priv 2374 drivers/gpu/drm/i915/display/intel_sprite.c if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { dev_priv 2383 drivers/gpu/drm/i915/display/intel_sprite.c static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, dev_priv 2387 drivers/gpu/drm/i915/display/intel_sprite.c if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { dev_priv 2396 drivers/gpu/drm/i915/display/intel_sprite.c static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, dev_priv 2400 drivers/gpu/drm/i915/display/intel_sprite.c if (icl_is_hdr_plane(dev_priv, plane_id)) { dev_priv 2412 drivers/gpu/drm/i915/display/intel_sprite.c static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, dev_priv 2418 drivers/gpu/drm/i915/display/intel_sprite.c if (INTEL_GEN(dev_priv) >= 10) dev_priv 2421 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_GEMINILAKE(dev_priv)) dev_priv 2430 drivers/gpu/drm/i915/display/intel_sprite.c skl_universal_plane_create(struct drm_i915_private *dev_priv, dev_priv 2450 drivers/gpu/drm/i915/display/intel_sprite.c plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id); dev_priv 2452 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 2465 drivers/gpu/drm/i915/display/intel_sprite.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 2466 drivers/gpu/drm/i915/display/intel_sprite.c formats = icl_get_plane_formats(dev_priv, pipe, dev_priv 2468 drivers/gpu/drm/i915/display/intel_sprite.c else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 2469 drivers/gpu/drm/i915/display/intel_sprite.c formats = glk_get_plane_formats(dev_priv, pipe, dev_priv 2472 drivers/gpu/drm/i915/display/intel_sprite.c formats = skl_get_plane_formats(dev_priv, pipe, dev_priv 2475 drivers/gpu/drm/i915/display/intel_sprite.c plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); dev_priv 2488 drivers/gpu/drm/i915/display/intel_sprite.c ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, dev_priv 2501 drivers/gpu/drm/i915/display/intel_sprite.c if (INTEL_GEN(dev_priv) >= 10) dev_priv 2533 drivers/gpu/drm/i915/display/intel_sprite.c intel_sprite_plane_create(struct drm_i915_private *dev_priv, dev_priv 2545 drivers/gpu/drm/i915/display/intel_sprite.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 2546 drivers/gpu/drm/i915/display/intel_sprite.c return skl_universal_plane_create(dev_priv, pipe, dev_priv 2553 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 2565 drivers/gpu/drm/i915/display/intel_sprite.c } else if (INTEL_GEN(dev_priv) >= 7) { dev_priv 2585 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_GEN(dev_priv, 6)) { dev_priv 2598 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { dev_priv 2613 drivers/gpu/drm/i915/display/intel_sprite.c ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, dev_priv 23 drivers/gpu/drm/i915/display/intel_sprite.h struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, dev_priv 33 drivers/gpu/drm/i915/display/intel_sprite.h skl_universal_plane_create(struct drm_i915_private *dev_priv, dev_priv 51 drivers/gpu/drm/i915/display/intel_sprite.h bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id); dev_priv 909 drivers/gpu/drm/i915/display/intel_tv.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 923 drivers/gpu/drm/i915/display/intel_tv.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 926 drivers/gpu/drm/i915/display/intel_tv.c intel_wait_for_vblank(dev_priv, dev_priv 938 drivers/gpu/drm/i915/display/intel_tv.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1087 drivers/gpu/drm/i915/display/intel_tv.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1161 drivers/gpu/drm/i915/display/intel_tv.c if (IS_I965GM(dev_priv)) dev_priv 1166 drivers/gpu/drm/i915/display/intel_tv.c static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv, dev_priv 1169 drivers/gpu/drm/i915/display/intel_tv.c return IS_GEN(dev_priv, 3) && hdisplay > 1024; dev_priv 1187 drivers/gpu/drm/i915/display/intel_tv.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1212 drivers/gpu/drm/i915/display/intel_tv.c if (intel_tv_source_too_wide(dev_priv, hdisplay) || dev_priv 1330 drivers/gpu/drm/i915/display/intel_tv.c if (IS_I965GM(dev_priv)) dev_priv 1338 drivers/gpu/drm/i915/display/intel_tv.c set_tv_mode_timings(struct drm_i915_private *dev_priv, dev_priv 1396 drivers/gpu/drm/i915/display/intel_tv.c static void set_color_conversion(struct drm_i915_private *dev_priv, dev_priv 1420 drivers/gpu/drm/i915/display/intel_tv.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1510 drivers/gpu/drm/i915/display/intel_tv.c if (IS_I915GM(dev_priv)) dev_priv 1513 drivers/gpu/drm/i915/display/intel_tv.c set_tv_mode_timings(dev_priv, tv_mode, burst_ena); dev_priv 1519 drivers/gpu/drm/i915/display/intel_tv.c set_color_conversion(dev_priv, color_conversion); dev_priv 1521 drivers/gpu/drm/i915/display/intel_tv.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 1531 drivers/gpu/drm/i915/display/intel_tv.c assert_pipe_disabled(dev_priv, intel_crtc->pipe); dev_priv 1571 drivers/gpu/drm/i915/display/intel_tv.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1578 drivers/gpu/drm/i915/display/intel_tv.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 1579 drivers/gpu/drm/i915/display/intel_tv.c i915_disable_pipestat(dev_priv, 0, dev_priv 1582 drivers/gpu/drm/i915/display/intel_tv.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 1608 drivers/gpu/drm/i915/display/intel_tv.c if (IS_GM45(dev_priv)) dev_priv 1616 drivers/gpu/drm/i915/display/intel_tv.c intel_wait_for_vblank(dev_priv, intel_crtc->pipe); dev_priv 1646 drivers/gpu/drm/i915/display/intel_tv.c intel_wait_for_vblank(dev_priv, intel_crtc->pipe); dev_priv 1650 drivers/gpu/drm/i915/display/intel_tv.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 1651 drivers/gpu/drm/i915/display/intel_tv.c i915_enable_pipestat(dev_priv, 0, dev_priv 1654 drivers/gpu/drm/i915/display/intel_tv.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 1767 drivers/gpu/drm/i915/display/intel_tv.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 1781 drivers/gpu/drm/i915/display/intel_tv.c if (IS_GEN(dev_priv, 3) && input->w > 1024 && dev_priv 1862 drivers/gpu/drm/i915/display/intel_tv.c intel_tv_init(struct drm_i915_private *dev_priv) dev_priv 1864 drivers/gpu/drm/i915/display/intel_tv.c struct drm_device *dev = &dev_priv->drm; dev_priv 1877 drivers/gpu/drm/i915/display/intel_tv.c if (!intel_bios_is_tv_present(dev_priv)) { dev_priv 1971 drivers/gpu/drm/i915/display/intel_tv.c if (IS_GEN(dev_priv, 3) && dev_priv 11 drivers/gpu/drm/i915/display/intel_tv.h void intel_tv_init(struct drm_i915_private *dev_priv); dev_priv 487 drivers/gpu/drm/i915/display/intel_vdsc.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 906 drivers/gpu/drm/i915/display/intel_vdsc.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 916 drivers/gpu/drm/i915/display/intel_vdsc.c intel_display_power_get(dev_priv, dev_priv 942 drivers/gpu/drm/i915/display/intel_vdsc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 970 drivers/gpu/drm/i915/display/intel_vdsc.c intel_display_power_put_unchecked(dev_priv, dev_priv 81 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 87 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), dev_priv 92 drivers/gpu/drm/i915/display/vlv_dsi.c static void write_data(struct drm_i915_private *dev_priv, dev_priv 108 drivers/gpu/drm/i915/display/vlv_dsi.c static void read_data(struct drm_i915_private *dev_priv, dev_priv 127 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 156 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), dev_priv 160 drivers/gpu/drm/i915/display/vlv_dsi.c write_data(dev_priv, data_reg, packet.payload, dev_priv 168 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), dev_priv 178 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), dev_priv 182 drivers/gpu/drm/i915/display/vlv_dsi.c read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); dev_priv 217 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 236 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) dev_priv 242 drivers/gpu/drm/i915/display/vlv_dsi.c static void band_gap_reset(struct drm_i915_private *dev_priv) dev_priv 244 drivers/gpu/drm/i915/display/vlv_dsi.c vlv_flisdsi_get(dev_priv); dev_priv 246 drivers/gpu/drm/i915/display/vlv_dsi.c vlv_flisdsi_write(dev_priv, 0x08, 0x0001); dev_priv 247 drivers/gpu/drm/i915/display/vlv_dsi.c vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); dev_priv 248 drivers/gpu/drm/i915/display/vlv_dsi.c vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); dev_priv 250 drivers/gpu/drm/i915/display/vlv_dsi.c vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); dev_priv 251 drivers/gpu/drm/i915/display/vlv_dsi.c vlv_flisdsi_write(dev_priv, 0x08, 0x0000); dev_priv 253 drivers/gpu/drm/i915/display/vlv_dsi.c vlv_flisdsi_put(dev_priv); dev_priv 260 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 275 drivers/gpu/drm/i915/display/vlv_dsi.c if (HAS_GMCH(dev_priv)) dev_priv 294 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEN9_LP(dev_priv)) { dev_priv 321 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 353 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), dev_priv 369 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 376 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), dev_priv 401 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), dev_priv 425 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), dev_priv 432 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), dev_priv 440 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 467 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 474 drivers/gpu/drm/i915/display/vlv_dsi.c vlv_flisdsi_get(dev_priv); dev_priv 477 drivers/gpu/drm/i915/display/vlv_dsi.c vlv_flisdsi_write(dev_priv, 0x04, 0x0004); dev_priv 478 drivers/gpu/drm/i915/display/vlv_dsi.c vlv_flisdsi_put(dev_priv); dev_priv 481 drivers/gpu/drm/i915/display/vlv_dsi.c band_gap_reset(dev_priv); dev_priv 506 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 508 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEMINILAKE(dev_priv)) dev_priv 510 drivers/gpu/drm/i915/display/vlv_dsi.c else if (IS_GEN9_LP(dev_priv)) dev_priv 518 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 533 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), dev_priv 540 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), dev_priv 548 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 560 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), dev_priv 581 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 588 drivers/gpu/drm/i915/display/vlv_dsi.c i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? dev_priv 608 drivers/gpu/drm/i915/display/vlv_dsi.c if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && dev_priv 609 drivers/gpu/drm/i915/display/vlv_dsi.c intel_de_wait_for_clear(dev_priv, port_ctrl, dev_priv 626 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 633 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEN9_LP(dev_priv)) { dev_priv 651 drivers/gpu/drm/i915/display/vlv_dsi.c i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? dev_priv 663 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_BROXTON(dev_priv)) dev_priv 683 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 688 drivers/gpu/drm/i915/display/vlv_dsi.c i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? dev_priv 750 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 759 drivers/gpu/drm/i915/display/vlv_dsi.c intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); dev_priv 765 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEN9_LP(dev_priv)) { dev_priv 773 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_BROXTON(dev_priv)) { dev_priv 784 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 793 drivers/gpu/drm/i915/display/vlv_dsi.c if (!IS_GEMINILAKE(dev_priv)) dev_priv 805 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEMINILAKE(dev_priv)) { dev_priv 817 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) dev_priv 876 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 878 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEMINILAKE(dev_priv)) dev_priv 888 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 916 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_BROXTON(dev_priv)) { dev_priv 927 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEN9_LP(dev_priv)) { dev_priv 958 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 966 drivers/gpu/drm/i915/display/vlv_dsi.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 976 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) dev_priv 981 drivers/gpu/drm/i915/display/vlv_dsi.c i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? dev_priv 990 drivers/gpu/drm/i915/display/vlv_dsi.c if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && dev_priv 1006 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEN9_LP(dev_priv)) { dev_priv 1024 drivers/gpu/drm/i915/display/vlv_dsi.c intel_display_power_put(dev_priv, encoder->power_domain, wakeref); dev_priv 1033 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1193 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1199 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEN9_LP(dev_priv)) { dev_priv 1230 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1265 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEN9_LP(dev_priv)) { dev_priv 1317 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1337 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 1352 drivers/gpu/drm/i915/display/vlv_dsi.c } else if (IS_GEN9_LP(dev_priv)) { dev_priv 1390 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEN9_LP(dev_priv)) { dev_priv 1441 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { dev_priv 1475 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEMINILAKE(dev_priv)) { dev_priv 1508 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 1513 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEMINILAKE(dev_priv)) dev_priv 1520 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEN9_LP(dev_priv)) dev_priv 1569 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1582 drivers/gpu/drm/i915/display/vlv_dsi.c crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 1586 drivers/gpu/drm/i915/display/vlv_dsi.c wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 1599 drivers/gpu/drm/i915/display/vlv_dsi.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 1607 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1610 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 1621 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); dev_priv 1627 drivers/gpu/drm/i915/display/vlv_dsi.c if (!HAS_GMCH(dev_priv)) dev_priv 1654 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1655 drivers/gpu/drm/i915/display/vlv_dsi.c struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; dev_priv 1702 drivers/gpu/drm/i915/display/vlv_dsi.c mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; dev_priv 1812 drivers/gpu/drm/i915/display/vlv_dsi.c void vlv_dsi_init(struct drm_i915_private *dev_priv) dev_priv 1814 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_device *dev = &dev_priv->drm; dev_priv 1826 drivers/gpu/drm/i915/display/vlv_dsi.c if (!intel_bios_is_dsi_present(dev_priv, &port)) dev_priv 1829 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEN9_LP(dev_priv)) dev_priv 1830 drivers/gpu/drm/i915/display/vlv_dsi.c dev_priv->mipi_mmio_base = BXT_MIPI_BASE; dev_priv 1832 drivers/gpu/drm/i915/display/vlv_dsi.c dev_priv->mipi_mmio_base = VLV_MIPI_BASE; dev_priv 1872 drivers/gpu/drm/i915/display/vlv_dsi.c if (IS_GEN9_LP(dev_priv)) dev_priv 1879 drivers/gpu/drm/i915/display/vlv_dsi.c if (dev_priv->vbt.dsi.config->dual_link) dev_priv 1884 drivers/gpu/drm/i915/display/vlv_dsi.c intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; dev_priv 1885 drivers/gpu/drm/i915/display/vlv_dsi.c intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; dev_priv 1924 drivers/gpu/drm/i915/display/vlv_dsi.c if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && dev_priv 1925 drivers/gpu/drm/i915/display/vlv_dsi.c (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) { dev_priv 56 drivers/gpu/drm/i915/display/vlv_dsi_pll.c static int dsi_calc_mnp(struct drm_i915_private *dev_priv, dev_priv 71 drivers/gpu/drm/i915/display/vlv_dsi_pll.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 119 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 127 drivers/gpu/drm/i915/display/vlv_dsi_pll.c ret = dsi_calc_mnp(dev_priv, config, dsi_clk); dev_priv 150 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 154 drivers/gpu/drm/i915/display/vlv_dsi_pll.c vlv_cck_get(dev_priv); dev_priv 156 drivers/gpu/drm/i915/display/vlv_dsi_pll.c vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); dev_priv 157 drivers/gpu/drm/i915/display/vlv_dsi_pll.c vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div); dev_priv 158 drivers/gpu/drm/i915/display/vlv_dsi_pll.c vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dev_priv 166 drivers/gpu/drm/i915/display/vlv_dsi_pll.c vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl); dev_priv 168 drivers/gpu/drm/i915/display/vlv_dsi_pll.c if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & dev_priv 171 drivers/gpu/drm/i915/display/vlv_dsi_pll.c vlv_cck_put(dev_priv); dev_priv 175 drivers/gpu/drm/i915/display/vlv_dsi_pll.c vlv_cck_put(dev_priv); dev_priv 182 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 187 drivers/gpu/drm/i915/display/vlv_dsi_pll.c vlv_cck_get(dev_priv); dev_priv 189 drivers/gpu/drm/i915/display/vlv_dsi_pll.c tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); dev_priv 192 drivers/gpu/drm/i915/display/vlv_dsi_pll.c vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); dev_priv 194 drivers/gpu/drm/i915/display/vlv_dsi_pll.c vlv_cck_put(dev_priv); dev_priv 197 drivers/gpu/drm/i915/display/vlv_dsi_pll.c bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) dev_priv 219 drivers/gpu/drm/i915/display/vlv_dsi_pll.c if (IS_GEMINILAKE(dev_priv)) { dev_priv 236 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 249 drivers/gpu/drm/i915/display/vlv_dsi_pll.c if (intel_de_wait_for_clear(dev_priv, BXT_DSI_PLL_ENABLE, dev_priv 257 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 263 drivers/gpu/drm/i915/display/vlv_dsi_pll.c int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; dev_priv 268 drivers/gpu/drm/i915/display/vlv_dsi_pll.c vlv_cck_get(dev_priv); dev_priv 269 drivers/gpu/drm/i915/display/vlv_dsi_pll.c pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); dev_priv 270 drivers/gpu/drm/i915/display/vlv_dsi_pll.c pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); dev_priv 271 drivers/gpu/drm/i915/display/vlv_dsi_pll.c vlv_cck_put(dev_priv); dev_priv 325 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 343 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 356 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 404 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 457 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 472 drivers/gpu/drm/i915/display/vlv_dsi_pll.c if (IS_BROXTON(dev_priv)) { dev_priv 496 drivers/gpu/drm/i915/display/vlv_dsi_pll.c if (IS_BROXTON(dev_priv) && dsi_ratio <= 50) dev_priv 505 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); dev_priv 517 drivers/gpu/drm/i915/display/vlv_dsi_pll.c if (IS_BROXTON(dev_priv)) { dev_priv 530 drivers/gpu/drm/i915/display/vlv_dsi_pll.c if (intel_de_wait_for_set(dev_priv, BXT_DSI_PLL_ENABLE, dev_priv 543 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 546 drivers/gpu/drm/i915/display/vlv_dsi_pll.c if (IS_BROXTON(dev_priv)) { dev_priv 523 drivers/gpu/drm/i915/gem/i915_gem_context.c i915_gem_create_context(struct drm_i915_private *dev_priv, unsigned int flags) dev_priv 527 drivers/gpu/drm/i915/gem/i915_gem_context.c lockdep_assert_held(&dev_priv->drm.struct_mutex); dev_priv 530 drivers/gpu/drm/i915/gem/i915_gem_context.c !HAS_EXECLISTS(dev_priv)) dev_priv 534 drivers/gpu/drm/i915/gem/i915_gem_context.c contexts_free_first(dev_priv); dev_priv 536 drivers/gpu/drm/i915/gem/i915_gem_context.c ctx = __create_context(dev_priv); dev_priv 540 drivers/gpu/drm/i915/gem/i915_gem_context.c if (HAS_FULL_PPGTT(dev_priv)) { dev_priv 543 drivers/gpu/drm/i915/gem/i915_gem_context.c ppgtt = i915_ppgtt_create(dev_priv); dev_priv 558 drivers/gpu/drm/i915/gem/i915_gem_context.c timeline = intel_timeline_create(&dev_priv->gt, NULL); dev_priv 625 drivers/gpu/drm/i915/gem/i915_gem_context.c int i915_gem_contexts_init(struct drm_i915_private *dev_priv) dev_priv 630 drivers/gpu/drm/i915/gem/i915_gem_context.c GEM_BUG_ON(dev_priv->kernel_context); dev_priv 632 drivers/gpu/drm/i915/gem/i915_gem_context.c init_contexts(dev_priv); dev_priv 635 drivers/gpu/drm/i915/gem/i915_gem_context.c ctx = i915_gem_context_create_kernel(dev_priv, I915_PRIORITY_MIN); dev_priv 649 drivers/gpu/drm/i915/gem/i915_gem_context.c dev_priv->kernel_context = ctx; dev_priv 652 drivers/gpu/drm/i915/gem/i915_gem_context.c DRIVER_CAPS(dev_priv)->has_logical_contexts ? dev_priv 2304 drivers/gpu/drm/i915/gem/i915_gem_context.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 2326 drivers/gpu/drm/i915/gem/i915_gem_context.c args->reset_count = i915_reset_count(&dev_priv->gpu_error); dev_priv 136 drivers/gpu/drm/i915/gem/i915_gem_context.h int __must_check i915_gem_contexts_init(struct drm_i915_private *dev_priv); dev_priv 137 drivers/gpu/drm/i915/gem/i915_gem_context.h void i915_gem_contexts_fini(struct drm_i915_private *dev_priv); dev_priv 1966 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c struct drm_i915_private *dev_priv = eb->i915; dev_priv 1975 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c if (CMDPARSER_USES_GGTT(dev_priv)) { dev_priv 1977 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c vm = &dev_priv->ggtt.vm; dev_priv 2119 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv, dev_priv 2127 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c get_random_int() % num_vcs_engines(dev_priv); dev_priv 532 drivers/gpu/drm/i915/gem/i915_gem_shmem.c i915_gem_object_create_shmem_from_data(struct drm_i915_private *dev_priv, dev_priv 540 drivers/gpu/drm/i915/gem/i915_gem_shmem.c obj = i915_gem_object_create_shmem(dev_priv, round_up(size, PAGE_SIZE)); dev_priv 28 drivers/gpu/drm/i915/gem/i915_gem_stolen.c int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, dev_priv 34 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (!drm_mm_initialized(&dev_priv->mm.stolen)) dev_priv 38 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (INTEL_GEN(dev_priv) >= 8 && start < 4096) dev_priv 41 drivers/gpu/drm/i915/gem/i915_gem_stolen.c mutex_lock(&dev_priv->mm.stolen_lock); dev_priv 42 drivers/gpu/drm/i915/gem/i915_gem_stolen.c ret = drm_mm_insert_node_in_range(&dev_priv->mm.stolen, node, dev_priv 45 drivers/gpu/drm/i915/gem/i915_gem_stolen.c mutex_unlock(&dev_priv->mm.stolen_lock); dev_priv 50 drivers/gpu/drm/i915/gem/i915_gem_stolen.c int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, dev_priv 54 drivers/gpu/drm/i915/gem/i915_gem_stolen.c return i915_gem_stolen_insert_node_in_range(dev_priv, node, size, dev_priv 58 drivers/gpu/drm/i915/gem/i915_gem_stolen.c void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, dev_priv 61 drivers/gpu/drm/i915/gem/i915_gem_stolen.c mutex_lock(&dev_priv->mm.stolen_lock); dev_priv 63 drivers/gpu/drm/i915/gem/i915_gem_stolen.c mutex_unlock(&dev_priv->mm.stolen_lock); dev_priv 66 drivers/gpu/drm/i915/gem/i915_gem_stolen.c static int i915_adjust_stolen(struct drm_i915_private *dev_priv, dev_priv 69 drivers/gpu/drm/i915/gem/i915_gem_stolen.c struct i915_ggtt *ggtt = &dev_priv->ggtt; dev_priv 81 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (INTEL_GEN(dev_priv) <= 4 && dev_priv 82 drivers/gpu/drm/i915/gem/i915_gem_stolen.c !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv) && !IS_G4X(dev_priv)) { dev_priv 88 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (IS_GEN(dev_priv, 4)) dev_priv 122 drivers/gpu/drm/i915/gem/i915_gem_stolen.c r = devm_request_mem_region(dev_priv->drm.dev, dsm->start, dev_priv 135 drivers/gpu/drm/i915/gem/i915_gem_stolen.c r = devm_request_mem_region(dev_priv->drm.dev, dsm->start + 1, dev_priv 142 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (r == NULL && !IS_GEN(dev_priv, 3)) { dev_priv 153 drivers/gpu/drm/i915/gem/i915_gem_stolen.c void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv) dev_priv 155 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (!drm_mm_initialized(&dev_priv->mm.stolen)) dev_priv 158 drivers/gpu/drm/i915/gem/i915_gem_stolen.c drm_mm_takedown(&dev_priv->mm.stolen); dev_priv 161 drivers/gpu/drm/i915/gem/i915_gem_stolen.c static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv, dev_priv 165 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u32 reg_val = I915_READ(IS_GM45(dev_priv) ? dev_priv 168 drivers/gpu/drm/i915/gem/i915_gem_stolen.c resource_size_t stolen_top = dev_priv->dsm.end + 1; dev_priv 171 drivers/gpu/drm/i915/gem/i915_gem_stolen.c IS_GM45(dev_priv) ? "CTG" : "ELK", reg_val); dev_priv 180 drivers/gpu/drm/i915/gem/i915_gem_stolen.c WARN(IS_GEN(dev_priv, 5), "ILK stolen reserved found? 0x%08x\n", dev_priv 192 drivers/gpu/drm/i915/gem/i915_gem_stolen.c static void gen6_get_stolen_reserved(struct drm_i915_private *dev_priv, dev_priv 224 drivers/gpu/drm/i915/gem/i915_gem_stolen.c static void vlv_get_stolen_reserved(struct drm_i915_private *dev_priv, dev_priv 229 drivers/gpu/drm/i915/gem/i915_gem_stolen.c resource_size_t stolen_top = dev_priv->dsm.end + 1; dev_priv 252 drivers/gpu/drm/i915/gem/i915_gem_stolen.c static void gen7_get_stolen_reserved(struct drm_i915_private *dev_priv, dev_priv 278 drivers/gpu/drm/i915/gem/i915_gem_stolen.c static void chv_get_stolen_reserved(struct drm_i915_private *dev_priv, dev_priv 310 drivers/gpu/drm/i915/gem/i915_gem_stolen.c static void bdw_get_stolen_reserved(struct drm_i915_private *dev_priv, dev_priv 315 drivers/gpu/drm/i915/gem/i915_gem_stolen.c resource_size_t stolen_top = dev_priv->dsm.end + 1; dev_priv 358 drivers/gpu/drm/i915/gem/i915_gem_stolen.c int i915_gem_init_stolen(struct drm_i915_private *dev_priv) dev_priv 363 drivers/gpu/drm/i915/gem/i915_gem_stolen.c mutex_init(&dev_priv->mm.stolen_lock); dev_priv 365 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (intel_vgpu_active(dev_priv)) { dev_priv 366 drivers/gpu/drm/i915/gem/i915_gem_stolen.c dev_notice(dev_priv->drm.dev, dev_priv 372 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) { dev_priv 373 drivers/gpu/drm/i915/gem/i915_gem_stolen.c dev_notice(dev_priv->drm.dev, dev_priv 382 drivers/gpu/drm/i915/gem/i915_gem_stolen.c dev_priv->dsm = intel_graphics_stolen_res; dev_priv 384 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (i915_adjust_stolen(dev_priv, &dev_priv->dsm)) dev_priv 387 drivers/gpu/drm/i915/gem/i915_gem_stolen.c GEM_BUG_ON(dev_priv->dsm.start == 0); dev_priv 388 drivers/gpu/drm/i915/gem/i915_gem_stolen.c GEM_BUG_ON(dev_priv->dsm.end <= dev_priv->dsm.start); dev_priv 390 drivers/gpu/drm/i915/gem/i915_gem_stolen.c stolen_top = dev_priv->dsm.end + 1; dev_priv 394 drivers/gpu/drm/i915/gem/i915_gem_stolen.c switch (INTEL_GEN(dev_priv)) { dev_priv 399 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (!IS_G4X(dev_priv)) dev_priv 403 drivers/gpu/drm/i915/gem/i915_gem_stolen.c g4x_get_stolen_reserved(dev_priv, dev_priv 407 drivers/gpu/drm/i915/gem/i915_gem_stolen.c gen6_get_stolen_reserved(dev_priv, dev_priv 411 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (IS_VALLEYVIEW(dev_priv)) dev_priv 412 drivers/gpu/drm/i915/gem/i915_gem_stolen.c vlv_get_stolen_reserved(dev_priv, dev_priv 415 drivers/gpu/drm/i915/gem/i915_gem_stolen.c gen7_get_stolen_reserved(dev_priv, dev_priv 421 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (IS_LP(dev_priv)) dev_priv 422 drivers/gpu/drm/i915/gem/i915_gem_stolen.c chv_get_stolen_reserved(dev_priv, dev_priv 425 drivers/gpu/drm/i915/gem/i915_gem_stolen.c bdw_get_stolen_reserved(dev_priv, dev_priv 430 drivers/gpu/drm/i915/gem/i915_gem_stolen.c icl_get_stolen_reserved(dev_priv, &reserved_base, dev_priv 447 drivers/gpu/drm/i915/gem/i915_gem_stolen.c dev_priv->dsm_reserved = dev_priv 450 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (!resource_contains(&dev_priv->dsm, &dev_priv->dsm_reserved)) { dev_priv 452 drivers/gpu/drm/i915/gem/i915_gem_stolen.c &dev_priv->dsm_reserved, &dev_priv->dsm); dev_priv 461 drivers/gpu/drm/i915/gem/i915_gem_stolen.c (u64)resource_size(&dev_priv->dsm) >> 10, dev_priv 462 drivers/gpu/drm/i915/gem/i915_gem_stolen.c ((u64)resource_size(&dev_priv->dsm) - reserved_total) >> 10); dev_priv 464 drivers/gpu/drm/i915/gem/i915_gem_stolen.c dev_priv->stolen_usable_size = dev_priv 465 drivers/gpu/drm/i915/gem/i915_gem_stolen.c resource_size(&dev_priv->dsm) - reserved_total; dev_priv 468 drivers/gpu/drm/i915/gem/i915_gem_stolen.c drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->stolen_usable_size); dev_priv 477 drivers/gpu/drm/i915/gem/i915_gem_stolen.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 481 drivers/gpu/drm/i915/gem/i915_gem_stolen.c GEM_BUG_ON(range_overflows(offset, size, resource_size(&dev_priv->dsm))); dev_priv 501 drivers/gpu/drm/i915/gem/i915_gem_stolen.c sg_dma_address(sg) = (dma_addr_t)dev_priv->dsm.start + offset; dev_priv 532 drivers/gpu/drm/i915/gem/i915_gem_stolen.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); dev_priv 537 drivers/gpu/drm/i915/gem/i915_gem_stolen.c i915_gem_stolen_remove_node(dev_priv, stolen); dev_priv 548 drivers/gpu/drm/i915/gem/i915_gem_stolen.c _i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, dev_priv 558 drivers/gpu/drm/i915/gem/i915_gem_stolen.c drm_gem_private_object_init(&dev_priv->drm, &obj->base, stolen->size); dev_priv 563 drivers/gpu/drm/i915/gem/i915_gem_stolen.c cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE; dev_priv 577 drivers/gpu/drm/i915/gem/i915_gem_stolen.c i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, dev_priv 584 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (!drm_mm_initialized(&dev_priv->mm.stolen)) dev_priv 594 drivers/gpu/drm/i915/gem/i915_gem_stolen.c ret = i915_gem_stolen_insert_node(dev_priv, stolen, size, 4096); dev_priv 600 drivers/gpu/drm/i915/gem/i915_gem_stolen.c obj = _i915_gem_object_create_stolen(dev_priv, stolen); dev_priv 604 drivers/gpu/drm/i915/gem/i915_gem_stolen.c i915_gem_stolen_remove_node(dev_priv, stolen); dev_priv 610 drivers/gpu/drm/i915/gem/i915_gem_stolen.c i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv, dev_priv 615 drivers/gpu/drm/i915/gem/i915_gem_stolen.c struct i915_ggtt *ggtt = &dev_priv->ggtt; dev_priv 621 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (!drm_mm_initialized(&dev_priv->mm.stolen)) dev_priv 624 drivers/gpu/drm/i915/gem/i915_gem_stolen.c lockdep_assert_held(&dev_priv->drm.struct_mutex); dev_priv 641 drivers/gpu/drm/i915/gem/i915_gem_stolen.c mutex_lock(&dev_priv->mm.stolen_lock); dev_priv 642 drivers/gpu/drm/i915/gem/i915_gem_stolen.c ret = drm_mm_reserve_node(&dev_priv->mm.stolen, stolen); dev_priv 643 drivers/gpu/drm/i915/gem/i915_gem_stolen.c mutex_unlock(&dev_priv->mm.stolen_lock); dev_priv 650 drivers/gpu/drm/i915/gem/i915_gem_stolen.c obj = _i915_gem_object_create_stolen(dev_priv, stolen); dev_priv 653 drivers/gpu/drm/i915/gem/i915_gem_stolen.c i915_gem_stolen_remove_node(dev_priv, stolen); dev_priv 15 drivers/gpu/drm/i915/gem/i915_gem_stolen.h int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, dev_priv 18 drivers/gpu/drm/i915/gem/i915_gem_stolen.h int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, dev_priv 22 drivers/gpu/drm/i915/gem/i915_gem_stolen.h void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, dev_priv 24 drivers/gpu/drm/i915/gem/i915_gem_stolen.h int i915_gem_init_stolen(struct drm_i915_private *dev_priv); dev_priv 25 drivers/gpu/drm/i915/gem/i915_gem_stolen.h void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv); dev_priv 27 drivers/gpu/drm/i915/gem/i915_gem_stolen.h i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, dev_priv 30 drivers/gpu/drm/i915/gem/i915_gem_stolen.h i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv, dev_priv 401 drivers/gpu/drm/i915/gem/i915_gem_tiling.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 418 drivers/gpu/drm/i915/gem/i915_gem_tiling.c args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; dev_priv 421 drivers/gpu/drm/i915/gem/i915_gem_tiling.c args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; dev_priv 430 drivers/gpu/drm/i915/gem/i915_gem_tiling.c if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) dev_priv 330 drivers/gpu/drm/i915/gem/i915_gem_userptr.c __i915_mm_struct_find(struct drm_i915_private *dev_priv, struct mm_struct *real) dev_priv 335 drivers/gpu/drm/i915/gem/i915_gem_userptr.c hash_for_each_possible(dev_priv->mm_structs, mm, node, (unsigned long)real) dev_priv 345 drivers/gpu/drm/i915/gem/i915_gem_userptr.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); dev_priv 359 drivers/gpu/drm/i915/gem/i915_gem_userptr.c mutex_lock(&dev_priv->mm_lock); dev_priv 360 drivers/gpu/drm/i915/gem/i915_gem_userptr.c mm = __i915_mm_struct_find(dev_priv, current->mm); dev_priv 377 drivers/gpu/drm/i915/gem/i915_gem_userptr.c hash_add(dev_priv->mm_structs, dev_priv 384 drivers/gpu/drm/i915/gem/i915_gem_userptr.c mutex_unlock(&dev_priv->mm_lock); dev_priv 782 drivers/gpu/drm/i915/gem/i915_gem_userptr.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 788 drivers/gpu/drm/i915/gem/i915_gem_userptr.c if (!HAS_LLC(dev_priv) && !HAS_SNOOP(dev_priv)) { dev_priv 815 drivers/gpu/drm/i915/gem/i915_gem_userptr.c vm = dev_priv->kernel_context->vm; dev_priv 853 drivers/gpu/drm/i915/gem/i915_gem_userptr.c int i915_gem_init_userptr(struct drm_i915_private *dev_priv) dev_priv 855 drivers/gpu/drm/i915/gem/i915_gem_userptr.c mutex_init(&dev_priv->mm_lock); dev_priv 856 drivers/gpu/drm/i915/gem/i915_gem_userptr.c hash_init(dev_priv->mm_structs); dev_priv 858 drivers/gpu/drm/i915/gem/i915_gem_userptr.c dev_priv->mm.userptr_wq = dev_priv 862 drivers/gpu/drm/i915/gem/i915_gem_userptr.c if (!dev_priv->mm.userptr_wq) dev_priv 868 drivers/gpu/drm/i915/gem/i915_gem_userptr.c void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv) dev_priv 870 drivers/gpu/drm/i915/gem/i915_gem_userptr.c destroy_workqueue(dev_priv->mm.userptr_wq); dev_priv 1315 drivers/gpu/drm/i915/gem/selftests/huge_pages.c struct drm_i915_private *dev_priv = ctx->i915; dev_priv 1316 drivers/gpu/drm/i915/gem/selftests/huge_pages.c unsigned long supported = INTEL_INFO(dev_priv)->page_sizes; dev_priv 1346 drivers/gpu/drm/i915/gem/selftests/huge_pages.c obj = i915_gem_object_create_internal(dev_priv, page_size); dev_priv 1400 drivers/gpu/drm/i915/gem/selftests/huge_pages.c obj = i915_gem_object_create_internal(dev_priv, PAGE_SIZE); dev_priv 1422 drivers/gpu/drm/i915/gem/selftests/huge_pages.c for_each_engine(engine, dev_priv, id) { dev_priv 1608 drivers/gpu/drm/i915/gem/selftests/huge_pages.c struct drm_i915_private *dev_priv; dev_priv 1612 drivers/gpu/drm/i915/gem/selftests/huge_pages.c dev_priv = mock_gem_device(); dev_priv 1613 drivers/gpu/drm/i915/gem/selftests/huge_pages.c if (!dev_priv) dev_priv 1617 drivers/gpu/drm/i915/gem/selftests/huge_pages.c mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL; dev_priv 1618 drivers/gpu/drm/i915/gem/selftests/huge_pages.c mkwrite_device_info(dev_priv)->ppgtt_size = 48; dev_priv 1620 drivers/gpu/drm/i915/gem/selftests/huge_pages.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 1621 drivers/gpu/drm/i915/gem/selftests/huge_pages.c ppgtt = i915_ppgtt_create(dev_priv); dev_priv 1646 drivers/gpu/drm/i915/gem/selftests/huge_pages.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1647 drivers/gpu/drm/i915/gem/selftests/huge_pages.c drm_dev_put(&dev_priv->drm); dev_priv 155 drivers/gpu/drm/i915/gt/intel_engine_cs.c u32 intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class) dev_priv 163 drivers/gpu/drm/i915/gt/intel_engine_cs.c switch (INTEL_GEN(dev_priv)) { dev_priv 165 drivers/gpu/drm/i915/gt/intel_engine_cs.c MISSING_CASE(INTEL_GEN(dev_priv)); dev_priv 177 drivers/gpu/drm/i915/gt/intel_engine_cs.c if (IS_HASWELL(dev_priv)) dev_priv 201 drivers/gpu/drm/i915/gt/intel_engine_cs.c INTEL_GEN(dev_priv), dev_priv 218 drivers/gpu/drm/i915/gt/intel_engine_cs.c if (INTEL_GEN(dev_priv) < 8) dev_priv 1199 drivers/gpu/drm/i915/gt/intel_engine_cs.c struct drm_i915_private *dev_priv = engine->i915; dev_priv 1203 drivers/gpu/drm/i915/gt/intel_engine_cs.c if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7)) dev_priv 1220 drivers/gpu/drm/i915/gt/intel_engine_cs.c if (INTEL_GEN(dev_priv) >= 6) { dev_priv 1231 drivers/gpu/drm/i915/gt/intel_engine_cs.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 1233 drivers/gpu/drm/i915/gt/intel_engine_cs.c else if (INTEL_GEN(dev_priv) >= 4) dev_priv 1239 drivers/gpu/drm/i915/gt/intel_engine_cs.c if (INTEL_GEN(dev_priv) >= 4) { dev_priv 1249 drivers/gpu/drm/i915/gt/intel_engine_cs.c if (HAS_EXECLISTS(dev_priv)) { dev_priv 1311 drivers/gpu/drm/i915/gt/intel_engine_cs.c } else if (INTEL_GEN(dev_priv) > 6) { dev_priv 55 drivers/gpu/drm/i915/gt/intel_hangcheck.c struct drm_i915_private *dev_priv = engine->i915; dev_priv 74 drivers/gpu/drm/i915/gt/intel_hangcheck.c for_each_instdone_slice_subslice(dev_priv, slice, subslice) { dev_priv 507 drivers/gpu/drm/i915/gt/intel_ringbuffer.c struct drm_i915_private *dev_priv = engine->i915; dev_priv 511 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 533 drivers/gpu/drm/i915/gt/intel_ringbuffer.c struct drm_i915_private *dev_priv = engine->i915; dev_priv 540 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (IS_GEN(dev_priv, 7)) { dev_priv 562 drivers/gpu/drm/i915/gt/intel_ringbuffer.c } else if (IS_GEN(dev_priv, 6)) { dev_priv 574 drivers/gpu/drm/i915/gt/intel_ringbuffer.c struct drm_i915_private *dev_priv = engine->i915; dev_priv 576 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (!IS_GEN_RANGE(dev_priv, 6, 7)) dev_priv 603 drivers/gpu/drm/i915/gt/intel_ringbuffer.c struct drm_i915_private *dev_priv = engine->i915; dev_priv 605 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (INTEL_GEN(dev_priv) > 2) { dev_priv 640 drivers/gpu/drm/i915/gt/intel_ringbuffer.c struct drm_i915_private *dev_priv = engine->i915; dev_priv 673 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (HWS_NEEDS_PHYSICAL(dev_priv)) dev_priv 721 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (INTEL_GEN(dev_priv) > 2) dev_priv 853 drivers/gpu/drm/i915/gt/intel_ringbuffer.c struct drm_i915_private *dev_priv = engine->i915; dev_priv 865 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (IS_GEN(dev_priv, 4)) dev_priv 870 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (IS_GEN_RANGE(dev_priv, 4, 6)) dev_priv 879 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (IS_GEN_RANGE(dev_priv, 6, 7)) dev_priv 884 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (IS_GEN(dev_priv, 6)) dev_priv 889 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (IS_GEN(dev_priv, 7)) dev_priv 894 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (IS_GEN(dev_priv, 6)) { dev_priv 904 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (IS_GEN_RANGE(dev_priv, 6, 7)) dev_priv 2155 drivers/gpu/drm/i915/gt/intel_ringbuffer.c struct drm_i915_private *dev_priv = engine->i915; dev_priv 2157 drivers/gpu/drm/i915/gt/intel_ringbuffer.c WARN_ON(INTEL_GEN(dev_priv) > 2 && dev_priv 431 drivers/gpu/drm/i915/gt/uc/intel_guc.c struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915; dev_priv 436 drivers/gpu/drm/i915/gt/uc/intel_guc.c if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) dev_priv 70 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915; dev_priv 96 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c intel_engine_context_size(dev_priv, engine_class) - dev_priv 101 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask); dev_priv 105 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv); dev_priv 106 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv); dev_priv 107 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access; dev_priv 369 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915; dev_priv 389 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c dev_priv->drm.primary->debugfs_root, dev_priv 391 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c &relay_callbacks, dev_priv); dev_priv 416 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915; dev_priv 425 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) dev_priv 512 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915; dev_priv 526 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 531 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) dev_priv 544 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 113 drivers/gpu/drm/i915/gt/uc/selftest_guc.c struct drm_i915_private *dev_priv = args; dev_priv 118 drivers/gpu/drm/i915/gt/uc/selftest_guc.c GEM_BUG_ON(!HAS_GT_UC(dev_priv)); dev_priv 119 drivers/gpu/drm/i915/gt/uc/selftest_guc.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 120 drivers/gpu/drm/i915/gt/uc/selftest_guc.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 122 drivers/gpu/drm/i915/gt/uc/selftest_guc.c guc = &dev_priv->gt.uc.guc; dev_priv 192 drivers/gpu/drm/i915/gt/uc/selftest_guc.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 193 drivers/gpu/drm/i915/gt/uc/selftest_guc.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 204 drivers/gpu/drm/i915/gt/uc/selftest_guc.c struct drm_i915_private *dev_priv = arg; dev_priv 210 drivers/gpu/drm/i915/gt/uc/selftest_guc.c GEM_BUG_ON(!HAS_GT_UC(dev_priv)); dev_priv 211 drivers/gpu/drm/i915/gt/uc/selftest_guc.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 212 drivers/gpu/drm/i915/gt/uc/selftest_guc.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 214 drivers/gpu/drm/i915/gt/uc/selftest_guc.c guc = &dev_priv->gt.uc.guc; dev_priv 301 drivers/gpu/drm/i915/gt/uc/selftest_guc.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 302 drivers/gpu/drm/i915/gt/uc/selftest_guc.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 306 drivers/gpu/drm/i915/gt/uc/selftest_guc.c int intel_guc_live_selftest(struct drm_i915_private *dev_priv) dev_priv 313 drivers/gpu/drm/i915/gt/uc/selftest_guc.c if (!USES_GUC_SUBMISSION(dev_priv)) dev_priv 316 drivers/gpu/drm/i915/gt/uc/selftest_guc.c return i915_subtests(tests, dev_priv); dev_priv 44 drivers/gpu/drm/i915/gvt/aperture_gm.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 64 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 65 drivers/gpu/drm/i915/gvt/aperture_gm.c mmio_hw_access_pre(dev_priv); dev_priv 66 drivers/gpu/drm/i915/gvt/aperture_gm.c ret = i915_gem_gtt_insert(&dev_priv->ggtt.vm, node, dev_priv 70 drivers/gpu/drm/i915/gvt/aperture_gm.c mmio_hw_access_post(dev_priv); dev_priv 71 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 82 drivers/gpu/drm/i915/gvt/aperture_gm.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 101 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 103 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 109 drivers/gpu/drm/i915/gvt/aperture_gm.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 111 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 114 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 131 drivers/gpu/drm/i915/gvt/aperture_gm.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 135 drivers/gpu/drm/i915/gvt/aperture_gm.c assert_rpm_wakelock_held(&dev_priv->runtime_pm); dev_priv 166 drivers/gpu/drm/i915/gvt/aperture_gm.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 173 drivers/gpu/drm/i915/gvt/aperture_gm.c intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 175 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_lock(&dev_priv->ggtt.vm.mutex); dev_priv 182 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_unlock(&dev_priv->ggtt.vm.mutex); dev_priv 184 drivers/gpu/drm/i915/gvt/aperture_gm.c intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); dev_priv 190 drivers/gpu/drm/i915/gvt/aperture_gm.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 191 drivers/gpu/drm/i915/gvt/aperture_gm.c struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; dev_priv 198 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_lock(&dev_priv->ggtt.vm.mutex); dev_priv 201 drivers/gpu/drm/i915/gvt/aperture_gm.c reg = i915_reserve_fence(dev_priv); dev_priv 210 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_unlock(&dev_priv->ggtt.vm.mutex); dev_priv 223 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_unlock(&dev_priv->ggtt.vm.mutex); dev_priv 318 drivers/gpu/drm/i915/gvt/aperture_gm.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 320 drivers/gpu/drm/i915/gvt/aperture_gm.c intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 322 drivers/gpu/drm/i915/gvt/aperture_gm.c intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); dev_priv 394 drivers/gpu/drm/i915/gvt/cfg_space.c pci_resource_len(gvt->dev_priv->drm.pdev, 0); dev_priv 396 drivers/gpu/drm/i915/gvt/cfg_space.c pci_resource_len(gvt->dev_priv->drm.pdev, 2); dev_priv 841 drivers/gpu/drm/i915/gvt/cmd_parser.c struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; dev_priv 851 drivers/gpu/drm/i915/gvt/cmd_parser.c ring_base = dev_priv->engine[s->ring_id]->mmio_base; dev_priv 927 drivers/gpu/drm/i915/gvt/cmd_parser.c if (IS_GEN(gvt->dev_priv, 9) && dev_priv 980 drivers/gpu/drm/i915/gvt/cmd_parser.c if (IS_BROADWELL(gvt->dev_priv) && s->ring_id != RCS0) { dev_priv 1002 drivers/gpu/drm/i915/gvt/cmd_parser.c if (IS_BROADWELL(s->vgpu->gvt->dev_priv)) dev_priv 1030 drivers/gpu/drm/i915/gvt/cmd_parser.c if (IS_BROADWELL(gvt->dev_priv)) dev_priv 1214 drivers/gpu/drm/i915/gvt/cmd_parser.c struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; dev_priv 1260 drivers/gpu/drm/i915/gvt/cmd_parser.c struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; dev_priv 1319 drivers/gpu/drm/i915/gvt/cmd_parser.c struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; dev_priv 1325 drivers/gpu/drm/i915/gvt/cmd_parser.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 1348 drivers/gpu/drm/i915/gvt/cmd_parser.c struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; dev_priv 1353 drivers/gpu/drm/i915/gvt/cmd_parser.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 1379 drivers/gpu/drm/i915/gvt/cmd_parser.c struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; dev_priv 1381 drivers/gpu/drm/i915/gvt/cmd_parser.c if (IS_BROADWELL(dev_priv)) dev_priv 1383 drivers/gpu/drm/i915/gvt/cmd_parser.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 1858 drivers/gpu/drm/i915/gvt/cmd_parser.c bb->obj = i915_gem_object_create_shmem(s->vgpu->gvt->dev_priv, dev_priv 2941 drivers/gpu/drm/i915/gvt/cmd_parser.c obj = i915_gem_object_create_shmem(workload->vgpu->gvt->dev_priv, dev_priv 61 drivers/gpu/drm/i915/gvt/debugfs.c struct drm_i915_private *i915 = gvt->dev_priv; dev_priv 101 drivers/gpu/drm/i915/gvt/debugfs.c mmio_hw_access_pre(gvt->dev_priv); dev_priv 104 drivers/gpu/drm/i915/gvt/debugfs.c mmio_hw_access_post(gvt->dev_priv); dev_priv 145 drivers/gpu/drm/i915/gvt/debugfs.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 167 drivers/gpu/drm/i915/gvt/debugfs.c engine = dev_priv->engine[id]; dev_priv 223 drivers/gpu/drm/i915/gvt/debugfs.c struct drm_minor *minor = gvt->dev_priv->drm.primary; dev_priv 60 drivers/gpu/drm/i915/gvt/display.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 72 drivers/gpu/drm/i915/gvt/display.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 171 drivers/gpu/drm/i915/gvt/display.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 174 drivers/gpu/drm/i915/gvt/display.c if (IS_BROXTON(dev_priv)) { dev_priv 201 drivers/gpu/drm/i915/gvt/display.c if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || dev_priv 202 drivers/gpu/drm/i915/gvt/display.c IS_COFFEELAKE(dev_priv)) { dev_priv 253 drivers/gpu/drm/i915/gvt/display.c if (IS_BROADWELL(dev_priv)) { dev_priv 279 drivers/gpu/drm/i915/gvt/display.c if (IS_BROADWELL(dev_priv)) { dev_priv 305 drivers/gpu/drm/i915/gvt/display.c if (IS_BROADWELL(dev_priv)) { dev_priv 316 drivers/gpu/drm/i915/gvt/display.c if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || dev_priv 317 drivers/gpu/drm/i915/gvt/display.c IS_COFFEELAKE(dev_priv)) && dev_priv 323 drivers/gpu/drm/i915/gvt/display.c if (IS_BROADWELL(dev_priv)) dev_priv 333 drivers/gpu/drm/i915/gvt/display.c if (IS_BROADWELL(dev_priv)) dev_priv 337 drivers/gpu/drm/i915/gvt/display.c for_each_pipe(dev_priv, pipe) { dev_priv 431 drivers/gpu/drm/i915/gvt/display.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 463 drivers/gpu/drm/i915/gvt/display.c for_each_pipe(vgpu->gvt->dev_priv, pipe) dev_priv 496 drivers/gpu/drm/i915/gvt/display.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 499 drivers/gpu/drm/i915/gvt/display.c if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || dev_priv 500 drivers/gpu/drm/i915/gvt/display.c IS_COFFEELAKE(dev_priv)) { dev_priv 526 drivers/gpu/drm/i915/gvt/display.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 528 drivers/gpu/drm/i915/gvt/display.c if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || dev_priv 529 drivers/gpu/drm/i915/gvt/display.c IS_COFFEELAKE(dev_priv)) dev_priv 548 drivers/gpu/drm/i915/gvt/display.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 552 drivers/gpu/drm/i915/gvt/display.c if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || dev_priv 553 drivers/gpu/drm/i915/gvt/display.c IS_COFFEELAKE(dev_priv)) dev_priv 42 drivers/gpu/drm/i915/gvt/dmabuf.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); dev_priv 64 drivers/gpu/drm/i915/gvt/dmabuf.c gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + dev_priv 155 drivers/gpu/drm/i915/gvt/dmabuf.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 168 drivers/gpu/drm/i915/gvt/dmabuf.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 363 drivers/gpu/drm/i915/gvt/dmabuf.c struct drm_device *dev = &vgpu->gvt->dev_priv->drm; dev_priv 469 drivers/gpu/drm/i915/gvt/dmabuf.c struct drm_device *dev = &vgpu->gvt->dev_priv->drm; dev_priv 138 drivers/gpu/drm/i915/gvt/edid.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 150 drivers/gpu/drm/i915/gvt/edid.c if (IS_BROXTON(dev_priv)) dev_priv 152 drivers/gpu/drm/i915/gvt/edid.c else if (IS_COFFEELAKE(dev_priv)) dev_priv 43 drivers/gpu/drm/i915/gvt/execlist.c (gvt->dev_priv->engine[ring_id]->mmio_base + (offset)) dev_priv 136 drivers/gpu/drm/i915/gvt/execlist.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 172 drivers/gpu/drm/i915/gvt/execlist.c intel_hws_csb_write_index(dev_priv) * 4, dev_priv 532 drivers/gpu/drm/i915/gvt/execlist.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 537 drivers/gpu/drm/i915/gvt/execlist.c for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { dev_priv 547 drivers/gpu/drm/i915/gvt/execlist.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 551 drivers/gpu/drm/i915/gvt/execlist.c for_each_engine_masked(engine, dev_priv, engine_mask, tmp) dev_priv 149 drivers/gpu/drm/i915/gvt/fb_decoder.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 154 drivers/gpu/drm/i915/gvt/fb_decoder.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 206 drivers/gpu/drm/i915/gvt/fb_decoder.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 218 drivers/gpu/drm/i915/gvt/fb_decoder.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 259 drivers/gpu/drm/i915/gvt/fb_decoder.c (INTEL_GEN(dev_priv) >= 9) ? dev_priv 337 drivers/gpu/drm/i915/gvt/fb_decoder.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 71 drivers/gpu/drm/i915/gvt/firmware.c struct drm_i915_private *i915 = gvt->dev_priv; dev_priv 81 drivers/gpu/drm/i915/gvt/firmware.c struct pci_dev *pdev = gvt->dev_priv->drm.pdev; dev_priv 132 drivers/gpu/drm/i915/gvt/firmware.c struct pci_dev *pdev = gvt->dev_priv->drm.pdev; dev_priv 156 drivers/gpu/drm/i915/gvt/firmware.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 157 drivers/gpu/drm/i915/gvt/firmware.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 211 drivers/gpu/drm/i915/gvt/firmware.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 212 drivers/gpu/drm/i915/gvt/firmware.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 247 drivers/gpu/drm/i915/gvt/firmware.c ret = request_firmware(&fw, path, &dev_priv->drm.pdev->dev); dev_priv 278 drivers/gpu/drm/i915/gvt/gtt.c static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index) dev_priv 280 drivers/gpu/drm/i915/gvt/gtt.c void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index; dev_priv 285 drivers/gpu/drm/i915/gvt/gtt.c static void ggtt_invalidate(struct drm_i915_private *dev_priv) dev_priv 287 drivers/gpu/drm/i915/gvt/gtt.c mmio_hw_access_pre(dev_priv); dev_priv 289 drivers/gpu/drm/i915/gvt/gtt.c mmio_hw_access_post(dev_priv); dev_priv 292 drivers/gpu/drm/i915/gvt/gtt.c static void write_pte64(struct drm_i915_private *dev_priv, dev_priv 295 drivers/gpu/drm/i915/gvt/gtt.c void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index; dev_priv 318 drivers/gpu/drm/i915/gvt/gtt.c e->val64 = read_pte64(vgpu->gvt->dev_priv, index); dev_priv 343 drivers/gpu/drm/i915/gvt/gtt.c write_pte64(vgpu->gvt->dev_priv, index, e->val64); dev_priv 737 drivers/gpu/drm/i915/gvt/gtt.c struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev; dev_priv 822 drivers/gpu/drm/i915/gvt/gtt.c struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev; dev_priv 1047 drivers/gpu/drm/i915/gvt/gtt.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 1049 drivers/gpu/drm/i915/gvt/gtt.c if (INTEL_GEN(dev_priv) == 9 || INTEL_GEN(dev_priv) == 10) { dev_priv 1054 drivers/gpu/drm/i915/gvt/gtt.c } else if (INTEL_GEN(dev_priv) >= 11) { dev_priv 1156 drivers/gpu/drm/i915/gvt/gtt.c if (!HAS_PAGE_SIZES(vgpu->gvt->dev_priv, I915_GTT_PAGE_SIZE_2M)) dev_priv 2317 drivers/gpu/drm/i915/gvt/gtt.c ggtt_invalidate(gvt->dev_priv); dev_priv 2356 drivers/gpu/drm/i915/gvt/gtt.c struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev; dev_priv 2413 drivers/gpu/drm/i915/gvt/gtt.c struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev; dev_priv 2685 drivers/gpu/drm/i915/gvt/gtt.c struct device *dev = &gvt->dev_priv->drm.pdev->dev; dev_priv 2734 drivers/gpu/drm/i915/gvt/gtt.c struct device *dev = &gvt->dev_priv->drm.pdev->dev; dev_priv 2782 drivers/gpu/drm/i915/gvt/gtt.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 2812 drivers/gpu/drm/i915/gvt/gtt.c ggtt_invalidate(dev_priv); dev_priv 55 drivers/gpu/drm/i915/gvt/gvt.c &gvt->dev_priv->drm.pdev->dev); dev_priv 194 drivers/gpu/drm/i915/gvt/gvt.c struct pci_dev *pdev = gvt->dev_priv->drm.pdev; dev_priv 266 drivers/gpu/drm/i915/gvt/gvt.c void intel_gvt_clean_device(struct drm_i915_private *dev_priv) dev_priv 268 drivers/gpu/drm/i915/gvt/gvt.c struct intel_gvt *gvt = to_gvt(dev_priv); dev_priv 288 drivers/gpu/drm/i915/gvt/gvt.c kfree(dev_priv->gvt); dev_priv 289 drivers/gpu/drm/i915/gvt/gvt.c dev_priv->gvt = NULL; dev_priv 303 drivers/gpu/drm/i915/gvt/gvt.c int intel_gvt_init_device(struct drm_i915_private *dev_priv) dev_priv 309 drivers/gpu/drm/i915/gvt/gvt.c if (WARN_ON(dev_priv->gvt)) dev_priv 322 drivers/gpu/drm/i915/gvt/gvt.c gvt->dev_priv = dev_priv; dev_priv 381 drivers/gpu/drm/i915/gvt/gvt.c dev_priv->gvt = gvt; dev_priv 382 drivers/gpu/drm/i915/gvt/gvt.c intel_gvt_host.dev = &dev_priv->drm.pdev->dev; dev_priv 309 drivers/gpu/drm/i915/gvt/gvt.h struct drm_i915_private *dev_priv; dev_priv 380 drivers/gpu/drm/i915/gvt/gvt.h #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) dev_priv 381 drivers/gpu/drm/i915/gvt/gvt.h #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start) dev_priv 383 drivers/gpu/drm/i915/gvt/gvt.h #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.vm.total) dev_priv 385 drivers/gpu/drm/i915/gvt/gvt.h ((gvt->dev_priv->ggtt.vm.total >> PAGE_SHIFT) << 3) dev_priv 397 drivers/gpu/drm/i915/gvt/gvt.h #define gvt_fence_sz(gvt) ((gvt)->dev_priv->ggtt.num_fences) dev_priv 589 drivers/gpu/drm/i915/gvt/gvt.h static inline void mmio_hw_access_pre(struct drm_i915_private *dev_priv) dev_priv 591 drivers/gpu/drm/i915/gvt/gvt.h intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 594 drivers/gpu/drm/i915/gvt/gvt.h static inline void mmio_hw_access_post(struct drm_i915_private *dev_priv) dev_priv 596 drivers/gpu/drm/i915/gvt/gvt.h intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); dev_priv 52 drivers/gpu/drm/i915/gvt/handlers.c if (IS_BROADWELL(gvt->dev_priv)) dev_priv 54 drivers/gpu/drm/i915/gvt/handlers.c else if (IS_SKYLAKE(gvt->dev_priv)) dev_priv 56 drivers/gpu/drm/i915/gvt/handlers.c else if (IS_KABYLAKE(gvt->dev_priv)) dev_priv 58 drivers/gpu/drm/i915/gvt/handlers.c else if (IS_BROXTON(gvt->dev_priv)) dev_priv 60 drivers/gpu/drm/i915/gvt/handlers.c else if (IS_COFFEELAKE(gvt->dev_priv)) dev_priv 159 drivers/gpu/drm/i915/gvt/handlers.c for_each_engine(engine, gvt->dev_priv, id) { dev_priv 220 drivers/gpu/drm/i915/gvt/handlers.c if (INTEL_GEN(vgpu->gvt->dev_priv) <= 10) { dev_priv 256 drivers/gpu/drm/i915/gvt/handlers.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 265 drivers/gpu/drm/i915/gvt/handlers.c mmio_hw_access_pre(dev_priv); dev_priv 268 drivers/gpu/drm/i915/gvt/handlers.c mmio_hw_access_post(dev_priv); dev_priv 286 drivers/gpu/drm/i915/gvt/handlers.c if (INTEL_GEN(vgpu->gvt->dev_priv) >= 9) { dev_priv 344 drivers/gpu/drm/i915/gvt/handlers.c engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask; dev_priv 514 drivers/gpu/drm/i915/gvt/handlers.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 523 drivers/gpu/drm/i915/gvt/handlers.c ring_base = dev_priv->engine[ring_id]->mmio_base; dev_priv 754 drivers/gpu/drm/i915/gvt/handlers.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 795 drivers/gpu/drm/i915/gvt/handlers.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 819 drivers/gpu/drm/i915/gvt/handlers.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 919 drivers/gpu/drm/i915/gvt/handlers.c if ((INTEL_GEN(vgpu->gvt->dev_priv) >= 9) dev_priv 923 drivers/gpu/drm/i915/gvt/handlers.c } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && dev_priv 1239 drivers/gpu/drm/i915/gvt/handlers.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 1240 drivers/gpu/drm/i915/gvt/handlers.c struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; dev_priv 1422 drivers/gpu/drm/i915/gvt/handlers.c if (IS_SKYLAKE(vgpu->gvt->dev_priv) dev_priv 1423 drivers/gpu/drm/i915/gvt/handlers.c || IS_KABYLAKE(vgpu->gvt->dev_priv) dev_priv 1424 drivers/gpu/drm/i915/gvt/handlers.c || IS_COFFEELAKE(vgpu->gvt->dev_priv)) { dev_priv 1434 drivers/gpu/drm/i915/gvt/handlers.c } else if (IS_BROXTON(vgpu->gvt->dev_priv)) { dev_priv 1447 drivers/gpu/drm/i915/gvt/handlers.c if (IS_SKYLAKE(vgpu->gvt->dev_priv) dev_priv 1448 drivers/gpu/drm/i915/gvt/handlers.c || IS_KABYLAKE(vgpu->gvt->dev_priv) dev_priv 1449 drivers/gpu/drm/i915/gvt/handlers.c || IS_COFFEELAKE(vgpu->gvt->dev_priv)) dev_priv 1502 drivers/gpu/drm/i915/gvt/handlers.c if (IS_BROXTON(vgpu->gvt->dev_priv)) dev_priv 1639 drivers/gpu/drm/i915/gvt/handlers.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 1651 drivers/gpu/drm/i915/gvt/handlers.c ring_base = dev_priv->engine[ring_id]->mmio_base; dev_priv 1656 drivers/gpu/drm/i915/gvt/handlers.c mmio_hw_access_pre(dev_priv); dev_priv 1658 drivers/gpu/drm/i915/gvt/handlers.c mmio_hw_access_post(dev_priv); dev_priv 1699 drivers/gpu/drm/i915/gvt/handlers.c if (IS_COFFEELAKE(vgpu->gvt->dev_priv)) dev_priv 1708 drivers/gpu/drm/i915/gvt/handlers.c if (IS_COFFEELAKE(vgpu->gvt->dev_priv) && dev_priv 1840 drivers/gpu/drm/i915/gvt/handlers.c if (HAS_ENGINE(dev_priv, VCS1)) \ dev_priv 1861 drivers/gpu/drm/i915/gvt/handlers.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 2676 drivers/gpu/drm/i915/gvt/handlers.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 2865 drivers/gpu/drm/i915/gvt/handlers.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 3114 drivers/gpu/drm/i915/gvt/handlers.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 3350 drivers/gpu/drm/i915/gvt/handlers.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 3362 drivers/gpu/drm/i915/gvt/handlers.c if (IS_BROADWELL(dev_priv)) { dev_priv 3366 drivers/gpu/drm/i915/gvt/handlers.c } else if (IS_SKYLAKE(dev_priv) dev_priv 3367 drivers/gpu/drm/i915/gvt/handlers.c || IS_KABYLAKE(dev_priv) dev_priv 3368 drivers/gpu/drm/i915/gvt/handlers.c || IS_COFFEELAKE(dev_priv)) { dev_priv 3375 drivers/gpu/drm/i915/gvt/handlers.c } else if (IS_BROXTON(dev_priv)) { dev_priv 539 drivers/gpu/drm/i915/gvt/interrupt.c if (HAS_ENGINE(gvt->dev_priv, VCS1)) { dev_priv 571 drivers/gpu/drm/i915/gvt/interrupt.c if (IS_BROADWELL(gvt->dev_priv)) { dev_priv 584 drivers/gpu/drm/i915/gvt/interrupt.c } else if (INTEL_GEN(gvt->dev_priv) >= 9) { dev_priv 190 drivers/gpu/drm/i915/gvt/kvmgt.c struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev; dev_priv 213 drivers/gpu/drm/i915/gvt/kvmgt.c struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev; dev_priv 916 drivers/gpu/drm/i915/gvt/kvmgt.c aperture_va = io_mapping_map_wc(&vgpu->gvt->dev_priv->ggtt.iomap, dev_priv 248 drivers/gpu/drm/i915/gvt/mmio.c if (IS_BROXTON(vgpu->gvt->dev_priv)) { dev_priv 159 drivers/gpu/drm/i915/gvt/mmio_context.c static void load_render_mocs(struct drm_i915_private *dev_priv) dev_priv 161 drivers/gpu/drm/i915/gvt/mmio_context.c struct intel_gvt *gvt = dev_priv->gvt; dev_priv 172 drivers/gpu/drm/i915/gvt/mmio_context.c if (!HAS_ENGINE(dev_priv, ring_id)) dev_priv 348 drivers/gpu/drm/i915/gvt/mmio_context.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 349 drivers/gpu/drm/i915/gvt/mmio_context.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 374 drivers/gpu/drm/i915/gvt/mmio_context.c if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9) dev_priv 394 drivers/gpu/drm/i915/gvt/mmio_context.c struct drm_i915_private *dev_priv; dev_priv 407 drivers/gpu/drm/i915/gvt/mmio_context.c dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; dev_priv 411 drivers/gpu/drm/i915/gvt/mmio_context.c if (ring_id == RCS0 && IS_GEN(dev_priv, 9)) dev_priv 415 drivers/gpu/drm/i915/gvt/mmio_context.c load_render_mocs(dev_priv); dev_priv 471 drivers/gpu/drm/i915/gvt/mmio_context.c struct drm_i915_private *dev_priv; dev_priv 476 drivers/gpu/drm/i915/gvt/mmio_context.c dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; dev_priv 477 drivers/gpu/drm/i915/gvt/mmio_context.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 480 drivers/gpu/drm/i915/gvt/mmio_context.c for (mmio = dev_priv->gvt->engine_mmio_list.mmio; dev_priv 489 drivers/gpu/drm/i915/gvt/mmio_context.c if (IS_GEN(dev_priv, 9) && mmio->in_context) dev_priv 553 drivers/gpu/drm/i915/gvt/mmio_context.c struct drm_i915_private *dev_priv; dev_priv 561 drivers/gpu/drm/i915/gvt/mmio_context.c dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; dev_priv 568 drivers/gpu/drm/i915/gvt/mmio_context.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 570 drivers/gpu/drm/i915/gvt/mmio_context.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 582 drivers/gpu/drm/i915/gvt/mmio_context.c if (INTEL_GEN(gvt->dev_priv) >= 9) { dev_priv 42 drivers/gpu/drm/i915/gvt/sched_policy.c for_each_engine(engine, vgpu->gvt->dev_priv, i) { dev_priv 155 drivers/gpu/drm/i915/gvt/sched_policy.c for_each_engine(engine, gvt->dev_priv, i) { dev_priv 172 drivers/gpu/drm/i915/gvt/sched_policy.c for_each_engine(engine, gvt->dev_priv, i) dev_priv 449 drivers/gpu/drm/i915/gvt/sched_policy.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 468 drivers/gpu/drm/i915/gvt/sched_policy.c intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 477 drivers/gpu/drm/i915/gvt/sched_policy.c intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); dev_priv 86 drivers/gpu/drm/i915/gvt/scheduler.c struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; dev_priv 87 drivers/gpu/drm/i915/gvt/scheduler.c u32 ctx_oactxctrl = dev_priv->perf.ctx_oactxctrl_offset; dev_priv 88 drivers/gpu/drm/i915/gvt/scheduler.c u32 ctx_flexeu0 = dev_priv->perf.ctx_flexeu0_offset; dev_priv 180 drivers/gpu/drm/i915/gvt/scheduler.c context_page_num = gvt->dev_priv->engine[ring_id]->context_size; dev_priv 184 drivers/gpu/drm/i915/gvt/scheduler.c if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS0) dev_priv 214 drivers/gpu/drm/i915/gvt/scheduler.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 215 drivers/gpu/drm/i915/gvt/scheduler.c u32 ring_base = dev_priv->engine[ring_id]->mmio_base; dev_priv 392 drivers/gpu/drm/i915/gvt/scheduler.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 395 drivers/gpu/drm/i915/gvt/scheduler.c lockdep_assert_held(&dev_priv->drm.struct_mutex); dev_priv 422 drivers/gpu/drm/i915/gvt/scheduler.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 425 drivers/gpu/drm/i915/gvt/scheduler.c lockdep_assert_held(&dev_priv->drm.struct_mutex); dev_priv 578 drivers/gpu/drm/i915/gvt/scheduler.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 581 drivers/gpu/drm/i915/gvt/scheduler.c ring_base = dev_priv->engine[workload->ring_id]->mmio_base; dev_priv 588 drivers/gpu/drm/i915/gvt/scheduler.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 597 drivers/gpu/drm/i915/gvt/scheduler.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 617 drivers/gpu/drm/i915/gvt/scheduler.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 692 drivers/gpu/drm/i915/gvt/scheduler.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 701 drivers/gpu/drm/i915/gvt/scheduler.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 736 drivers/gpu/drm/i915/gvt/scheduler.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 809 drivers/gpu/drm/i915/gvt/scheduler.c struct drm_i915_private *dev_priv = gvt->dev_priv; dev_priv 830 drivers/gpu/drm/i915/gvt/scheduler.c ring_base = dev_priv->engine[workload->ring_id]->mmio_base; dev_priv 837 drivers/gpu/drm/i915/gvt/scheduler.c if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS0) dev_priv 888 drivers/gpu/drm/i915/gvt/scheduler.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 894 drivers/gpu/drm/i915/gvt/scheduler.c for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { dev_priv 999 drivers/gpu/drm/i915/gvt/scheduler.c bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9); dev_priv 1001 drivers/gpu/drm/i915/gvt/scheduler.c struct intel_runtime_pm *rpm = &gvt->dev_priv->runtime_pm; dev_priv 1031 drivers/gpu/drm/i915/gvt/scheduler.c intel_uncore_forcewake_get(&gvt->dev_priv->uncore, dev_priv 1060 drivers/gpu/drm/i915/gvt/scheduler.c intel_uncore_forcewake_put(&gvt->dev_priv->uncore, dev_priv 1092 drivers/gpu/drm/i915/gvt/scheduler.c for_each_engine(engine, gvt->dev_priv, i) { dev_priv 1112 drivers/gpu/drm/i915/gvt/scheduler.c for_each_engine(engine, gvt->dev_priv, i) { dev_priv 1179 drivers/gpu/drm/i915/gvt/scheduler.c for_each_engine(engine, vgpu->gvt->dev_priv, id) dev_priv 1236 drivers/gpu/drm/i915/gvt/scheduler.c struct drm_i915_private *i915 = vgpu->gvt->dev_priv; dev_priv 1483 drivers/gpu/drm/i915/gvt/scheduler.c struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; dev_priv 1603 drivers/gpu/drm/i915/gvt/scheduler.c intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 1604 drivers/gpu/drm/i915/gvt/scheduler.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 1606 drivers/gpu/drm/i915/gvt/scheduler.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1607 drivers/gpu/drm/i915/gvt/scheduler.c intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); dev_priv 151 drivers/gpu/drm/i915/gvt/vgpu.c if (IS_GEN(gvt->dev_priv, 8)) dev_priv 154 drivers/gpu/drm/i915/gvt/vgpu.c else if (IS_GEN(gvt->dev_priv, 9)) dev_priv 436 drivers/gpu/drm/i915/gvt/vgpu.c if (IS_SKYLAKE(gvt->dev_priv) || IS_KABYLAKE(gvt->dev_priv)) dev_priv 1529 drivers/gpu/drm/i915/i915_cmd_parser.c int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv) dev_priv 1535 drivers/gpu/drm/i915/i915_cmd_parser.c for_each_uabi_engine(engine, dev_priv) { dev_priv 61 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 62 drivers/gpu/drm/i915/i915_debugfs.c const struct intel_device_info *info = INTEL_INFO(dev_priv); dev_priv 65 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); dev_priv 67 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); dev_priv 70 drivers/gpu/drm/i915/i915_debugfs.c intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p); dev_priv 71 drivers/gpu/drm/i915/i915_debugfs.c intel_driver_caps_print(&dev_priv->caps, &p); dev_priv 138 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); dev_priv 152 drivers/gpu/drm/i915/i915_debugfs.c i915_cache_level_str(dev_priv, obj->cache_level), dev_priv 378 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 381 drivers/gpu/drm/i915/i915_debugfs.c for_each_pipe(dev_priv, pipe) { dev_priv 386 drivers/gpu/drm/i915/i915_debugfs.c wakeref = intel_display_power_get_if_enabled(dev_priv, dev_priv 403 drivers/gpu/drm/i915/i915_debugfs.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 430 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 435 drivers/gpu/drm/i915/i915_debugfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 437 drivers/gpu/drm/i915/i915_debugfs.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 451 drivers/gpu/drm/i915/i915_debugfs.c for_each_pipe(dev_priv, pipe) { dev_priv 455 drivers/gpu/drm/i915/i915_debugfs.c pref = intel_display_power_get_if_enabled(dev_priv, dev_priv 467 drivers/gpu/drm/i915/i915_debugfs.c intel_display_power_put(dev_priv, power_domain, pref); dev_priv 470 drivers/gpu/drm/i915/i915_debugfs.c pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); dev_priv 477 drivers/gpu/drm/i915/i915_debugfs.c intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref); dev_priv 494 drivers/gpu/drm/i915/i915_debugfs.c } else if (INTEL_GEN(dev_priv) >= 11) { dev_priv 515 drivers/gpu/drm/i915/i915_debugfs.c } else if (INTEL_GEN(dev_priv) >= 8) { dev_priv 529 drivers/gpu/drm/i915/i915_debugfs.c } else if (IS_VALLEYVIEW(dev_priv)) { dev_priv 538 drivers/gpu/drm/i915/i915_debugfs.c for_each_pipe(dev_priv, pipe) { dev_priv 543 drivers/gpu/drm/i915/i915_debugfs.c pref = intel_display_power_get_if_enabled(dev_priv, dev_priv 554 drivers/gpu/drm/i915/i915_debugfs.c intel_display_power_put(dev_priv, power_domain, pref); dev_priv 581 drivers/gpu/drm/i915/i915_debugfs.c } else if (!HAS_PCH_SPLIT(dev_priv)) { dev_priv 588 drivers/gpu/drm/i915/i915_debugfs.c for_each_pipe(dev_priv, pipe) dev_priv 613 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 11) { dev_priv 633 drivers/gpu/drm/i915/i915_debugfs.c } else if (INTEL_GEN(dev_priv) >= 6) { dev_priv 634 drivers/gpu/drm/i915/i915_debugfs.c for_each_uabi_engine(engine, dev_priv) { dev_priv 641 drivers/gpu/drm/i915/i915_debugfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 773 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 774 drivers/gpu/drm/i915/i915_debugfs.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 775 drivers/gpu/drm/i915/i915_debugfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 779 drivers/gpu/drm/i915/i915_debugfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 781 drivers/gpu/drm/i915/i915_debugfs.c if (IS_GEN(dev_priv, 5)) { dev_priv 791 drivers/gpu/drm/i915/i915_debugfs.c } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 803 drivers/gpu/drm/i915/i915_debugfs.c vlv_punit_get(dev_priv); dev_priv 804 drivers/gpu/drm/i915/i915_debugfs.c freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); dev_priv 805 drivers/gpu/drm/i915/i915_debugfs.c vlv_punit_put(dev_priv); dev_priv 808 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); dev_priv 811 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); dev_priv 814 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->cur_freq)); dev_priv 817 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->max_freq)); dev_priv 820 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->min_freq)); dev_priv 823 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->idle_freq)); dev_priv 827 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->efficient_freq)); dev_priv 828 drivers/gpu/drm/i915/i915_debugfs.c } else if (INTEL_GEN(dev_priv) >= 6) { dev_priv 840 drivers/gpu/drm/i915/i915_debugfs.c if (IS_GEN9_LP(dev_priv)) { dev_priv 849 drivers/gpu/drm/i915/i915_debugfs.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 852 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 856 drivers/gpu/drm/i915/i915_debugfs.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 861 drivers/gpu/drm/i915/i915_debugfs.c reqf = intel_gpu_freq(dev_priv, reqf); dev_priv 874 drivers/gpu/drm/i915/i915_debugfs.c cagf = intel_gpu_freq(dev_priv, dev_priv 875 drivers/gpu/drm/i915/i915_debugfs.c intel_get_cagf(dev_priv, rpstat)); dev_priv 877 drivers/gpu/drm/i915/i915_debugfs.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 879 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 11) { dev_priv 888 drivers/gpu/drm/i915/i915_debugfs.c } else if (INTEL_GEN(dev_priv) >= 8) { dev_priv 911 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) <= 10) dev_priv 918 drivers/gpu/drm/i915/i915_debugfs.c (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); dev_priv 930 drivers/gpu/drm/i915/i915_debugfs.c rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); dev_priv 932 drivers/gpu/drm/i915/i915_debugfs.c rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); dev_priv 934 drivers/gpu/drm/i915/i915_debugfs.c rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); dev_priv 939 drivers/gpu/drm/i915/i915_debugfs.c rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); dev_priv 941 drivers/gpu/drm/i915/i915_debugfs.c rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); dev_priv 943 drivers/gpu/drm/i915/i915_debugfs.c rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); dev_priv 947 drivers/gpu/drm/i915/i915_debugfs.c max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : dev_priv 949 drivers/gpu/drm/i915/i915_debugfs.c max_freq *= (IS_GEN9_BC(dev_priv) || dev_priv 950 drivers/gpu/drm/i915/i915_debugfs.c INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); dev_priv 952 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, max_freq)); dev_priv 955 drivers/gpu/drm/i915/i915_debugfs.c max_freq *= (IS_GEN9_BC(dev_priv) || dev_priv 956 drivers/gpu/drm/i915/i915_debugfs.c INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); dev_priv 958 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, max_freq)); dev_priv 960 drivers/gpu/drm/i915/i915_debugfs.c max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : dev_priv 962 drivers/gpu/drm/i915/i915_debugfs.c max_freq *= (IS_GEN9_BC(dev_priv) || dev_priv 963 drivers/gpu/drm/i915/i915_debugfs.c INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); dev_priv 965 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, max_freq)); dev_priv 967 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->max_freq)); dev_priv 970 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->cur_freq)); dev_priv 973 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->idle_freq)); dev_priv 975 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->min_freq)); dev_priv 977 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->boost_freq)); dev_priv 979 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->max_freq)); dev_priv 982 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->efficient_freq)); dev_priv 987 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); dev_priv 988 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); dev_priv 989 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); dev_priv 991 drivers/gpu/drm/i915/i915_debugfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 995 drivers/gpu/drm/i915/i915_debugfs.c static void i915_instdone_info(struct drm_i915_private *dev_priv, dev_priv 1005 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) <= 3) dev_priv 1011 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) <= 6) dev_priv 1014 drivers/gpu/drm/i915/i915_debugfs.c for_each_instdone_slice_subslice(dev_priv, slice, subslice) dev_priv 1018 drivers/gpu/drm/i915/i915_debugfs.c for_each_instdone_slice_subslice(dev_priv, slice, subslice) dev_priv 1160 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1164 drivers/gpu/drm/i915/i915_debugfs.c intel_rc6_residency_us(dev_priv, reg)); dev_priv 1169 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1191 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1199 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 1204 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) <= 7) dev_priv 1205 drivers/gpu/drm/i915/i915_debugfs.c sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, dev_priv 1212 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 1246 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 1262 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) <= 7) { dev_priv 1276 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1280 drivers/gpu/drm/i915/i915_debugfs.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { dev_priv 1281 drivers/gpu/drm/i915/i915_debugfs.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 1283 drivers/gpu/drm/i915/i915_debugfs.c else if (INTEL_GEN(dev_priv) >= 6) dev_priv 1294 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1297 drivers/gpu/drm/i915/i915_debugfs.c dev_priv->fb_tracking.busy_bits); dev_priv 1300 drivers/gpu/drm/i915/i915_debugfs.c dev_priv->fb_tracking.flip_bits); dev_priv 1307 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1308 drivers/gpu/drm/i915/i915_debugfs.c struct intel_fbc *fbc = &dev_priv->fbc; dev_priv 1311 drivers/gpu/drm/i915/i915_debugfs.c if (!HAS_FBC(dev_priv)) dev_priv 1314 drivers/gpu/drm/i915/i915_debugfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 1317 drivers/gpu/drm/i915/i915_debugfs.c if (intel_fbc_is_active(dev_priv)) dev_priv 1322 drivers/gpu/drm/i915/i915_debugfs.c if (intel_fbc_is_active(dev_priv)) { dev_priv 1325 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 1327 drivers/gpu/drm/i915/i915_debugfs.c else if (INTEL_GEN(dev_priv) >= 7) dev_priv 1329 drivers/gpu/drm/i915/i915_debugfs.c else if (INTEL_GEN(dev_priv) >= 5) dev_priv 1331 drivers/gpu/drm/i915/i915_debugfs.c else if (IS_G4X(dev_priv)) dev_priv 1341 drivers/gpu/drm/i915/i915_debugfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 1348 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = data; dev_priv 1350 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) dev_priv 1353 drivers/gpu/drm/i915/i915_debugfs.c *val = dev_priv->fbc.false_color; dev_priv 1360 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = data; dev_priv 1363 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) dev_priv 1366 drivers/gpu/drm/i915/i915_debugfs.c mutex_lock(&dev_priv->fbc.lock); dev_priv 1369 drivers/gpu/drm/i915/i915_debugfs.c dev_priv->fbc.false_color = val; dev_priv 1375 drivers/gpu/drm/i915/i915_debugfs.c mutex_unlock(&dev_priv->fbc.lock); dev_priv 1385 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1388 drivers/gpu/drm/i915/i915_debugfs.c if (!HAS_IPS(dev_priv)) dev_priv 1391 drivers/gpu/drm/i915/i915_debugfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 1396 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 8) { dev_priv 1405 drivers/gpu/drm/i915/i915_debugfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 1412 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1416 drivers/gpu/drm/i915/i915_debugfs.c wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); dev_priv 1418 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 1420 drivers/gpu/drm/i915/i915_debugfs.c else if (HAS_PCH_SPLIT(dev_priv)) dev_priv 1422 drivers/gpu/drm/i915/i915_debugfs.c else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || dev_priv 1423 drivers/gpu/drm/i915/i915_debugfs.c IS_I945G(dev_priv) || IS_I945GM(dev_priv)) dev_priv 1425 drivers/gpu/drm/i915/i915_debugfs.c else if (IS_I915GM(dev_priv)) dev_priv 1427 drivers/gpu/drm/i915/i915_debugfs.c else if (IS_PINEVIEW(dev_priv)) dev_priv 1429 drivers/gpu/drm/i915/i915_debugfs.c else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 1432 drivers/gpu/drm/i915/i915_debugfs.c intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); dev_priv 1441 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1442 drivers/gpu/drm/i915/i915_debugfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 1447 drivers/gpu/drm/i915/i915_debugfs.c if (!HAS_LLC(dev_priv)) dev_priv 1452 drivers/gpu/drm/i915/i915_debugfs.c if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { dev_priv 1460 drivers/gpu/drm/i915/i915_debugfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 1463 drivers/gpu/drm/i915/i915_debugfs.c sandybridge_pcode_read(dev_priv, dev_priv 1467 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, (gpu_freq * dev_priv 1468 drivers/gpu/drm/i915/i915_debugfs.c (IS_GEN9_BC(dev_priv) || dev_priv 1469 drivers/gpu/drm/i915/i915_debugfs.c INTEL_GEN(dev_priv) >= 10 ? dev_priv 1474 drivers/gpu/drm/i915/i915_debugfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 1481 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1482 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 1483 drivers/gpu/drm/i915/i915_debugfs.c struct intel_opregion *opregion = &dev_priv->opregion; dev_priv 1511 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1512 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 1522 drivers/gpu/drm/i915/i915_debugfs.c if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) { dev_priv 1523 drivers/gpu/drm/i915/i915_debugfs.c fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); dev_priv 1567 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1568 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 1576 drivers/gpu/drm/i915/i915_debugfs.c list_for_each_entry(ctx, &dev_priv->contexts.list, link) { dev_priv 1650 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1651 drivers/gpu/drm/i915/i915_debugfs.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 1654 drivers/gpu/drm/i915/i915_debugfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 1657 drivers/gpu/drm/i915/i915_debugfs.c swizzle_string(dev_priv->mm.bit_6_swizzle_x)); dev_priv 1659 drivers/gpu/drm/i915/i915_debugfs.c swizzle_string(dev_priv->mm.bit_6_swizzle_y)); dev_priv 1661 drivers/gpu/drm/i915/i915_debugfs.c if (IS_GEN_RANGE(dev_priv, 3, 4)) { dev_priv 1670 drivers/gpu/drm/i915/i915_debugfs.c } else if (INTEL_GEN(dev_priv) >= 6) { dev_priv 1679 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 1689 drivers/gpu/drm/i915/i915_debugfs.c if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) dev_priv 1692 drivers/gpu/drm/i915/i915_debugfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 1713 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1714 drivers/gpu/drm/i915/i915_debugfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 1718 drivers/gpu/drm/i915/i915_debugfs.c with_intel_runtime_pm_if_in_use(&dev_priv->runtime_pm, wakeref) { dev_priv 1719 drivers/gpu/drm/i915/i915_debugfs.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 1720 drivers/gpu/drm/i915/i915_debugfs.c vlv_punit_get(dev_priv); dev_priv 1721 drivers/gpu/drm/i915/i915_debugfs.c act_freq = vlv_punit_read(dev_priv, dev_priv 1723 drivers/gpu/drm/i915/i915_debugfs.c vlv_punit_put(dev_priv); dev_priv 1726 drivers/gpu/drm/i915/i915_debugfs.c act_freq = intel_get_cagf(dev_priv, dev_priv 1732 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake)); dev_priv 1737 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->cur_freq), dev_priv 1738 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, act_freq)); dev_priv 1740 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->min_freq), dev_priv 1741 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->min_freq_softlimit), dev_priv 1742 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->max_freq_softlimit), dev_priv 1743 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->max_freq)); dev_priv 1745 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->idle_freq), dev_priv 1746 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->efficient_freq), dev_priv 1747 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->boost_freq)); dev_priv 1751 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 6 && rps->enabled && dev_priv->gt.awake) { dev_priv 1755 drivers/gpu/drm/i915/i915_debugfs.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 1760 drivers/gpu/drm/i915/i915_debugfs.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 1779 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1780 drivers/gpu/drm/i915/i915_debugfs.c const bool edram = INTEL_GEN(dev_priv) > 8; dev_priv 1782 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); dev_priv 1784 drivers/gpu/drm/i915/i915_debugfs.c dev_priv->edram_size_mb); dev_priv 1791 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1795 drivers/gpu/drm/i915/i915_debugfs.c if (!HAS_GT_UC(dev_priv)) dev_priv 1799 drivers/gpu/drm/i915/i915_debugfs.c intel_uc_fw_dump(&dev_priv->gt.uc.huc.fw, &p); dev_priv 1801 drivers/gpu/drm/i915/i915_debugfs.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) dev_priv 1809 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1813 drivers/gpu/drm/i915/i915_debugfs.c if (!HAS_GT_UC(dev_priv)) dev_priv 1817 drivers/gpu/drm/i915/i915_debugfs.c intel_uc_fw_dump(&dev_priv->gt.uc.guc.fw, &p); dev_priv 1819 drivers/gpu/drm/i915/i915_debugfs.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { dev_priv 1858 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv) dev_priv 1860 drivers/gpu/drm/i915/i915_debugfs.c struct intel_guc_log *log = &dev_priv->gt.uc.guc.log; dev_priv 1883 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1884 drivers/gpu/drm/i915/i915_debugfs.c const struct intel_guc *guc = &dev_priv->gt.uc.guc; dev_priv 1887 drivers/gpu/drm/i915/i915_debugfs.c if (!USES_GUC(dev_priv)) dev_priv 1890 drivers/gpu/drm/i915/i915_debugfs.c i915_guc_log_info(m, dev_priv); dev_priv 1892 drivers/gpu/drm/i915/i915_debugfs.c if (!USES_GUC_SUBMISSION(dev_priv)) dev_priv 1915 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 1916 drivers/gpu/drm/i915/i915_debugfs.c const struct intel_guc *guc = &dev_priv->gt.uc.guc; dev_priv 1920 drivers/gpu/drm/i915/i915_debugfs.c if (!USES_GUC_SUBMISSION(dev_priv)) dev_priv 1946 drivers/gpu/drm/i915/i915_debugfs.c for_each_uabi_engine(engine, dev_priv) { dev_priv 1968 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(node); dev_priv 1974 drivers/gpu/drm/i915/i915_debugfs.c if (!HAS_GT_UC(dev_priv)) dev_priv 1978 drivers/gpu/drm/i915/i915_debugfs.c obj = dev_priv->gt.uc.load_err_log; dev_priv 1979 drivers/gpu/drm/i915/i915_debugfs.c else if (dev_priv->gt.uc.guc.log.vma) dev_priv 1980 drivers/gpu/drm/i915/i915_debugfs.c obj = dev_priv->gt.uc.guc.log.vma->obj; dev_priv 2006 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = data; dev_priv 2008 drivers/gpu/drm/i915/i915_debugfs.c if (!USES_GUC(dev_priv)) dev_priv 2011 drivers/gpu/drm/i915/i915_debugfs.c *val = intel_guc_log_get_level(&dev_priv->gt.uc.guc.log); dev_priv 2018 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = data; dev_priv 2020 drivers/gpu/drm/i915/i915_debugfs.c if (!USES_GUC(dev_priv)) dev_priv 2023 drivers/gpu/drm/i915/i915_debugfs.c return intel_guc_log_set_level(&dev_priv->gt.uc.guc.log, val); dev_priv 2086 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 2091 drivers/gpu/drm/i915/i915_debugfs.c if (!CAN_PSR(dev_priv)) { dev_priv 2117 drivers/gpu/drm/i915/i915_debugfs.c psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m) dev_priv 2122 drivers/gpu/drm/i915/i915_debugfs.c if (dev_priv->psr.psr2_enabled) { dev_priv 2164 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 2165 drivers/gpu/drm/i915/i915_debugfs.c struct i915_psr *psr = &dev_priv->psr; dev_priv 2171 drivers/gpu/drm/i915/i915_debugfs.c if (!HAS_PSR(dev_priv)) dev_priv 2182 drivers/gpu/drm/i915/i915_debugfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 2203 drivers/gpu/drm/i915/i915_debugfs.c psr_source_status(dev_priv, m); dev_priv 2210 drivers/gpu/drm/i915/i915_debugfs.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { dev_priv 2246 drivers/gpu/drm/i915/i915_debugfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 2254 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = data; dev_priv 2258 drivers/gpu/drm/i915/i915_debugfs.c if (!CAN_PSR(dev_priv)) dev_priv 2263 drivers/gpu/drm/i915/i915_debugfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 2265 drivers/gpu/drm/i915/i915_debugfs.c ret = intel_psr_debug_set(dev_priv, val); dev_priv 2267 drivers/gpu/drm/i915/i915_debugfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 2275 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = data; dev_priv 2277 drivers/gpu/drm/i915/i915_debugfs.c if (!CAN_PSR(dev_priv)) dev_priv 2280 drivers/gpu/drm/i915/i915_debugfs.c *val = READ_ONCE(dev_priv->psr.debug); dev_priv 2290 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 2295 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) < 6) dev_priv 2302 drivers/gpu/drm/i915/i915_debugfs.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) dev_priv 2313 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 2314 drivers/gpu/drm/i915/i915_debugfs.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 2316 drivers/gpu/drm/i915/i915_debugfs.c if (!HAS_RUNTIME_PM(dev_priv)) dev_priv 2320 drivers/gpu/drm/i915/i915_debugfs.c enableddisabled(!dev_priv->power_domains.wakeref)); dev_priv 2322 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); dev_priv 2324 drivers/gpu/drm/i915/i915_debugfs.c yesno(!intel_irqs_enabled(dev_priv))); dev_priv 2327 drivers/gpu/drm/i915/i915_debugfs.c atomic_read(&dev_priv->drm.dev->power.usage_count)); dev_priv 2338 drivers/gpu/drm/i915/i915_debugfs.c print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p); dev_priv 2346 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 2347 drivers/gpu/drm/i915/i915_debugfs.c struct i915_power_domains *power_domains = &dev_priv->power_domains; dev_priv 2363 drivers/gpu/drm/i915/i915_debugfs.c intel_display_power_domain_str(dev_priv, dev_priv 2375 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 2380 drivers/gpu/drm/i915/i915_debugfs.c if (!HAS_CSR(dev_priv)) dev_priv 2383 drivers/gpu/drm/i915/i915_debugfs.c csr = &dev_priv->csr; dev_priv 2385 drivers/gpu/drm/i915/i915_debugfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 2396 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 12) { dev_priv 2400 drivers/gpu/drm/i915/i915_debugfs.c dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT : dev_priv 2402 drivers/gpu/drm/i915/i915_debugfs.c if (!IS_GEN9_LP(dev_priv)) dev_priv 2415 drivers/gpu/drm/i915/i915_debugfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 2435 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 2436 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 2462 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 2463 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 2645 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 2646 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 2719 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 2720 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 2726 drivers/gpu/drm/i915/i915_debugfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 2775 drivers/gpu/drm/i915/i915_debugfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 2782 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 2787 drivers/gpu/drm/i915/i915_debugfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 2790 drivers/gpu/drm/i915/i915_debugfs.c yesno(dev_priv->gt.awake), dev_priv 2791 drivers/gpu/drm/i915/i915_debugfs.c atomic_read(&dev_priv->gt.wakeref.count)); dev_priv 2793 drivers/gpu/drm/i915/i915_debugfs.c RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz); dev_priv 2796 drivers/gpu/drm/i915/i915_debugfs.c for_each_uabi_engine(engine, dev_priv) dev_priv 2799 drivers/gpu/drm/i915/i915_debugfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 2806 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 2809 drivers/gpu/drm/i915/i915_debugfs.c intel_device_info_dump_topology(&RUNTIME_INFO(dev_priv)->sseu, &p); dev_priv 2826 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 2827 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 2831 drivers/gpu/drm/i915/i915_debugfs.c for (i = 0; i < dev_priv->num_shared_dpll; i++) { dev_priv 2832 drivers/gpu/drm/i915/i915_debugfs.c struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; dev_priv 2903 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 2906 drivers/gpu/drm/i915/i915_debugfs.c yesno(dev_priv->ipc_enabled)); dev_priv 2912 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = inode->i_private; dev_priv 2914 drivers/gpu/drm/i915/i915_debugfs.c if (!HAS_IPC(dev_priv)) dev_priv 2917 drivers/gpu/drm/i915/i915_debugfs.c return single_open(file, i915_ipc_status_show, dev_priv); dev_priv 2924 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 2933 drivers/gpu/drm/i915/i915_debugfs.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { dev_priv 2934 drivers/gpu/drm/i915/i915_debugfs.c if (!dev_priv->ipc_enabled && enable) dev_priv 2936 drivers/gpu/drm/i915/i915_debugfs.c dev_priv->wm.distrust_bios_wm = true; dev_priv 2937 drivers/gpu/drm/i915/i915_debugfs.c dev_priv->ipc_enabled = enable; dev_priv 2938 drivers/gpu/drm/i915/i915_debugfs.c intel_enable_ipc(dev_priv); dev_priv 2955 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 2956 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 2960 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) < 9) dev_priv 2967 drivers/gpu/drm/i915/i915_debugfs.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 2996 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 2997 drivers/gpu/drm/i915/i915_debugfs.c struct i915_drrs *drrs = &dev_priv->drrs; dev_priv 3011 drivers/gpu/drm/i915/i915_debugfs.c if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) dev_priv 3013 drivers/gpu/drm/i915/i915_debugfs.c else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) dev_priv 3015 drivers/gpu/drm/i915/i915_debugfs.c else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) dev_priv 3032 drivers/gpu/drm/i915/i915_debugfs.c if (dev_priv->psr.enabled) dev_priv 3069 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 3070 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 3093 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 3094 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 3183 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 3184 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 3233 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 3234 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 3277 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 3278 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 3309 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 3310 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 3314 drivers/gpu/drm/i915/i915_debugfs.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 3316 drivers/gpu/drm/i915/i915_debugfs.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 3318 drivers/gpu/drm/i915/i915_debugfs.c else if (IS_G4X(dev_priv)) dev_priv 3321 drivers/gpu/drm/i915/i915_debugfs.c num_levels = ilk_wm_max_level(dev_priv) + 1; dev_priv 3332 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 9 || dev_priv 3333 drivers/gpu/drm/i915/i915_debugfs.c IS_VALLEYVIEW(dev_priv) || dev_priv 3334 drivers/gpu/drm/i915/i915_debugfs.c IS_CHERRYVIEW(dev_priv) || dev_priv 3335 drivers/gpu/drm/i915/i915_debugfs.c IS_G4X(dev_priv)) dev_priv 3349 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 3352 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 3353 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.skl_latency; dev_priv 3355 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.pri_latency; dev_priv 3364 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 3367 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 3368 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.skl_latency; dev_priv 3370 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.spr_latency; dev_priv 3379 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 3382 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 3383 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.skl_latency; dev_priv 3385 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.cur_latency; dev_priv 3394 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = inode->i_private; dev_priv 3396 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) dev_priv 3399 drivers/gpu/drm/i915/i915_debugfs.c return single_open(file, pri_wm_latency_show, dev_priv); dev_priv 3404 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = inode->i_private; dev_priv 3406 drivers/gpu/drm/i915/i915_debugfs.c if (HAS_GMCH(dev_priv)) dev_priv 3409 drivers/gpu/drm/i915/i915_debugfs.c return single_open(file, spr_wm_latency_show, dev_priv); dev_priv 3414 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = inode->i_private; dev_priv 3416 drivers/gpu/drm/i915/i915_debugfs.c if (HAS_GMCH(dev_priv)) dev_priv 3419 drivers/gpu/drm/i915/i915_debugfs.c return single_open(file, cur_wm_latency_show, dev_priv); dev_priv 3426 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 3427 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 3434 drivers/gpu/drm/i915/i915_debugfs.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 3436 drivers/gpu/drm/i915/i915_debugfs.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 3438 drivers/gpu/drm/i915/i915_debugfs.c else if (IS_G4X(dev_priv)) dev_priv 3441 drivers/gpu/drm/i915/i915_debugfs.c num_levels = ilk_wm_max_level(dev_priv) + 1; dev_priv 3472 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 3475 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 3476 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.skl_latency; dev_priv 3478 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.pri_latency; dev_priv 3487 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 3490 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 3491 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.skl_latency; dev_priv 3493 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.spr_latency; dev_priv 3502 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 3505 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 3506 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.skl_latency; dev_priv 3508 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.cur_latency; dev_priv 3683 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = data; dev_priv 3687 drivers/gpu/drm/i915/i915_debugfs.c if (!(IS_GEN_RANGE(dev_priv, 6, 7))) dev_priv 3690 drivers/gpu/drm/i915/i915_debugfs.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) dev_priv 3701 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = data; dev_priv 3704 drivers/gpu/drm/i915/i915_debugfs.c if (!(IS_GEN_RANGE(dev_priv, 6, 7))) dev_priv 3711 drivers/gpu/drm/i915/i915_debugfs.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { dev_priv 3728 drivers/gpu/drm/i915/i915_debugfs.c static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, dev_priv 3761 drivers/gpu/drm/i915/i915_debugfs.c static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, dev_priv 3765 drivers/gpu/drm/i915/i915_debugfs.c const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); dev_priv 3817 drivers/gpu/drm/i915/i915_debugfs.c static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, dev_priv 3821 drivers/gpu/drm/i915/i915_debugfs.c const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); dev_priv 3847 drivers/gpu/drm/i915/i915_debugfs.c if (IS_GEN9_BC(dev_priv)) dev_priv 3849 drivers/gpu/drm/i915/i915_debugfs.c RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; dev_priv 3854 drivers/gpu/drm/i915/i915_debugfs.c if (IS_GEN9_LP(dev_priv)) { dev_priv 3873 drivers/gpu/drm/i915/i915_debugfs.c static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, dev_priv 3883 drivers/gpu/drm/i915/i915_debugfs.c RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice; dev_priv 3886 drivers/gpu/drm/i915/i915_debugfs.c RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; dev_priv 3894 drivers/gpu/drm/i915/i915_debugfs.c RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s]; dev_priv 3904 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 3926 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); dev_priv 3927 drivers/gpu/drm/i915/i915_debugfs.c if (HAS_POOLED_EU(dev_priv)) dev_priv 3940 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = node_to_i915(m->private); dev_priv 3944 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) < 8) dev_priv 3948 drivers/gpu/drm/i915/i915_debugfs.c i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu); dev_priv 3952 drivers/gpu/drm/i915/i915_debugfs.c sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices; dev_priv 3953 drivers/gpu/drm/i915/i915_debugfs.c sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices; dev_priv 3955 drivers/gpu/drm/i915/i915_debugfs.c RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice; dev_priv 3957 drivers/gpu/drm/i915/i915_debugfs.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { dev_priv 3958 drivers/gpu/drm/i915/i915_debugfs.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 3959 drivers/gpu/drm/i915/i915_debugfs.c cherryview_sseu_device_status(dev_priv, &sseu); dev_priv 3960 drivers/gpu/drm/i915/i915_debugfs.c else if (IS_BROADWELL(dev_priv)) dev_priv 3961 drivers/gpu/drm/i915/i915_debugfs.c broadwell_sseu_device_status(dev_priv, &sseu); dev_priv 3962 drivers/gpu/drm/i915/i915_debugfs.c else if (IS_GEN(dev_priv, 9)) dev_priv 3963 drivers/gpu/drm/i915/i915_debugfs.c gen9_sseu_device_status(dev_priv, &sseu); dev_priv 3964 drivers/gpu/drm/i915/i915_debugfs.c else if (INTEL_GEN(dev_priv) >= 10) dev_priv 3965 drivers/gpu/drm/i915/i915_debugfs.c gen10_sseu_device_status(dev_priv, &sseu); dev_priv 4009 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 4010 drivers/gpu/drm/i915/i915_debugfs.c struct i915_hotplug *hotplug = &dev_priv->hotplug; dev_priv 4015 drivers/gpu/drm/i915/i915_debugfs.c intel_synchronize_irq(dev_priv); dev_priv 4016 drivers/gpu/drm/i915/i915_debugfs.c flush_work(&dev_priv->hotplug.dig_port_work); dev_priv 4017 drivers/gpu/drm/i915/i915_debugfs.c flush_delayed_work(&dev_priv->hotplug.hotplug_work); dev_priv 4031 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 4032 drivers/gpu/drm/i915/i915_debugfs.c struct i915_hotplug *hotplug = &dev_priv->hotplug; dev_priv 4062 drivers/gpu/drm/i915/i915_debugfs.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 4067 drivers/gpu/drm/i915/i915_debugfs.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 4070 drivers/gpu/drm/i915/i915_debugfs.c flush_delayed_work(&dev_priv->hotplug.reenable_work); dev_priv 4091 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 4094 drivers/gpu/drm/i915/i915_debugfs.c yesno(dev_priv->hotplug.hpd_short_storm_enabled)); dev_priv 4111 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = m->private; dev_priv 4112 drivers/gpu/drm/i915/i915_debugfs.c struct i915_hotplug *hotplug = &dev_priv->hotplug; dev_priv 4133 drivers/gpu/drm/i915/i915_debugfs.c new_state = !HAS_DP_MST(dev_priv); dev_priv 4140 drivers/gpu/drm/i915/i915_debugfs.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 4145 drivers/gpu/drm/i915/i915_debugfs.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 4148 drivers/gpu/drm/i915/i915_debugfs.c flush_delayed_work(&dev_priv->hotplug.reenable_work); dev_priv 4164 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = data; dev_priv 4165 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 4168 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) < 7) dev_priv 4237 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = filp->private_data; dev_priv 4239 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 4279 drivers/gpu/drm/i915/i915_debugfs.c ret = intel_fbc_reset_underrun(dev_priv); dev_priv 4366 drivers/gpu/drm/i915/i915_debugfs.c int i915_debugfs_register(struct drm_i915_private *dev_priv) dev_priv 4368 drivers/gpu/drm/i915/i915_debugfs.c struct drm_minor *minor = dev_priv->drm.primary; dev_priv 4604 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = to_i915(connector->dev); dev_priv 4629 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 10 && dev_priv 13 drivers/gpu/drm/i915/i915_debugfs.h int i915_debugfs_register(struct drm_i915_private *dev_priv); dev_priv 16 drivers/gpu/drm/i915/i915_debugfs.h static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) { return 0; } dev_priv 145 drivers/gpu/drm/i915/i915_drv.c static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) dev_priv 147 drivers/gpu/drm/i915/i915_drv.c int domain = pci_domain_nr(dev_priv->drm.pdev->bus); dev_priv 149 drivers/gpu/drm/i915/i915_drv.c dev_priv->bridge_dev = dev_priv 151 drivers/gpu/drm/i915/i915_drv.c if (!dev_priv->bridge_dev) { dev_priv 160 drivers/gpu/drm/i915/i915_drv.c intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) dev_priv 162 drivers/gpu/drm/i915/i915_drv.c int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; dev_priv 167 drivers/gpu/drm/i915/i915_drv.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 168 drivers/gpu/drm/i915/i915_drv.c pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); dev_priv 169 drivers/gpu/drm/i915/i915_drv.c pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); dev_priv 180 drivers/gpu/drm/i915/i915_drv.c dev_priv->mch_res.name = "i915 MCHBAR"; dev_priv 181 drivers/gpu/drm/i915/i915_drv.c dev_priv->mch_res.flags = IORESOURCE_MEM; dev_priv 182 drivers/gpu/drm/i915/i915_drv.c ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, dev_priv 183 drivers/gpu/drm/i915/i915_drv.c &dev_priv->mch_res, dev_priv 187 drivers/gpu/drm/i915/i915_drv.c dev_priv->bridge_dev); dev_priv 190 drivers/gpu/drm/i915/i915_drv.c dev_priv->mch_res.start = 0; dev_priv 194 drivers/gpu/drm/i915/i915_drv.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 195 drivers/gpu/drm/i915/i915_drv.c pci_write_config_dword(dev_priv->bridge_dev, reg + 4, dev_priv 196 drivers/gpu/drm/i915/i915_drv.c upper_32_bits(dev_priv->mch_res.start)); dev_priv 198 drivers/gpu/drm/i915/i915_drv.c pci_write_config_dword(dev_priv->bridge_dev, reg, dev_priv 199 drivers/gpu/drm/i915/i915_drv.c lower_32_bits(dev_priv->mch_res.start)); dev_priv 205 drivers/gpu/drm/i915/i915_drv.c intel_setup_mchbar(struct drm_i915_private *dev_priv) dev_priv 207 drivers/gpu/drm/i915/i915_drv.c int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; dev_priv 211 drivers/gpu/drm/i915/i915_drv.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 214 drivers/gpu/drm/i915/i915_drv.c dev_priv->mchbar_need_disable = false; dev_priv 216 drivers/gpu/drm/i915/i915_drv.c if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { dev_priv 217 drivers/gpu/drm/i915/i915_drv.c pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); dev_priv 220 drivers/gpu/drm/i915/i915_drv.c pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); dev_priv 228 drivers/gpu/drm/i915/i915_drv.c if (intel_alloc_mchbar_resource(dev_priv)) dev_priv 231 drivers/gpu/drm/i915/i915_drv.c dev_priv->mchbar_need_disable = true; dev_priv 234 drivers/gpu/drm/i915/i915_drv.c if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { dev_priv 235 drivers/gpu/drm/i915/i915_drv.c pci_write_config_dword(dev_priv->bridge_dev, DEVEN, dev_priv 238 drivers/gpu/drm/i915/i915_drv.c pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); dev_priv 239 drivers/gpu/drm/i915/i915_drv.c pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); dev_priv 244 drivers/gpu/drm/i915/i915_drv.c intel_teardown_mchbar(struct drm_i915_private *dev_priv) dev_priv 246 drivers/gpu/drm/i915/i915_drv.c int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; dev_priv 248 drivers/gpu/drm/i915/i915_drv.c if (dev_priv->mchbar_need_disable) { dev_priv 249 drivers/gpu/drm/i915/i915_drv.c if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { dev_priv 252 drivers/gpu/drm/i915/i915_drv.c pci_read_config_dword(dev_priv->bridge_dev, DEVEN, dev_priv 255 drivers/gpu/drm/i915/i915_drv.c pci_write_config_dword(dev_priv->bridge_dev, DEVEN, dev_priv 260 drivers/gpu/drm/i915/i915_drv.c pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, dev_priv 263 drivers/gpu/drm/i915/i915_drv.c pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, dev_priv 268 drivers/gpu/drm/i915/i915_drv.c if (dev_priv->mch_res.start) dev_priv 269 drivers/gpu/drm/i915/i915_drv.c release_resource(&dev_priv->mch_res); dev_priv 275 drivers/gpu/drm/i915/i915_drv.c struct drm_i915_private *dev_priv = cookie; dev_priv 277 drivers/gpu/drm/i915/i915_drv.c intel_modeset_vga_set_state(dev_priv, state); dev_priv 334 drivers/gpu/drm/i915/i915_drv.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 335 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 338 drivers/gpu/drm/i915/i915_drv.c if (i915_inject_probe_failure(dev_priv)) dev_priv 341 drivers/gpu/drm/i915/i915_drv.c if (HAS_DISPLAY(dev_priv)) { dev_priv 342 drivers/gpu/drm/i915/i915_drv.c ret = drm_vblank_init(&dev_priv->drm, dev_priv 343 drivers/gpu/drm/i915/i915_drv.c INTEL_INFO(dev_priv)->num_pipes); dev_priv 348 drivers/gpu/drm/i915/i915_drv.c intel_bios_init(dev_priv); dev_priv 357 drivers/gpu/drm/i915/i915_drv.c ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode); dev_priv 367 drivers/gpu/drm/i915/i915_drv.c intel_power_domains_init_hw(dev_priv, false); dev_priv 369 drivers/gpu/drm/i915/i915_drv.c intel_csr_ucode_init(dev_priv); dev_priv 371 drivers/gpu/drm/i915/i915_drv.c ret = intel_irq_install(dev_priv); dev_priv 375 drivers/gpu/drm/i915/i915_drv.c intel_gmbus_setup(dev_priv); dev_priv 383 drivers/gpu/drm/i915/i915_drv.c ret = i915_gem_init(dev_priv); dev_priv 387 drivers/gpu/drm/i915/i915_drv.c intel_overlay_setup(dev_priv); dev_priv 389 drivers/gpu/drm/i915/i915_drv.c if (!HAS_DISPLAY(dev_priv)) dev_priv 397 drivers/gpu/drm/i915/i915_drv.c intel_hpd_init(dev_priv); dev_priv 399 drivers/gpu/drm/i915/i915_drv.c intel_init_ipc(dev_priv); dev_priv 404 drivers/gpu/drm/i915/i915_drv.c i915_gem_suspend(dev_priv); dev_priv 405 drivers/gpu/drm/i915/i915_drv.c i915_gem_driver_remove(dev_priv); dev_priv 406 drivers/gpu/drm/i915/i915_drv.c i915_gem_driver_release(dev_priv); dev_priv 410 drivers/gpu/drm/i915/i915_drv.c intel_irq_uninstall(dev_priv); dev_priv 411 drivers/gpu/drm/i915/i915_drv.c intel_gmbus_teardown(dev_priv); dev_priv 413 drivers/gpu/drm/i915/i915_drv.c intel_csr_ucode_fini(dev_priv); dev_priv 414 drivers/gpu/drm/i915/i915_drv.c intel_power_domains_driver_remove(dev_priv); dev_priv 422 drivers/gpu/drm/i915/i915_drv.c static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) dev_priv 425 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 426 drivers/gpu/drm/i915/i915_drv.c struct i915_ggtt *ggtt = &dev_priv->ggtt; dev_priv 447 drivers/gpu/drm/i915/i915_drv.c static void intel_init_dpio(struct drm_i915_private *dev_priv) dev_priv 454 drivers/gpu/drm/i915/i915_drv.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 457 drivers/gpu/drm/i915/i915_drv.c } else if (IS_VALLEYVIEW(dev_priv)) { dev_priv 462 drivers/gpu/drm/i915/i915_drv.c static int i915_workqueues_init(struct drm_i915_private *dev_priv) dev_priv 478 drivers/gpu/drm/i915/i915_drv.c dev_priv->wq = alloc_ordered_workqueue("i915", 0); dev_priv 479 drivers/gpu/drm/i915/i915_drv.c if (dev_priv->wq == NULL) dev_priv 482 drivers/gpu/drm/i915/i915_drv.c dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); dev_priv 483 drivers/gpu/drm/i915/i915_drv.c if (dev_priv->hotplug.dp_wq == NULL) dev_priv 489 drivers/gpu/drm/i915/i915_drv.c destroy_workqueue(dev_priv->wq); dev_priv 496 drivers/gpu/drm/i915/i915_drv.c static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) dev_priv 498 drivers/gpu/drm/i915/i915_drv.c destroy_workqueue(dev_priv->hotplug.dp_wq); dev_priv 499 drivers/gpu/drm/i915/i915_drv.c destroy_workqueue(dev_priv->wq); dev_priv 512 drivers/gpu/drm/i915/i915_drv.c static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) dev_priv 516 drivers/gpu/drm/i915/i915_drv.c pre |= IS_HSW_EARLY_SDV(dev_priv); dev_priv 517 drivers/gpu/drm/i915/i915_drv.c pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0); dev_priv 518 drivers/gpu/drm/i915/i915_drv.c pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST); dev_priv 519 drivers/gpu/drm/i915/i915_drv.c pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0); dev_priv 561 drivers/gpu/drm/i915/i915_drv.c static int i915_driver_early_probe(struct drm_i915_private *dev_priv) dev_priv 565 drivers/gpu/drm/i915/i915_drv.c if (i915_inject_probe_failure(dev_priv)) dev_priv 568 drivers/gpu/drm/i915/i915_drv.c intel_device_info_subplatform_init(dev_priv); dev_priv 570 drivers/gpu/drm/i915/i915_drv.c intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug); dev_priv 571 drivers/gpu/drm/i915/i915_drv.c intel_uncore_init_early(&dev_priv->uncore, dev_priv); dev_priv 573 drivers/gpu/drm/i915/i915_drv.c spin_lock_init(&dev_priv->irq_lock); dev_priv 574 drivers/gpu/drm/i915/i915_drv.c spin_lock_init(&dev_priv->gpu_error.lock); dev_priv 575 drivers/gpu/drm/i915/i915_drv.c mutex_init(&dev_priv->backlight_lock); dev_priv 577 drivers/gpu/drm/i915/i915_drv.c mutex_init(&dev_priv->sb_lock); dev_priv 578 drivers/gpu/drm/i915/i915_drv.c pm_qos_add_request(&dev_priv->sb_qos, dev_priv 581 drivers/gpu/drm/i915/i915_drv.c mutex_init(&dev_priv->av_mutex); dev_priv 582 drivers/gpu/drm/i915/i915_drv.c mutex_init(&dev_priv->wm.wm_mutex); dev_priv 583 drivers/gpu/drm/i915/i915_drv.c mutex_init(&dev_priv->pps_mutex); dev_priv 584 drivers/gpu/drm/i915/i915_drv.c mutex_init(&dev_priv->hdcp_comp_mutex); dev_priv 586 drivers/gpu/drm/i915/i915_drv.c i915_memcpy_init_early(dev_priv); dev_priv 587 drivers/gpu/drm/i915/i915_drv.c intel_runtime_pm_init_early(&dev_priv->runtime_pm); dev_priv 589 drivers/gpu/drm/i915/i915_drv.c ret = i915_workqueues_init(dev_priv); dev_priv 593 drivers/gpu/drm/i915/i915_drv.c ret = vlv_alloc_s0ix_state(dev_priv); dev_priv 597 drivers/gpu/drm/i915/i915_drv.c intel_wopcm_init_early(&dev_priv->wopcm); dev_priv 599 drivers/gpu/drm/i915/i915_drv.c intel_gt_init_early(&dev_priv->gt, dev_priv); dev_priv 601 drivers/gpu/drm/i915/i915_drv.c ret = i915_gem_init_early(dev_priv); dev_priv 606 drivers/gpu/drm/i915/i915_drv.c intel_detect_pch(dev_priv); dev_priv 608 drivers/gpu/drm/i915/i915_drv.c intel_pm_setup(dev_priv); dev_priv 609 drivers/gpu/drm/i915/i915_drv.c intel_init_dpio(dev_priv); dev_priv 610 drivers/gpu/drm/i915/i915_drv.c ret = intel_power_domains_init(dev_priv); dev_priv 613 drivers/gpu/drm/i915/i915_drv.c intel_irq_init(dev_priv); dev_priv 614 drivers/gpu/drm/i915/i915_drv.c intel_init_display_hooks(dev_priv); dev_priv 615 drivers/gpu/drm/i915/i915_drv.c intel_init_clock_gating_hooks(dev_priv); dev_priv 616 drivers/gpu/drm/i915/i915_drv.c intel_init_audio_hooks(dev_priv); dev_priv 617 drivers/gpu/drm/i915/i915_drv.c intel_display_crc_init(dev_priv); dev_priv 619 drivers/gpu/drm/i915/i915_drv.c intel_detect_preproduction_hw(dev_priv); dev_priv 624 drivers/gpu/drm/i915/i915_drv.c i915_gem_cleanup_early(dev_priv); dev_priv 626 drivers/gpu/drm/i915/i915_drv.c intel_gt_driver_late_release(&dev_priv->gt); dev_priv 627 drivers/gpu/drm/i915/i915_drv.c vlv_free_s0ix_state(dev_priv); dev_priv 629 drivers/gpu/drm/i915/i915_drv.c i915_workqueues_cleanup(dev_priv); dev_priv 638 drivers/gpu/drm/i915/i915_drv.c static void i915_driver_late_release(struct drm_i915_private *dev_priv) dev_priv 640 drivers/gpu/drm/i915/i915_drv.c intel_irq_fini(dev_priv); dev_priv 641 drivers/gpu/drm/i915/i915_drv.c intel_power_domains_cleanup(dev_priv); dev_priv 642 drivers/gpu/drm/i915/i915_drv.c i915_gem_cleanup_early(dev_priv); dev_priv 643 drivers/gpu/drm/i915/i915_drv.c intel_gt_driver_late_release(&dev_priv->gt); dev_priv 644 drivers/gpu/drm/i915/i915_drv.c vlv_free_s0ix_state(dev_priv); dev_priv 645 drivers/gpu/drm/i915/i915_drv.c i915_workqueues_cleanup(dev_priv); dev_priv 647 drivers/gpu/drm/i915/i915_drv.c pm_qos_remove_request(&dev_priv->sb_qos); dev_priv 648 drivers/gpu/drm/i915/i915_drv.c mutex_destroy(&dev_priv->sb_lock); dev_priv 660 drivers/gpu/drm/i915/i915_drv.c static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) dev_priv 664 drivers/gpu/drm/i915/i915_drv.c if (i915_inject_probe_failure(dev_priv)) dev_priv 667 drivers/gpu/drm/i915/i915_drv.c if (i915_get_bridge_dev(dev_priv)) dev_priv 670 drivers/gpu/drm/i915/i915_drv.c ret = intel_uncore_init_mmio(&dev_priv->uncore); dev_priv 675 drivers/gpu/drm/i915/i915_drv.c intel_setup_mchbar(dev_priv); dev_priv 677 drivers/gpu/drm/i915/i915_drv.c intel_device_info_init_mmio(dev_priv); dev_priv 679 drivers/gpu/drm/i915/i915_drv.c intel_uncore_prune_mmio_domains(&dev_priv->uncore); dev_priv 681 drivers/gpu/drm/i915/i915_drv.c intel_uc_init_mmio(&dev_priv->gt.uc); dev_priv 683 drivers/gpu/drm/i915/i915_drv.c ret = intel_engines_init_mmio(dev_priv); dev_priv 687 drivers/gpu/drm/i915/i915_drv.c i915_gem_init_mmio(dev_priv); dev_priv 692 drivers/gpu/drm/i915/i915_drv.c intel_teardown_mchbar(dev_priv); dev_priv 693 drivers/gpu/drm/i915/i915_drv.c intel_uncore_fini_mmio(&dev_priv->uncore); dev_priv 695 drivers/gpu/drm/i915/i915_drv.c pci_dev_put(dev_priv->bridge_dev); dev_priv 704 drivers/gpu/drm/i915/i915_drv.c static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) dev_priv 706 drivers/gpu/drm/i915/i915_drv.c intel_engines_cleanup(dev_priv); dev_priv 707 drivers/gpu/drm/i915/i915_drv.c intel_teardown_mchbar(dev_priv); dev_priv 708 drivers/gpu/drm/i915/i915_drv.c intel_uncore_fini_mmio(&dev_priv->uncore); dev_priv 709 drivers/gpu/drm/i915/i915_drv.c pci_dev_put(dev_priv->bridge_dev); dev_priv 712 drivers/gpu/drm/i915/i915_drv.c static void intel_sanitize_options(struct drm_i915_private *dev_priv) dev_priv 714 drivers/gpu/drm/i915/i915_drv.c intel_gvt_sanitize_options(dev_priv); dev_priv 816 drivers/gpu/drm/i915/i915_drv.c skl_dram_get_dimm_info(struct drm_i915_private *dev_priv, dev_priv 820 drivers/gpu/drm/i915/i915_drv.c if (INTEL_GEN(dev_priv) >= 10) { dev_priv 836 drivers/gpu/drm/i915/i915_drv.c skl_dram_get_channel_info(struct drm_i915_private *dev_priv, dev_priv 840 drivers/gpu/drm/i915/i915_drv.c skl_dram_get_dimm_info(dev_priv, &ch->dimm_l, dev_priv 842 drivers/gpu/drm/i915/i915_drv.c skl_dram_get_dimm_info(dev_priv, &ch->dimm_s, dev_priv 877 drivers/gpu/drm/i915/i915_drv.c skl_dram_get_channels_info(struct drm_i915_private *dev_priv) dev_priv 879 drivers/gpu/drm/i915/i915_drv.c struct dram_info *dram_info = &dev_priv->dram_info; dev_priv 885 drivers/gpu/drm/i915/i915_drv.c ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val); dev_priv 890 drivers/gpu/drm/i915/i915_drv.c ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val); dev_priv 924 drivers/gpu/drm/i915/i915_drv.c skl_get_dram_type(struct drm_i915_private *dev_priv) dev_priv 946 drivers/gpu/drm/i915/i915_drv.c skl_get_dram_info(struct drm_i915_private *dev_priv) dev_priv 948 drivers/gpu/drm/i915/i915_drv.c struct dram_info *dram_info = &dev_priv->dram_info; dev_priv 952 drivers/gpu/drm/i915/i915_drv.c dram_info->type = skl_get_dram_type(dev_priv); dev_priv 955 drivers/gpu/drm/i915/i915_drv.c ret = skl_dram_get_channels_info(dev_priv); dev_priv 1055 drivers/gpu/drm/i915/i915_drv.c bxt_get_dram_info(struct drm_i915_private *dev_priv) dev_priv 1057 drivers/gpu/drm/i915/i915_drv.c struct dram_info *dram_info = &dev_priv->dram_info; dev_priv 1128 drivers/gpu/drm/i915/i915_drv.c intel_get_dram_info(struct drm_i915_private *dev_priv) dev_priv 1130 drivers/gpu/drm/i915/i915_drv.c struct dram_info *dram_info = &dev_priv->dram_info; dev_priv 1138 drivers/gpu/drm/i915/i915_drv.c dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv); dev_priv 1140 drivers/gpu/drm/i915/i915_drv.c if (INTEL_GEN(dev_priv) < 9) dev_priv 1143 drivers/gpu/drm/i915/i915_drv.c if (IS_GEN9_LP(dev_priv)) dev_priv 1144 drivers/gpu/drm/i915/i915_drv.c ret = bxt_get_dram_info(dev_priv); dev_priv 1146 drivers/gpu/drm/i915/i915_drv.c ret = skl_get_dram_info(dev_priv); dev_priv 1158 drivers/gpu/drm/i915/i915_drv.c static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap) dev_priv 1168 drivers/gpu/drm/i915/i915_drv.c static void edram_detect(struct drm_i915_private *dev_priv) dev_priv 1172 drivers/gpu/drm/i915/i915_drv.c if (!(IS_HASWELL(dev_priv) || dev_priv 1173 drivers/gpu/drm/i915/i915_drv.c IS_BROADWELL(dev_priv) || dev_priv 1174 drivers/gpu/drm/i915/i915_drv.c INTEL_GEN(dev_priv) >= 9)) dev_priv 1177 drivers/gpu/drm/i915/i915_drv.c edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP); dev_priv 1188 drivers/gpu/drm/i915/i915_drv.c if (INTEL_GEN(dev_priv) < 9) dev_priv 1189 drivers/gpu/drm/i915/i915_drv.c dev_priv->edram_size_mb = 128; dev_priv 1191 drivers/gpu/drm/i915/i915_drv.c dev_priv->edram_size_mb = dev_priv 1192 drivers/gpu/drm/i915/i915_drv.c gen9_edram_size_mb(dev_priv, edram_cap); dev_priv 1194 drivers/gpu/drm/i915/i915_drv.c dev_info(dev_priv->drm.dev, dev_priv 1195 drivers/gpu/drm/i915/i915_drv.c "Found %uMB of eDRAM\n", dev_priv->edram_size_mb); dev_priv 1205 drivers/gpu/drm/i915/i915_drv.c static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) dev_priv 1207 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 1210 drivers/gpu/drm/i915/i915_drv.c if (i915_inject_probe_failure(dev_priv)) dev_priv 1213 drivers/gpu/drm/i915/i915_drv.c intel_device_info_runtime_init(dev_priv); dev_priv 1215 drivers/gpu/drm/i915/i915_drv.c if (HAS_PPGTT(dev_priv)) { dev_priv 1216 drivers/gpu/drm/i915/i915_drv.c if (intel_vgpu_active(dev_priv) && dev_priv 1217 drivers/gpu/drm/i915/i915_drv.c !intel_vgpu_has_full_ppgtt(dev_priv)) { dev_priv 1218 drivers/gpu/drm/i915/i915_drv.c i915_report_error(dev_priv, dev_priv 1224 drivers/gpu/drm/i915/i915_drv.c if (HAS_EXECLISTS(dev_priv)) { dev_priv 1230 drivers/gpu/drm/i915/i915_drv.c if (intel_vgpu_active(dev_priv) && dev_priv 1231 drivers/gpu/drm/i915/i915_drv.c !intel_vgpu_has_hwsp_emulation(dev_priv)) { dev_priv 1232 drivers/gpu/drm/i915/i915_drv.c i915_report_error(dev_priv, dev_priv 1238 drivers/gpu/drm/i915/i915_drv.c intel_sanitize_options(dev_priv); dev_priv 1241 drivers/gpu/drm/i915/i915_drv.c edram_detect(dev_priv); dev_priv 1243 drivers/gpu/drm/i915/i915_drv.c i915_perf_init(dev_priv); dev_priv 1245 drivers/gpu/drm/i915/i915_drv.c ret = i915_ggtt_probe_hw(dev_priv); dev_priv 1253 drivers/gpu/drm/i915/i915_drv.c ret = i915_kick_out_firmware_fb(dev_priv); dev_priv 1265 drivers/gpu/drm/i915/i915_drv.c ret = i915_ggtt_init_hw(dev_priv); dev_priv 1269 drivers/gpu/drm/i915/i915_drv.c intel_gt_init_hw(dev_priv); dev_priv 1271 drivers/gpu/drm/i915/i915_drv.c ret = i915_ggtt_enable_hw(dev_priv); dev_priv 1286 drivers/gpu/drm/i915/i915_drv.c if (IS_GEN(dev_priv, 2)) { dev_priv 1303 drivers/gpu/drm/i915/i915_drv.c if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) { dev_priv 1313 drivers/gpu/drm/i915/i915_drv.c pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, dev_priv 1317 drivers/gpu/drm/i915/i915_drv.c intel_sanitize_gt_powersave(dev_priv); dev_priv 1319 drivers/gpu/drm/i915/i915_drv.c intel_gt_init_workarounds(dev_priv); dev_priv 1340 drivers/gpu/drm/i915/i915_drv.c if (INTEL_GEN(dev_priv) >= 5) { dev_priv 1345 drivers/gpu/drm/i915/i915_drv.c ret = intel_gvt_init(dev_priv); dev_priv 1349 drivers/gpu/drm/i915/i915_drv.c intel_opregion_setup(dev_priv); dev_priv 1354 drivers/gpu/drm/i915/i915_drv.c intel_get_dram_info(dev_priv); dev_priv 1356 drivers/gpu/drm/i915/i915_drv.c intel_bw_init_hw(dev_priv); dev_priv 1363 drivers/gpu/drm/i915/i915_drv.c pm_qos_remove_request(&dev_priv->pm_qos); dev_priv 1365 drivers/gpu/drm/i915/i915_drv.c i915_ggtt_driver_release(dev_priv); dev_priv 1367 drivers/gpu/drm/i915/i915_drv.c i915_perf_fini(dev_priv); dev_priv 1375 drivers/gpu/drm/i915/i915_drv.c static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) dev_priv 1377 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 1379 drivers/gpu/drm/i915/i915_drv.c i915_perf_fini(dev_priv); dev_priv 1384 drivers/gpu/drm/i915/i915_drv.c pm_qos_remove_request(&dev_priv->pm_qos); dev_priv 1394 drivers/gpu/drm/i915/i915_drv.c static void i915_driver_register(struct drm_i915_private *dev_priv) dev_priv 1396 drivers/gpu/drm/i915/i915_drv.c struct drm_device *dev = &dev_priv->drm; dev_priv 1398 drivers/gpu/drm/i915/i915_drv.c i915_gem_driver_register(dev_priv); dev_priv 1399 drivers/gpu/drm/i915/i915_drv.c i915_pmu_register(dev_priv); dev_priv 1405 drivers/gpu/drm/i915/i915_drv.c if (intel_vgpu_active(dev_priv)) dev_priv 1410 drivers/gpu/drm/i915/i915_drv.c i915_debugfs_register(dev_priv); dev_priv 1411 drivers/gpu/drm/i915/i915_drv.c i915_setup_sysfs(dev_priv); dev_priv 1414 drivers/gpu/drm/i915/i915_drv.c i915_perf_register(dev_priv); dev_priv 1418 drivers/gpu/drm/i915/i915_drv.c if (HAS_DISPLAY(dev_priv)) { dev_priv 1420 drivers/gpu/drm/i915/i915_drv.c intel_opregion_register(dev_priv); dev_priv 1424 drivers/gpu/drm/i915/i915_drv.c if (IS_GEN(dev_priv, 5)) dev_priv 1425 drivers/gpu/drm/i915/i915_drv.c intel_gpu_ips_init(dev_priv); dev_priv 1427 drivers/gpu/drm/i915/i915_drv.c intel_audio_init(dev_priv); dev_priv 1442 drivers/gpu/drm/i915/i915_drv.c if (HAS_DISPLAY(dev_priv)) dev_priv 1445 drivers/gpu/drm/i915/i915_drv.c intel_power_domains_enable(dev_priv); dev_priv 1446 drivers/gpu/drm/i915/i915_drv.c intel_runtime_pm_enable(&dev_priv->runtime_pm); dev_priv 1453 drivers/gpu/drm/i915/i915_drv.c static void i915_driver_unregister(struct drm_i915_private *dev_priv) dev_priv 1455 drivers/gpu/drm/i915/i915_drv.c intel_runtime_pm_disable(&dev_priv->runtime_pm); dev_priv 1456 drivers/gpu/drm/i915/i915_drv.c intel_power_domains_disable(dev_priv); dev_priv 1458 drivers/gpu/drm/i915/i915_drv.c intel_fbdev_unregister(dev_priv); dev_priv 1459 drivers/gpu/drm/i915/i915_drv.c intel_audio_deinit(dev_priv); dev_priv 1466 drivers/gpu/drm/i915/i915_drv.c drm_kms_helper_poll_fini(&dev_priv->drm); dev_priv 1470 drivers/gpu/drm/i915/i915_drv.c intel_opregion_unregister(dev_priv); dev_priv 1472 drivers/gpu/drm/i915/i915_drv.c i915_perf_unregister(dev_priv); dev_priv 1473 drivers/gpu/drm/i915/i915_drv.c i915_pmu_unregister(dev_priv); dev_priv 1475 drivers/gpu/drm/i915/i915_drv.c i915_teardown_sysfs(dev_priv); dev_priv 1476 drivers/gpu/drm/i915/i915_drv.c drm_dev_unplug(&dev_priv->drm); dev_priv 1478 drivers/gpu/drm/i915/i915_drv.c i915_gem_driver_unregister(dev_priv); dev_priv 1481 drivers/gpu/drm/i915/i915_drv.c static void i915_welcome_messages(struct drm_i915_private *dev_priv) dev_priv 1487 drivers/gpu/drm/i915/i915_drv.c INTEL_DEVID(dev_priv), dev_priv 1488 drivers/gpu/drm/i915/i915_drv.c INTEL_REVID(dev_priv), dev_priv 1489 drivers/gpu/drm/i915/i915_drv.c intel_platform_name(INTEL_INFO(dev_priv)->platform), dev_priv 1490 drivers/gpu/drm/i915/i915_drv.c intel_subplatform(RUNTIME_INFO(dev_priv), dev_priv 1491 drivers/gpu/drm/i915/i915_drv.c INTEL_INFO(dev_priv)->platform), dev_priv 1492 drivers/gpu/drm/i915/i915_drv.c INTEL_GEN(dev_priv)); dev_priv 1494 drivers/gpu/drm/i915/i915_drv.c intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p); dev_priv 1495 drivers/gpu/drm/i915/i915_drv.c intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p); dev_priv 1566 drivers/gpu/drm/i915/i915_drv.c struct drm_i915_private *dev_priv; dev_priv 1569 drivers/gpu/drm/i915/i915_drv.c dev_priv = i915_driver_create(pdev, ent); dev_priv 1570 drivers/gpu/drm/i915/i915_drv.c if (IS_ERR(dev_priv)) dev_priv 1571 drivers/gpu/drm/i915/i915_drv.c return PTR_ERR(dev_priv); dev_priv 1575 drivers/gpu/drm/i915/i915_drv.c dev_priv->drm.driver_features &= ~DRIVER_ATOMIC; dev_priv 1581 drivers/gpu/drm/i915/i915_drv.c ret = i915_driver_early_probe(dev_priv); dev_priv 1585 drivers/gpu/drm/i915/i915_drv.c disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 1587 drivers/gpu/drm/i915/i915_drv.c i915_detect_vgpu(dev_priv); dev_priv 1589 drivers/gpu/drm/i915/i915_drv.c ret = i915_driver_mmio_probe(dev_priv); dev_priv 1593 drivers/gpu/drm/i915/i915_drv.c ret = i915_driver_hw_probe(dev_priv); dev_priv 1597 drivers/gpu/drm/i915/i915_drv.c ret = i915_driver_modeset_probe(&dev_priv->drm); dev_priv 1601 drivers/gpu/drm/i915/i915_drv.c i915_driver_register(dev_priv); dev_priv 1603 drivers/gpu/drm/i915/i915_drv.c enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 1605 drivers/gpu/drm/i915/i915_drv.c i915_welcome_messages(dev_priv); dev_priv 1610 drivers/gpu/drm/i915/i915_drv.c i915_driver_hw_remove(dev_priv); dev_priv 1611 drivers/gpu/drm/i915/i915_drv.c i915_ggtt_driver_release(dev_priv); dev_priv 1614 drivers/gpu/drm/i915/i915_drv.c intel_sanitize_gt_powersave(dev_priv); dev_priv 1616 drivers/gpu/drm/i915/i915_drv.c i915_driver_mmio_release(dev_priv); dev_priv 1618 drivers/gpu/drm/i915/i915_drv.c enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 1619 drivers/gpu/drm/i915/i915_drv.c i915_driver_late_release(dev_priv); dev_priv 1623 drivers/gpu/drm/i915/i915_drv.c i915_probe_error(dev_priv, "Device initialization failed (%d)\n", ret); dev_priv 1624 drivers/gpu/drm/i915/i915_drv.c i915_driver_destroy(dev_priv); dev_priv 1676 drivers/gpu/drm/i915/i915_drv.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1677 drivers/gpu/drm/i915/i915_drv.c struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; dev_priv 1681 drivers/gpu/drm/i915/i915_drv.c i915_gem_driver_release(dev_priv); dev_priv 1683 drivers/gpu/drm/i915/i915_drv.c i915_ggtt_driver_release(dev_priv); dev_priv 1686 drivers/gpu/drm/i915/i915_drv.c intel_sanitize_gt_powersave(dev_priv); dev_priv 1688 drivers/gpu/drm/i915/i915_drv.c i915_driver_mmio_release(dev_priv); dev_priv 1693 drivers/gpu/drm/i915/i915_drv.c i915_driver_late_release(dev_priv); dev_priv 1694 drivers/gpu/drm/i915/i915_drv.c i915_driver_destroy(dev_priv); dev_priv 1742 drivers/gpu/drm/i915/i915_drv.c static void intel_suspend_encoders(struct drm_i915_private *dev_priv) dev_priv 1744 drivers/gpu/drm/i915/i915_drv.c struct drm_device *dev = &dev_priv->drm; dev_priv 1754 drivers/gpu/drm/i915/i915_drv.c static int vlv_resume_prepare(struct drm_i915_private *dev_priv, dev_priv 1756 drivers/gpu/drm/i915/i915_drv.c static int vlv_suspend_complete(struct drm_i915_private *dev_priv); dev_priv 1758 drivers/gpu/drm/i915/i915_drv.c static bool suspend_to_idle(struct drm_i915_private *dev_priv) dev_priv 1784 drivers/gpu/drm/i915/i915_drv.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1785 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 1788 drivers/gpu/drm/i915/i915_drv.c disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 1792 drivers/gpu/drm/i915/i915_drv.c intel_power_domains_disable(dev_priv); dev_priv 1800 drivers/gpu/drm/i915/i915_drv.c intel_dp_mst_suspend(dev_priv); dev_priv 1802 drivers/gpu/drm/i915/i915_drv.c intel_runtime_pm_disable_interrupts(dev_priv); dev_priv 1803 drivers/gpu/drm/i915/i915_drv.c intel_hpd_cancel_work(dev_priv); dev_priv 1805 drivers/gpu/drm/i915/i915_drv.c intel_suspend_encoders(dev_priv); dev_priv 1807 drivers/gpu/drm/i915/i915_drv.c intel_suspend_hw(dev_priv); dev_priv 1809 drivers/gpu/drm/i915/i915_drv.c i915_gem_suspend_gtt_mappings(dev_priv); dev_priv 1811 drivers/gpu/drm/i915/i915_drv.c i915_save_state(dev_priv); dev_priv 1813 drivers/gpu/drm/i915/i915_drv.c opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; dev_priv 1814 drivers/gpu/drm/i915/i915_drv.c intel_opregion_suspend(dev_priv, opregion_target_state); dev_priv 1818 drivers/gpu/drm/i915/i915_drv.c dev_priv->suspend_count++; dev_priv 1820 drivers/gpu/drm/i915/i915_drv.c intel_csr_ucode_suspend(dev_priv); dev_priv 1822 drivers/gpu/drm/i915/i915_drv.c enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 1828 drivers/gpu/drm/i915/i915_drv.c get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) dev_priv 1833 drivers/gpu/drm/i915/i915_drv.c if (suspend_to_idle(dev_priv)) dev_priv 1841 drivers/gpu/drm/i915/i915_drv.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1842 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 1843 drivers/gpu/drm/i915/i915_drv.c struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; dev_priv 1848 drivers/gpu/drm/i915/i915_drv.c i915_gem_suspend_late(dev_priv); dev_priv 1850 drivers/gpu/drm/i915/i915_drv.c i915_rc6_ctx_wa_suspend(dev_priv); dev_priv 1852 drivers/gpu/drm/i915/i915_drv.c intel_uncore_suspend(&dev_priv->uncore); dev_priv 1854 drivers/gpu/drm/i915/i915_drv.c intel_power_domains_suspend(dev_priv, dev_priv 1855 drivers/gpu/drm/i915/i915_drv.c get_suspend_mode(dev_priv, hibernation)); dev_priv 1857 drivers/gpu/drm/i915/i915_drv.c intel_display_power_suspend_late(dev_priv); dev_priv 1859 drivers/gpu/drm/i915/i915_drv.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 1860 drivers/gpu/drm/i915/i915_drv.c ret = vlv_suspend_complete(dev_priv); dev_priv 1864 drivers/gpu/drm/i915/i915_drv.c intel_power_domains_resume(dev_priv); dev_priv 1882 drivers/gpu/drm/i915/i915_drv.c if (!(hibernation && INTEL_GEN(dev_priv) < 6)) dev_priv 1887 drivers/gpu/drm/i915/i915_drv.c if (!dev_priv->uncore.user_forcewake_count) dev_priv 1914 drivers/gpu/drm/i915/i915_drv.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1917 drivers/gpu/drm/i915/i915_drv.c disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 1918 drivers/gpu/drm/i915/i915_drv.c intel_sanitize_gt_powersave(dev_priv); dev_priv 1920 drivers/gpu/drm/i915/i915_drv.c i915_gem_sanitize(dev_priv); dev_priv 1922 drivers/gpu/drm/i915/i915_drv.c ret = i915_ggtt_enable_hw(dev_priv); dev_priv 1926 drivers/gpu/drm/i915/i915_drv.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 1927 drivers/gpu/drm/i915/i915_drv.c i915_gem_restore_gtt_mappings(dev_priv); dev_priv 1928 drivers/gpu/drm/i915/i915_drv.c i915_gem_restore_fences(dev_priv); dev_priv 1929 drivers/gpu/drm/i915/i915_drv.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1931 drivers/gpu/drm/i915/i915_drv.c intel_csr_ucode_resume(dev_priv); dev_priv 1933 drivers/gpu/drm/i915/i915_drv.c i915_restore_state(dev_priv); dev_priv 1934 drivers/gpu/drm/i915/i915_drv.c intel_pps_unlock_regs_wa(dev_priv); dev_priv 1936 drivers/gpu/drm/i915/i915_drv.c intel_init_pch_refclk(dev_priv); dev_priv 1948 drivers/gpu/drm/i915/i915_drv.c intel_runtime_pm_enable_interrupts(dev_priv); dev_priv 1952 drivers/gpu/drm/i915/i915_drv.c i915_gem_resume(dev_priv); dev_priv 1955 drivers/gpu/drm/i915/i915_drv.c intel_init_clock_gating(dev_priv); dev_priv 1957 drivers/gpu/drm/i915/i915_drv.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 1958 drivers/gpu/drm/i915/i915_drv.c if (dev_priv->display.hpd_irq_setup) dev_priv 1959 drivers/gpu/drm/i915/i915_drv.c dev_priv->display.hpd_irq_setup(dev_priv); dev_priv 1960 drivers/gpu/drm/i915/i915_drv.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 1962 drivers/gpu/drm/i915/i915_drv.c intel_dp_mst_resume(dev_priv); dev_priv 1974 drivers/gpu/drm/i915/i915_drv.c intel_hpd_init(dev_priv); dev_priv 1976 drivers/gpu/drm/i915/i915_drv.c intel_opregion_resume(dev_priv); dev_priv 1980 drivers/gpu/drm/i915/i915_drv.c intel_power_domains_enable(dev_priv); dev_priv 1982 drivers/gpu/drm/i915/i915_drv.c enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 1989 drivers/gpu/drm/i915/i915_drv.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 1990 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 2037 drivers/gpu/drm/i915/i915_drv.c disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 2039 drivers/gpu/drm/i915/i915_drv.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 2040 drivers/gpu/drm/i915/i915_drv.c ret = vlv_resume_prepare(dev_priv, false); dev_priv 2045 drivers/gpu/drm/i915/i915_drv.c intel_uncore_resume_early(&dev_priv->uncore); dev_priv 2047 drivers/gpu/drm/i915/i915_drv.c intel_gt_check_and_clear_faults(&dev_priv->gt); dev_priv 2049 drivers/gpu/drm/i915/i915_drv.c intel_display_power_resume_early(dev_priv); dev_priv 2051 drivers/gpu/drm/i915/i915_drv.c intel_sanitize_gt_powersave(dev_priv); dev_priv 2053 drivers/gpu/drm/i915/i915_drv.c intel_power_domains_resume(dev_priv); dev_priv 2055 drivers/gpu/drm/i915/i915_drv.c i915_rc6_ctx_wa_resume(dev_priv); dev_priv 2057 drivers/gpu/drm/i915/i915_drv.c intel_gt_sanitize(&dev_priv->gt, true); dev_priv 2059 drivers/gpu/drm/i915/i915_drv.c enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 2242 drivers/gpu/drm/i915/i915_drv.c static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) dev_priv 2244 drivers/gpu/drm/i915/i915_drv.c struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state; dev_priv 2326 drivers/gpu/drm/i915/i915_drv.c static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) dev_priv 2328 drivers/gpu/drm/i915/i915_drv.c struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state; dev_priv 2440 drivers/gpu/drm/i915/i915_drv.c int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) dev_priv 2454 drivers/gpu/drm/i915/i915_drv.c err = intel_wait_for_register(&dev_priv->uncore, dev_priv 2466 drivers/gpu/drm/i915/i915_drv.c static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) dev_priv 2482 drivers/gpu/drm/i915/i915_drv.c err = vlv_wait_for_pw_status(dev_priv, mask, val); dev_priv 2489 drivers/gpu/drm/i915/i915_drv.c static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, dev_priv 2505 drivers/gpu/drm/i915/i915_drv.c if (vlv_wait_for_pw_status(dev_priv, mask, val)) dev_priv 2510 drivers/gpu/drm/i915/i915_drv.c static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) dev_priv 2519 drivers/gpu/drm/i915/i915_drv.c static int vlv_suspend_complete(struct drm_i915_private *dev_priv) dev_priv 2528 drivers/gpu/drm/i915/i915_drv.c vlv_wait_for_gt_wells(dev_priv, false); dev_priv 2533 drivers/gpu/drm/i915/i915_drv.c vlv_check_no_gt_access(dev_priv); dev_priv 2535 drivers/gpu/drm/i915/i915_drv.c err = vlv_force_gfx_clock(dev_priv, true); dev_priv 2539 drivers/gpu/drm/i915/i915_drv.c err = vlv_allow_gt_wake(dev_priv, false); dev_priv 2543 drivers/gpu/drm/i915/i915_drv.c vlv_save_gunit_s0ix_state(dev_priv); dev_priv 2545 drivers/gpu/drm/i915/i915_drv.c err = vlv_force_gfx_clock(dev_priv, false); dev_priv 2553 drivers/gpu/drm/i915/i915_drv.c vlv_allow_gt_wake(dev_priv, true); dev_priv 2555 drivers/gpu/drm/i915/i915_drv.c vlv_force_gfx_clock(dev_priv, false); dev_priv 2560 drivers/gpu/drm/i915/i915_drv.c static int vlv_resume_prepare(struct drm_i915_private *dev_priv, dev_priv 2571 drivers/gpu/drm/i915/i915_drv.c ret = vlv_force_gfx_clock(dev_priv, true); dev_priv 2573 drivers/gpu/drm/i915/i915_drv.c vlv_restore_gunit_s0ix_state(dev_priv); dev_priv 2575 drivers/gpu/drm/i915/i915_drv.c err = vlv_allow_gt_wake(dev_priv, true); dev_priv 2579 drivers/gpu/drm/i915/i915_drv.c err = vlv_force_gfx_clock(dev_priv, false); dev_priv 2583 drivers/gpu/drm/i915/i915_drv.c vlv_check_no_gt_access(dev_priv); dev_priv 2586 drivers/gpu/drm/i915/i915_drv.c intel_init_clock_gating(dev_priv); dev_priv 2593 drivers/gpu/drm/i915/i915_drv.c struct drm_i915_private *dev_priv = kdev_to_i915(kdev); dev_priv 2594 drivers/gpu/drm/i915/i915_drv.c struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; dev_priv 2597 drivers/gpu/drm/i915/i915_drv.c if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv)))) dev_priv 2600 drivers/gpu/drm/i915/i915_drv.c if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) dev_priv 2611 drivers/gpu/drm/i915/i915_drv.c i915_gem_runtime_suspend(dev_priv); dev_priv 2613 drivers/gpu/drm/i915/i915_drv.c intel_gt_runtime_suspend(&dev_priv->gt); dev_priv 2615 drivers/gpu/drm/i915/i915_drv.c intel_runtime_pm_disable_interrupts(dev_priv); dev_priv 2617 drivers/gpu/drm/i915/i915_drv.c intel_uncore_suspend(&dev_priv->uncore); dev_priv 2619 drivers/gpu/drm/i915/i915_drv.c intel_display_power_suspend(dev_priv); dev_priv 2621 drivers/gpu/drm/i915/i915_drv.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 2622 drivers/gpu/drm/i915/i915_drv.c ret = vlv_suspend_complete(dev_priv); dev_priv 2626 drivers/gpu/drm/i915/i915_drv.c intel_uncore_runtime_resume(&dev_priv->uncore); dev_priv 2628 drivers/gpu/drm/i915/i915_drv.c intel_runtime_pm_enable_interrupts(dev_priv); dev_priv 2630 drivers/gpu/drm/i915/i915_drv.c intel_gt_runtime_resume(&dev_priv->gt); dev_priv 2632 drivers/gpu/drm/i915/i915_drv.c i915_gem_restore_fences(dev_priv); dev_priv 2642 drivers/gpu/drm/i915/i915_drv.c if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) dev_priv 2651 drivers/gpu/drm/i915/i915_drv.c if (IS_BROADWELL(dev_priv)) { dev_priv 2658 drivers/gpu/drm/i915/i915_drv.c intel_opregion_notify_adapter(dev_priv, PCI_D3hot); dev_priv 2667 drivers/gpu/drm/i915/i915_drv.c intel_opregion_notify_adapter(dev_priv, PCI_D1); dev_priv 2670 drivers/gpu/drm/i915/i915_drv.c assert_forcewakes_inactive(&dev_priv->uncore); dev_priv 2672 drivers/gpu/drm/i915/i915_drv.c if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) dev_priv 2673 drivers/gpu/drm/i915/i915_drv.c intel_hpd_poll_init(dev_priv); dev_priv 2681 drivers/gpu/drm/i915/i915_drv.c struct drm_i915_private *dev_priv = kdev_to_i915(kdev); dev_priv 2682 drivers/gpu/drm/i915/i915_drv.c struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; dev_priv 2685 drivers/gpu/drm/i915/i915_drv.c if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv))) dev_priv 2693 drivers/gpu/drm/i915/i915_drv.c intel_opregion_notify_adapter(dev_priv, PCI_D0); dev_priv 2695 drivers/gpu/drm/i915/i915_drv.c if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) dev_priv 2698 drivers/gpu/drm/i915/i915_drv.c intel_display_power_resume(dev_priv); dev_priv 2700 drivers/gpu/drm/i915/i915_drv.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 2701 drivers/gpu/drm/i915/i915_drv.c ret = vlv_resume_prepare(dev_priv, true); dev_priv 2703 drivers/gpu/drm/i915/i915_drv.c intel_uncore_runtime_resume(&dev_priv->uncore); dev_priv 2705 drivers/gpu/drm/i915/i915_drv.c intel_runtime_pm_enable_interrupts(dev_priv); dev_priv 2711 drivers/gpu/drm/i915/i915_drv.c intel_gt_runtime_resume(&dev_priv->gt); dev_priv 2712 drivers/gpu/drm/i915/i915_drv.c i915_gem_restore_fences(dev_priv); dev_priv 2719 drivers/gpu/drm/i915/i915_drv.c if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) dev_priv 2720 drivers/gpu/drm/i915/i915_drv.c intel_hpd_init(dev_priv); dev_priv 2722 drivers/gpu/drm/i915/i915_drv.c intel_enable_ipc(dev_priv); dev_priv 187 drivers/gpu/drm/i915/i915_drv.h struct drm_i915_private *dev_priv; dev_priv 257 drivers/gpu/drm/i915/i915_drv.h void (*get_cdclk)(struct drm_i915_private *dev_priv, dev_priv 259 drivers/gpu/drm/i915/i915_drv.h void (*set_cdclk)(struct drm_i915_private *dev_priv, dev_priv 262 drivers/gpu/drm/i915/i915_drv.h int (*get_fifo_size)(struct drm_i915_private *dev_priv, dev_priv 296 drivers/gpu/drm/i915/i915_drv.h void (*init_clock_gating)(struct drm_i915_private *dev_priv); dev_priv 297 drivers/gpu/drm/i915/i915_drv.h void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); dev_priv 514 drivers/gpu/drm/i915/i915_drv.h struct drm_i915_private *dev_priv; dev_priv 1079 drivers/gpu/drm/i915/i915_drv.h struct drm_i915_private *dev_priv; dev_priv 1219 drivers/gpu/drm/i915/i915_drv.h bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv, dev_priv 1226 drivers/gpu/drm/i915/i915_drv.h bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr); dev_priv 1232 drivers/gpu/drm/i915/i915_drv.h bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr); dev_priv 1835 drivers/gpu/drm/i915/i915_drv.h #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) dev_priv 1836 drivers/gpu/drm/i915/i915_drv.h #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) dev_priv 1837 drivers/gpu/drm/i915/i915_drv.h #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) dev_priv 1839 drivers/gpu/drm/i915/i915_drv.h #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) dev_priv 1840 drivers/gpu/drm/i915/i915_drv.h #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) dev_priv 1843 drivers/gpu/drm/i915/i915_drv.h #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) dev_priv 1851 drivers/gpu/drm/i915/i915_drv.h #define IS_GEN_RANGE(dev_priv, s, e) \ dev_priv 1852 drivers/gpu/drm/i915/i915_drv.h (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e)))) dev_priv 1854 drivers/gpu/drm/i915/i915_drv.h #define IS_GEN(dev_priv, n) \ dev_priv 1856 drivers/gpu/drm/i915/i915_drv.h INTEL_INFO(dev_priv)->gen == (n)) dev_priv 1928 drivers/gpu/drm/i915/i915_drv.h #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) dev_priv 1930 drivers/gpu/drm/i915/i915_drv.h #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) dev_priv 1931 drivers/gpu/drm/i915/i915_drv.h #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) dev_priv 1932 drivers/gpu/drm/i915/i915_drv.h #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) dev_priv 1933 drivers/gpu/drm/i915/i915_drv.h #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) dev_priv 1934 drivers/gpu/drm/i915/i915_drv.h #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) dev_priv 1935 drivers/gpu/drm/i915/i915_drv.h #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) dev_priv 1936 drivers/gpu/drm/i915/i915_drv.h #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) dev_priv 1937 drivers/gpu/drm/i915/i915_drv.h #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) dev_priv 1938 drivers/gpu/drm/i915/i915_drv.h #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) dev_priv 1939 drivers/gpu/drm/i915/i915_drv.h #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) dev_priv 1940 drivers/gpu/drm/i915/i915_drv.h #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) dev_priv 1941 drivers/gpu/drm/i915/i915_drv.h #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) dev_priv 1942 drivers/gpu/drm/i915/i915_drv.h #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) dev_priv 1943 drivers/gpu/drm/i915/i915_drv.h #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) dev_priv 1944 drivers/gpu/drm/i915/i915_drv.h #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) dev_priv 1945 drivers/gpu/drm/i915/i915_drv.h #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) dev_priv 1946 drivers/gpu/drm/i915/i915_drv.h #define IS_IRONLAKE_M(dev_priv) \ dev_priv 1947 drivers/gpu/drm/i915/i915_drv.h (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) dev_priv 1948 drivers/gpu/drm/i915/i915_drv.h #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) dev_priv 1949 drivers/gpu/drm/i915/i915_drv.h #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ dev_priv 1950 drivers/gpu/drm/i915/i915_drv.h INTEL_INFO(dev_priv)->gt == 1) dev_priv 1951 drivers/gpu/drm/i915/i915_drv.h #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) dev_priv 1952 drivers/gpu/drm/i915/i915_drv.h #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) dev_priv 1953 drivers/gpu/drm/i915/i915_drv.h #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) dev_priv 1954 drivers/gpu/drm/i915/i915_drv.h #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) dev_priv 1955 drivers/gpu/drm/i915/i915_drv.h #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) dev_priv 1956 drivers/gpu/drm/i915/i915_drv.h #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) dev_priv 1957 drivers/gpu/drm/i915/i915_drv.h #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) dev_priv 1958 drivers/gpu/drm/i915/i915_drv.h #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) dev_priv 1959 drivers/gpu/drm/i915/i915_drv.h #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) dev_priv 1960 drivers/gpu/drm/i915/i915_drv.h #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) dev_priv 1961 drivers/gpu/drm/i915/i915_drv.h #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) dev_priv 1962 drivers/gpu/drm/i915/i915_drv.h #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) dev_priv 1963 drivers/gpu/drm/i915/i915_drv.h #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) dev_priv 1964 drivers/gpu/drm/i915/i915_drv.h #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ dev_priv 1965 drivers/gpu/drm/i915/i915_drv.h (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) dev_priv 1966 drivers/gpu/drm/i915/i915_drv.h #define IS_BDW_ULT(dev_priv) \ dev_priv 1967 drivers/gpu/drm/i915/i915_drv.h IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) dev_priv 1968 drivers/gpu/drm/i915/i915_drv.h #define IS_BDW_ULX(dev_priv) \ dev_priv 1969 drivers/gpu/drm/i915/i915_drv.h IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) dev_priv 1970 drivers/gpu/drm/i915/i915_drv.h #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ dev_priv 1971 drivers/gpu/drm/i915/i915_drv.h INTEL_INFO(dev_priv)->gt == 3) dev_priv 1972 drivers/gpu/drm/i915/i915_drv.h #define IS_HSW_ULT(dev_priv) \ dev_priv 1973 drivers/gpu/drm/i915/i915_drv.h IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) dev_priv 1974 drivers/gpu/drm/i915/i915_drv.h #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ dev_priv 1975 drivers/gpu/drm/i915/i915_drv.h INTEL_INFO(dev_priv)->gt == 3) dev_priv 1976 drivers/gpu/drm/i915/i915_drv.h #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ dev_priv 1977 drivers/gpu/drm/i915/i915_drv.h INTEL_INFO(dev_priv)->gt == 1) dev_priv 1979 drivers/gpu/drm/i915/i915_drv.h #define IS_HSW_ULX(dev_priv) \ dev_priv 1980 drivers/gpu/drm/i915/i915_drv.h IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) dev_priv 1981 drivers/gpu/drm/i915/i915_drv.h #define IS_SKL_ULT(dev_priv) \ dev_priv 1982 drivers/gpu/drm/i915/i915_drv.h IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) dev_priv 1983 drivers/gpu/drm/i915/i915_drv.h #define IS_SKL_ULX(dev_priv) \ dev_priv 1984 drivers/gpu/drm/i915/i915_drv.h IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) dev_priv 1985 drivers/gpu/drm/i915/i915_drv.h #define IS_KBL_ULT(dev_priv) \ dev_priv 1986 drivers/gpu/drm/i915/i915_drv.h IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) dev_priv 1987 drivers/gpu/drm/i915/i915_drv.h #define IS_KBL_ULX(dev_priv) \ dev_priv 1988 drivers/gpu/drm/i915/i915_drv.h IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) dev_priv 1989 drivers/gpu/drm/i915/i915_drv.h #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ dev_priv 1990 drivers/gpu/drm/i915/i915_drv.h INTEL_INFO(dev_priv)->gt == 2) dev_priv 1991 drivers/gpu/drm/i915/i915_drv.h #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ dev_priv 1992 drivers/gpu/drm/i915/i915_drv.h INTEL_INFO(dev_priv)->gt == 3) dev_priv 1993 drivers/gpu/drm/i915/i915_drv.h #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ dev_priv 1994 drivers/gpu/drm/i915/i915_drv.h INTEL_INFO(dev_priv)->gt == 4) dev_priv 1995 drivers/gpu/drm/i915/i915_drv.h #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ dev_priv 1996 drivers/gpu/drm/i915/i915_drv.h INTEL_INFO(dev_priv)->gt == 2) dev_priv 1997 drivers/gpu/drm/i915/i915_drv.h #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ dev_priv 1998 drivers/gpu/drm/i915/i915_drv.h INTEL_INFO(dev_priv)->gt == 3) dev_priv 1999 drivers/gpu/drm/i915/i915_drv.h #define IS_CFL_ULT(dev_priv) \ dev_priv 2000 drivers/gpu/drm/i915/i915_drv.h IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) dev_priv 2001 drivers/gpu/drm/i915/i915_drv.h #define IS_CFL_ULX(dev_priv) \ dev_priv 2002 drivers/gpu/drm/i915/i915_drv.h IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) dev_priv 2003 drivers/gpu/drm/i915/i915_drv.h #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ dev_priv 2004 drivers/gpu/drm/i915/i915_drv.h INTEL_INFO(dev_priv)->gt == 2) dev_priv 2005 drivers/gpu/drm/i915/i915_drv.h #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ dev_priv 2006 drivers/gpu/drm/i915/i915_drv.h INTEL_INFO(dev_priv)->gt == 3) dev_priv 2007 drivers/gpu/drm/i915/i915_drv.h #define IS_CNL_WITH_PORT_F(dev_priv) \ dev_priv 2008 drivers/gpu/drm/i915/i915_drv.h IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) dev_priv 2009 drivers/gpu/drm/i915/i915_drv.h #define IS_ICL_WITH_PORT_F(dev_priv) \ dev_priv 2010 drivers/gpu/drm/i915/i915_drv.h IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) dev_priv 2029 drivers/gpu/drm/i915/i915_drv.h #define IS_BXT_REVID(dev_priv, since, until) \ dev_priv 2030 drivers/gpu/drm/i915/i915_drv.h (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) dev_priv 2038 drivers/gpu/drm/i915/i915_drv.h #define IS_KBL_REVID(dev_priv, since, until) \ dev_priv 2039 drivers/gpu/drm/i915/i915_drv.h (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) dev_priv 2044 drivers/gpu/drm/i915/i915_drv.h #define IS_GLK_REVID(dev_priv, since, until) \ dev_priv 2045 drivers/gpu/drm/i915/i915_drv.h (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) dev_priv 2063 drivers/gpu/drm/i915/i915_drv.h #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) dev_priv 2064 drivers/gpu/drm/i915/i915_drv.h #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) dev_priv 2065 drivers/gpu/drm/i915/i915_drv.h #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) dev_priv 2067 drivers/gpu/drm/i915/i915_drv.h #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) dev_priv 2069 drivers/gpu/drm/i915/i915_drv.h #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \ dev_priv 2072 drivers/gpu/drm/i915/i915_drv.h (INTEL_INFO(dev_priv)->engine_mask & \ dev_priv 2075 drivers/gpu/drm/i915/i915_drv.h #define VDBOX_MASK(dev_priv) \ dev_priv 2076 drivers/gpu/drm/i915/i915_drv.h ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS) dev_priv 2077 drivers/gpu/drm/i915/i915_drv.h #define VEBOX_MASK(dev_priv) \ dev_priv 2078 drivers/gpu/drm/i915/i915_drv.h ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS) dev_priv 2084 drivers/gpu/drm/i915/i915_drv.h #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7) dev_priv 2086 drivers/gpu/drm/i915/i915_drv.h #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) dev_priv 2087 drivers/gpu/drm/i915/i915_drv.h #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) dev_priv 2088 drivers/gpu/drm/i915/i915_drv.h #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) dev_priv 2089 drivers/gpu/drm/i915/i915_drv.h #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6) dev_priv 2090 drivers/gpu/drm/i915/i915_drv.h #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ dev_priv 2091 drivers/gpu/drm/i915/i915_drv.h IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) dev_priv 2093 drivers/gpu/drm/i915/i915_drv.h #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) dev_priv 2095 drivers/gpu/drm/i915/i915_drv.h #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ dev_priv 2096 drivers/gpu/drm/i915/i915_drv.h (INTEL_INFO(dev_priv)->has_logical_ring_contexts) dev_priv 2097 drivers/gpu/drm/i915/i915_drv.h #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ dev_priv 2098 drivers/gpu/drm/i915/i915_drv.h (INTEL_INFO(dev_priv)->has_logical_ring_elsq) dev_priv 2099 drivers/gpu/drm/i915/i915_drv.h #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ dev_priv 2100 drivers/gpu/drm/i915/i915_drv.h (INTEL_INFO(dev_priv)->has_logical_ring_preemption) dev_priv 2102 drivers/gpu/drm/i915/i915_drv.h #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) dev_priv 2104 drivers/gpu/drm/i915/i915_drv.h #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) dev_priv 2105 drivers/gpu/drm/i915/i915_drv.h #define HAS_PPGTT(dev_priv) \ dev_priv 2106 drivers/gpu/drm/i915/i915_drv.h (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) dev_priv 2107 drivers/gpu/drm/i915/i915_drv.h #define HAS_FULL_PPGTT(dev_priv) \ dev_priv 2108 drivers/gpu/drm/i915/i915_drv.h (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) dev_priv 2110 drivers/gpu/drm/i915/i915_drv.h #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ dev_priv 2112 drivers/gpu/drm/i915/i915_drv.h ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ dev_priv 2115 drivers/gpu/drm/i915/i915_drv.h #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) dev_priv 2116 drivers/gpu/drm/i915/i915_drv.h #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ dev_priv 2117 drivers/gpu/drm/i915/i915_drv.h (INTEL_INFO(dev_priv)->display.overlay_needs_physical) dev_priv 2120 drivers/gpu/drm/i915/i915_drv.h #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) dev_priv 2122 drivers/gpu/drm/i915/i915_drv.h #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ dev_priv 2123 drivers/gpu/drm/i915/i915_drv.h (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9)) dev_priv 2126 drivers/gpu/drm/i915/i915_drv.h #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ dev_priv 2127 drivers/gpu/drm/i915/i915_drv.h (IS_CANNONLAKE(dev_priv) || IS_GEN(dev_priv, 9)) dev_priv 2129 drivers/gpu/drm/i915/i915_drv.h #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) dev_priv 2130 drivers/gpu/drm/i915/i915_drv.h #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ dev_priv 2131 drivers/gpu/drm/i915/i915_drv.h IS_GEMINILAKE(dev_priv) || \ dev_priv 2132 drivers/gpu/drm/i915/i915_drv.h IS_KABYLAKE(dev_priv)) dev_priv 2137 drivers/gpu/drm/i915/i915_drv.h #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ dev_priv 2138 drivers/gpu/drm/i915/i915_drv.h !(IS_I915G(dev_priv) || \ dev_priv 2139 drivers/gpu/drm/i915/i915_drv.h IS_I915GM(dev_priv))) dev_priv 2140 drivers/gpu/drm/i915/i915_drv.h #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) dev_priv 2141 drivers/gpu/drm/i915/i915_drv.h #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) dev_priv 2143 drivers/gpu/drm/i915/i915_drv.h #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) dev_priv 2144 drivers/gpu/drm/i915/i915_drv.h #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) dev_priv 2145 drivers/gpu/drm/i915/i915_drv.h #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) dev_priv 2147 drivers/gpu/drm/i915/i915_drv.h #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 2149 drivers/gpu/drm/i915/i915_drv.h #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) dev_priv 2151 drivers/gpu/drm/i915/i915_drv.h #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) dev_priv 2152 drivers/gpu/drm/i915/i915_drv.h #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) dev_priv 2153 drivers/gpu/drm/i915/i915_drv.h #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) dev_priv 2154 drivers/gpu/drm/i915/i915_drv.h #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0) dev_priv 2156 drivers/gpu/drm/i915/i915_drv.h #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) dev_priv 2157 drivers/gpu/drm/i915/i915_drv.h #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) dev_priv 2158 drivers/gpu/drm/i915/i915_drv.h #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ dev_priv 2160 drivers/gpu/drm/i915/i915_drv.h #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) dev_priv 2162 drivers/gpu/drm/i915/i915_drv.h #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) dev_priv 2164 drivers/gpu/drm/i915/i915_drv.h #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) dev_priv 2165 drivers/gpu/drm/i915/i915_drv.h #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) dev_priv 2167 drivers/gpu/drm/i915/i915_drv.h #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) dev_priv 2169 drivers/gpu/drm/i915/i915_drv.h #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) dev_priv 2172 drivers/gpu/drm/i915/i915_drv.h #define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc) dev_priv 2173 drivers/gpu/drm/i915/i915_drv.h #define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc) dev_priv 2175 drivers/gpu/drm/i915/i915_drv.h #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) dev_priv 2177 drivers/gpu/drm/i915/i915_drv.h #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) dev_priv 2180 drivers/gpu/drm/i915/i915_drv.h #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) dev_priv 2182 drivers/gpu/drm/i915/i915_drv.h #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) dev_priv 2185 drivers/gpu/drm/i915/i915_drv.h #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) dev_priv 2186 drivers/gpu/drm/i915/i915_drv.h #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ dev_priv 2187 drivers/gpu/drm/i915/i915_drv.h 2 : HAS_L3_DPF(dev_priv)) dev_priv 2192 drivers/gpu/drm/i915/i915_drv.h #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0) dev_priv 2203 drivers/gpu/drm/i915/i915_drv.h static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) dev_priv 2205 drivers/gpu/drm/i915/i915_drv.h return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); dev_priv 2209 drivers/gpu/drm/i915/i915_drv.h intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) dev_priv 2211 drivers/gpu/drm/i915/i915_drv.h return IS_BROXTON(dev_priv) && intel_vtd_active(); dev_priv 2226 drivers/gpu/drm/i915/i915_drv.h int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); dev_priv 2228 drivers/gpu/drm/i915/i915_drv.h static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) dev_priv 2230 drivers/gpu/drm/i915/i915_drv.h return dev_priv->gvt; dev_priv 2233 drivers/gpu/drm/i915/i915_drv.h static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) dev_priv 2235 drivers/gpu/drm/i915/i915_drv.h return dev_priv->vgpu.active; dev_priv 2242 drivers/gpu/drm/i915/i915_drv.h int i915_gem_init_userptr(struct drm_i915_private *dev_priv); dev_priv 2243 drivers/gpu/drm/i915/i915_drv.h void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); dev_priv 2245 drivers/gpu/drm/i915/i915_drv.h int i915_gem_init_early(struct drm_i915_private *dev_priv); dev_priv 2246 drivers/gpu/drm/i915/i915_drv.h void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); dev_priv 2247 drivers/gpu/drm/i915/i915_drv.h int i915_gem_freeze(struct drm_i915_private *dev_priv); dev_priv 2248 drivers/gpu/drm/i915/i915_drv.h int i915_gem_freeze_late(struct drm_i915_private *dev_priv); dev_priv 2306 drivers/gpu/drm/i915/i915_drv.h void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); dev_priv 2335 drivers/gpu/drm/i915/i915_drv.h int __must_check i915_gem_init(struct drm_i915_private *dev_priv); dev_priv 2336 drivers/gpu/drm/i915/i915_drv.h int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv); dev_priv 2339 drivers/gpu/drm/i915/i915_drv.h void i915_gem_driver_remove(struct drm_i915_private *dev_priv); dev_priv 2340 drivers/gpu/drm/i915/i915_drv.h void i915_gem_driver_release(struct drm_i915_private *dev_priv); dev_priv 2341 drivers/gpu/drm/i915/i915_drv.h int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, dev_priv 2343 drivers/gpu/drm/i915/i915_drv.h void i915_gem_suspend(struct drm_i915_private *dev_priv); dev_priv 2344 drivers/gpu/drm/i915/i915_drv.h void i915_gem_suspend_late(struct drm_i915_private *dev_priv); dev_priv 2345 drivers/gpu/drm/i915/i915_drv.h void i915_gem_resume(struct drm_i915_private *dev_priv); dev_priv 2392 drivers/gpu/drm/i915/i915_drv.h i915_gem_object_create_internal(struct drm_i915_private *dev_priv, dev_priv 2398 drivers/gpu/drm/i915/i915_drv.h struct drm_i915_private *dev_priv = to_i915(obj->base.dev); dev_priv 2400 drivers/gpu/drm/i915/i915_drv.h return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && dev_priv 2404 drivers/gpu/drm/i915/i915_drv.h u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, dev_priv 2406 drivers/gpu/drm/i915/i915_drv.h u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, dev_priv 2412 drivers/gpu/drm/i915/i915_drv.h int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); dev_priv 2426 drivers/gpu/drm/i915/i915_drv.h mkwrite_device_info(struct drm_i915_private *dev_priv) dev_priv 2428 drivers/gpu/drm/i915/i915_drv.h return (struct intel_device_info *)INTEL_INFO(dev_priv); dev_priv 2437 drivers/gpu/drm/i915/i915_drv.h #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__)) dev_priv 2438 drivers/gpu/drm/i915/i915_drv.h #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__)) dev_priv 2440 drivers/gpu/drm/i915/i915_drv.h #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__)) dev_priv 2468 drivers/gpu/drm/i915/i915_drv.h #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) dev_priv 2469 drivers/gpu/drm/i915/i915_drv.h #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) dev_priv 160 drivers/gpu/drm/i915/i915_gem.c struct drm_i915_private *dev_priv, dev_priv 174 drivers/gpu/drm/i915/i915_gem.c obj = i915_gem_object_create_shmem(dev_priv, size); dev_priv 234 drivers/gpu/drm/i915/i915_gem.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 237 drivers/gpu/drm/i915/i915_gem.c i915_gem_flush_free_objects(dev_priv); dev_priv 239 drivers/gpu/drm/i915/i915_gem.c return i915_gem_create(file, dev_priv, dev_priv 965 drivers/gpu/drm/i915/i915_gem.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); dev_priv 966 drivers/gpu/drm/i915/i915_gem.c struct i915_address_space *vm = &dev_priv->ggtt.vm; dev_priv 980 drivers/gpu/drm/i915/i915_gem.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); dev_priv 998 drivers/gpu/drm/i915/i915_gem.c if (obj->base.size > dev_priv->ggtt.mappable_end) dev_priv 1017 drivers/gpu/drm/i915/i915_gem.c obj->base.size > dev_priv->ggtt.mappable_end / 2) dev_priv 1031 drivers/gpu/drm/i915/i915_gem.c vma->fence_size > dev_priv->ggtt.mappable_end / 2) dev_priv 1423 drivers/gpu/drm/i915/i915_gem.c int i915_gem_init(struct drm_i915_private *dev_priv) dev_priv 1428 drivers/gpu/drm/i915/i915_gem.c if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv)) dev_priv 1429 drivers/gpu/drm/i915/i915_gem.c mkwrite_device_info(dev_priv)->page_sizes = dev_priv 1432 drivers/gpu/drm/i915/i915_gem.c intel_timelines_init(dev_priv); dev_priv 1434 drivers/gpu/drm/i915/i915_gem.c ret = i915_gem_init_userptr(dev_priv); dev_priv 1438 drivers/gpu/drm/i915/i915_gem.c intel_uc_fetch_firmwares(&dev_priv->gt.uc); dev_priv 1439 drivers/gpu/drm/i915/i915_gem.c intel_wopcm_init(&dev_priv->wopcm); dev_priv 1447 drivers/gpu/drm/i915/i915_gem.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 1448 drivers/gpu/drm/i915/i915_gem.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 1450 drivers/gpu/drm/i915/i915_gem.c ret = i915_init_ggtt(dev_priv); dev_priv 1456 drivers/gpu/drm/i915/i915_gem.c ret = i915_gem_init_scratch(dev_priv, dev_priv 1457 drivers/gpu/drm/i915/i915_gem.c IS_GEN(dev_priv, 2) ? SZ_256K : PAGE_SIZE); dev_priv 1463 drivers/gpu/drm/i915/i915_gem.c ret = intel_engines_setup(dev_priv); dev_priv 1469 drivers/gpu/drm/i915/i915_gem.c ret = i915_gem_contexts_init(dev_priv); dev_priv 1475 drivers/gpu/drm/i915/i915_gem.c ret = intel_engines_init(dev_priv); dev_priv 1481 drivers/gpu/drm/i915/i915_gem.c intel_init_gt_powersave(dev_priv); dev_priv 1483 drivers/gpu/drm/i915/i915_gem.c intel_uc_init(&dev_priv->gt.uc); dev_priv 1485 drivers/gpu/drm/i915/i915_gem.c ret = i915_gem_init_hw(dev_priv); dev_priv 1490 drivers/gpu/drm/i915/i915_gem.c ret = intel_gt_resume(&dev_priv->gt); dev_priv 1503 drivers/gpu/drm/i915/i915_gem.c intel_init_clock_gating(dev_priv); dev_priv 1505 drivers/gpu/drm/i915/i915_gem.c ret = intel_engines_verify_workarounds(dev_priv); dev_priv 1509 drivers/gpu/drm/i915/i915_gem.c ret = __intel_engines_record_defaults(dev_priv); dev_priv 1513 drivers/gpu/drm/i915/i915_gem.c ret = i915_inject_load_error(dev_priv, -ENODEV); dev_priv 1517 drivers/gpu/drm/i915/i915_gem.c ret = i915_inject_load_error(dev_priv, -EIO); dev_priv 1521 drivers/gpu/drm/i915/i915_gem.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 1522 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1533 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1535 drivers/gpu/drm/i915/i915_gem.c intel_gt_set_wedged(&dev_priv->gt); dev_priv 1536 drivers/gpu/drm/i915/i915_gem.c i915_gem_suspend(dev_priv); dev_priv 1537 drivers/gpu/drm/i915/i915_gem.c i915_gem_suspend_late(dev_priv); dev_priv 1539 drivers/gpu/drm/i915/i915_gem.c i915_gem_drain_workqueue(dev_priv); dev_priv 1541 drivers/gpu/drm/i915/i915_gem.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 1543 drivers/gpu/drm/i915/i915_gem.c intel_uc_fini_hw(&dev_priv->gt.uc); dev_priv 1546 drivers/gpu/drm/i915/i915_gem.c intel_uc_fini(&dev_priv->gt.uc); dev_priv 1547 drivers/gpu/drm/i915/i915_gem.c intel_cleanup_gt_powersave(dev_priv); dev_priv 1548 drivers/gpu/drm/i915/i915_gem.c intel_engines_cleanup(dev_priv); dev_priv 1552 drivers/gpu/drm/i915/i915_gem.c i915_gem_contexts_fini(dev_priv); dev_priv 1554 drivers/gpu/drm/i915/i915_gem.c i915_gem_fini_scratch(dev_priv); dev_priv 1557 drivers/gpu/drm/i915/i915_gem.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 1558 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1561 drivers/gpu/drm/i915/i915_gem.c intel_uc_cleanup_firmwares(&dev_priv->gt.uc); dev_priv 1562 drivers/gpu/drm/i915/i915_gem.c i915_gem_cleanup_userptr(dev_priv); dev_priv 1563 drivers/gpu/drm/i915/i915_gem.c intel_timelines_fini(dev_priv); dev_priv 1567 drivers/gpu/drm/i915/i915_gem.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 1574 drivers/gpu/drm/i915/i915_gem.c if (!intel_gt_is_wedged(&dev_priv->gt)) { dev_priv 1575 drivers/gpu/drm/i915/i915_gem.c i915_probe_error(dev_priv, dev_priv 1577 drivers/gpu/drm/i915/i915_gem.c intel_gt_set_wedged(&dev_priv->gt); dev_priv 1581 drivers/gpu/drm/i915/i915_gem.c ret = i915_ggtt_enable_hw(dev_priv); dev_priv 1582 drivers/gpu/drm/i915/i915_gem.c i915_gem_restore_gtt_mappings(dev_priv); dev_priv 1583 drivers/gpu/drm/i915/i915_gem.c i915_gem_restore_fences(dev_priv); dev_priv 1584 drivers/gpu/drm/i915/i915_gem.c intel_init_clock_gating(dev_priv); dev_priv 1586 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1589 drivers/gpu/drm/i915/i915_gem.c i915_gem_drain_freed_objects(dev_priv); dev_priv 1605 drivers/gpu/drm/i915/i915_gem.c void i915_gem_driver_remove(struct drm_i915_private *dev_priv) dev_priv 1607 drivers/gpu/drm/i915/i915_gem.c GEM_BUG_ON(dev_priv->gt.awake); dev_priv 1609 drivers/gpu/drm/i915/i915_gem.c intel_wakeref_auto_fini(&dev_priv->ggtt.userfault_wakeref); dev_priv 1611 drivers/gpu/drm/i915/i915_gem.c i915_gem_suspend_late(dev_priv); dev_priv 1612 drivers/gpu/drm/i915/i915_gem.c intel_disable_gt_powersave(dev_priv); dev_priv 1615 drivers/gpu/drm/i915/i915_gem.c i915_gem_drain_workqueue(dev_priv); dev_priv 1617 drivers/gpu/drm/i915/i915_gem.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 1618 drivers/gpu/drm/i915/i915_gem.c intel_uc_fini_hw(&dev_priv->gt.uc); dev_priv 1619 drivers/gpu/drm/i915/i915_gem.c intel_uc_fini(&dev_priv->gt.uc); dev_priv 1620 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1622 drivers/gpu/drm/i915/i915_gem.c i915_gem_drain_freed_objects(dev_priv); dev_priv 1625 drivers/gpu/drm/i915/i915_gem.c void i915_gem_driver_release(struct drm_i915_private *dev_priv) dev_priv 1627 drivers/gpu/drm/i915/i915_gem.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 1628 drivers/gpu/drm/i915/i915_gem.c intel_engines_cleanup(dev_priv); dev_priv 1629 drivers/gpu/drm/i915/i915_gem.c i915_gem_contexts_fini(dev_priv); dev_priv 1630 drivers/gpu/drm/i915/i915_gem.c i915_gem_fini_scratch(dev_priv); dev_priv 1631 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1633 drivers/gpu/drm/i915/i915_gem.c intel_wa_list_free(&dev_priv->gt_wa_list); dev_priv 1635 drivers/gpu/drm/i915/i915_gem.c intel_cleanup_gt_powersave(dev_priv); dev_priv 1637 drivers/gpu/drm/i915/i915_gem.c intel_uc_cleanup_firmwares(&dev_priv->gt.uc); dev_priv 1638 drivers/gpu/drm/i915/i915_gem.c i915_gem_cleanup_userptr(dev_priv); dev_priv 1639 drivers/gpu/drm/i915/i915_gem.c intel_timelines_fini(dev_priv); dev_priv 1641 drivers/gpu/drm/i915/i915_gem.c i915_gem_drain_freed_objects(dev_priv); dev_priv 1643 drivers/gpu/drm/i915/i915_gem.c WARN_ON(!list_empty(&dev_priv->contexts.list)); dev_priv 1663 drivers/gpu/drm/i915/i915_gem.c int i915_gem_init_early(struct drm_i915_private *dev_priv) dev_priv 1667 drivers/gpu/drm/i915/i915_gem.c i915_gem_init__mm(dev_priv); dev_priv 1668 drivers/gpu/drm/i915/i915_gem.c i915_gem_init__pm(dev_priv); dev_priv 1670 drivers/gpu/drm/i915/i915_gem.c spin_lock_init(&dev_priv->fb_tracking.lock); dev_priv 1672 drivers/gpu/drm/i915/i915_gem.c err = i915_gemfs_init(dev_priv); dev_priv 1679 drivers/gpu/drm/i915/i915_gem.c void i915_gem_cleanup_early(struct drm_i915_private *dev_priv) dev_priv 1681 drivers/gpu/drm/i915/i915_gem.c i915_gem_drain_freed_objects(dev_priv); dev_priv 1682 drivers/gpu/drm/i915/i915_gem.c GEM_BUG_ON(!llist_empty(&dev_priv->mm.free_list)); dev_priv 1683 drivers/gpu/drm/i915/i915_gem.c GEM_BUG_ON(atomic_read(&dev_priv->mm.free_count)); dev_priv 1684 drivers/gpu/drm/i915/i915_gem.c WARN_ON(dev_priv->mm.shrink_count); dev_priv 1686 drivers/gpu/drm/i915/i915_gem.c i915_gemfs_fini(dev_priv); dev_priv 1689 drivers/gpu/drm/i915/i915_gem.c int i915_gem_freeze(struct drm_i915_private *dev_priv) dev_priv 1694 drivers/gpu/drm/i915/i915_gem.c i915_gem_shrink_all(dev_priv); dev_priv 1762 drivers/gpu/drm/i915/i915_gem.c file_priv->dev_priv = i915; dev_priv 98 drivers/gpu/drm/i915/i915_gem_evict.c struct drm_i915_private *dev_priv = vm->i915; dev_priv 137 drivers/gpu/drm/i915/i915_gem_evict.c i915_retire_requests(dev_priv); dev_priv 210 drivers/gpu/drm/i915/i915_gem_evict.c ret = ggtt_flush(dev_priv); dev_priv 832 drivers/gpu/drm/i915/i915_gem_gtt.c struct drm_i915_private *dev_priv = ppgtt->vm.i915; dev_priv 841 drivers/gpu/drm/i915/i915_gem_gtt.c mutex_lock(&dev_priv->vgpu.lock); dev_priv 866 drivers/gpu/drm/i915/i915_gem_gtt.c mutex_unlock(&dev_priv->vgpu.lock); dev_priv 2113 drivers/gpu/drm/i915/i915_gem_gtt.c static bool needs_idle_maps(struct drm_i915_private *dev_priv) dev_priv 2118 drivers/gpu/drm/i915/i915_gem_gtt.c return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active(); dev_priv 2286 drivers/gpu/drm/i915/i915_gem_gtt.c struct drm_i915_private *dev_priv = vm->i915; dev_priv 2530 drivers/gpu/drm/i915/i915_gem_gtt.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); dev_priv 2531 drivers/gpu/drm/i915/i915_gem_gtt.c struct device *kdev = &dev_priv->drm.pdev->dev; dev_priv 2532 drivers/gpu/drm/i915/i915_gem_gtt.c struct i915_ggtt *ggtt = &dev_priv->ggtt; dev_priv 2535 drivers/gpu/drm/i915/i915_gem_gtt.c if (i915_gem_wait_for_idle(dev_priv, 0, MAX_SCHEDULE_TIMEOUT)) { dev_priv 2839 drivers/gpu/drm/i915/i915_gem_gtt.c struct drm_i915_private *dev_priv = ggtt->vm.i915; dev_priv 2840 drivers/gpu/drm/i915/i915_gem_gtt.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 2854 drivers/gpu/drm/i915/i915_gem_gtt.c if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) dev_priv 2878 drivers/gpu/drm/i915/i915_gem_gtt.c static void tgl_setup_private_ppat(struct drm_i915_private *dev_priv) dev_priv 2891 drivers/gpu/drm/i915/i915_gem_gtt.c static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv) dev_priv 2906 drivers/gpu/drm/i915/i915_gem_gtt.c static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) dev_priv 2923 drivers/gpu/drm/i915/i915_gem_gtt.c static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) dev_priv 2967 drivers/gpu/drm/i915/i915_gem_gtt.c static void setup_private_pat(struct drm_i915_private *dev_priv) dev_priv 2969 drivers/gpu/drm/i915/i915_gem_gtt.c GEM_BUG_ON(INTEL_GEN(dev_priv) < 8); dev_priv 2971 drivers/gpu/drm/i915/i915_gem_gtt.c if (INTEL_GEN(dev_priv) >= 12) dev_priv 2972 drivers/gpu/drm/i915/i915_gem_gtt.c tgl_setup_private_ppat(dev_priv); dev_priv 2973 drivers/gpu/drm/i915/i915_gem_gtt.c else if (INTEL_GEN(dev_priv) >= 10) dev_priv 2974 drivers/gpu/drm/i915/i915_gem_gtt.c cnl_setup_private_ppat(dev_priv); dev_priv 2975 drivers/gpu/drm/i915/i915_gem_gtt.c else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) dev_priv 2976 drivers/gpu/drm/i915/i915_gem_gtt.c chv_setup_private_ppat(dev_priv); dev_priv 2978 drivers/gpu/drm/i915/i915_gem_gtt.c bdw_setup_private_ppat(dev_priv); dev_priv 2983 drivers/gpu/drm/i915/i915_gem_gtt.c struct drm_i915_private *dev_priv = ggtt->vm.i915; dev_priv 2984 drivers/gpu/drm/i915/i915_gem_gtt.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 3002 drivers/gpu/drm/i915/i915_gem_gtt.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 3011 drivers/gpu/drm/i915/i915_gem_gtt.c if (intel_scanout_needs_vtd_wa(dev_priv)) dev_priv 3017 drivers/gpu/drm/i915/i915_gem_gtt.c if (intel_ggtt_update_needs_vtd_wa(dev_priv) || dev_priv 3018 drivers/gpu/drm/i915/i915_gem_gtt.c IS_CHERRYVIEW(dev_priv) /* fails with concurrent use/update */) { dev_priv 3034 drivers/gpu/drm/i915/i915_gem_gtt.c setup_private_pat(dev_priv); dev_priv 3041 drivers/gpu/drm/i915/i915_gem_gtt.c struct drm_i915_private *dev_priv = ggtt->vm.i915; dev_priv 3042 drivers/gpu/drm/i915/i915_gem_gtt.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 3071 drivers/gpu/drm/i915/i915_gem_gtt.c if (!HAS_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) dev_priv 3079 drivers/gpu/drm/i915/i915_gem_gtt.c if (HAS_EDRAM(dev_priv)) dev_priv 3081 drivers/gpu/drm/i915/i915_gem_gtt.c else if (IS_HASWELL(dev_priv)) dev_priv 3083 drivers/gpu/drm/i915/i915_gem_gtt.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 3085 drivers/gpu/drm/i915/i915_gem_gtt.c else if (INTEL_GEN(dev_priv) >= 7) dev_priv 3105 drivers/gpu/drm/i915/i915_gem_gtt.c struct drm_i915_private *dev_priv = ggtt->vm.i915; dev_priv 3109 drivers/gpu/drm/i915/i915_gem_gtt.c ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); dev_priv 3121 drivers/gpu/drm/i915/i915_gem_gtt.c ggtt->do_idle_maps = needs_idle_maps(dev_priv); dev_priv 3135 drivers/gpu/drm/i915/i915_gem_gtt.c dev_notice(dev_priv->drm.dev, dev_priv 3241 drivers/gpu/drm/i915/i915_gem_gtt.c int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) dev_priv 3245 drivers/gpu/drm/i915/i915_gem_gtt.c stash_init(&dev_priv->mm.wc_stash); dev_priv 3252 drivers/gpu/drm/i915/i915_gem_gtt.c ret = ggtt_init_hw(&dev_priv->ggtt); dev_priv 3260 drivers/gpu/drm/i915/i915_gem_gtt.c ret = i915_gem_init_stolen(dev_priv); dev_priv 3267 drivers/gpu/drm/i915/i915_gem_gtt.c dev_priv->ggtt.vm.cleanup(&dev_priv->ggtt.vm); dev_priv 3271 drivers/gpu/drm/i915/i915_gem_gtt.c int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) dev_priv 3273 drivers/gpu/drm/i915/i915_gem_gtt.c if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) dev_priv 554 drivers/gpu/drm/i915/i915_gem_gtt.h int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); dev_priv 555 drivers/gpu/drm/i915/i915_gem_gtt.h int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); dev_priv 556 drivers/gpu/drm/i915/i915_gem_gtt.h int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); dev_priv 559 drivers/gpu/drm/i915/i915_gem_gtt.h int i915_init_ggtt(struct drm_i915_private *dev_priv); dev_priv 560 drivers/gpu/drm/i915/i915_gem_gtt.h void i915_ggtt_driver_release(struct drm_i915_private *dev_priv); dev_priv 564 drivers/gpu/drm/i915/i915_gem_gtt.h struct i915_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv); dev_priv 584 drivers/gpu/drm/i915/i915_gem_gtt.h void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); dev_priv 585 drivers/gpu/drm/i915/i915_gem_gtt.h void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); dev_priv 1040 drivers/gpu/drm/i915/i915_gpu_error.c struct drm_i915_private *dev_priv = error->i915; dev_priv 1041 drivers/gpu/drm/i915/i915_gpu_error.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 1044 drivers/gpu/drm/i915/i915_gpu_error.c if (INTEL_GEN(dev_priv) >= 6) { dev_priv 1045 drivers/gpu/drm/i915/i915_gpu_error.c for (i = 0; i < dev_priv->ggtt.num_fences; i++) dev_priv 1049 drivers/gpu/drm/i915/i915_gpu_error.c } else if (INTEL_GEN(dev_priv) >= 4) { dev_priv 1050 drivers/gpu/drm/i915/i915_gpu_error.c for (i = 0; i < dev_priv->ggtt.num_fences; i++) dev_priv 1055 drivers/gpu/drm/i915/i915_gpu_error.c for (i = 0; i < dev_priv->ggtt.num_fences; i++) dev_priv 1066 drivers/gpu/drm/i915/i915_gpu_error.c struct drm_i915_private *dev_priv = engine->i915; dev_priv 1068 drivers/gpu/drm/i915/i915_gpu_error.c if (INTEL_GEN(dev_priv) >= 6) { dev_priv 1071 drivers/gpu/drm/i915/i915_gpu_error.c if (INTEL_GEN(dev_priv) >= 12) dev_priv 1073 drivers/gpu/drm/i915/i915_gpu_error.c else if (INTEL_GEN(dev_priv) >= 8) dev_priv 1079 drivers/gpu/drm/i915/i915_gpu_error.c if (INTEL_GEN(dev_priv) >= 4) { dev_priv 1085 drivers/gpu/drm/i915/i915_gpu_error.c if (INTEL_GEN(dev_priv) >= 8) { dev_priv 1104 drivers/gpu/drm/i915/i915_gpu_error.c if (INTEL_GEN(dev_priv) > 2) dev_priv 1107 drivers/gpu/drm/i915/i915_gpu_error.c if (!HWS_NEEDS_PHYSICAL(dev_priv)) { dev_priv 1110 drivers/gpu/drm/i915/i915_gpu_error.c if (IS_GEN(dev_priv, 7)) { dev_priv 1141 drivers/gpu/drm/i915/i915_gpu_error.c ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error, dev_priv 1144 drivers/gpu/drm/i915/i915_gpu_error.c if (HAS_PPGTT(dev_priv)) { dev_priv 1149 drivers/gpu/drm/i915/i915_gpu_error.c if (IS_GEN(dev_priv, 6)) { dev_priv 1152 drivers/gpu/drm/i915/i915_gpu_error.c } else if (IS_GEN(dev_priv, 7)) { dev_priv 1155 drivers/gpu/drm/i915/i915_gpu_error.c } else if (INTEL_GEN(dev_priv) >= 8) { dev_priv 1344 drivers/gpu/drm/i915/i915_gpu_error.c capture_object(struct drm_i915_private *dev_priv, dev_priv 1356 drivers/gpu/drm/i915/i915_gpu_error.c return i915_error_object_create(dev_priv, &fake, compress); dev_priv 202 drivers/gpu/drm/i915/i915_gpu_error.h void i915_capture_error_state(struct drm_i915_private *dev_priv, dev_priv 229 drivers/gpu/drm/i915/i915_gpu_error.h static inline void i915_capture_error_state(struct drm_i915_private *dev_priv, dev_priv 264 drivers/gpu/drm/i915/i915_irq.c i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, dev_priv 270 drivers/gpu/drm/i915/i915_irq.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 291 drivers/gpu/drm/i915/i915_irq.c void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, dev_priv 295 drivers/gpu/drm/i915/i915_irq.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 296 drivers/gpu/drm/i915/i915_irq.c i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); dev_priv 297 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 306 drivers/gpu/drm/i915/i915_irq.c void ilk_update_display_irq(struct drm_i915_private *dev_priv, dev_priv 312 drivers/gpu/drm/i915/i915_irq.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 316 drivers/gpu/drm/i915/i915_irq.c if (WARN_ON(!intel_irqs_enabled(dev_priv))) dev_priv 319 drivers/gpu/drm/i915/i915_irq.c new_val = dev_priv->irq_mask; dev_priv 323 drivers/gpu/drm/i915/i915_irq.c if (new_val != dev_priv->irq_mask) { dev_priv 324 drivers/gpu/drm/i915/i915_irq.c dev_priv->irq_mask = new_val; dev_priv 325 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(DEIMR, dev_priv->irq_mask); dev_priv 330 drivers/gpu/drm/i915/i915_irq.c static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) dev_priv 332 drivers/gpu/drm/i915/i915_irq.c WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11); dev_priv 334 drivers/gpu/drm/i915/i915_irq.c return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; dev_priv 337 drivers/gpu/drm/i915/i915_irq.c void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv) dev_priv 339 drivers/gpu/drm/i915/i915_irq.c struct intel_gt *gt = &dev_priv->gt; dev_priv 346 drivers/gpu/drm/i915/i915_irq.c dev_priv->gt_pm.rps.pm_iir = 0; dev_priv 351 drivers/gpu/drm/i915/i915_irq.c void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv) dev_priv 353 drivers/gpu/drm/i915/i915_irq.c struct intel_gt *gt = &dev_priv->gt; dev_priv 357 drivers/gpu/drm/i915/i915_irq.c dev_priv->gt_pm.rps.pm_iir = 0; dev_priv 361 drivers/gpu/drm/i915/i915_irq.c void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) dev_priv 363 drivers/gpu/drm/i915/i915_irq.c struct intel_gt *gt = &dev_priv->gt; dev_priv 364 drivers/gpu/drm/i915/i915_irq.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 372 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 375 drivers/gpu/drm/i915/i915_irq.c WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); dev_priv 378 drivers/gpu/drm/i915/i915_irq.c gen6_gt_pm_enable_irq(gt, dev_priv->pm_rps_events); dev_priv 388 drivers/gpu/drm/i915/i915_irq.c void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) dev_priv 390 drivers/gpu/drm/i915/i915_irq.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 391 drivers/gpu/drm/i915/i915_irq.c struct intel_gt *gt = &dev_priv->gt; dev_priv 399 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u)); dev_priv 404 drivers/gpu/drm/i915/i915_irq.c intel_synchronize_irq(dev_priv); dev_priv 412 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 413 drivers/gpu/drm/i915/i915_irq.c gen11_reset_rps_interrupts(dev_priv); dev_priv 415 drivers/gpu/drm/i915/i915_irq.c gen6_reset_rps_interrupts(dev_priv); dev_priv 510 drivers/gpu/drm/i915/i915_irq.c static void bdw_update_port_irq(struct drm_i915_private *dev_priv, dev_priv 517 drivers/gpu/drm/i915/i915_irq.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 521 drivers/gpu/drm/i915/i915_irq.c if (WARN_ON(!intel_irqs_enabled(dev_priv))) dev_priv 543 drivers/gpu/drm/i915/i915_irq.c void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, dev_priv 550 drivers/gpu/drm/i915/i915_irq.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 554 drivers/gpu/drm/i915/i915_irq.c if (WARN_ON(!intel_irqs_enabled(dev_priv))) dev_priv 557 drivers/gpu/drm/i915/i915_irq.c new_val = dev_priv->de_irq_mask[pipe]; dev_priv 561 drivers/gpu/drm/i915/i915_irq.c if (new_val != dev_priv->de_irq_mask[pipe]) { dev_priv 562 drivers/gpu/drm/i915/i915_irq.c dev_priv->de_irq_mask[pipe] = new_val; dev_priv 563 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); dev_priv 574 drivers/gpu/drm/i915/i915_irq.c void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, dev_priv 584 drivers/gpu/drm/i915/i915_irq.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 586 drivers/gpu/drm/i915/i915_irq.c if (WARN_ON(!intel_irqs_enabled(dev_priv))) dev_priv 593 drivers/gpu/drm/i915/i915_irq.c u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, dev_priv 596 drivers/gpu/drm/i915/i915_irq.c u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; dev_priv 599 drivers/gpu/drm/i915/i915_irq.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 601 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) < 5) dev_priv 634 drivers/gpu/drm/i915/i915_irq.c void i915_enable_pipestat(struct drm_i915_private *dev_priv, dev_priv 644 drivers/gpu/drm/i915/i915_irq.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 645 drivers/gpu/drm/i915/i915_irq.c WARN_ON(!intel_irqs_enabled(dev_priv)); dev_priv 647 drivers/gpu/drm/i915/i915_irq.c if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask) dev_priv 650 drivers/gpu/drm/i915/i915_irq.c dev_priv->pipestat_irq_mask[pipe] |= status_mask; dev_priv 651 drivers/gpu/drm/i915/i915_irq.c enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); dev_priv 657 drivers/gpu/drm/i915/i915_irq.c void i915_disable_pipestat(struct drm_i915_private *dev_priv, dev_priv 667 drivers/gpu/drm/i915/i915_irq.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 668 drivers/gpu/drm/i915/i915_irq.c WARN_ON(!intel_irqs_enabled(dev_priv)); dev_priv 670 drivers/gpu/drm/i915/i915_irq.c if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0) dev_priv 673 drivers/gpu/drm/i915/i915_irq.c dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; dev_priv 674 drivers/gpu/drm/i915/i915_irq.c enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); dev_priv 680 drivers/gpu/drm/i915/i915_irq.c static bool i915_has_asle(struct drm_i915_private *dev_priv) dev_priv 682 drivers/gpu/drm/i915/i915_irq.c if (!dev_priv->opregion.asle) dev_priv 685 drivers/gpu/drm/i915/i915_irq.c return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); dev_priv 692 drivers/gpu/drm/i915/i915_irq.c static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) dev_priv 694 drivers/gpu/drm/i915/i915_irq.c if (!i915_has_asle(dev_priv)) dev_priv 697 drivers/gpu/drm/i915/i915_irq.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 699 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); dev_priv 700 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 4) dev_priv 701 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_A, dev_priv 704 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 762 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 763 drivers/gpu/drm/i915/i915_irq.c struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; dev_priv 799 drivers/gpu/drm/i915/i915_irq.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 812 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 828 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 844 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 889 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 908 drivers/gpu/drm/i915/i915_irq.c if (IS_GEN(dev_priv, 2)) dev_priv 925 drivers/gpu/drm/i915/i915_irq.c if (HAS_DDI(dev_priv) && !position) { dev_priv 950 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 951 drivers/gpu/drm/i915/i915_irq.c struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, dev_priv 956 drivers/gpu/drm/i915/i915_irq.c bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 || dev_priv 957 drivers/gpu/drm/i915/i915_irq.c IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) || dev_priv 983 drivers/gpu/drm/i915/i915_irq.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 1038 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 1064 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1068 drivers/gpu/drm/i915/i915_irq.c spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); dev_priv 1070 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); dev_priv 1075 drivers/gpu/drm/i915/i915_irq.c static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv) dev_priv 1077 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 1087 drivers/gpu/drm/i915/i915_irq.c new_delay = dev_priv->ips.cur_delay; dev_priv 1097 drivers/gpu/drm/i915/i915_irq.c if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) dev_priv 1098 drivers/gpu/drm/i915/i915_irq.c new_delay = dev_priv->ips.cur_delay - 1; dev_priv 1099 drivers/gpu/drm/i915/i915_irq.c if (new_delay < dev_priv->ips.max_delay) dev_priv 1100 drivers/gpu/drm/i915/i915_irq.c new_delay = dev_priv->ips.max_delay; dev_priv 1102 drivers/gpu/drm/i915/i915_irq.c if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) dev_priv 1103 drivers/gpu/drm/i915/i915_irq.c new_delay = dev_priv->ips.cur_delay + 1; dev_priv 1104 drivers/gpu/drm/i915/i915_irq.c if (new_delay > dev_priv->ips.min_delay) dev_priv 1105 drivers/gpu/drm/i915/i915_irq.c new_delay = dev_priv->ips.min_delay; dev_priv 1108 drivers/gpu/drm/i915/i915_irq.c if (ironlake_set_drps(dev_priv, new_delay)) dev_priv 1109 drivers/gpu/drm/i915/i915_irq.c dev_priv->ips.cur_delay = new_delay; dev_priv 1116 drivers/gpu/drm/i915/i915_irq.c static void vlv_c0_read(struct drm_i915_private *dev_priv, dev_priv 1124 drivers/gpu/drm/i915/i915_irq.c void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) dev_priv 1126 drivers/gpu/drm/i915/i915_irq.c memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei)); dev_priv 1129 drivers/gpu/drm/i915/i915_irq.c static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) dev_priv 1131 drivers/gpu/drm/i915/i915_irq.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 1139 drivers/gpu/drm/i915/i915_irq.c vlv_c0_read(dev_priv, &now); dev_priv 1147 drivers/gpu/drm/i915/i915_irq.c time *= dev_priv->czclk_freq; dev_priv 1171 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = dev_priv 1173 drivers/gpu/drm/i915/i915_irq.c struct intel_gt *gt = &dev_priv->gt; dev_priv 1174 drivers/gpu/drm/i915/i915_irq.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 1187 drivers/gpu/drm/i915/i915_irq.c WARN_ON(pm_iir & ~dev_priv->pm_rps_events); dev_priv 1188 drivers/gpu/drm/i915/i915_irq.c if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) dev_priv 1193 drivers/gpu/drm/i915/i915_irq.c pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); dev_priv 1208 drivers/gpu/drm/i915/i915_irq.c adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; dev_priv 1224 drivers/gpu/drm/i915/i915_irq.c adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; dev_priv 1252 drivers/gpu/drm/i915/i915_irq.c if (intel_set_rps(dev_priv, new_delay)) { dev_priv 1263 drivers/gpu/drm/i915/i915_irq.c gen6_gt_pm_unmask_irq(gt, dev_priv->pm_rps_events); dev_priv 1279 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = dev_priv 1280 drivers/gpu/drm/i915/i915_irq.c container_of(work, typeof(*dev_priv), l3_parity.error_work); dev_priv 1281 drivers/gpu/drm/i915/i915_irq.c struct intel_gt *gt = &dev_priv->gt; dev_priv 1291 drivers/gpu/drm/i915/i915_irq.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 1294 drivers/gpu/drm/i915/i915_irq.c if (WARN_ON(!dev_priv->l3_parity.which_slice)) dev_priv 1301 drivers/gpu/drm/i915/i915_irq.c while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { dev_priv 1305 drivers/gpu/drm/i915/i915_irq.c if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv))) dev_priv 1308 drivers/gpu/drm/i915/i915_irq.c dev_priv->l3_parity.which_slice &= ~(1<<slice); dev_priv 1327 drivers/gpu/drm/i915/i915_irq.c kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, dev_priv 1342 drivers/gpu/drm/i915/i915_irq.c WARN_ON(dev_priv->l3_parity.which_slice); dev_priv 1344 drivers/gpu/drm/i915/i915_irq.c gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv)); dev_priv 1347 drivers/gpu/drm/i915/i915_irq.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1535 drivers/gpu/drm/i915/i915_irq.c static void intel_get_hpd_pins(struct drm_i915_private *dev_priv, dev_priv 1560 drivers/gpu/drm/i915/i915_irq.c static void gmbus_irq_handler(struct drm_i915_private *dev_priv) dev_priv 1562 drivers/gpu/drm/i915/i915_irq.c wake_up_all(&dev_priv->gmbus_wait_queue); dev_priv 1565 drivers/gpu/drm/i915/i915_irq.c static void dp_aux_irq_handler(struct drm_i915_private *dev_priv) dev_priv 1567 drivers/gpu/drm/i915/i915_irq.c wake_up_all(&dev_priv->gmbus_wait_queue); dev_priv 1571 drivers/gpu/drm/i915/i915_irq.c static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, dev_priv 1577 drivers/gpu/drm/i915/i915_irq.c struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; dev_priv 1578 drivers/gpu/drm/i915/i915_irq.c struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 1593 drivers/gpu/drm/i915/i915_irq.c (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) { dev_priv 1606 drivers/gpu/drm/i915/i915_irq.c display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, dev_priv 1614 drivers/gpu/drm/i915/i915_irq.c static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, dev_priv 1617 drivers/gpu/drm/i915/i915_irq.c display_pipe_crc_irq_handler(dev_priv, pipe, dev_priv 1622 drivers/gpu/drm/i915/i915_irq.c static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, dev_priv 1625 drivers/gpu/drm/i915/i915_irq.c display_pipe_crc_irq_handler(dev_priv, pipe, dev_priv 1633 drivers/gpu/drm/i915/i915_irq.c static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, dev_priv 1638 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 3) dev_priv 1643 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) dev_priv 1648 drivers/gpu/drm/i915/i915_irq.c display_pipe_crc_irq_handler(dev_priv, pipe, dev_priv 1678 drivers/gpu/drm/i915/i915_irq.c void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) dev_priv 1680 drivers/gpu/drm/i915/i915_irq.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 1681 drivers/gpu/drm/i915/i915_irq.c struct intel_gt *gt = &dev_priv->gt; dev_priv 1683 drivers/gpu/drm/i915/i915_irq.c if (pm_iir & dev_priv->pm_rps_events) { dev_priv 1685 drivers/gpu/drm/i915/i915_irq.c gen6_gt_pm_mask_irq(gt, pm_iir & dev_priv->pm_rps_events); dev_priv 1687 drivers/gpu/drm/i915/i915_irq.c rps->pm_iir |= pm_iir & dev_priv->pm_rps_events; dev_priv 1693 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 1697 drivers/gpu/drm/i915/i915_irq.c intel_engine_breadcrumbs_irq(dev_priv->engine[VECS0]); dev_priv 1703 drivers/gpu/drm/i915/i915_irq.c static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) dev_priv 1707 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) { dev_priv 1712 drivers/gpu/drm/i915/i915_irq.c dev_priv->pipestat_irq_mask[pipe] = 0; dev_priv 1716 drivers/gpu/drm/i915/i915_irq.c static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, dev_priv 1721 drivers/gpu/drm/i915/i915_irq.c spin_lock(&dev_priv->irq_lock); dev_priv 1723 drivers/gpu/drm/i915/i915_irq.c if (!dev_priv->display_irqs_enabled) { dev_priv 1724 drivers/gpu/drm/i915/i915_irq.c spin_unlock(&dev_priv->irq_lock); dev_priv 1728 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) { dev_priv 1755 drivers/gpu/drm/i915/i915_irq.c status_mask |= dev_priv->pipestat_irq_mask[pipe]; dev_priv 1762 drivers/gpu/drm/i915/i915_irq.c enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); dev_priv 1778 drivers/gpu/drm/i915/i915_irq.c spin_unlock(&dev_priv->irq_lock); dev_priv 1781 drivers/gpu/drm/i915/i915_irq.c static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv, dev_priv 1786 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) { dev_priv 1788 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); dev_priv 1791 drivers/gpu/drm/i915/i915_irq.c i9xx_pipe_crc_irq_handler(dev_priv, pipe); dev_priv 1794 drivers/gpu/drm/i915/i915_irq.c intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); dev_priv 1798 drivers/gpu/drm/i915/i915_irq.c static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv, dev_priv 1804 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) { dev_priv 1806 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); dev_priv 1812 drivers/gpu/drm/i915/i915_irq.c i9xx_pipe_crc_irq_handler(dev_priv, pipe); dev_priv 1815 drivers/gpu/drm/i915/i915_irq.c intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); dev_priv 1819 drivers/gpu/drm/i915/i915_irq.c intel_opregion_asle_intr(dev_priv); dev_priv 1822 drivers/gpu/drm/i915/i915_irq.c static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv, dev_priv 1828 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) { dev_priv 1830 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); dev_priv 1836 drivers/gpu/drm/i915/i915_irq.c i9xx_pipe_crc_irq_handler(dev_priv, pipe); dev_priv 1839 drivers/gpu/drm/i915/i915_irq.c intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); dev_priv 1843 drivers/gpu/drm/i915/i915_irq.c intel_opregion_asle_intr(dev_priv); dev_priv 1846 drivers/gpu/drm/i915/i915_irq.c gmbus_irq_handler(dev_priv); dev_priv 1849 drivers/gpu/drm/i915/i915_irq.c static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, dev_priv 1854 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) { dev_priv 1856 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); dev_priv 1859 drivers/gpu/drm/i915/i915_irq.c i9xx_pipe_crc_irq_handler(dev_priv, pipe); dev_priv 1862 drivers/gpu/drm/i915/i915_irq.c intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); dev_priv 1866 drivers/gpu/drm/i915/i915_irq.c gmbus_irq_handler(dev_priv); dev_priv 1869 drivers/gpu/drm/i915/i915_irq.c static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) dev_priv 1874 drivers/gpu/drm/i915/i915_irq.c if (IS_G4X(dev_priv) || dev_priv 1875 drivers/gpu/drm/i915/i915_irq.c IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 1907 drivers/gpu/drm/i915/i915_irq.c static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, dev_priv 1912 drivers/gpu/drm/i915/i915_irq.c if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || dev_priv 1913 drivers/gpu/drm/i915/i915_irq.c IS_CHERRYVIEW(dev_priv)) { dev_priv 1917 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, dev_priv 1922 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); dev_priv 1926 drivers/gpu/drm/i915/i915_irq.c dp_aux_irq_handler(dev_priv); dev_priv 1931 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, dev_priv 1935 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); dev_priv 1942 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = arg; dev_priv 1945 drivers/gpu/drm/i915/i915_irq.c if (!intel_irqs_enabled(dev_priv)) dev_priv 1949 drivers/gpu/drm/i915/i915_irq.c disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 1989 drivers/gpu/drm/i915/i915_irq.c hotplug_status = i9xx_hpd_irq_ack(dev_priv); dev_priv 1993 drivers/gpu/drm/i915/i915_irq.c i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); dev_priv 1997 drivers/gpu/drm/i915/i915_irq.c intel_lpe_audio_irq_handler(dev_priv); dev_priv 2010 drivers/gpu/drm/i915/i915_irq.c gen6_gt_irq_handler(&dev_priv->gt, gt_iir); dev_priv 2012 drivers/gpu/drm/i915/i915_irq.c gen6_rps_irq_handler(dev_priv, pm_iir); dev_priv 2015 drivers/gpu/drm/i915/i915_irq.c i9xx_hpd_irq_handler(dev_priv, hotplug_status); dev_priv 2017 drivers/gpu/drm/i915/i915_irq.c valleyview_pipestat_irq_handler(dev_priv, pipe_stats); dev_priv 2020 drivers/gpu/drm/i915/i915_irq.c enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 2027 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = arg; dev_priv 2030 drivers/gpu/drm/i915/i915_irq.c if (!intel_irqs_enabled(dev_priv)) dev_priv 2034 drivers/gpu/drm/i915/i915_irq.c disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 2068 drivers/gpu/drm/i915/i915_irq.c gen8_gt_irq_ack(&dev_priv->gt, master_ctl, gt_iir); dev_priv 2071 drivers/gpu/drm/i915/i915_irq.c hotplug_status = i9xx_hpd_irq_ack(dev_priv); dev_priv 2075 drivers/gpu/drm/i915/i915_irq.c i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); dev_priv 2080 drivers/gpu/drm/i915/i915_irq.c intel_lpe_audio_irq_handler(dev_priv); dev_priv 2092 drivers/gpu/drm/i915/i915_irq.c gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir); dev_priv 2095 drivers/gpu/drm/i915/i915_irq.c i9xx_hpd_irq_handler(dev_priv, hotplug_status); dev_priv 2097 drivers/gpu/drm/i915/i915_irq.c valleyview_pipestat_irq_handler(dev_priv, pipe_stats); dev_priv 2100 drivers/gpu/drm/i915/i915_irq.c enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 2105 drivers/gpu/drm/i915/i915_irq.c static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, dev_priv 2130 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger, dev_priv 2134 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); dev_priv 2137 drivers/gpu/drm/i915/i915_irq.c static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) dev_priv 2142 drivers/gpu/drm/i915/i915_irq.c ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx); dev_priv 2152 drivers/gpu/drm/i915/i915_irq.c dp_aux_irq_handler(dev_priv); dev_priv 2155 drivers/gpu/drm/i915/i915_irq.c gmbus_irq_handler(dev_priv); dev_priv 2167 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) dev_priv 2179 drivers/gpu/drm/i915/i915_irq.c intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); dev_priv 2182 drivers/gpu/drm/i915/i915_irq.c intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); dev_priv 2185 drivers/gpu/drm/i915/i915_irq.c static void ivb_err_int_handler(struct drm_i915_private *dev_priv) dev_priv 2193 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) { dev_priv 2195 drivers/gpu/drm/i915/i915_irq.c intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); dev_priv 2198 drivers/gpu/drm/i915/i915_irq.c if (IS_IVYBRIDGE(dev_priv)) dev_priv 2199 drivers/gpu/drm/i915/i915_irq.c ivb_pipe_crc_irq_handler(dev_priv, pipe); dev_priv 2201 drivers/gpu/drm/i915/i915_irq.c hsw_pipe_crc_irq_handler(dev_priv, pipe); dev_priv 2208 drivers/gpu/drm/i915/i915_irq.c static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) dev_priv 2216 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) dev_priv 2218 drivers/gpu/drm/i915/i915_irq.c intel_pch_fifo_underrun_irq_handler(dev_priv, pipe); dev_priv 2223 drivers/gpu/drm/i915/i915_irq.c static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) dev_priv 2228 drivers/gpu/drm/i915/i915_irq.c ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt); dev_priv 2238 drivers/gpu/drm/i915/i915_irq.c dp_aux_irq_handler(dev_priv); dev_priv 2241 drivers/gpu/drm/i915/i915_irq.c gmbus_irq_handler(dev_priv); dev_priv 2250 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) dev_priv 2256 drivers/gpu/drm/i915/i915_irq.c cpt_serr_int_handler(dev_priv); dev_priv 2259 drivers/gpu/drm/i915/i915_irq.c static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir, dev_priv 2266 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_MCC(dev_priv)) { dev_priv 2280 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, dev_priv 2292 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, dev_priv 2299 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); dev_priv 2302 drivers/gpu/drm/i915/i915_irq.c gmbus_irq_handler(dev_priv); dev_priv 2305 drivers/gpu/drm/i915/i915_irq.c static void tgp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) dev_priv 2317 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, dev_priv 2329 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, dev_priv 2336 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); dev_priv 2339 drivers/gpu/drm/i915/i915_irq.c gmbus_irq_handler(dev_priv); dev_priv 2342 drivers/gpu/drm/i915/i915_irq.c static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) dev_priv 2355 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, dev_priv 2366 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, dev_priv 2372 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); dev_priv 2375 drivers/gpu/drm/i915/i915_irq.c gmbus_irq_handler(dev_priv); dev_priv 2378 drivers/gpu/drm/i915/i915_irq.c static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, dev_priv 2387 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger, dev_priv 2391 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); dev_priv 2394 drivers/gpu/drm/i915/i915_irq.c static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, dev_priv 2401 drivers/gpu/drm/i915/i915_irq.c ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk); dev_priv 2404 drivers/gpu/drm/i915/i915_irq.c dp_aux_irq_handler(dev_priv); dev_priv 2407 drivers/gpu/drm/i915/i915_irq.c intel_opregion_asle_intr(dev_priv); dev_priv 2412 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) { dev_priv 2414 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); dev_priv 2417 drivers/gpu/drm/i915/i915_irq.c intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); dev_priv 2420 drivers/gpu/drm/i915/i915_irq.c i9xx_pipe_crc_irq_handler(dev_priv, pipe); dev_priv 2427 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_CPT(dev_priv)) dev_priv 2428 drivers/gpu/drm/i915/i915_irq.c cpt_irq_handler(dev_priv, pch_iir); dev_priv 2430 drivers/gpu/drm/i915/i915_irq.c ibx_irq_handler(dev_priv, pch_iir); dev_priv 2436 drivers/gpu/drm/i915/i915_irq.c if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT) dev_priv 2437 drivers/gpu/drm/i915/i915_irq.c ironlake_rps_change_irq_handler(dev_priv); dev_priv 2440 drivers/gpu/drm/i915/i915_irq.c static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, dev_priv 2447 drivers/gpu/drm/i915/i915_irq.c ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb); dev_priv 2450 drivers/gpu/drm/i915/i915_irq.c ivb_err_int_handler(dev_priv); dev_priv 2455 drivers/gpu/drm/i915/i915_irq.c intel_psr_irq_handler(dev_priv, psr_iir); dev_priv 2460 drivers/gpu/drm/i915/i915_irq.c dp_aux_irq_handler(dev_priv); dev_priv 2463 drivers/gpu/drm/i915/i915_irq.c intel_opregion_asle_intr(dev_priv); dev_priv 2465 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) { dev_priv 2467 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); dev_priv 2471 drivers/gpu/drm/i915/i915_irq.c if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { dev_priv 2474 drivers/gpu/drm/i915/i915_irq.c cpt_irq_handler(dev_priv, pch_iir); dev_priv 2491 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = arg; dev_priv 2495 drivers/gpu/drm/i915/i915_irq.c if (!intel_irqs_enabled(dev_priv)) dev_priv 2499 drivers/gpu/drm/i915/i915_irq.c disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 2510 drivers/gpu/drm/i915/i915_irq.c if (!HAS_PCH_NOP(dev_priv)) { dev_priv 2521 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 6) dev_priv 2522 drivers/gpu/drm/i915/i915_irq.c gen6_gt_irq_handler(&dev_priv->gt, gt_iir); dev_priv 2524 drivers/gpu/drm/i915/i915_irq.c gen5_gt_irq_handler(&dev_priv->gt, gt_iir); dev_priv 2531 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 7) dev_priv 2532 drivers/gpu/drm/i915/i915_irq.c ivb_display_irq_handler(dev_priv, de_iir); dev_priv 2534 drivers/gpu/drm/i915/i915_irq.c ilk_display_irq_handler(dev_priv, de_iir); dev_priv 2537 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 6) { dev_priv 2542 drivers/gpu/drm/i915/i915_irq.c gen6_rps_irq_handler(dev_priv, pm_iir); dev_priv 2547 drivers/gpu/drm/i915/i915_irq.c if (!HAS_PCH_NOP(dev_priv)) dev_priv 2551 drivers/gpu/drm/i915/i915_irq.c enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 2556 drivers/gpu/drm/i915/i915_irq.c static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, dev_priv 2565 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger, dev_priv 2569 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); dev_priv 2572 drivers/gpu/drm/i915/i915_irq.c static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) dev_priv 2580 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 12) { dev_priv 2594 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc, dev_priv 2604 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt, dev_priv 2609 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); dev_priv 2614 drivers/gpu/drm/i915/i915_irq.c static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) dev_priv 2618 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 12) dev_priv 2625 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 2630 drivers/gpu/drm/i915/i915_irq.c if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11)) dev_priv 2633 drivers/gpu/drm/i915/i915_irq.c if (IS_GEN(dev_priv, 11)) dev_priv 2639 drivers/gpu/drm/i915/i915_irq.c static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) dev_priv 2641 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 2648 drivers/gpu/drm/i915/i915_irq.c gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) dev_priv 2653 drivers/gpu/drm/i915/i915_irq.c intel_opregion_asle_intr(dev_priv); dev_priv 2660 drivers/gpu/drm/i915/i915_irq.c intel_psr_irq_handler(dev_priv, psr_iir); dev_priv 2670 drivers/gpu/drm/i915/i915_irq.c gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) dev_priv 2681 drivers/gpu/drm/i915/i915_irq.c gen8_de_misc_irq_handler(dev_priv, iir); dev_priv 2687 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) { dev_priv 2692 drivers/gpu/drm/i915/i915_irq.c gen11_hpd_irq_handler(dev_priv, iir); dev_priv 2707 drivers/gpu/drm/i915/i915_irq.c if (iir & gen8_de_port_aux_mask(dev_priv)) { dev_priv 2708 drivers/gpu/drm/i915/i915_irq.c dp_aux_irq_handler(dev_priv); dev_priv 2712 drivers/gpu/drm/i915/i915_irq.c if (IS_GEN9_LP(dev_priv)) { dev_priv 2715 drivers/gpu/drm/i915/i915_irq.c bxt_hpd_irq_handler(dev_priv, tmp_mask, dev_priv 2719 drivers/gpu/drm/i915/i915_irq.c } else if (IS_BROADWELL(dev_priv)) { dev_priv 2722 drivers/gpu/drm/i915/i915_irq.c ilk_hpd_irq_handler(dev_priv, dev_priv 2728 drivers/gpu/drm/i915/i915_irq.c if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { dev_priv 2729 drivers/gpu/drm/i915/i915_irq.c gmbus_irq_handler(dev_priv); dev_priv 2740 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) { dev_priv 2756 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); dev_priv 2759 drivers/gpu/drm/i915/i915_irq.c hsw_pipe_crc_irq_handler(dev_priv, pipe); dev_priv 2762 drivers/gpu/drm/i915/i915_irq.c intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); dev_priv 2764 drivers/gpu/drm/i915/i915_irq.c fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv); dev_priv 2771 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && dev_priv 2783 drivers/gpu/drm/i915/i915_irq.c if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP) dev_priv 2784 drivers/gpu/drm/i915/i915_irq.c tgp_irq_handler(dev_priv, iir); dev_priv 2785 drivers/gpu/drm/i915/i915_irq.c else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MCC) dev_priv 2786 drivers/gpu/drm/i915/i915_irq.c icp_irq_handler(dev_priv, iir, hpd_mcc); dev_priv 2787 drivers/gpu/drm/i915/i915_irq.c else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) dev_priv 2788 drivers/gpu/drm/i915/i915_irq.c icp_irq_handler(dev_priv, iir, hpd_icp); dev_priv 2789 drivers/gpu/drm/i915/i915_irq.c else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) dev_priv 2790 drivers/gpu/drm/i915/i915_irq.c spt_irq_handler(dev_priv, iir); dev_priv 2792 drivers/gpu/drm/i915/i915_irq.c cpt_irq_handler(dev_priv, iir); dev_priv 2825 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = arg; dev_priv 2826 drivers/gpu/drm/i915/i915_irq.c void __iomem * const regs = dev_priv->uncore.regs; dev_priv 2830 drivers/gpu/drm/i915/i915_irq.c if (!intel_irqs_enabled(dev_priv)) dev_priv 2840 drivers/gpu/drm/i915/i915_irq.c gen8_gt_irq_ack(&dev_priv->gt, master_ctl, gt_iir); dev_priv 2844 drivers/gpu/drm/i915/i915_irq.c disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 2845 drivers/gpu/drm/i915/i915_irq.c gen8_de_irq_handler(dev_priv, master_ctl); dev_priv 2846 drivers/gpu/drm/i915/i915_irq.c enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 2851 drivers/gpu/drm/i915/i915_irq.c gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir); dev_priv 2944 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 2948 drivers/gpu/drm/i915/i915_irq.c spin_lock_irqsave(&dev_priv->irq_lock, irqflags); dev_priv 2949 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); dev_priv 2950 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); dev_priv 2957 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 2959 drivers/gpu/drm/i915/i915_irq.c if (dev_priv->i945gm_vblank.enabled++ == 0) dev_priv 2960 drivers/gpu/drm/i915/i915_irq.c schedule_work(&dev_priv->i945gm_vblank.work); dev_priv 2967 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 2971 drivers/gpu/drm/i915/i915_irq.c spin_lock_irqsave(&dev_priv->irq_lock, irqflags); dev_priv 2972 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, pipe, dev_priv 2974 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); dev_priv 2981 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 2984 drivers/gpu/drm/i915/i915_irq.c u32 bit = INTEL_GEN(dev_priv) >= 7 ? dev_priv 2987 drivers/gpu/drm/i915/i915_irq.c spin_lock_irqsave(&dev_priv->irq_lock, irqflags); dev_priv 2988 drivers/gpu/drm/i915/i915_irq.c ilk_enable_display_irq(dev_priv, bit); dev_priv 2989 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); dev_priv 2994 drivers/gpu/drm/i915/i915_irq.c if (HAS_PSR(dev_priv)) dev_priv 3002 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 3006 drivers/gpu/drm/i915/i915_irq.c spin_lock_irqsave(&dev_priv->irq_lock, irqflags); dev_priv 3007 drivers/gpu/drm/i915/i915_irq.c bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); dev_priv 3008 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); dev_priv 3013 drivers/gpu/drm/i915/i915_irq.c if (HAS_PSR(dev_priv)) dev_priv 3024 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 3028 drivers/gpu/drm/i915/i915_irq.c spin_lock_irqsave(&dev_priv->irq_lock, irqflags); dev_priv 3029 drivers/gpu/drm/i915/i915_irq.c i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); dev_priv 3030 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); dev_priv 3035 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 3039 drivers/gpu/drm/i915/i915_irq.c if (--dev_priv->i945gm_vblank.enabled == 0) dev_priv 3040 drivers/gpu/drm/i915/i915_irq.c schedule_work(&dev_priv->i945gm_vblank.work); dev_priv 3045 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 3049 drivers/gpu/drm/i915/i915_irq.c spin_lock_irqsave(&dev_priv->irq_lock, irqflags); dev_priv 3050 drivers/gpu/drm/i915/i915_irq.c i915_disable_pipestat(dev_priv, pipe, dev_priv 3052 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); dev_priv 3057 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 3060 drivers/gpu/drm/i915/i915_irq.c u32 bit = INTEL_GEN(dev_priv) >= 7 ? dev_priv 3063 drivers/gpu/drm/i915/i915_irq.c spin_lock_irqsave(&dev_priv->irq_lock, irqflags); dev_priv 3064 drivers/gpu/drm/i915/i915_irq.c ilk_disable_display_irq(dev_priv, bit); dev_priv 3065 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); dev_priv 3070 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 3074 drivers/gpu/drm/i915/i915_irq.c spin_lock_irqsave(&dev_priv->irq_lock, irqflags); dev_priv 3075 drivers/gpu/drm/i915/i915_irq.c bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); dev_priv 3076 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); dev_priv 3081 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = dev_priv 3089 drivers/gpu/drm/i915/i915_irq.c pm_qos_update_request(&dev_priv->i945gm_vblank.pm_qos, dev_priv 3090 drivers/gpu/drm/i915/i915_irq.c READ_ONCE(dev_priv->i945gm_vblank.enabled) ? dev_priv 3091 drivers/gpu/drm/i915/i915_irq.c dev_priv->i945gm_vblank.c3_disable_latency : dev_priv 3115 drivers/gpu/drm/i915/i915_irq.c static void i945gm_vblank_work_init(struct drm_i915_private *dev_priv) dev_priv 3117 drivers/gpu/drm/i915/i915_irq.c INIT_WORK(&dev_priv->i945gm_vblank.work, dev_priv 3120 drivers/gpu/drm/i915/i915_irq.c dev_priv->i945gm_vblank.c3_disable_latency = dev_priv 3122 drivers/gpu/drm/i915/i915_irq.c pm_qos_add_request(&dev_priv->i945gm_vblank.pm_qos, dev_priv 3127 drivers/gpu/drm/i915/i915_irq.c static void i945gm_vblank_work_fini(struct drm_i915_private *dev_priv) dev_priv 3129 drivers/gpu/drm/i915/i915_irq.c cancel_work_sync(&dev_priv->i945gm_vblank.work); dev_priv 3130 drivers/gpu/drm/i915/i915_irq.c pm_qos_remove_request(&dev_priv->i945gm_vblank.pm_qos); dev_priv 3133 drivers/gpu/drm/i915/i915_irq.c static void ibx_irq_reset(struct drm_i915_private *dev_priv) dev_priv 3135 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3137 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_NOP(dev_priv)) dev_priv 3142 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) dev_priv 3154 drivers/gpu/drm/i915/i915_irq.c static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv) dev_priv 3156 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_NOP(dev_priv)) dev_priv 3164 drivers/gpu/drm/i915/i915_irq.c static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) dev_priv 3166 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3168 drivers/gpu/drm/i915/i915_irq.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 3173 drivers/gpu/drm/i915/i915_irq.c i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); dev_priv 3176 drivers/gpu/drm/i915/i915_irq.c i9xx_pipestat_irq_reset(dev_priv); dev_priv 3179 drivers/gpu/drm/i915/i915_irq.c dev_priv->irq_mask = ~0u; dev_priv 3182 drivers/gpu/drm/i915/i915_irq.c static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv 3184 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3192 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); dev_priv 3193 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) dev_priv 3194 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, pipe, pipestat_mask); dev_priv 3202 drivers/gpu/drm/i915/i915_irq.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 3206 drivers/gpu/drm/i915/i915_irq.c WARN_ON(dev_priv->irq_mask != ~0u); dev_priv 3208 drivers/gpu/drm/i915/i915_irq.c dev_priv->irq_mask = ~enable_mask; dev_priv 3210 drivers/gpu/drm/i915/i915_irq.c GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask); dev_priv 3215 drivers/gpu/drm/i915/i915_irq.c static void ironlake_irq_reset(struct drm_i915_private *dev_priv) dev_priv 3217 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3220 drivers/gpu/drm/i915/i915_irq.c if (IS_GEN(dev_priv, 7)) dev_priv 3223 drivers/gpu/drm/i915/i915_irq.c if (IS_HASWELL(dev_priv)) { dev_priv 3228 drivers/gpu/drm/i915/i915_irq.c gen5_gt_irq_reset(&dev_priv->gt); dev_priv 3230 drivers/gpu/drm/i915/i915_irq.c ibx_irq_reset(dev_priv); dev_priv 3233 drivers/gpu/drm/i915/i915_irq.c static void valleyview_irq_reset(struct drm_i915_private *dev_priv) dev_priv 3238 drivers/gpu/drm/i915/i915_irq.c gen5_gt_irq_reset(&dev_priv->gt); dev_priv 3240 drivers/gpu/drm/i915/i915_irq.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 3241 drivers/gpu/drm/i915/i915_irq.c if (dev_priv->display_irqs_enabled) dev_priv 3242 drivers/gpu/drm/i915/i915_irq.c vlv_display_irq_reset(dev_priv); dev_priv 3243 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 3246 drivers/gpu/drm/i915/i915_irq.c static void gen8_irq_reset(struct drm_i915_private *dev_priv) dev_priv 3248 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3251 drivers/gpu/drm/i915/i915_irq.c gen8_master_intr_disable(dev_priv->uncore.regs); dev_priv 3253 drivers/gpu/drm/i915/i915_irq.c gen8_gt_irq_reset(&dev_priv->gt); dev_priv 3258 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) dev_priv 3259 drivers/gpu/drm/i915/i915_irq.c if (intel_display_power_is_enabled(dev_priv, dev_priv 3267 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_SPLIT(dev_priv)) dev_priv 3268 drivers/gpu/drm/i915/i915_irq.c ibx_irq_reset(dev_priv); dev_priv 3271 drivers/gpu/drm/i915/i915_irq.c static void gen11_irq_reset(struct drm_i915_private *dev_priv) dev_priv 3273 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3276 drivers/gpu/drm/i915/i915_irq.c gen11_master_intr_disable(dev_priv->uncore.regs); dev_priv 3278 drivers/gpu/drm/i915/i915_irq.c gen11_gt_irq_reset(&dev_priv->gt); dev_priv 3285 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) dev_priv 3286 drivers/gpu/drm/i915/i915_irq.c if (intel_display_power_is_enabled(dev_priv, dev_priv 3296 drivers/gpu/drm/i915/i915_irq.c if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) dev_priv 3300 drivers/gpu/drm/i915/i915_irq.c void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, dev_priv 3303 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3308 drivers/gpu/drm/i915/i915_irq.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 3310 drivers/gpu/drm/i915/i915_irq.c if (!intel_irqs_enabled(dev_priv)) { dev_priv 3311 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 3315 drivers/gpu/drm/i915/i915_irq.c for_each_pipe_masked(dev_priv, pipe, pipe_mask) dev_priv 3317 drivers/gpu/drm/i915/i915_irq.c dev_priv->de_irq_mask[pipe], dev_priv 3318 drivers/gpu/drm/i915/i915_irq.c ~dev_priv->de_irq_mask[pipe] | extra_ier); dev_priv 3320 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 3323 drivers/gpu/drm/i915/i915_irq.c void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, dev_priv 3326 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3329 drivers/gpu/drm/i915/i915_irq.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 3331 drivers/gpu/drm/i915/i915_irq.c if (!intel_irqs_enabled(dev_priv)) { dev_priv 3332 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 3336 drivers/gpu/drm/i915/i915_irq.c for_each_pipe_masked(dev_priv, pipe, pipe_mask) dev_priv 3339 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 3342 drivers/gpu/drm/i915/i915_irq.c intel_synchronize_irq(dev_priv); dev_priv 3345 drivers/gpu/drm/i915/i915_irq.c static void cherryview_irq_reset(struct drm_i915_private *dev_priv) dev_priv 3347 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3352 drivers/gpu/drm/i915/i915_irq.c gen8_gt_irq_reset(&dev_priv->gt); dev_priv 3356 drivers/gpu/drm/i915/i915_irq.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 3357 drivers/gpu/drm/i915/i915_irq.c if (dev_priv->display_irqs_enabled) dev_priv 3358 drivers/gpu/drm/i915/i915_irq.c vlv_display_irq_reset(dev_priv); dev_priv 3359 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 3362 drivers/gpu/drm/i915/i915_irq.c static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, dev_priv 3368 drivers/gpu/drm/i915/i915_irq.c for_each_intel_encoder(&dev_priv->drm, encoder) dev_priv 3369 drivers/gpu/drm/i915/i915_irq.c if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) dev_priv 3375 drivers/gpu/drm/i915/i915_irq.c static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) dev_priv 3395 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_LPT_LP(dev_priv)) dev_priv 3400 drivers/gpu/drm/i915/i915_irq.c static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) dev_priv 3404 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_IBX(dev_priv)) { dev_priv 3406 drivers/gpu/drm/i915/i915_irq.c enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx); dev_priv 3409 drivers/gpu/drm/i915/i915_irq.c enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt); dev_priv 3412 drivers/gpu/drm/i915/i915_irq.c ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); dev_priv 3414 drivers/gpu/drm/i915/i915_irq.c ibx_hpd_detection_setup(dev_priv); dev_priv 3417 drivers/gpu/drm/i915/i915_irq.c static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv, dev_priv 3434 drivers/gpu/drm/i915/i915_irq.c static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv) dev_priv 3439 drivers/gpu/drm/i915/i915_irq.c enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp); dev_priv 3441 drivers/gpu/drm/i915/i915_irq.c ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); dev_priv 3443 drivers/gpu/drm/i915/i915_irq.c icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK, dev_priv 3447 drivers/gpu/drm/i915/i915_irq.c static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) dev_priv 3452 drivers/gpu/drm/i915/i915_irq.c enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_mcc); dev_priv 3454 drivers/gpu/drm/i915/i915_irq.c ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); dev_priv 3456 drivers/gpu/drm/i915/i915_irq.c icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, 0); dev_priv 3459 drivers/gpu/drm/i915/i915_irq.c static void tgp_hpd_irq_setup(struct drm_i915_private *dev_priv) dev_priv 3464 drivers/gpu/drm/i915/i915_irq.c enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_tgp); dev_priv 3466 drivers/gpu/drm/i915/i915_irq.c ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); dev_priv 3468 drivers/gpu/drm/i915/i915_irq.c icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, dev_priv 3472 drivers/gpu/drm/i915/i915_irq.c static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) dev_priv 3491 drivers/gpu/drm/i915/i915_irq.c static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) dev_priv 3497 drivers/gpu/drm/i915/i915_irq.c hpd = INTEL_GEN(dev_priv) >= 12 ? hpd_gen12 : hpd_gen11; dev_priv 3498 drivers/gpu/drm/i915/i915_irq.c enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd); dev_priv 3506 drivers/gpu/drm/i915/i915_irq.c gen11_hpd_detection_setup(dev_priv); dev_priv 3508 drivers/gpu/drm/i915/i915_irq.c if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP) dev_priv 3509 drivers/gpu/drm/i915/i915_irq.c tgp_hpd_irq_setup(dev_priv); dev_priv 3510 drivers/gpu/drm/i915/i915_irq.c else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) dev_priv 3511 drivers/gpu/drm/i915/i915_irq.c icp_hpd_irq_setup(dev_priv); dev_priv 3514 drivers/gpu/drm/i915/i915_irq.c static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) dev_priv 3519 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_CNP(dev_priv)) { dev_priv 3539 drivers/gpu/drm/i915/i915_irq.c static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) dev_priv 3544 drivers/gpu/drm/i915/i915_irq.c enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt); dev_priv 3546 drivers/gpu/drm/i915/i915_irq.c ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); dev_priv 3548 drivers/gpu/drm/i915/i915_irq.c spt_hpd_detection_setup(dev_priv); dev_priv 3551 drivers/gpu/drm/i915/i915_irq.c static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv) dev_priv 3567 drivers/gpu/drm/i915/i915_irq.c static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) dev_priv 3571 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 8) { dev_priv 3573 drivers/gpu/drm/i915/i915_irq.c enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw); dev_priv 3575 drivers/gpu/drm/i915/i915_irq.c bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); dev_priv 3576 drivers/gpu/drm/i915/i915_irq.c } else if (INTEL_GEN(dev_priv) >= 7) { dev_priv 3578 drivers/gpu/drm/i915/i915_irq.c enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb); dev_priv 3580 drivers/gpu/drm/i915/i915_irq.c ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); dev_priv 3583 drivers/gpu/drm/i915/i915_irq.c enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk); dev_priv 3585 drivers/gpu/drm/i915/i915_irq.c ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); dev_priv 3588 drivers/gpu/drm/i915/i915_irq.c ilk_hpd_detection_setup(dev_priv); dev_priv 3590 drivers/gpu/drm/i915/i915_irq.c ibx_hpd_irq_setup(dev_priv); dev_priv 3593 drivers/gpu/drm/i915/i915_irq.c static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, dev_priv 3612 drivers/gpu/drm/i915/i915_irq.c intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) dev_priv 3615 drivers/gpu/drm/i915/i915_irq.c intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) dev_priv 3618 drivers/gpu/drm/i915/i915_irq.c intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) dev_priv 3624 drivers/gpu/drm/i915/i915_irq.c static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) dev_priv 3626 drivers/gpu/drm/i915/i915_irq.c __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK); dev_priv 3629 drivers/gpu/drm/i915/i915_irq.c static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) dev_priv 3633 drivers/gpu/drm/i915/i915_irq.c enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt); dev_priv 3636 drivers/gpu/drm/i915/i915_irq.c bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); dev_priv 3638 drivers/gpu/drm/i915/i915_irq.c __bxt_hpd_detection_setup(dev_priv, enabled_irqs); dev_priv 3641 drivers/gpu/drm/i915/i915_irq.c static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv 3645 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_NOP(dev_priv)) dev_priv 3648 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_IBX(dev_priv)) dev_priv 3650 drivers/gpu/drm/i915/i915_irq.c else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) dev_priv 3655 drivers/gpu/drm/i915/i915_irq.c gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); dev_priv 3658 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || dev_priv 3659 drivers/gpu/drm/i915/i915_irq.c HAS_PCH_LPT(dev_priv)) dev_priv 3660 drivers/gpu/drm/i915/i915_irq.c ibx_hpd_detection_setup(dev_priv); dev_priv 3662 drivers/gpu/drm/i915/i915_irq.c spt_hpd_detection_setup(dev_priv); dev_priv 3665 drivers/gpu/drm/i915/i915_irq.c static void ironlake_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv 3667 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3670 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 7) { dev_priv 3685 drivers/gpu/drm/i915/i915_irq.c if (IS_HASWELL(dev_priv)) { dev_priv 3687 drivers/gpu/drm/i915/i915_irq.c intel_psr_irq_control(dev_priv, dev_priv->psr.debug); dev_priv 3691 drivers/gpu/drm/i915/i915_irq.c dev_priv->irq_mask = ~display_mask; dev_priv 3693 drivers/gpu/drm/i915/i915_irq.c ibx_irq_pre_postinstall(dev_priv); dev_priv 3695 drivers/gpu/drm/i915/i915_irq.c GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask, dev_priv 3698 drivers/gpu/drm/i915/i915_irq.c gen5_gt_irq_postinstall(&dev_priv->gt); dev_priv 3700 drivers/gpu/drm/i915/i915_irq.c ilk_hpd_detection_setup(dev_priv); dev_priv 3702 drivers/gpu/drm/i915/i915_irq.c ibx_irq_postinstall(dev_priv); dev_priv 3704 drivers/gpu/drm/i915/i915_irq.c if (IS_IRONLAKE_M(dev_priv)) { dev_priv 3710 drivers/gpu/drm/i915/i915_irq.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 3711 drivers/gpu/drm/i915/i915_irq.c ilk_enable_display_irq(dev_priv, DE_PCU_EVENT); dev_priv 3712 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 3716 drivers/gpu/drm/i915/i915_irq.c void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) dev_priv 3718 drivers/gpu/drm/i915/i915_irq.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 3720 drivers/gpu/drm/i915/i915_irq.c if (dev_priv->display_irqs_enabled) dev_priv 3723 drivers/gpu/drm/i915/i915_irq.c dev_priv->display_irqs_enabled = true; dev_priv 3725 drivers/gpu/drm/i915/i915_irq.c if (intel_irqs_enabled(dev_priv)) { dev_priv 3726 drivers/gpu/drm/i915/i915_irq.c vlv_display_irq_reset(dev_priv); dev_priv 3727 drivers/gpu/drm/i915/i915_irq.c vlv_display_irq_postinstall(dev_priv); dev_priv 3731 drivers/gpu/drm/i915/i915_irq.c void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) dev_priv 3733 drivers/gpu/drm/i915/i915_irq.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 3735 drivers/gpu/drm/i915/i915_irq.c if (!dev_priv->display_irqs_enabled) dev_priv 3738 drivers/gpu/drm/i915/i915_irq.c dev_priv->display_irqs_enabled = false; dev_priv 3740 drivers/gpu/drm/i915/i915_irq.c if (intel_irqs_enabled(dev_priv)) dev_priv 3741 drivers/gpu/drm/i915/i915_irq.c vlv_display_irq_reset(dev_priv); dev_priv 3745 drivers/gpu/drm/i915/i915_irq.c static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv 3747 drivers/gpu/drm/i915/i915_irq.c gen5_gt_irq_postinstall(&dev_priv->gt); dev_priv 3749 drivers/gpu/drm/i915/i915_irq.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 3750 drivers/gpu/drm/i915/i915_irq.c if (dev_priv->display_irqs_enabled) dev_priv 3751 drivers/gpu/drm/i915/i915_irq.c vlv_display_irq_postinstall(dev_priv); dev_priv 3752 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 3758 drivers/gpu/drm/i915/i915_irq.c static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv 3760 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3769 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) <= 10) dev_priv 3772 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 3776 drivers/gpu/drm/i915/i915_irq.c if (IS_GEN9_LP(dev_priv)) dev_priv 3782 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 3785 drivers/gpu/drm/i915/i915_irq.c if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11) dev_priv 3792 drivers/gpu/drm/i915/i915_irq.c if (IS_GEN9_LP(dev_priv)) dev_priv 3794 drivers/gpu/drm/i915/i915_irq.c else if (IS_BROADWELL(dev_priv)) dev_priv 3798 drivers/gpu/drm/i915/i915_irq.c intel_psr_irq_control(dev_priv, dev_priv->psr.debug); dev_priv 3800 drivers/gpu/drm/i915/i915_irq.c for_each_pipe(dev_priv, pipe) { dev_priv 3801 drivers/gpu/drm/i915/i915_irq.c dev_priv->de_irq_mask[pipe] = ~de_pipe_masked; dev_priv 3803 drivers/gpu/drm/i915/i915_irq.c if (intel_display_power_is_enabled(dev_priv, dev_priv 3806 drivers/gpu/drm/i915/i915_irq.c dev_priv->de_irq_mask[pipe], dev_priv 3813 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 11) { dev_priv 3820 drivers/gpu/drm/i915/i915_irq.c gen11_hpd_detection_setup(dev_priv); dev_priv 3821 drivers/gpu/drm/i915/i915_irq.c } else if (IS_GEN9_LP(dev_priv)) { dev_priv 3822 drivers/gpu/drm/i915/i915_irq.c bxt_hpd_detection_setup(dev_priv); dev_priv 3823 drivers/gpu/drm/i915/i915_irq.c } else if (IS_BROADWELL(dev_priv)) { dev_priv 3824 drivers/gpu/drm/i915/i915_irq.c ilk_hpd_detection_setup(dev_priv); dev_priv 3828 drivers/gpu/drm/i915/i915_irq.c static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv 3830 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_SPLIT(dev_priv)) dev_priv 3831 drivers/gpu/drm/i915/i915_irq.c ibx_irq_pre_postinstall(dev_priv); dev_priv 3833 drivers/gpu/drm/i915/i915_irq.c gen8_gt_irq_postinstall(&dev_priv->gt); dev_priv 3834 drivers/gpu/drm/i915/i915_irq.c gen8_de_irq_postinstall(dev_priv); dev_priv 3836 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_SPLIT(dev_priv)) dev_priv 3837 drivers/gpu/drm/i915/i915_irq.c ibx_irq_postinstall(dev_priv); dev_priv 3839 drivers/gpu/drm/i915/i915_irq.c gen8_master_intr_enable(dev_priv->uncore.regs); dev_priv 3842 drivers/gpu/drm/i915/i915_irq.c static void icp_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv 3850 drivers/gpu/drm/i915/i915_irq.c gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); dev_priv 3853 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_TGP(dev_priv)) dev_priv 3854 drivers/gpu/drm/i915/i915_irq.c icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, dev_priv 3856 drivers/gpu/drm/i915/i915_irq.c else if (HAS_PCH_MCC(dev_priv)) dev_priv 3857 drivers/gpu/drm/i915/i915_irq.c icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, 0); dev_priv 3859 drivers/gpu/drm/i915/i915_irq.c icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK, dev_priv 3863 drivers/gpu/drm/i915/i915_irq.c static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv 3865 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3868 drivers/gpu/drm/i915/i915_irq.c if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) dev_priv 3869 drivers/gpu/drm/i915/i915_irq.c icp_irq_postinstall(dev_priv); dev_priv 3871 drivers/gpu/drm/i915/i915_irq.c gen11_gt_irq_postinstall(&dev_priv->gt); dev_priv 3872 drivers/gpu/drm/i915/i915_irq.c gen8_de_irq_postinstall(dev_priv); dev_priv 3882 drivers/gpu/drm/i915/i915_irq.c static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv 3884 drivers/gpu/drm/i915/i915_irq.c gen8_gt_irq_postinstall(&dev_priv->gt); dev_priv 3886 drivers/gpu/drm/i915/i915_irq.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 3887 drivers/gpu/drm/i915/i915_irq.c if (dev_priv->display_irqs_enabled) dev_priv 3888 drivers/gpu/drm/i915/i915_irq.c vlv_display_irq_postinstall(dev_priv); dev_priv 3889 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 3895 drivers/gpu/drm/i915/i915_irq.c static void i8xx_irq_reset(struct drm_i915_private *dev_priv) dev_priv 3897 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3899 drivers/gpu/drm/i915/i915_irq.c i9xx_pipestat_irq_reset(dev_priv); dev_priv 3904 drivers/gpu/drm/i915/i915_irq.c static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv 3906 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 3915 drivers/gpu/drm/i915/i915_irq.c dev_priv->irq_mask = dev_priv 3926 drivers/gpu/drm/i915/i915_irq.c GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask); dev_priv 3930 drivers/gpu/drm/i915/i915_irq.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 3931 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); dev_priv 3932 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); dev_priv 3933 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 3966 drivers/gpu/drm/i915/i915_irq.c static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv, dev_priv 3975 drivers/gpu/drm/i915/i915_irq.c static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, dev_priv 4003 drivers/gpu/drm/i915/i915_irq.c static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv, dev_priv 4014 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = arg; dev_priv 4017 drivers/gpu/drm/i915/i915_irq.c if (!intel_irqs_enabled(dev_priv)) dev_priv 4021 drivers/gpu/drm/i915/i915_irq.c disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 4028 drivers/gpu/drm/i915/i915_irq.c iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR); dev_priv 4036 drivers/gpu/drm/i915/i915_irq.c i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); dev_priv 4039 drivers/gpu/drm/i915/i915_irq.c i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck); dev_priv 4041 drivers/gpu/drm/i915/i915_irq.c intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); dev_priv 4044 drivers/gpu/drm/i915/i915_irq.c intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]); dev_priv 4047 drivers/gpu/drm/i915/i915_irq.c i8xx_error_irq_handler(dev_priv, eir, eir_stuck); dev_priv 4049 drivers/gpu/drm/i915/i915_irq.c i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats); dev_priv 4052 drivers/gpu/drm/i915/i915_irq.c enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 4057 drivers/gpu/drm/i915/i915_irq.c static void i915_irq_reset(struct drm_i915_private *dev_priv) dev_priv 4059 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 4061 drivers/gpu/drm/i915/i915_irq.c if (I915_HAS_HOTPLUG(dev_priv)) { dev_priv 4062 drivers/gpu/drm/i915/i915_irq.c i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); dev_priv 4066 drivers/gpu/drm/i915/i915_irq.c i9xx_pipestat_irq_reset(dev_priv); dev_priv 4071 drivers/gpu/drm/i915/i915_irq.c static void i915_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv 4073 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 4080 drivers/gpu/drm/i915/i915_irq.c dev_priv->irq_mask = dev_priv 4093 drivers/gpu/drm/i915/i915_irq.c if (I915_HAS_HOTPLUG(dev_priv)) { dev_priv 4097 drivers/gpu/drm/i915/i915_irq.c dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; dev_priv 4100 drivers/gpu/drm/i915/i915_irq.c GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); dev_priv 4104 drivers/gpu/drm/i915/i915_irq.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 4105 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); dev_priv 4106 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); dev_priv 4107 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 4109 drivers/gpu/drm/i915/i915_irq.c i915_enable_asle_pipestat(dev_priv); dev_priv 4114 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = arg; dev_priv 4117 drivers/gpu/drm/i915/i915_irq.c if (!intel_irqs_enabled(dev_priv)) dev_priv 4121 drivers/gpu/drm/i915/i915_irq.c disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 4135 drivers/gpu/drm/i915/i915_irq.c if (I915_HAS_HOTPLUG(dev_priv) && dev_priv 4137 drivers/gpu/drm/i915/i915_irq.c hotplug_status = i9xx_hpd_irq_ack(dev_priv); dev_priv 4141 drivers/gpu/drm/i915/i915_irq.c i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); dev_priv 4144 drivers/gpu/drm/i915/i915_irq.c i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); dev_priv 4149 drivers/gpu/drm/i915/i915_irq.c intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]); dev_priv 4152 drivers/gpu/drm/i915/i915_irq.c i9xx_error_irq_handler(dev_priv, eir, eir_stuck); dev_priv 4155 drivers/gpu/drm/i915/i915_irq.c i9xx_hpd_irq_handler(dev_priv, hotplug_status); dev_priv 4157 drivers/gpu/drm/i915/i915_irq.c i915_pipestat_irq_handler(dev_priv, iir, pipe_stats); dev_priv 4160 drivers/gpu/drm/i915/i915_irq.c enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 4165 drivers/gpu/drm/i915/i915_irq.c static void i965_irq_reset(struct drm_i915_private *dev_priv) dev_priv 4167 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 4169 drivers/gpu/drm/i915/i915_irq.c i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); dev_priv 4172 drivers/gpu/drm/i915/i915_irq.c i9xx_pipestat_irq_reset(dev_priv); dev_priv 4177 drivers/gpu/drm/i915/i915_irq.c static void i965_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv 4179 drivers/gpu/drm/i915/i915_irq.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 4187 drivers/gpu/drm/i915/i915_irq.c if (IS_G4X(dev_priv)) { dev_priv 4199 drivers/gpu/drm/i915/i915_irq.c dev_priv->irq_mask = dev_priv 4214 drivers/gpu/drm/i915/i915_irq.c if (IS_G4X(dev_priv)) dev_priv 4217 drivers/gpu/drm/i915/i915_irq.c GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); dev_priv 4221 drivers/gpu/drm/i915/i915_irq.c spin_lock_irq(&dev_priv->irq_lock); dev_priv 4222 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); dev_priv 4223 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); dev_priv 4224 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); dev_priv 4225 drivers/gpu/drm/i915/i915_irq.c spin_unlock_irq(&dev_priv->irq_lock); dev_priv 4227 drivers/gpu/drm/i915/i915_irq.c i915_enable_asle_pipestat(dev_priv); dev_priv 4230 drivers/gpu/drm/i915/i915_irq.c static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) dev_priv 4234 drivers/gpu/drm/i915/i915_irq.c lockdep_assert_held(&dev_priv->irq_lock); dev_priv 4238 drivers/gpu/drm/i915/i915_irq.c hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915); dev_priv 4243 drivers/gpu/drm/i915/i915_irq.c if (IS_G4X(dev_priv)) dev_priv 4248 drivers/gpu/drm/i915/i915_irq.c i915_hotplug_interrupt_update_locked(dev_priv, dev_priv 4257 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = arg; dev_priv 4260 drivers/gpu/drm/i915/i915_irq.c if (!intel_irqs_enabled(dev_priv)) dev_priv 4264 drivers/gpu/drm/i915/i915_irq.c disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 4279 drivers/gpu/drm/i915/i915_irq.c hotplug_status = i9xx_hpd_irq_ack(dev_priv); dev_priv 4283 drivers/gpu/drm/i915/i915_irq.c i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); dev_priv 4286 drivers/gpu/drm/i915/i915_irq.c i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); dev_priv 4291 drivers/gpu/drm/i915/i915_irq.c intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]); dev_priv 4294 drivers/gpu/drm/i915/i915_irq.c intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]); dev_priv 4297 drivers/gpu/drm/i915/i915_irq.c i9xx_error_irq_handler(dev_priv, eir, eir_stuck); dev_priv 4300 drivers/gpu/drm/i915/i915_irq.c i9xx_hpd_irq_handler(dev_priv, hotplug_status); dev_priv 4302 drivers/gpu/drm/i915/i915_irq.c i965_pipestat_irq_handler(dev_priv, iir, pipe_stats); dev_priv 4305 drivers/gpu/drm/i915/i915_irq.c enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); dev_priv 4317 drivers/gpu/drm/i915/i915_irq.c void intel_irq_init(struct drm_i915_private *dev_priv) dev_priv 4319 drivers/gpu/drm/i915/i915_irq.c struct drm_device *dev = &dev_priv->drm; dev_priv 4320 drivers/gpu/drm/i915/i915_irq.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 4323 drivers/gpu/drm/i915/i915_irq.c if (IS_I945GM(dev_priv)) dev_priv 4324 drivers/gpu/drm/i915/i915_irq.c i945gm_vblank_work_init(dev_priv); dev_priv 4326 drivers/gpu/drm/i915/i915_irq.c intel_hpd_init_work(dev_priv); dev_priv 4330 drivers/gpu/drm/i915/i915_irq.c INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); dev_priv 4332 drivers/gpu/drm/i915/i915_irq.c dev_priv->l3_parity.remap_info[i] = NULL; dev_priv 4335 drivers/gpu/drm/i915/i915_irq.c if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11) dev_priv 4336 drivers/gpu/drm/i915/i915_irq.c dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16; dev_priv 4339 drivers/gpu/drm/i915/i915_irq.c if (IS_VALLEYVIEW(dev_priv)) dev_priv 4341 drivers/gpu/drm/i915/i915_irq.c dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; dev_priv 4343 drivers/gpu/drm/i915/i915_irq.c dev_priv->pm_rps_events = (GEN6_PM_RP_UP_THRESHOLD | dev_priv 4348 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) > 9) dev_priv 4349 drivers/gpu/drm/i915/i915_irq.c GEM_WARN_ON(dev_priv->pm_rps_events & 0xffff0000); dev_priv 4359 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) <= 7) dev_priv 4362 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 4373 drivers/gpu/drm/i915/i915_irq.c dev_priv->display_irqs_enabled = true; dev_priv 4374 drivers/gpu/drm/i915/i915_irq.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 4375 drivers/gpu/drm/i915/i915_irq.c dev_priv->display_irqs_enabled = false; dev_priv 4377 drivers/gpu/drm/i915/i915_irq.c dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD; dev_priv 4384 drivers/gpu/drm/i915/i915_irq.c dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv); dev_priv 4386 drivers/gpu/drm/i915/i915_irq.c if (HAS_GMCH(dev_priv)) { dev_priv 4387 drivers/gpu/drm/i915/i915_irq.c if (I915_HAS_HOTPLUG(dev_priv)) dev_priv 4388 drivers/gpu/drm/i915/i915_irq.c dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; dev_priv 4390 drivers/gpu/drm/i915/i915_irq.c if (HAS_PCH_MCC(dev_priv)) dev_priv 4392 drivers/gpu/drm/i915/i915_irq.c dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup; dev_priv 4393 drivers/gpu/drm/i915/i915_irq.c else if (INTEL_GEN(dev_priv) >= 11) dev_priv 4394 drivers/gpu/drm/i915/i915_irq.c dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup; dev_priv 4395 drivers/gpu/drm/i915/i915_irq.c else if (IS_GEN9_LP(dev_priv)) dev_priv 4396 drivers/gpu/drm/i915/i915_irq.c dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; dev_priv 4397 drivers/gpu/drm/i915/i915_irq.c else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) dev_priv 4398 drivers/gpu/drm/i915/i915_irq.c dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; dev_priv 4400 drivers/gpu/drm/i915/i915_irq.c dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; dev_priv 4421 drivers/gpu/drm/i915/i915_irq.c static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv) dev_priv 4423 drivers/gpu/drm/i915/i915_irq.c if (HAS_GMCH(dev_priv)) { dev_priv 4424 drivers/gpu/drm/i915/i915_irq.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 4426 drivers/gpu/drm/i915/i915_irq.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 4428 drivers/gpu/drm/i915/i915_irq.c else if (IS_GEN(dev_priv, 4)) dev_priv 4430 drivers/gpu/drm/i915/i915_irq.c else if (IS_GEN(dev_priv, 3)) dev_priv 4435 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 4437 drivers/gpu/drm/i915/i915_irq.c else if (INTEL_GEN(dev_priv) >= 8) dev_priv 4444 drivers/gpu/drm/i915/i915_irq.c static void intel_irq_reset(struct drm_i915_private *dev_priv) dev_priv 4446 drivers/gpu/drm/i915/i915_irq.c if (HAS_GMCH(dev_priv)) { dev_priv 4447 drivers/gpu/drm/i915/i915_irq.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 4448 drivers/gpu/drm/i915/i915_irq.c cherryview_irq_reset(dev_priv); dev_priv 4449 drivers/gpu/drm/i915/i915_irq.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 4450 drivers/gpu/drm/i915/i915_irq.c valleyview_irq_reset(dev_priv); dev_priv 4451 drivers/gpu/drm/i915/i915_irq.c else if (IS_GEN(dev_priv, 4)) dev_priv 4452 drivers/gpu/drm/i915/i915_irq.c i965_irq_reset(dev_priv); dev_priv 4453 drivers/gpu/drm/i915/i915_irq.c else if (IS_GEN(dev_priv, 3)) dev_priv 4454 drivers/gpu/drm/i915/i915_irq.c i915_irq_reset(dev_priv); dev_priv 4456 drivers/gpu/drm/i915/i915_irq.c i8xx_irq_reset(dev_priv); dev_priv 4458 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 4459 drivers/gpu/drm/i915/i915_irq.c gen11_irq_reset(dev_priv); dev_priv 4460 drivers/gpu/drm/i915/i915_irq.c else if (INTEL_GEN(dev_priv) >= 8) dev_priv 4461 drivers/gpu/drm/i915/i915_irq.c gen8_irq_reset(dev_priv); dev_priv 4463 drivers/gpu/drm/i915/i915_irq.c ironlake_irq_reset(dev_priv); dev_priv 4467 drivers/gpu/drm/i915/i915_irq.c static void intel_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv 4469 drivers/gpu/drm/i915/i915_irq.c if (HAS_GMCH(dev_priv)) { dev_priv 4470 drivers/gpu/drm/i915/i915_irq.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 4471 drivers/gpu/drm/i915/i915_irq.c cherryview_irq_postinstall(dev_priv); dev_priv 4472 drivers/gpu/drm/i915/i915_irq.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 4473 drivers/gpu/drm/i915/i915_irq.c valleyview_irq_postinstall(dev_priv); dev_priv 4474 drivers/gpu/drm/i915/i915_irq.c else if (IS_GEN(dev_priv, 4)) dev_priv 4475 drivers/gpu/drm/i915/i915_irq.c i965_irq_postinstall(dev_priv); dev_priv 4476 drivers/gpu/drm/i915/i915_irq.c else if (IS_GEN(dev_priv, 3)) dev_priv 4477 drivers/gpu/drm/i915/i915_irq.c i915_irq_postinstall(dev_priv); dev_priv 4479 drivers/gpu/drm/i915/i915_irq.c i8xx_irq_postinstall(dev_priv); dev_priv 4481 drivers/gpu/drm/i915/i915_irq.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 4482 drivers/gpu/drm/i915/i915_irq.c gen11_irq_postinstall(dev_priv); dev_priv 4483 drivers/gpu/drm/i915/i915_irq.c else if (INTEL_GEN(dev_priv) >= 8) dev_priv 4484 drivers/gpu/drm/i915/i915_irq.c gen8_irq_postinstall(dev_priv); dev_priv 4486 drivers/gpu/drm/i915/i915_irq.c ironlake_irq_postinstall(dev_priv); dev_priv 4501 drivers/gpu/drm/i915/i915_irq.c int intel_irq_install(struct drm_i915_private *dev_priv) dev_priv 4503 drivers/gpu/drm/i915/i915_irq.c int irq = dev_priv->drm.pdev->irq; dev_priv 4511 drivers/gpu/drm/i915/i915_irq.c dev_priv->runtime_pm.irqs_enabled = true; dev_priv 4513 drivers/gpu/drm/i915/i915_irq.c dev_priv->drm.irq_enabled = true; dev_priv 4515 drivers/gpu/drm/i915/i915_irq.c intel_irq_reset(dev_priv); dev_priv 4517 drivers/gpu/drm/i915/i915_irq.c ret = request_irq(irq, intel_irq_handler(dev_priv), dev_priv 4518 drivers/gpu/drm/i915/i915_irq.c IRQF_SHARED, DRIVER_NAME, dev_priv); dev_priv 4520 drivers/gpu/drm/i915/i915_irq.c dev_priv->drm.irq_enabled = false; dev_priv 4524 drivers/gpu/drm/i915/i915_irq.c intel_irq_postinstall(dev_priv); dev_priv 4536 drivers/gpu/drm/i915/i915_irq.c void intel_irq_uninstall(struct drm_i915_private *dev_priv) dev_priv 4538 drivers/gpu/drm/i915/i915_irq.c int irq = dev_priv->drm.pdev->irq; dev_priv 4546 drivers/gpu/drm/i915/i915_irq.c if (!dev_priv->drm.irq_enabled) dev_priv 4549 drivers/gpu/drm/i915/i915_irq.c dev_priv->drm.irq_enabled = false; dev_priv 4551 drivers/gpu/drm/i915/i915_irq.c intel_irq_reset(dev_priv); dev_priv 4553 drivers/gpu/drm/i915/i915_irq.c free_irq(irq, dev_priv); dev_priv 4555 drivers/gpu/drm/i915/i915_irq.c intel_hpd_cancel_work(dev_priv); dev_priv 4556 drivers/gpu/drm/i915/i915_irq.c dev_priv->runtime_pm.irqs_enabled = false; dev_priv 4566 drivers/gpu/drm/i915/i915_irq.c void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) dev_priv 4568 drivers/gpu/drm/i915/i915_irq.c intel_irq_reset(dev_priv); dev_priv 4569 drivers/gpu/drm/i915/i915_irq.c dev_priv->runtime_pm.irqs_enabled = false; dev_priv 4570 drivers/gpu/drm/i915/i915_irq.c intel_synchronize_irq(dev_priv); dev_priv 4580 drivers/gpu/drm/i915/i915_irq.c void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) dev_priv 4582 drivers/gpu/drm/i915/i915_irq.c dev_priv->runtime_pm.irqs_enabled = true; dev_priv 4583 drivers/gpu/drm/i915/i915_irq.c intel_irq_reset(dev_priv); dev_priv 4584 drivers/gpu/drm/i915/i915_irq.c intel_irq_postinstall(dev_priv); dev_priv 4587 drivers/gpu/drm/i915/i915_irq.c bool intel_irqs_enabled(struct drm_i915_private *dev_priv) dev_priv 4593 drivers/gpu/drm/i915/i915_irq.c return dev_priv->runtime_pm.irqs_enabled; dev_priv 26 drivers/gpu/drm/i915/i915_irq.h void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); dev_priv 28 drivers/gpu/drm/i915/i915_irq.h void intel_irq_init(struct drm_i915_private *dev_priv); dev_priv 29 drivers/gpu/drm/i915/i915_irq.h void intel_irq_fini(struct drm_i915_private *dev_priv); dev_priv 30 drivers/gpu/drm/i915/i915_irq.h int intel_irq_install(struct drm_i915_private *dev_priv); dev_priv 31 drivers/gpu/drm/i915/i915_irq.h void intel_irq_uninstall(struct drm_i915_private *dev_priv); dev_priv 33 drivers/gpu/drm/i915/i915_irq.h u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, dev_priv 36 drivers/gpu/drm/i915/i915_irq.h i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, dev_priv 40 drivers/gpu/drm/i915/i915_irq.h i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, dev_priv 43 drivers/gpu/drm/i915/i915_irq.h void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); dev_priv 44 drivers/gpu/drm/i915/i915_irq.h void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); dev_priv 46 drivers/gpu/drm/i915/i915_irq.h void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, dev_priv 49 drivers/gpu/drm/i915/i915_irq.h void ilk_update_display_irq(struct drm_i915_private *dev_priv, dev_priv 53 drivers/gpu/drm/i915/i915_irq.h ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits) dev_priv 55 drivers/gpu/drm/i915/i915_irq.h ilk_update_display_irq(dev_priv, bits, bits); dev_priv 58 drivers/gpu/drm/i915/i915_irq.h ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits) dev_priv 60 drivers/gpu/drm/i915/i915_irq.h ilk_update_display_irq(dev_priv, bits, 0); dev_priv 62 drivers/gpu/drm/i915/i915_irq.h void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, dev_priv 66 drivers/gpu/drm/i915/i915_irq.h static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, dev_priv 69 drivers/gpu/drm/i915/i915_irq.h bdw_update_pipe_irq(dev_priv, pipe, bits, bits); dev_priv 71 drivers/gpu/drm/i915/i915_irq.h static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, dev_priv 74 drivers/gpu/drm/i915/i915_irq.h bdw_update_pipe_irq(dev_priv, pipe, bits, 0); dev_priv 76 drivers/gpu/drm/i915/i915_irq.h void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, dev_priv 80 drivers/gpu/drm/i915/i915_irq.h ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits) dev_priv 82 drivers/gpu/drm/i915/i915_irq.h ibx_display_interrupt_update(dev_priv, bits, bits); dev_priv 85 drivers/gpu/drm/i915/i915_irq.h ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits) dev_priv 87 drivers/gpu/drm/i915/i915_irq.h ibx_display_interrupt_update(dev_priv, bits, 0); dev_priv 90 drivers/gpu/drm/i915/i915_irq.h void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); dev_priv 91 drivers/gpu/drm/i915/i915_irq.h void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); dev_priv 92 drivers/gpu/drm/i915/i915_irq.h void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv); dev_priv 93 drivers/gpu/drm/i915/i915_irq.h void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); dev_priv 94 drivers/gpu/drm/i915/i915_irq.h void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); dev_priv 95 drivers/gpu/drm/i915/i915_irq.h void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); dev_priv 96 drivers/gpu/drm/i915/i915_irq.h void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); dev_priv 99 drivers/gpu/drm/i915/i915_irq.h void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); dev_priv 100 drivers/gpu/drm/i915/i915_irq.h void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); dev_priv 101 drivers/gpu/drm/i915/i915_irq.h bool intel_irqs_enabled(struct drm_i915_private *dev_priv); dev_priv 105 drivers/gpu/drm/i915/i915_irq.h void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, dev_priv 107 drivers/gpu/drm/i915/i915_irq.h void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, dev_priv 97 drivers/gpu/drm/i915/i915_memcpy.c void i915_memcpy_init_early(struct drm_i915_private *dev_priv) dev_priv 370 drivers/gpu/drm/i915/i915_perf.c static void free_oa_config(struct drm_i915_private *dev_priv, dev_priv 382 drivers/gpu/drm/i915/i915_perf.c static void put_oa_config(struct drm_i915_private *dev_priv, dev_priv 388 drivers/gpu/drm/i915/i915_perf.c free_oa_config(dev_priv, oa_config); dev_priv 391 drivers/gpu/drm/i915/i915_perf.c static int get_oa_config(struct drm_i915_private *dev_priv, dev_priv 398 drivers/gpu/drm/i915/i915_perf.c *out_config = &dev_priv->perf.test_config; dev_priv 399 drivers/gpu/drm/i915/i915_perf.c atomic_inc(&dev_priv->perf.test_config.ref_count); dev_priv 403 drivers/gpu/drm/i915/i915_perf.c ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock); dev_priv 407 drivers/gpu/drm/i915/i915_perf.c *out_config = idr_find(&dev_priv->perf.metrics_idr, metrics_set); dev_priv 413 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->perf.metrics_lock); dev_priv 420 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 427 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 459 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 482 drivers/gpu/drm/i915/i915_perf.c hw_tail = dev_priv->perf.ops.oa_hw_tail_read(stream); dev_priv 658 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 743 drivers/gpu/drm/i915/i915_perf.c if (__ratelimit(&dev_priv->perf.spurious_report_rs)) dev_priv 758 drivers/gpu/drm/i915/i915_perf.c if (!(report32[0] & dev_priv->perf.gen8_valid_ctx_bit)) dev_priv 792 drivers/gpu/drm/i915/i915_perf.c if (!dev_priv->perf.exclusive_stream->ctx || dev_priv 801 drivers/gpu/drm/i915/i915_perf.c if (dev_priv->perf.exclusive_stream->ctx && dev_priv 867 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 899 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.oa_disable(stream); dev_priv 900 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.oa_enable(stream); dev_priv 946 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 1020 drivers/gpu/drm/i915/i915_perf.c if (__ratelimit(&dev_priv->perf.spurious_report_rs)) dev_priv 1078 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 1092 drivers/gpu/drm/i915/i915_perf.c oastatus1 &= ~dev_priv->perf.gen7_latched_oastatus1; dev_priv 1123 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.oa_disable(stream); dev_priv 1124 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.oa_enable(stream); dev_priv 1134 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.gen7_latched_oastatus1 |= dev_priv 1199 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 1201 drivers/gpu/drm/i915/i915_perf.c return dev_priv->perf.ops.read(stream, buf, count, offset); dev_priv 1207 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *i915 = stream->dev_priv; dev_priv 1251 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *i915 = stream->dev_priv; dev_priv 1333 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 1341 drivers/gpu/drm/i915/i915_perf.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 1343 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1350 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *i915 = stream->dev_priv; dev_priv 1364 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 1366 drivers/gpu/drm/i915/i915_perf.c BUG_ON(stream != dev_priv->perf.exclusive_stream); dev_priv 1372 drivers/gpu/drm/i915/i915_perf.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 1373 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.exclusive_stream = NULL; dev_priv 1374 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.disable_metric_set(stream); dev_priv 1375 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1379 drivers/gpu/drm/i915/i915_perf.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 1380 drivers/gpu/drm/i915/i915_perf.c intel_runtime_pm_put(&dev_priv->runtime_pm, stream->wakeref); dev_priv 1385 drivers/gpu/drm/i915/i915_perf.c put_oa_config(dev_priv, stream->oa_config); dev_priv 1387 drivers/gpu/drm/i915/i915_perf.c if (dev_priv->perf.spurious_report_rs.missed) { dev_priv 1389 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.spurious_report_rs.missed); dev_priv 1395 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 1422 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.gen7_latched_oastatus1 = 0; dev_priv 1445 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 1506 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 1513 drivers/gpu/drm/i915/i915_perf.c ret = i915_mutex_lock_interruptible(&dev_priv->drm); dev_priv 1520 drivers/gpu/drm/i915/i915_perf.c bo = i915_gem_object_create_shmem(dev_priv, OA_BUFFER_SIZE); dev_priv 1560 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1564 drivers/gpu/drm/i915/i915_perf.c static void config_oa_regs(struct drm_i915_private *dev_priv, dev_priv 1606 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 1624 drivers/gpu/drm/i915/i915_perf.c config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len); dev_priv 1627 drivers/gpu/drm/i915/i915_perf.c config_oa_regs(dev_priv, oa_config->b_counter_regs, dev_priv 1635 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 1862 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *i915 = stream->dev_priv; dev_priv 1947 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 1974 drivers/gpu/drm/i915/i915_perf.c if (IS_GEN_RANGE(dev_priv, 9, 11)) { dev_priv 1989 drivers/gpu/drm/i915/i915_perf.c config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len); dev_priv 1992 drivers/gpu/drm/i915/i915_perf.c config_oa_regs(dev_priv, oa_config->b_counter_regs, dev_priv 2000 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 2011 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 2023 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 2053 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 2088 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 2090 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.oa_enable(stream); dev_priv 2100 drivers/gpu/drm/i915/i915_perf.c struct intel_uncore *uncore = &stream->dev_priv->uncore; dev_priv 2111 drivers/gpu/drm/i915/i915_perf.c struct intel_uncore *uncore = &stream->dev_priv->uncore; dev_priv 2130 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 2132 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.oa_disable(stream); dev_priv 2169 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 2177 drivers/gpu/drm/i915/i915_perf.c if (!dev_priv->perf.metrics_kobj) { dev_priv 2187 drivers/gpu/drm/i915/i915_perf.c if (!dev_priv->perf.ops.enable_metric_set) { dev_priv 2196 drivers/gpu/drm/i915/i915_perf.c if (dev_priv->perf.exclusive_stream) { dev_priv 2208 drivers/gpu/drm/i915/i915_perf.c format_size = dev_priv->perf.oa_formats[props->oa_format].size; dev_priv 2218 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.oa_formats[props->oa_format].format; dev_priv 2232 drivers/gpu/drm/i915/i915_perf.c ret = get_oa_config(dev_priv, props->metrics_set, &stream->oa_config); dev_priv 2250 drivers/gpu/drm/i915/i915_perf.c stream->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 2251 drivers/gpu/drm/i915/i915_perf.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 2257 drivers/gpu/drm/i915/i915_perf.c ret = i915_mutex_lock_interruptible(&dev_priv->drm); dev_priv 2262 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.exclusive_stream = stream; dev_priv 2264 drivers/gpu/drm/i915/i915_perf.c ret = dev_priv->perf.ops.enable_metric_set(stream); dev_priv 2270 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 2281 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.exclusive_stream = NULL; dev_priv 2282 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.disable_metric_set(stream); dev_priv 2283 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 2289 drivers/gpu/drm/i915/i915_perf.c put_oa_config(dev_priv, stream->oa_config); dev_priv 2291 drivers/gpu/drm/i915/i915_perf.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 2292 drivers/gpu/drm/i915/i915_perf.c intel_runtime_pm_put(&dev_priv->runtime_pm, stream->wakeref); dev_priv 2382 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 2405 drivers/gpu/drm/i915/i915_perf.c mutex_lock(&dev_priv->perf.lock); dev_priv 2408 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->perf.lock); dev_priv 2411 drivers/gpu/drm/i915/i915_perf.c mutex_lock(&dev_priv->perf.lock); dev_priv 2413 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->perf.lock); dev_priv 2465 drivers/gpu/drm/i915/i915_perf.c static __poll_t i915_perf_poll_locked(struct drm_i915_private *dev_priv, dev_priv 2502 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 2505 drivers/gpu/drm/i915/i915_perf.c mutex_lock(&dev_priv->perf.lock); dev_priv 2506 drivers/gpu/drm/i915/i915_perf.c ret = i915_perf_poll_locked(dev_priv, stream, file, wait); dev_priv 2507 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->perf.lock); dev_priv 2604 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 2607 drivers/gpu/drm/i915/i915_perf.c mutex_lock(&dev_priv->perf.lock); dev_priv 2609 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->perf.lock); dev_priv 2654 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = stream->dev_priv; dev_priv 2656 drivers/gpu/drm/i915/i915_perf.c mutex_lock(&dev_priv->perf.lock); dev_priv 2658 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->perf.lock); dev_priv 2661 drivers/gpu/drm/i915/i915_perf.c drm_dev_put(&dev_priv->drm); dev_priv 2706 drivers/gpu/drm/i915/i915_perf.c i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv, dev_priv 2745 drivers/gpu/drm/i915/i915_perf.c if (IS_HASWELL(dev_priv) && specific_ctx) dev_priv 2766 drivers/gpu/drm/i915/i915_perf.c stream->dev_priv = dev_priv; dev_priv 2782 drivers/gpu/drm/i915/i915_perf.c list_add(&stream->link, &dev_priv->perf.streams); dev_priv 2801 drivers/gpu/drm/i915/i915_perf.c drm_dev_get(&dev_priv->drm); dev_priv 2819 drivers/gpu/drm/i915/i915_perf.c static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent) dev_priv 2822 drivers/gpu/drm/i915/i915_perf.c 1000ULL * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz); dev_priv 2840 drivers/gpu/drm/i915/i915_perf.c static int read_properties_unlocked(struct drm_i915_private *dev_priv, dev_priv 2906 drivers/gpu/drm/i915/i915_perf.c if (!dev_priv->perf.oa_formats[value].size) { dev_priv 2927 drivers/gpu/drm/i915/i915_perf.c oa_period = oa_exponent_to_ns(dev_priv, value); dev_priv 2990 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = dev->dev_private; dev_priv 2996 drivers/gpu/drm/i915/i915_perf.c if (!dev_priv->perf.initialized) { dev_priv 3009 drivers/gpu/drm/i915/i915_perf.c ret = read_properties_unlocked(dev_priv, dev_priv 3016 drivers/gpu/drm/i915/i915_perf.c mutex_lock(&dev_priv->perf.lock); dev_priv 3017 drivers/gpu/drm/i915/i915_perf.c ret = i915_perf_open_ioctl_locked(dev_priv, param, &props, file); dev_priv 3018 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->perf.lock); dev_priv 3031 drivers/gpu/drm/i915/i915_perf.c void i915_perf_register(struct drm_i915_private *dev_priv) dev_priv 3035 drivers/gpu/drm/i915/i915_perf.c if (!dev_priv->perf.initialized) dev_priv 3042 drivers/gpu/drm/i915/i915_perf.c mutex_lock(&dev_priv->perf.lock); dev_priv 3044 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.metrics_kobj = dev_priv 3046 drivers/gpu/drm/i915/i915_perf.c &dev_priv->drm.primary->kdev->kobj); dev_priv 3047 drivers/gpu/drm/i915/i915_perf.c if (!dev_priv->perf.metrics_kobj) dev_priv 3050 drivers/gpu/drm/i915/i915_perf.c sysfs_attr_init(&dev_priv->perf.test_config.sysfs_metric_id.attr); dev_priv 3052 drivers/gpu/drm/i915/i915_perf.c if (INTEL_GEN(dev_priv) >= 11) { dev_priv 3053 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_icl(dev_priv); dev_priv 3054 drivers/gpu/drm/i915/i915_perf.c } else if (IS_CANNONLAKE(dev_priv)) { dev_priv 3055 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_cnl(dev_priv); dev_priv 3056 drivers/gpu/drm/i915/i915_perf.c } else if (IS_COFFEELAKE(dev_priv)) { dev_priv 3057 drivers/gpu/drm/i915/i915_perf.c if (IS_CFL_GT2(dev_priv)) dev_priv 3058 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_cflgt2(dev_priv); dev_priv 3059 drivers/gpu/drm/i915/i915_perf.c if (IS_CFL_GT3(dev_priv)) dev_priv 3060 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_cflgt3(dev_priv); dev_priv 3061 drivers/gpu/drm/i915/i915_perf.c } else if (IS_GEMINILAKE(dev_priv)) { dev_priv 3062 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_glk(dev_priv); dev_priv 3063 drivers/gpu/drm/i915/i915_perf.c } else if (IS_KABYLAKE(dev_priv)) { dev_priv 3064 drivers/gpu/drm/i915/i915_perf.c if (IS_KBL_GT2(dev_priv)) dev_priv 3065 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_kblgt2(dev_priv); dev_priv 3066 drivers/gpu/drm/i915/i915_perf.c else if (IS_KBL_GT3(dev_priv)) dev_priv 3067 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_kblgt3(dev_priv); dev_priv 3068 drivers/gpu/drm/i915/i915_perf.c } else if (IS_BROXTON(dev_priv)) { dev_priv 3069 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_bxt(dev_priv); dev_priv 3070 drivers/gpu/drm/i915/i915_perf.c } else if (IS_SKYLAKE(dev_priv)) { dev_priv 3071 drivers/gpu/drm/i915/i915_perf.c if (IS_SKL_GT2(dev_priv)) dev_priv 3072 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_sklgt2(dev_priv); dev_priv 3073 drivers/gpu/drm/i915/i915_perf.c else if (IS_SKL_GT3(dev_priv)) dev_priv 3074 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_sklgt3(dev_priv); dev_priv 3075 drivers/gpu/drm/i915/i915_perf.c else if (IS_SKL_GT4(dev_priv)) dev_priv 3076 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_sklgt4(dev_priv); dev_priv 3077 drivers/gpu/drm/i915/i915_perf.c } else if (IS_CHERRYVIEW(dev_priv)) { dev_priv 3078 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_chv(dev_priv); dev_priv 3079 drivers/gpu/drm/i915/i915_perf.c } else if (IS_BROADWELL(dev_priv)) { dev_priv 3080 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_bdw(dev_priv); dev_priv 3081 drivers/gpu/drm/i915/i915_perf.c } else if (IS_HASWELL(dev_priv)) { dev_priv 3082 drivers/gpu/drm/i915/i915_perf.c i915_perf_load_test_config_hsw(dev_priv); dev_priv 3085 drivers/gpu/drm/i915/i915_perf.c if (dev_priv->perf.test_config.id == 0) dev_priv 3088 drivers/gpu/drm/i915/i915_perf.c ret = sysfs_create_group(dev_priv->perf.metrics_kobj, dev_priv 3089 drivers/gpu/drm/i915/i915_perf.c &dev_priv->perf.test_config.sysfs_metric); dev_priv 3093 drivers/gpu/drm/i915/i915_perf.c atomic_set(&dev_priv->perf.test_config.ref_count, 1); dev_priv 3098 drivers/gpu/drm/i915/i915_perf.c kobject_put(dev_priv->perf.metrics_kobj); dev_priv 3099 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.metrics_kobj = NULL; dev_priv 3102 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->perf.lock); dev_priv 3114 drivers/gpu/drm/i915/i915_perf.c void i915_perf_unregister(struct drm_i915_private *dev_priv) dev_priv 3116 drivers/gpu/drm/i915/i915_perf.c if (!dev_priv->perf.metrics_kobj) dev_priv 3119 drivers/gpu/drm/i915/i915_perf.c sysfs_remove_group(dev_priv->perf.metrics_kobj, dev_priv 3120 drivers/gpu/drm/i915/i915_perf.c &dev_priv->perf.test_config.sysfs_metric); dev_priv 3122 drivers/gpu/drm/i915/i915_perf.c kobject_put(dev_priv->perf.metrics_kobj); dev_priv 3123 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.metrics_kobj = NULL; dev_priv 3126 drivers/gpu/drm/i915/i915_perf.c static bool gen8_is_valid_flex_addr(struct drm_i915_private *dev_priv, u32 addr) dev_priv 3146 drivers/gpu/drm/i915/i915_perf.c static bool gen7_is_valid_b_counter_addr(struct drm_i915_private *dev_priv, u32 addr) dev_priv 3156 drivers/gpu/drm/i915/i915_perf.c static bool gen7_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) dev_priv 3167 drivers/gpu/drm/i915/i915_perf.c static bool gen8_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) dev_priv 3169 drivers/gpu/drm/i915/i915_perf.c return gen7_is_valid_mux_addr(dev_priv, addr) || dev_priv 3175 drivers/gpu/drm/i915/i915_perf.c static bool gen10_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) dev_priv 3177 drivers/gpu/drm/i915/i915_perf.c return gen8_is_valid_mux_addr(dev_priv, addr) || dev_priv 3183 drivers/gpu/drm/i915/i915_perf.c static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) dev_priv 3185 drivers/gpu/drm/i915/i915_perf.c return gen7_is_valid_mux_addr(dev_priv, addr) || dev_priv 3192 drivers/gpu/drm/i915/i915_perf.c static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) dev_priv 3194 drivers/gpu/drm/i915/i915_perf.c return gen7_is_valid_mux_addr(dev_priv, addr) || dev_priv 3217 drivers/gpu/drm/i915/i915_perf.c static struct i915_oa_reg *alloc_oa_regs(struct drm_i915_private *dev_priv, dev_priv 3218 drivers/gpu/drm/i915/i915_perf.c bool (*is_valid)(struct drm_i915_private *dev_priv, u32 addr), dev_priv 3248 drivers/gpu/drm/i915/i915_perf.c if (!is_valid(dev_priv, addr)) { dev_priv 3281 drivers/gpu/drm/i915/i915_perf.c static int create_dynamic_oa_sysfs_entry(struct drm_i915_private *dev_priv, dev_priv 3296 drivers/gpu/drm/i915/i915_perf.c return sysfs_create_group(dev_priv->perf.metrics_kobj, dev_priv 3316 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = dev->dev_private; dev_priv 3321 drivers/gpu/drm/i915/i915_perf.c if (!dev_priv->perf.initialized) { dev_priv 3326 drivers/gpu/drm/i915/i915_perf.c if (!dev_priv->perf.metrics_kobj) { dev_priv 3364 drivers/gpu/drm/i915/i915_perf.c alloc_oa_regs(dev_priv, dev_priv 3365 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.is_valid_mux_reg, dev_priv 3377 drivers/gpu/drm/i915/i915_perf.c alloc_oa_regs(dev_priv, dev_priv 3378 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.is_valid_b_counter_reg, dev_priv 3388 drivers/gpu/drm/i915/i915_perf.c if (INTEL_GEN(dev_priv) < 8) { dev_priv 3396 drivers/gpu/drm/i915/i915_perf.c alloc_oa_regs(dev_priv, dev_priv 3397 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.is_valid_flex_reg, dev_priv 3408 drivers/gpu/drm/i915/i915_perf.c err = mutex_lock_interruptible(&dev_priv->perf.metrics_lock); dev_priv 3415 drivers/gpu/drm/i915/i915_perf.c idr_for_each_entry(&dev_priv->perf.metrics_idr, tmp, id) { dev_priv 3423 drivers/gpu/drm/i915/i915_perf.c err = create_dynamic_oa_sysfs_entry(dev_priv, oa_config); dev_priv 3430 drivers/gpu/drm/i915/i915_perf.c oa_config->id = idr_alloc(&dev_priv->perf.metrics_idr, dev_priv 3439 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->perf.metrics_lock); dev_priv 3446 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->perf.metrics_lock); dev_priv 3448 drivers/gpu/drm/i915/i915_perf.c put_oa_config(dev_priv, oa_config); dev_priv 3467 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = dev->dev_private; dev_priv 3472 drivers/gpu/drm/i915/i915_perf.c if (!dev_priv->perf.initialized) { dev_priv 3482 drivers/gpu/drm/i915/i915_perf.c ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock); dev_priv 3486 drivers/gpu/drm/i915/i915_perf.c oa_config = idr_find(&dev_priv->perf.metrics_idr, *arg); dev_priv 3495 drivers/gpu/drm/i915/i915_perf.c sysfs_remove_group(dev_priv->perf.metrics_kobj, dev_priv 3498 drivers/gpu/drm/i915/i915_perf.c idr_remove(&dev_priv->perf.metrics_idr, *arg); dev_priv 3502 drivers/gpu/drm/i915/i915_perf.c put_oa_config(dev_priv, oa_config); dev_priv 3505 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->perf.metrics_lock); dev_priv 3561 drivers/gpu/drm/i915/i915_perf.c void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv 3563 drivers/gpu/drm/i915/i915_perf.c if (IS_HASWELL(dev_priv)) { dev_priv 3564 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.is_valid_b_counter_reg = dev_priv 3566 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.is_valid_mux_reg = dev_priv 3568 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.is_valid_flex_reg = NULL; dev_priv 3569 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.enable_metric_set = hsw_enable_metric_set; dev_priv 3570 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.disable_metric_set = hsw_disable_metric_set; dev_priv 3571 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.oa_enable = gen7_oa_enable; dev_priv 3572 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.oa_disable = gen7_oa_disable; dev_priv 3573 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.read = gen7_oa_read; dev_priv 3574 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.oa_hw_tail_read = dev_priv 3577 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.oa_formats = hsw_oa_formats; dev_priv 3578 drivers/gpu/drm/i915/i915_perf.c } else if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { dev_priv 3585 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.oa_formats = gen8_plus_oa_formats; dev_priv 3587 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.oa_enable = gen8_oa_enable; dev_priv 3588 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.oa_disable = gen8_oa_disable; dev_priv 3589 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.read = gen8_oa_read; dev_priv 3590 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; dev_priv 3592 drivers/gpu/drm/i915/i915_perf.c if (IS_GEN_RANGE(dev_priv, 8, 9)) { dev_priv 3593 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.is_valid_b_counter_reg = dev_priv 3595 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.is_valid_mux_reg = dev_priv 3597 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.is_valid_flex_reg = dev_priv 3600 drivers/gpu/drm/i915/i915_perf.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 3601 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.is_valid_mux_reg = dev_priv 3605 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.enable_metric_set = gen8_enable_metric_set; dev_priv 3606 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.disable_metric_set = gen8_disable_metric_set; dev_priv 3608 drivers/gpu/drm/i915/i915_perf.c if (IS_GEN(dev_priv, 8)) { dev_priv 3609 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ctx_oactxctrl_offset = 0x120; dev_priv 3610 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ctx_flexeu0_offset = 0x2ce; dev_priv 3612 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.gen8_valid_ctx_bit = BIT(25); dev_priv 3614 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ctx_oactxctrl_offset = 0x128; dev_priv 3615 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ctx_flexeu0_offset = 0x3de; dev_priv 3617 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.gen8_valid_ctx_bit = BIT(16); dev_priv 3619 drivers/gpu/drm/i915/i915_perf.c } else if (IS_GEN_RANGE(dev_priv, 10, 11)) { dev_priv 3620 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.is_valid_b_counter_reg = dev_priv 3622 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.is_valid_mux_reg = dev_priv 3624 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.is_valid_flex_reg = dev_priv 3627 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.enable_metric_set = gen8_enable_metric_set; dev_priv 3628 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ops.disable_metric_set = gen10_disable_metric_set; dev_priv 3630 drivers/gpu/drm/i915/i915_perf.c if (IS_GEN(dev_priv, 10)) { dev_priv 3631 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ctx_oactxctrl_offset = 0x128; dev_priv 3632 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ctx_flexeu0_offset = 0x3de; dev_priv 3634 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ctx_oactxctrl_offset = 0x124; dev_priv 3635 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.ctx_flexeu0_offset = 0x78e; dev_priv 3637 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.gen8_valid_ctx_bit = BIT(16); dev_priv 3641 drivers/gpu/drm/i915/i915_perf.c if (dev_priv->perf.ops.enable_metric_set) { dev_priv 3642 drivers/gpu/drm/i915/i915_perf.c INIT_LIST_HEAD(&dev_priv->perf.streams); dev_priv 3643 drivers/gpu/drm/i915/i915_perf.c mutex_init(&dev_priv->perf.lock); dev_priv 3646 drivers/gpu/drm/i915/i915_perf.c (RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz / 2); dev_priv 3647 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.sysctl_header = register_sysctl_table(dev_root); dev_priv 3649 drivers/gpu/drm/i915/i915_perf.c mutex_init(&dev_priv->perf.metrics_lock); dev_priv 3650 drivers/gpu/drm/i915/i915_perf.c idr_init(&dev_priv->perf.metrics_idr); dev_priv 3662 drivers/gpu/drm/i915/i915_perf.c ratelimit_state_init(&dev_priv->perf.spurious_report_rs, dev_priv 3668 drivers/gpu/drm/i915/i915_perf.c ratelimit_set_flags(&dev_priv->perf.spurious_report_rs, dev_priv 3671 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.initialized = true; dev_priv 3677 drivers/gpu/drm/i915/i915_perf.c struct drm_i915_private *dev_priv = data; dev_priv 3680 drivers/gpu/drm/i915/i915_perf.c put_oa_config(dev_priv, oa_config); dev_priv 3689 drivers/gpu/drm/i915/i915_perf.c void i915_perf_fini(struct drm_i915_private *dev_priv) dev_priv 3691 drivers/gpu/drm/i915/i915_perf.c if (!dev_priv->perf.initialized) dev_priv 3694 drivers/gpu/drm/i915/i915_perf.c idr_for_each(&dev_priv->perf.metrics_idr, destroy_config, dev_priv); dev_priv 3695 drivers/gpu/drm/i915/i915_perf.c idr_destroy(&dev_priv->perf.metrics_idr); dev_priv 3697 drivers/gpu/drm/i915/i915_perf.c unregister_sysctl_table(dev_priv->perf.sysctl_header); dev_priv 3699 drivers/gpu/drm/i915/i915_perf.c memset(&dev_priv->perf.ops, 0, sizeof(dev_priv->perf.ops)); dev_priv 3701 drivers/gpu/drm/i915/i915_perf.c dev_priv->perf.initialized = false; dev_priv 34 drivers/gpu/drm/i915/i915_query.c static int query_topology_info(struct drm_i915_private *dev_priv, dev_priv 37 drivers/gpu/drm/i915/i915_query.c const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; dev_priv 145 drivers/gpu/drm/i915/i915_query.c static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, dev_priv 153 drivers/gpu/drm/i915/i915_query.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 182 drivers/gpu/drm/i915/i915_query.c ret = i915_query_funcs[func_idx](dev_priv, &item); dev_priv 208 drivers/gpu/drm/i915/i915_reg.h #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset) dev_priv 251 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ dev_priv 252 drivers/gpu/drm/i915/i915_reg.h INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \ dev_priv 253 drivers/gpu/drm/i915/i915_reg.h DISPLAY_MMIO_BASE(dev_priv)) dev_priv 254 drivers/gpu/drm/i915/i915_reg.h #define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \ dev_priv 255 drivers/gpu/drm/i915/i915_reg.h INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ dev_priv 256 drivers/gpu/drm/i915/i915_reg.h DISPLAY_MMIO_BASE(dev_priv)) dev_priv 258 drivers/gpu/drm/i915/i915_reg.h #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ dev_priv 259 drivers/gpu/drm/i915/i915_reg.h INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ dev_priv 260 drivers/gpu/drm/i915/i915_reg.h DISPLAY_MMIO_BASE(dev_priv)) dev_priv 1273 drivers/gpu/drm/i915/i915_reg.h #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) dev_priv 2999 drivers/gpu/drm/i915/i915_reg.h #define GT_PARITY_ERROR(dev_priv) \ dev_priv 3001 drivers/gpu/drm/i915/i915_reg.h (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) dev_priv 3191 drivers/gpu/drm/i915/i915_reg.h #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \ dev_priv 3209 drivers/gpu/drm/i915/i915_reg.h #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ dev_priv 3218 drivers/gpu/drm/i915/i915_reg.h #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ dev_priv 3233 drivers/gpu/drm/i915/i915_reg.h #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ dev_priv 3241 drivers/gpu/drm/i915/i915_reg.h #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ dev_priv 3242 drivers/gpu/drm/i915/i915_reg.h #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ dev_priv 3248 drivers/gpu/drm/i915/i915_reg.h #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ dev_priv 3254 drivers/gpu/drm/i915/i915_reg.h #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) dev_priv 3255 drivers/gpu/drm/i915/i915_reg.h #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) dev_priv 3256 drivers/gpu/drm/i915/i915_reg.h #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) dev_priv 3353 drivers/gpu/drm/i915/i915_reg.h #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) dev_priv 3354 drivers/gpu/drm/i915/i915_reg.h #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) dev_priv 3355 drivers/gpu/drm/i915/i915_reg.h #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) dev_priv 3427 drivers/gpu/drm/i915/i915_reg.h #define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200) dev_priv 3567 drivers/gpu/drm/i915/i915_reg.h #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ dev_priv 3914 drivers/gpu/drm/i915/i915_reg.h #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \ dev_priv 3915 drivers/gpu/drm/i915/i915_reg.h (IS_GEN9_LP(dev_priv) ? \ dev_priv 3923 drivers/gpu/drm/i915/i915_reg.h #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \ dev_priv 3924 drivers/gpu/drm/i915/i915_reg.h (IS_GEN9_LP(dev_priv) ? \ dev_priv 4204 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) dev_priv 4241 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) dev_priv 4248 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */ dev_priv 4250 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40) dev_priv 4275 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44) dev_priv 4278 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */ dev_priv 4390 drivers/gpu/drm/i915/i915_reg.h #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) dev_priv 4420 drivers/gpu/drm/i915/i915_reg.h #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) dev_priv 4502 drivers/gpu/drm/i915/i915_reg.h #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) dev_priv 4704 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ dev_priv 4777 drivers/gpu/drm/i915/i915_reg.h #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) dev_priv 4795 drivers/gpu/drm/i915/i915_reg.h #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) dev_priv 4807 drivers/gpu/drm/i915/i915_reg.h #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) dev_priv 4809 drivers/gpu/drm/i915/i915_reg.h #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250) dev_priv 4810 drivers/gpu/drm/i915/i915_reg.h #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350) dev_priv 4814 drivers/gpu/drm/i915/i915_reg.h #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254) dev_priv 4815 drivers/gpu/drm/i915/i915_reg.h #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354) dev_priv 4819 drivers/gpu/drm/i915/i915_reg.h #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260) dev_priv 4820 drivers/gpu/drm/i915/i915_reg.h #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360) dev_priv 4825 drivers/gpu/drm/i915/i915_reg.h #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */ dev_priv 4848 drivers/gpu/drm/i915/i915_reg.h #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254) dev_priv 4870 drivers/gpu/drm/i915/i915_reg.h #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260) dev_priv 5495 drivers/gpu/drm/i915/i915_reg.h #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) dev_priv 5496 drivers/gpu/drm/i915/i915_reg.h #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) dev_priv 5497 drivers/gpu/drm/i915/i915_reg.h #define _DPA_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64018) dev_priv 5498 drivers/gpu/drm/i915/i915_reg.h #define _DPA_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6401c) dev_priv 5499 drivers/gpu/drm/i915/i915_reg.h #define _DPA_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64020) dev_priv 5500 drivers/gpu/drm/i915/i915_reg.h #define _DPA_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64024) dev_priv 5502 drivers/gpu/drm/i915/i915_reg.h #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) dev_priv 5503 drivers/gpu/drm/i915/i915_reg.h #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) dev_priv 5504 drivers/gpu/drm/i915/i915_reg.h #define _DPB_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64118) dev_priv 5505 drivers/gpu/drm/i915/i915_reg.h #define _DPB_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6411c) dev_priv 5506 drivers/gpu/drm/i915/i915_reg.h #define _DPB_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64120) dev_priv 5507 drivers/gpu/drm/i915/i915_reg.h #define _DPB_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64124) dev_priv 5509 drivers/gpu/drm/i915/i915_reg.h #define _DPC_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64210) dev_priv 5510 drivers/gpu/drm/i915/i915_reg.h #define _DPC_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64214) dev_priv 5511 drivers/gpu/drm/i915/i915_reg.h #define _DPC_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64218) dev_priv 5512 drivers/gpu/drm/i915/i915_reg.h #define _DPC_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6421c) dev_priv 5513 drivers/gpu/drm/i915/i915_reg.h #define _DPC_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64220) dev_priv 5514 drivers/gpu/drm/i915/i915_reg.h #define _DPC_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64224) dev_priv 5516 drivers/gpu/drm/i915/i915_reg.h #define _DPD_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64310) dev_priv 5517 drivers/gpu/drm/i915/i915_reg.h #define _DPD_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64314) dev_priv 5518 drivers/gpu/drm/i915/i915_reg.h #define _DPD_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64318) dev_priv 5519 drivers/gpu/drm/i915/i915_reg.h #define _DPD_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6431c) dev_priv 5520 drivers/gpu/drm/i915/i915_reg.h #define _DPD_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64320) dev_priv 5521 drivers/gpu/drm/i915/i915_reg.h #define _DPD_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64324) dev_priv 5523 drivers/gpu/drm/i915/i915_reg.h #define _DPE_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64410) dev_priv 5524 drivers/gpu/drm/i915/i915_reg.h #define _DPE_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64414) dev_priv 5525 drivers/gpu/drm/i915/i915_reg.h #define _DPE_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64418) dev_priv 5526 drivers/gpu/drm/i915/i915_reg.h #define _DPE_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6441c) dev_priv 5527 drivers/gpu/drm/i915/i915_reg.h #define _DPE_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64420) dev_priv 5528 drivers/gpu/drm/i915/i915_reg.h #define _DPE_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64424) dev_priv 5530 drivers/gpu/drm/i915/i915_reg.h #define _DPF_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64510) dev_priv 5531 drivers/gpu/drm/i915/i915_reg.h #define _DPF_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64514) dev_priv 5532 drivers/gpu/drm/i915/i915_reg.h #define _DPF_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64518) dev_priv 5533 drivers/gpu/drm/i915/i915_reg.h #define _DPF_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6451c) dev_priv 5534 drivers/gpu/drm/i915/i915_reg.h #define _DPF_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64520) dev_priv 5535 drivers/gpu/drm/i915/i915_reg.h #define _DPF_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64524) dev_priv 5829 drivers/gpu/drm/i915/i915_reg.h #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) dev_priv 5864 drivers/gpu/drm/i915/i915_reg.h #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) dev_priv 5875 drivers/gpu/drm/i915/i915_reg.h #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) dev_priv 5891 drivers/gpu/drm/i915/i915_reg.h #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) dev_priv 6310 drivers/gpu/drm/i915/i915_reg.h #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) dev_priv 6311 drivers/gpu/drm/i915/i915_reg.h #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) dev_priv 6312 drivers/gpu/drm/i915/i915_reg.h #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) dev_priv 6316 drivers/gpu/drm/i915/i915_reg.h #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) dev_priv 6317 drivers/gpu/drm/i915/i915_reg.h #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) dev_priv 6318 drivers/gpu/drm/i915/i915_reg.h #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) dev_priv 6321 drivers/gpu/drm/i915/i915_reg.h #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) dev_priv 6322 drivers/gpu/drm/i915/i915_reg.h #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) dev_priv 6326 drivers/gpu/drm/i915/i915_reg.h #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) dev_priv 6331 drivers/gpu/drm/i915/i915_reg.h #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) dev_priv 6332 drivers/gpu/drm/i915/i915_reg.h #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) dev_priv 6333 drivers/gpu/drm/i915/i915_reg.h #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) dev_priv 6334 drivers/gpu/drm/i915/i915_reg.h #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) dev_priv 6335 drivers/gpu/drm/i915/i915_reg.h #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) dev_priv 6336 drivers/gpu/drm/i915/i915_reg.h #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) dev_priv 6337 drivers/gpu/drm/i915/i915_reg.h #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) dev_priv 6338 drivers/gpu/drm/i915/i915_reg.h #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) dev_priv 8990 drivers/gpu/drm/i915/i915_reg.h #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) dev_priv 10580 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) dev_priv 10581 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) dev_priv 10590 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) dev_priv 10591 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) dev_priv 10593 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) dev_priv 10594 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) dev_priv 10629 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) dev_priv 10630 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) dev_priv 10652 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) dev_priv 10653 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) dev_priv 10657 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) dev_priv 10658 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) dev_priv 10662 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) dev_priv 10663 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) dev_priv 10667 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) dev_priv 10668 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) dev_priv 10672 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) dev_priv 10673 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) dev_priv 10680 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) dev_priv 10681 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) dev_priv 10688 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) dev_priv 10689 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) dev_priv 10692 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) dev_priv 10693 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) dev_priv 10696 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) dev_priv 10697 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) dev_priv 10700 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) dev_priv 10701 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) dev_priv 10704 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) dev_priv 10705 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) dev_priv 10708 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) dev_priv 10709 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) dev_priv 10712 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) dev_priv 10713 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) dev_priv 10716 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) dev_priv 10717 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) dev_priv 10722 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) dev_priv 10723 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) dev_priv 10733 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) dev_priv 10734 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) dev_priv 10739 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) dev_priv 10740 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) dev_priv 10745 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) dev_priv 10746 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) dev_priv 10752 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) dev_priv 10753 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) dev_priv 10762 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) dev_priv 10763 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) dev_priv 10776 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) dev_priv 10777 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) dev_priv 10782 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4) dev_priv 10783 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4) dev_priv 10786 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098) dev_priv 10787 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898) dev_priv 10791 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) dev_priv 10792 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) dev_priv 10796 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) dev_priv 10797 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) dev_priv 10800 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) dev_priv 10801 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) dev_priv 10803 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) dev_priv 10804 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) dev_priv 10816 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) dev_priv 10817 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) dev_priv 10834 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) dev_priv 10835 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) dev_priv 10841 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) dev_priv 10842 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) dev_priv 11090 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) dev_priv 11091 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) dev_priv 11094 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088) dev_priv 11095 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888) dev_priv 11102 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) dev_priv 11103 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) dev_priv 11108 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) dev_priv 11109 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) dev_priv 11111 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) dev_priv 11112 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) dev_priv 11117 drivers/gpu/drm/i915/i915_reg.h #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) dev_priv 11131 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) dev_priv 11132 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) dev_priv 11164 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) dev_priv 11165 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) dev_priv 11171 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) dev_priv 11172 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) dev_priv 11177 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) dev_priv 11178 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) dev_priv 11186 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) dev_priv 11187 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) dev_priv 11192 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) dev_priv 11193 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) dev_priv 11196 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) dev_priv 11197 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) dev_priv 36 drivers/gpu/drm/i915/i915_suspend.c static void i915_save_display(struct drm_i915_private *dev_priv) dev_priv 39 drivers/gpu/drm/i915/i915_suspend.c if (INTEL_GEN(dev_priv) <= 4) dev_priv 40 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); dev_priv 43 drivers/gpu/drm/i915/i915_suspend.c if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) dev_priv 44 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); dev_priv 47 drivers/gpu/drm/i915/i915_suspend.c static void i915_restore_display(struct drm_i915_private *dev_priv) dev_priv 50 drivers/gpu/drm/i915/i915_suspend.c if (INTEL_GEN(dev_priv) <= 4) dev_priv 51 drivers/gpu/drm/i915/i915_suspend.c I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); dev_priv 54 drivers/gpu/drm/i915/i915_suspend.c intel_fbc_global_disable(dev_priv); dev_priv 57 drivers/gpu/drm/i915/i915_suspend.c if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) dev_priv 58 drivers/gpu/drm/i915/i915_suspend.c I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); dev_priv 60 drivers/gpu/drm/i915/i915_suspend.c i915_redisable_vga(dev_priv); dev_priv 63 drivers/gpu/drm/i915/i915_suspend.c int i915_save_state(struct drm_i915_private *dev_priv) dev_priv 65 drivers/gpu/drm/i915/i915_suspend.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 68 drivers/gpu/drm/i915/i915_suspend.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 70 drivers/gpu/drm/i915/i915_suspend.c i915_save_display(dev_priv); dev_priv 72 drivers/gpu/drm/i915/i915_suspend.c if (IS_GEN(dev_priv, 4)) dev_priv 74 drivers/gpu/drm/i915/i915_suspend.c &dev_priv->regfile.saveGCDGMBUS); dev_priv 77 drivers/gpu/drm/i915/i915_suspend.c if (INTEL_GEN(dev_priv) < 7) dev_priv 78 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); dev_priv 81 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); dev_priv 84 drivers/gpu/drm/i915/i915_suspend.c if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { dev_priv 86 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); dev_priv 87 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); dev_priv 90 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); dev_priv 91 drivers/gpu/drm/i915/i915_suspend.c } else if (IS_GEN(dev_priv, 2)) { dev_priv 93 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); dev_priv 94 drivers/gpu/drm/i915/i915_suspend.c } else if (HAS_GMCH(dev_priv)) { dev_priv 96 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); dev_priv 97 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); dev_priv 100 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); dev_priv 103 drivers/gpu/drm/i915/i915_suspend.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 108 drivers/gpu/drm/i915/i915_suspend.c int i915_restore_state(struct drm_i915_private *dev_priv) dev_priv 110 drivers/gpu/drm/i915/i915_suspend.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 113 drivers/gpu/drm/i915/i915_suspend.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 115 drivers/gpu/drm/i915/i915_suspend.c if (IS_GEN(dev_priv, 4)) dev_priv 117 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveGCDGMBUS); dev_priv 118 drivers/gpu/drm/i915/i915_suspend.c i915_restore_display(dev_priv); dev_priv 121 drivers/gpu/drm/i915/i915_suspend.c if (INTEL_GEN(dev_priv) < 7) dev_priv 122 drivers/gpu/drm/i915/i915_suspend.c I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | dev_priv 126 drivers/gpu/drm/i915/i915_suspend.c I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); dev_priv 129 drivers/gpu/drm/i915/i915_suspend.c if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { dev_priv 131 drivers/gpu/drm/i915/i915_suspend.c I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); dev_priv 132 drivers/gpu/drm/i915/i915_suspend.c I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); dev_priv 135 drivers/gpu/drm/i915/i915_suspend.c I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); dev_priv 136 drivers/gpu/drm/i915/i915_suspend.c } else if (IS_GEN(dev_priv, 2)) { dev_priv 138 drivers/gpu/drm/i915/i915_suspend.c I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); dev_priv 139 drivers/gpu/drm/i915/i915_suspend.c } else if (HAS_GMCH(dev_priv)) { dev_priv 141 drivers/gpu/drm/i915/i915_suspend.c I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); dev_priv 142 drivers/gpu/drm/i915/i915_suspend.c I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); dev_priv 145 drivers/gpu/drm/i915/i915_suspend.c I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); dev_priv 148 drivers/gpu/drm/i915/i915_suspend.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 150 drivers/gpu/drm/i915/i915_suspend.c intel_gmbus_reset(dev_priv); dev_priv 45 drivers/gpu/drm/i915/i915_sysfs.c static u32 calc_residency(struct drm_i915_private *dev_priv, dev_priv 51 drivers/gpu/drm/i915/i915_sysfs.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) dev_priv 52 drivers/gpu/drm/i915/i915_sysfs.c res = intel_rc6_residency_us(dev_priv, reg); dev_priv 60 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 64 drivers/gpu/drm/i915/i915_sysfs.c if (HAS_RC6(dev_priv)) dev_priv 66 drivers/gpu/drm/i915/i915_sysfs.c if (HAS_RC6p(dev_priv)) dev_priv 68 drivers/gpu/drm/i915/i915_sysfs.c if (HAS_RC6pp(dev_priv)) dev_priv 77 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 78 drivers/gpu/drm/i915/i915_sysfs.c u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6); dev_priv 85 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 86 drivers/gpu/drm/i915/i915_sysfs.c u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p); dev_priv 93 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 94 drivers/gpu/drm/i915/i915_sysfs.c u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp); dev_priv 101 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 102 drivers/gpu/drm/i915/i915_sysfs.c u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6); dev_priv 145 drivers/gpu/drm/i915/i915_sysfs.c static int l3_access_valid(struct drm_i915_private *dev_priv, loff_t offset) dev_priv 147 drivers/gpu/drm/i915/i915_sysfs.c if (!HAS_L3_DPF(dev_priv)) dev_priv 165 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 166 drivers/gpu/drm/i915/i915_sysfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 172 drivers/gpu/drm/i915/i915_sysfs.c ret = l3_access_valid(dev_priv, offset); dev_priv 182 drivers/gpu/drm/i915/i915_sysfs.c if (dev_priv->l3_parity.remap_info[slice]) dev_priv 184 drivers/gpu/drm/i915/i915_sysfs.c dev_priv->l3_parity.remap_info[slice] + (offset/4), dev_priv 200 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 201 drivers/gpu/drm/i915/i915_sysfs.c struct drm_device *dev = &dev_priv->drm; dev_priv 207 drivers/gpu/drm/i915/i915_sysfs.c ret = l3_access_valid(dev_priv, offset); dev_priv 215 drivers/gpu/drm/i915/i915_sysfs.c remap_info = &dev_priv->l3_parity.remap_info[slice]; dev_priv 231 drivers/gpu/drm/i915/i915_sysfs.c list_for_each_entry(ctx, &dev_priv->contexts.list, link) dev_priv 263 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 267 drivers/gpu/drm/i915/i915_sysfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 269 drivers/gpu/drm/i915/i915_sysfs.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 270 drivers/gpu/drm/i915/i915_sysfs.c vlv_punit_get(dev_priv); dev_priv 271 drivers/gpu/drm/i915/i915_sysfs.c freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); dev_priv 272 drivers/gpu/drm/i915/i915_sysfs.c vlv_punit_put(dev_priv); dev_priv 276 drivers/gpu/drm/i915/i915_sysfs.c freq = intel_get_cagf(dev_priv, I915_READ(GEN6_RPSTAT1)); dev_priv 279 drivers/gpu/drm/i915/i915_sysfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 281 drivers/gpu/drm/i915/i915_sysfs.c return snprintf(buf, PAGE_SIZE, "%d\n", intel_gpu_freq(dev_priv, freq)); dev_priv 287 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 290 drivers/gpu/drm/i915/i915_sysfs.c intel_gpu_freq(dev_priv, dev_priv 291 drivers/gpu/drm/i915/i915_sysfs.c dev_priv->gt_pm.rps.cur_freq)); dev_priv 296 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 299 drivers/gpu/drm/i915/i915_sysfs.c intel_gpu_freq(dev_priv, dev_priv 300 drivers/gpu/drm/i915/i915_sysfs.c dev_priv->gt_pm.rps.boost_freq)); dev_priv 307 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 308 drivers/gpu/drm/i915/i915_sysfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 318 drivers/gpu/drm/i915/i915_sysfs.c val = intel_freq_opcode(dev_priv, val); dev_priv 337 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 340 drivers/gpu/drm/i915/i915_sysfs.c intel_gpu_freq(dev_priv, dev_priv 341 drivers/gpu/drm/i915/i915_sysfs.c dev_priv->gt_pm.rps.efficient_freq)); dev_priv 346 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 349 drivers/gpu/drm/i915/i915_sysfs.c intel_gpu_freq(dev_priv, dev_priv 350 drivers/gpu/drm/i915/i915_sysfs.c dev_priv->gt_pm.rps.max_freq_softlimit)); dev_priv 357 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 358 drivers/gpu/drm/i915/i915_sysfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 367 drivers/gpu/drm/i915/i915_sysfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 370 drivers/gpu/drm/i915/i915_sysfs.c val = intel_freq_opcode(dev_priv, val); dev_priv 380 drivers/gpu/drm/i915/i915_sysfs.c intel_gpu_freq(dev_priv, val)); dev_priv 391 drivers/gpu/drm/i915/i915_sysfs.c ret = intel_set_rps(dev_priv, val); dev_priv 395 drivers/gpu/drm/i915/i915_sysfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 402 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 405 drivers/gpu/drm/i915/i915_sysfs.c intel_gpu_freq(dev_priv, dev_priv 406 drivers/gpu/drm/i915/i915_sysfs.c dev_priv->gt_pm.rps.min_freq_softlimit)); dev_priv 413 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 414 drivers/gpu/drm/i915/i915_sysfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 423 drivers/gpu/drm/i915/i915_sysfs.c wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); dev_priv 426 drivers/gpu/drm/i915/i915_sysfs.c val = intel_freq_opcode(dev_priv, val); dev_priv 443 drivers/gpu/drm/i915/i915_sysfs.c ret = intel_set_rps(dev_priv, val); dev_priv 447 drivers/gpu/drm/i915/i915_sysfs.c intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); dev_priv 468 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 469 drivers/gpu/drm/i915/i915_sysfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 473 drivers/gpu/drm/i915/i915_sysfs.c val = intel_gpu_freq(dev_priv, rps->rp0_freq); dev_priv 475 drivers/gpu/drm/i915/i915_sysfs.c val = intel_gpu_freq(dev_priv, rps->rp1_freq); dev_priv 477 drivers/gpu/drm/i915/i915_sysfs.c val = intel_gpu_freq(dev_priv, rps->min_freq); dev_priv 543 drivers/gpu/drm/i915/i915_sysfs.c struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); dev_priv 546 drivers/gpu/drm/i915/i915_sysfs.c i915_reset_error_state(dev_priv); dev_priv 574 drivers/gpu/drm/i915/i915_sysfs.c void i915_setup_sysfs(struct drm_i915_private *dev_priv) dev_priv 576 drivers/gpu/drm/i915/i915_sysfs.c struct device *kdev = dev_priv->drm.primary->kdev; dev_priv 580 drivers/gpu/drm/i915/i915_sysfs.c if (HAS_RC6(dev_priv)) { dev_priv 586 drivers/gpu/drm/i915/i915_sysfs.c if (HAS_RC6p(dev_priv)) { dev_priv 592 drivers/gpu/drm/i915/i915_sysfs.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 599 drivers/gpu/drm/i915/i915_sysfs.c if (HAS_L3_DPF(dev_priv)) { dev_priv 604 drivers/gpu/drm/i915/i915_sysfs.c if (NUM_L3_SLICES(dev_priv) > 1) { dev_priv 613 drivers/gpu/drm/i915/i915_sysfs.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 615 drivers/gpu/drm/i915/i915_sysfs.c else if (INTEL_GEN(dev_priv) >= 6) dev_priv 623 drivers/gpu/drm/i915/i915_sysfs.c void i915_teardown_sysfs(struct drm_i915_private *dev_priv) dev_priv 625 drivers/gpu/drm/i915/i915_sysfs.c struct device *kdev = dev_priv->drm.primary->kdev; dev_priv 629 drivers/gpu/drm/i915/i915_sysfs.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 33 drivers/gpu/drm/i915/i915_trace.h struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 35 drivers/gpu/drm/i915/i915_trace.h for_each_intel_crtc(&dev_priv->drm, it__) { dev_priv 60 drivers/gpu/drm/i915/i915_trace.h struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 62 drivers/gpu/drm/i915/i915_trace.h for_each_intel_crtc(&dev_priv->drm, it__) { dev_priv 101 drivers/gpu/drm/i915/i915_trace.h TP_PROTO(struct drm_i915_private *dev_priv, enum pipe pipe), dev_priv 102 drivers/gpu/drm/i915/i915_trace.h TP_ARGS(dev_priv, pipe), dev_priv 111 drivers/gpu/drm/i915/i915_trace.h struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 123 drivers/gpu/drm/i915/i915_trace.h TP_PROTO(struct drm_i915_private *dev_priv, enum pipe pch_transcoder), dev_priv 124 drivers/gpu/drm/i915/i915_trace.h TP_ARGS(dev_priv, pch_transcoder), dev_priv 134 drivers/gpu/drm/i915/i915_trace.h struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 146 drivers/gpu/drm/i915/i915_trace.h TP_PROTO(struct drm_i915_private *dev_priv, bool old, bool new), dev_priv 147 drivers/gpu/drm/i915/i915_trace.h TP_ARGS(dev_priv, old, new), dev_priv 158 drivers/gpu/drm/i915/i915_trace.h for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 15 drivers/gpu/drm/i915/i915_utils.c __i915_printk(struct drm_i915_private *dev_priv, const char *level, dev_priv 19 drivers/gpu/drm/i915/i915_utils.c struct device *kdev = dev_priv->drm.dev; dev_priv 55 drivers/gpu/drm/i915/i915_utils.h __i915_printk(struct drm_i915_private *dev_priv, const char *level, dev_priv 58 drivers/gpu/drm/i915/i915_utils.h #define i915_report_error(dev_priv, fmt, ...) \ dev_priv 59 drivers/gpu/drm/i915/i915_utils.h __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) dev_priv 60 drivers/gpu/drm/i915/i915_vgpu.c void i915_detect_vgpu(struct drm_i915_private *dev_priv) dev_priv 62 drivers/gpu/drm/i915/i915_vgpu.c struct pci_dev *pdev = dev_priv->drm.pdev; dev_priv 75 drivers/gpu/drm/i915/i915_vgpu.c if (INTEL_GEN(dev_priv) < 6) dev_priv 94 drivers/gpu/drm/i915/i915_vgpu.c dev_priv->vgpu.caps = readl(shared_area + vgtif_offset(vgt_caps)); dev_priv 96 drivers/gpu/drm/i915/i915_vgpu.c dev_priv->vgpu.active = true; dev_priv 97 drivers/gpu/drm/i915/i915_vgpu.c mutex_init(&dev_priv->vgpu.lock); dev_priv 104 drivers/gpu/drm/i915/i915_vgpu.c bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv) dev_priv 106 drivers/gpu/drm/i915/i915_vgpu.c return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT; dev_priv 30 drivers/gpu/drm/i915/i915_vgpu.h void i915_detect_vgpu(struct drm_i915_private *dev_priv); dev_priv 32 drivers/gpu/drm/i915/i915_vgpu.h bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv); dev_priv 35 drivers/gpu/drm/i915/i915_vgpu.h intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv) dev_priv 37 drivers/gpu/drm/i915/i915_vgpu.h return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION; dev_priv 41 drivers/gpu/drm/i915/i915_vgpu.h intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv) dev_priv 43 drivers/gpu/drm/i915/i915_vgpu.h return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT; dev_priv 544 drivers/gpu/drm/i915/i915_vma.c struct drm_i915_private *dev_priv = vma->vm->i915; dev_priv 570 drivers/gpu/drm/i915/i915_vma.c end = min_t(u64, end, dev_priv->ggtt.mappable_end); dev_priv 244 drivers/gpu/drm/i915/intel_csr.c intel_get_stepping_info(struct drm_i915_private *dev_priv) dev_priv 249 drivers/gpu/drm/i915/intel_csr.c if (IS_ICELAKE(dev_priv)) { dev_priv 252 drivers/gpu/drm/i915/intel_csr.c } else if (IS_SKYLAKE(dev_priv)) { dev_priv 255 drivers/gpu/drm/i915/intel_csr.c } else if (IS_BROXTON(dev_priv)) { dev_priv 263 drivers/gpu/drm/i915/intel_csr.c if (INTEL_REVID(dev_priv) < size) dev_priv 264 drivers/gpu/drm/i915/intel_csr.c return si + INTEL_REVID(dev_priv); dev_priv 269 drivers/gpu/drm/i915/intel_csr.c static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) dev_priv 275 drivers/gpu/drm/i915/intel_csr.c if (IS_GEN9_LP(dev_priv)) dev_priv 295 drivers/gpu/drm/i915/intel_csr.c void intel_csr_load_program(struct drm_i915_private *dev_priv) dev_priv 297 drivers/gpu/drm/i915/intel_csr.c u32 *payload = dev_priv->csr.dmc_payload; dev_priv 300 drivers/gpu/drm/i915/intel_csr.c if (!HAS_CSR(dev_priv)) { dev_priv 305 drivers/gpu/drm/i915/intel_csr.c if (!dev_priv->csr.dmc_payload) { dev_priv 310 drivers/gpu/drm/i915/intel_csr.c fw_size = dev_priv->csr.dmc_fw_size; dev_priv 311 drivers/gpu/drm/i915/intel_csr.c assert_rpm_wakelock_held(&dev_priv->runtime_pm); dev_priv 320 drivers/gpu/drm/i915/intel_csr.c for (i = 0; i < dev_priv->csr.mmio_count; i++) { dev_priv 321 drivers/gpu/drm/i915/intel_csr.c I915_WRITE(dev_priv->csr.mmioaddr[i], dev_priv 322 drivers/gpu/drm/i915/intel_csr.c dev_priv->csr.mmiodata[i]); dev_priv 325 drivers/gpu/drm/i915/intel_csr.c dev_priv->csr.dc_state = 0; dev_priv 327 drivers/gpu/drm/i915/intel_csr.c gen9_set_dc_state_debugmask(dev_priv); dev_priv 573 drivers/gpu/drm/i915/intel_csr.c static void parse_csr_fw(struct drm_i915_private *dev_priv, dev_priv 579 drivers/gpu/drm/i915/intel_csr.c struct intel_csr *csr = &dev_priv->csr; dev_priv 580 drivers/gpu/drm/i915/intel_csr.c const struct stepping_info *si = intel_get_stepping_info(dev_priv); dev_priv 608 drivers/gpu/drm/i915/intel_csr.c static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv) dev_priv 610 drivers/gpu/drm/i915/intel_csr.c WARN_ON(dev_priv->csr.wakeref); dev_priv 611 drivers/gpu/drm/i915/intel_csr.c dev_priv->csr.wakeref = dev_priv 612 drivers/gpu/drm/i915/intel_csr.c intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); dev_priv 615 drivers/gpu/drm/i915/intel_csr.c static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv) dev_priv 618 drivers/gpu/drm/i915/intel_csr.c fetch_and_zero(&dev_priv->csr.wakeref); dev_priv 620 drivers/gpu/drm/i915/intel_csr.c intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); dev_priv 625 drivers/gpu/drm/i915/intel_csr.c struct drm_i915_private *dev_priv; dev_priv 629 drivers/gpu/drm/i915/intel_csr.c dev_priv = container_of(work, typeof(*dev_priv), csr.work); dev_priv 630 drivers/gpu/drm/i915/intel_csr.c csr = &dev_priv->csr; dev_priv 632 drivers/gpu/drm/i915/intel_csr.c request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev); dev_priv 633 drivers/gpu/drm/i915/intel_csr.c parse_csr_fw(dev_priv, fw); dev_priv 635 drivers/gpu/drm/i915/intel_csr.c if (dev_priv->csr.dmc_payload) { dev_priv 636 drivers/gpu/drm/i915/intel_csr.c intel_csr_load_program(dev_priv); dev_priv 637 drivers/gpu/drm/i915/intel_csr.c intel_csr_runtime_pm_put(dev_priv); dev_priv 640 drivers/gpu/drm/i915/intel_csr.c dev_priv->csr.fw_path, dev_priv 644 drivers/gpu/drm/i915/intel_csr.c dev_notice(dev_priv->drm.dev, dev_priv 648 drivers/gpu/drm/i915/intel_csr.c dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s", dev_priv 662 drivers/gpu/drm/i915/intel_csr.c void intel_csr_ucode_init(struct drm_i915_private *dev_priv) dev_priv 664 drivers/gpu/drm/i915/intel_csr.c struct intel_csr *csr = &dev_priv->csr; dev_priv 666 drivers/gpu/drm/i915/intel_csr.c INIT_WORK(&dev_priv->csr.work, csr_load_work_fn); dev_priv 668 drivers/gpu/drm/i915/intel_csr.c if (!HAS_CSR(dev_priv)) dev_priv 679 drivers/gpu/drm/i915/intel_csr.c intel_csr_runtime_pm_get(dev_priv); dev_priv 681 drivers/gpu/drm/i915/intel_csr.c if (INTEL_GEN(dev_priv) >= 12) { dev_priv 686 drivers/gpu/drm/i915/intel_csr.c } else if (IS_GEN(dev_priv, 11)) { dev_priv 690 drivers/gpu/drm/i915/intel_csr.c } else if (IS_CANNONLAKE(dev_priv)) { dev_priv 694 drivers/gpu/drm/i915/intel_csr.c } else if (IS_GEMINILAKE(dev_priv)) { dev_priv 698 drivers/gpu/drm/i915/intel_csr.c } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { dev_priv 702 drivers/gpu/drm/i915/intel_csr.c } else if (IS_SKYLAKE(dev_priv)) { dev_priv 706 drivers/gpu/drm/i915/intel_csr.c } else if (IS_BROXTON(dev_priv)) { dev_priv 730 drivers/gpu/drm/i915/intel_csr.c schedule_work(&dev_priv->csr.work); dev_priv 741 drivers/gpu/drm/i915/intel_csr.c void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) dev_priv 743 drivers/gpu/drm/i915/intel_csr.c if (!HAS_CSR(dev_priv)) dev_priv 746 drivers/gpu/drm/i915/intel_csr.c flush_work(&dev_priv->csr.work); dev_priv 749 drivers/gpu/drm/i915/intel_csr.c if (!dev_priv->csr.dmc_payload) dev_priv 750 drivers/gpu/drm/i915/intel_csr.c intel_csr_runtime_pm_put(dev_priv); dev_priv 760 drivers/gpu/drm/i915/intel_csr.c void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) dev_priv 762 drivers/gpu/drm/i915/intel_csr.c if (!HAS_CSR(dev_priv)) dev_priv 769 drivers/gpu/drm/i915/intel_csr.c if (!dev_priv->csr.dmc_payload) dev_priv 770 drivers/gpu/drm/i915/intel_csr.c intel_csr_runtime_pm_get(dev_priv); dev_priv 780 drivers/gpu/drm/i915/intel_csr.c void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) dev_priv 782 drivers/gpu/drm/i915/intel_csr.c if (!HAS_CSR(dev_priv)) dev_priv 785 drivers/gpu/drm/i915/intel_csr.c intel_csr_ucode_suspend(dev_priv); dev_priv 786 drivers/gpu/drm/i915/intel_csr.c WARN_ON(dev_priv->csr.wakeref); dev_priv 788 drivers/gpu/drm/i915/intel_csr.c kfree(dev_priv->csr.dmc_payload); dev_priv 186 drivers/gpu/drm/i915/intel_device_info.c static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) dev_priv 188 drivers/gpu/drm/i915/intel_device_info.c struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; dev_priv 194 drivers/gpu/drm/i915/intel_device_info.c if (IS_ELKHARTLAKE(dev_priv)) { dev_priv 231 drivers/gpu/drm/i915/intel_device_info.c static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) dev_priv 233 drivers/gpu/drm/i915/intel_device_info.c struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; dev_priv 309 drivers/gpu/drm/i915/intel_device_info.c static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) dev_priv 311 drivers/gpu/drm/i915/intel_device_info.c struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; dev_priv 363 drivers/gpu/drm/i915/intel_device_info.c static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) dev_priv 365 drivers/gpu/drm/i915/intel_device_info.c struct intel_device_info *info = mkwrite_device_info(dev_priv); dev_priv 366 drivers/gpu/drm/i915/intel_device_info.c struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; dev_priv 375 drivers/gpu/drm/i915/intel_device_info.c sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3; dev_priv 376 drivers/gpu/drm/i915/intel_device_info.c sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4; dev_priv 446 drivers/gpu/drm/i915/intel_device_info.c !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; dev_priv 448 drivers/gpu/drm/i915/intel_device_info.c IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1; dev_priv 451 drivers/gpu/drm/i915/intel_device_info.c if (IS_GEN9_LP(dev_priv)) { dev_priv 468 drivers/gpu/drm/i915/intel_device_info.c static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) dev_priv 470 drivers/gpu/drm/i915/intel_device_info.c struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; dev_priv 551 drivers/gpu/drm/i915/intel_device_info.c static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) dev_priv 553 drivers/gpu/drm/i915/intel_device_info.c struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; dev_priv 561 drivers/gpu/drm/i915/intel_device_info.c switch (INTEL_INFO(dev_priv)->gt) { dev_priv 563 drivers/gpu/drm/i915/intel_device_info.c MISSING_CASE(INTEL_INFO(dev_priv)->gt); dev_priv 616 drivers/gpu/drm/i915/intel_device_info.c static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) dev_priv 633 drivers/gpu/drm/i915/intel_device_info.c static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv, dev_priv 653 drivers/gpu/drm/i915/intel_device_info.c static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv, dev_priv 679 drivers/gpu/drm/i915/intel_device_info.c static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) dev_priv 685 drivers/gpu/drm/i915/intel_device_info.c if (INTEL_GEN(dev_priv) <= 4) { dev_priv 692 drivers/gpu/drm/i915/intel_device_info.c return dev_priv->rawclk_freq / 16; dev_priv 693 drivers/gpu/drm/i915/intel_device_info.c } else if (INTEL_GEN(dev_priv) <= 8) { dev_priv 701 drivers/gpu/drm/i915/intel_device_info.c } else if (INTEL_GEN(dev_priv) <= 9) { dev_priv 706 drivers/gpu/drm/i915/intel_device_info.c freq = read_reference_ts_freq(dev_priv); dev_priv 708 drivers/gpu/drm/i915/intel_device_info.c freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; dev_priv 719 drivers/gpu/drm/i915/intel_device_info.c } else if (INTEL_GEN(dev_priv) <= 12) { dev_priv 729 drivers/gpu/drm/i915/intel_device_info.c freq = read_reference_ts_freq(dev_priv); dev_priv 733 drivers/gpu/drm/i915/intel_device_info.c if (INTEL_GEN(dev_priv) <= 10) dev_priv 734 drivers/gpu/drm/i915/intel_device_info.c freq = gen10_get_crystal_clock_freq(dev_priv, dev_priv 737 drivers/gpu/drm/i915/intel_device_info.c freq = gen11_get_crystal_clock_freq(dev_priv, dev_priv 859 drivers/gpu/drm/i915/intel_device_info.c void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) dev_priv 861 drivers/gpu/drm/i915/intel_device_info.c struct intel_device_info *info = mkwrite_device_info(dev_priv); dev_priv 862 drivers/gpu/drm/i915/intel_device_info.c struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); dev_priv 865 drivers/gpu/drm/i915/intel_device_info.c if (INTEL_GEN(dev_priv) >= 10) { dev_priv 866 drivers/gpu/drm/i915/intel_device_info.c for_each_pipe(dev_priv, pipe) dev_priv 868 drivers/gpu/drm/i915/intel_device_info.c } else if (IS_GEN(dev_priv, 9)) { dev_priv 876 drivers/gpu/drm/i915/intel_device_info.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 877 drivers/gpu/drm/i915/intel_device_info.c for_each_pipe(dev_priv, pipe) dev_priv 879 drivers/gpu/drm/i915/intel_device_info.c else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) dev_priv 880 drivers/gpu/drm/i915/intel_device_info.c for_each_pipe(dev_priv, pipe) dev_priv 882 drivers/gpu/drm/i915/intel_device_info.c else if (IS_BROXTON(dev_priv)) { dev_priv 895 drivers/gpu/drm/i915/intel_device_info.c } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 896 drivers/gpu/drm/i915/intel_device_info.c for_each_pipe(dev_priv, pipe) dev_priv 898 drivers/gpu/drm/i915/intel_device_info.c } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { dev_priv 899 drivers/gpu/drm/i915/intel_device_info.c for_each_pipe(dev_priv, pipe) dev_priv 906 drivers/gpu/drm/i915/intel_device_info.c } else if (HAS_DISPLAY(dev_priv) && dev_priv 907 drivers/gpu/drm/i915/intel_device_info.c (IS_GEN_RANGE(dev_priv, 7, 8)) && dev_priv 908 drivers/gpu/drm/i915/intel_device_info.c HAS_PCH_SPLIT(dev_priv)) { dev_priv 923 drivers/gpu/drm/i915/intel_device_info.c (HAS_PCH_CPT(dev_priv) && dev_priv 931 drivers/gpu/drm/i915/intel_device_info.c } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) { dev_priv 941 drivers/gpu/drm/i915/intel_device_info.c if (INTEL_GEN(dev_priv) >= 12 && dev_priv 958 drivers/gpu/drm/i915/intel_device_info.c if (IS_HASWELL(dev_priv)) dev_priv 959 drivers/gpu/drm/i915/intel_device_info.c haswell_sseu_info_init(dev_priv); dev_priv 960 drivers/gpu/drm/i915/intel_device_info.c else if (IS_CHERRYVIEW(dev_priv)) dev_priv 961 drivers/gpu/drm/i915/intel_device_info.c cherryview_sseu_info_init(dev_priv); dev_priv 962 drivers/gpu/drm/i915/intel_device_info.c else if (IS_BROADWELL(dev_priv)) dev_priv 963 drivers/gpu/drm/i915/intel_device_info.c broadwell_sseu_info_init(dev_priv); dev_priv 964 drivers/gpu/drm/i915/intel_device_info.c else if (IS_GEN(dev_priv, 9)) dev_priv 965 drivers/gpu/drm/i915/intel_device_info.c gen9_sseu_info_init(dev_priv); dev_priv 966 drivers/gpu/drm/i915/intel_device_info.c else if (IS_GEN(dev_priv, 10)) dev_priv 967 drivers/gpu/drm/i915/intel_device_info.c gen10_sseu_info_init(dev_priv); dev_priv 968 drivers/gpu/drm/i915/intel_device_info.c else if (INTEL_GEN(dev_priv) >= 11) dev_priv 969 drivers/gpu/drm/i915/intel_device_info.c gen11_sseu_info_init(dev_priv); dev_priv 971 drivers/gpu/drm/i915/intel_device_info.c if (IS_GEN(dev_priv, 6) && intel_vtd_active()) { dev_priv 977 drivers/gpu/drm/i915/intel_device_info.c runtime->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv); dev_priv 994 drivers/gpu/drm/i915/intel_device_info.c void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) dev_priv 996 drivers/gpu/drm/i915/intel_device_info.c struct intel_device_info *info = mkwrite_device_info(dev_priv); dev_priv 1003 drivers/gpu/drm/i915/intel_device_info.c if (INTEL_GEN(dev_priv) < 11) dev_priv 1013 drivers/gpu/drm/i915/intel_device_info.c if (!HAS_ENGINE(dev_priv, _VCS(i))) dev_priv 1027 drivers/gpu/drm/i915/intel_device_info.c if (IS_TIGERLAKE(dev_priv) || logical_vdbox++ % 2 == 0) dev_priv 1028 drivers/gpu/drm/i915/intel_device_info.c RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); dev_priv 1031 drivers/gpu/drm/i915/intel_device_info.c vdbox_mask, VDBOX_MASK(dev_priv)); dev_priv 1032 drivers/gpu/drm/i915/intel_device_info.c GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv)); dev_priv 1035 drivers/gpu/drm/i915/intel_device_info.c if (!HAS_ENGINE(dev_priv, _VECS(i))) dev_priv 1044 drivers/gpu/drm/i915/intel_device_info.c vebox_mask, VEBOX_MASK(dev_priv)); dev_priv 1045 drivers/gpu/drm/i915/intel_device_info.c GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv)); dev_priv 225 drivers/gpu/drm/i915/intel_device_info.h void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); dev_priv 226 drivers/gpu/drm/i915/intel_device_info.h void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); dev_priv 234 drivers/gpu/drm/i915/intel_device_info.h void intel_device_info_init_mmio(struct drm_i915_private *dev_priv); dev_priv 42 drivers/gpu/drm/i915/intel_gvt.c static bool is_supported_device(struct drm_i915_private *dev_priv) dev_priv 44 drivers/gpu/drm/i915/intel_gvt.c if (IS_BROADWELL(dev_priv)) dev_priv 46 drivers/gpu/drm/i915/intel_gvt.c if (IS_SKYLAKE(dev_priv)) dev_priv 48 drivers/gpu/drm/i915/intel_gvt.c if (IS_KABYLAKE(dev_priv)) dev_priv 50 drivers/gpu/drm/i915/intel_gvt.c if (IS_BROXTON(dev_priv)) dev_priv 52 drivers/gpu/drm/i915/intel_gvt.c if (IS_COFFEELAKE(dev_priv)) dev_priv 64 drivers/gpu/drm/i915/intel_gvt.c void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv) dev_priv 69 drivers/gpu/drm/i915/intel_gvt.c if (intel_vgpu_active(dev_priv)) { dev_priv 74 drivers/gpu/drm/i915/intel_gvt.c if (!is_supported_device(dev_priv)) { dev_priv 94 drivers/gpu/drm/i915/intel_gvt.c int intel_gvt_init(struct drm_i915_private *dev_priv) dev_priv 98 drivers/gpu/drm/i915/intel_gvt.c if (i915_inject_probe_failure(dev_priv)) dev_priv 106 drivers/gpu/drm/i915/intel_gvt.c if (USES_GUC_SUBMISSION(dev_priv)) { dev_priv 111 drivers/gpu/drm/i915/intel_gvt.c ret = intel_gvt_init_device(dev_priv); dev_priv 132 drivers/gpu/drm/i915/intel_gvt.c void intel_gvt_driver_remove(struct drm_i915_private *dev_priv) dev_priv 134 drivers/gpu/drm/i915/intel_gvt.c if (!intel_gvt_active(dev_priv)) dev_priv 137 drivers/gpu/drm/i915/intel_gvt.c intel_gvt_clean_device(dev_priv); dev_priv 30 drivers/gpu/drm/i915/intel_gvt.h int intel_gvt_init(struct drm_i915_private *dev_priv); dev_priv 31 drivers/gpu/drm/i915/intel_gvt.h void intel_gvt_driver_remove(struct drm_i915_private *dev_priv); dev_priv 32 drivers/gpu/drm/i915/intel_gvt.h int intel_gvt_init_device(struct drm_i915_private *dev_priv); dev_priv 33 drivers/gpu/drm/i915/intel_gvt.h void intel_gvt_clean_device(struct drm_i915_private *dev_priv); dev_priv 35 drivers/gpu/drm/i915/intel_gvt.h void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv); dev_priv 37 drivers/gpu/drm/i915/intel_gvt.h static inline int intel_gvt_init(struct drm_i915_private *dev_priv) dev_priv 42 drivers/gpu/drm/i915/intel_gvt.h static inline void intel_gvt_driver_remove(struct drm_i915_private *dev_priv) dev_priv 46 drivers/gpu/drm/i915/intel_gvt.h static inline void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv) dev_priv 11 drivers/gpu/drm/i915/intel_pch.c intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) dev_priv 16 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_GEN(dev_priv, 5)); dev_priv 20 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); dev_priv 24 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); dev_priv 29 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); dev_priv 30 drivers/gpu/drm/i915/intel_pch.c WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); dev_priv 34 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); dev_priv 35 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); dev_priv 39 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); dev_priv 40 drivers/gpu/drm/i915/intel_pch.c WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); dev_priv 45 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); dev_priv 46 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); dev_priv 51 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); dev_priv 55 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); dev_priv 59 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && dev_priv 60 drivers/gpu/drm/i915/intel_pch.c !IS_COFFEELAKE(dev_priv)); dev_priv 65 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); dev_priv 69 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); dev_priv 74 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_COFFEELAKE(dev_priv)); dev_priv 79 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_ICELAKE(dev_priv)); dev_priv 84 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_ELKHARTLAKE(dev_priv)); dev_priv 88 drivers/gpu/drm/i915/intel_pch.c WARN_ON(!IS_TIGERLAKE(dev_priv)); dev_priv 106 drivers/gpu/drm/i915/intel_pch.c intel_virt_detect_pch(const struct drm_i915_private *dev_priv) dev_priv 117 drivers/gpu/drm/i915/intel_pch.c if (IS_TIGERLAKE(dev_priv)) dev_priv 119 drivers/gpu/drm/i915/intel_pch.c else if (IS_ELKHARTLAKE(dev_priv)) dev_priv 121 drivers/gpu/drm/i915/intel_pch.c else if (IS_ICELAKE(dev_priv)) dev_priv 123 drivers/gpu/drm/i915/intel_pch.c else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) dev_priv 125 drivers/gpu/drm/i915/intel_pch.c else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) dev_priv 127 drivers/gpu/drm/i915/intel_pch.c else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) dev_priv 129 drivers/gpu/drm/i915/intel_pch.c else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 131 drivers/gpu/drm/i915/intel_pch.c else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) dev_priv 133 drivers/gpu/drm/i915/intel_pch.c else if (IS_GEN(dev_priv, 5)) dev_priv 144 drivers/gpu/drm/i915/intel_pch.c void intel_detect_pch(struct drm_i915_private *dev_priv) dev_priv 168 drivers/gpu/drm/i915/intel_pch.c pch_type = intel_pch_type(dev_priv, id); dev_priv 170 drivers/gpu/drm/i915/intel_pch.c dev_priv->pch_type = pch_type; dev_priv 171 drivers/gpu/drm/i915/intel_pch.c dev_priv->pch_id = id; dev_priv 175 drivers/gpu/drm/i915/intel_pch.c id = intel_virt_detect_pch(dev_priv); dev_priv 176 drivers/gpu/drm/i915/intel_pch.c pch_type = intel_pch_type(dev_priv, id); dev_priv 182 drivers/gpu/drm/i915/intel_pch.c dev_priv->pch_type = pch_type; dev_priv 183 drivers/gpu/drm/i915/intel_pch.c dev_priv->pch_id = id; dev_priv 192 drivers/gpu/drm/i915/intel_pch.c if (pch && !HAS_DISPLAY(dev_priv)) { dev_priv 194 drivers/gpu/drm/i915/intel_pch.c dev_priv->pch_type = PCH_NOP; dev_priv 195 drivers/gpu/drm/i915/intel_pch.c dev_priv->pch_id = 0; dev_priv 53 drivers/gpu/drm/i915/intel_pch.h #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) dev_priv 54 drivers/gpu/drm/i915/intel_pch.h #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) dev_priv 55 drivers/gpu/drm/i915/intel_pch.h #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC) dev_priv 56 drivers/gpu/drm/i915/intel_pch.h #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) dev_priv 57 drivers/gpu/drm/i915/intel_pch.h #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) dev_priv 58 drivers/gpu/drm/i915/intel_pch.h #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) dev_priv 59 drivers/gpu/drm/i915/intel_pch.h #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) dev_priv 60 drivers/gpu/drm/i915/intel_pch.h #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) dev_priv 61 drivers/gpu/drm/i915/intel_pch.h #define HAS_PCH_LPT_LP(dev_priv) \ dev_priv 62 drivers/gpu/drm/i915/intel_pch.h (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \ dev_priv 63 drivers/gpu/drm/i915/intel_pch.h INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) dev_priv 64 drivers/gpu/drm/i915/intel_pch.h #define HAS_PCH_LPT_H(dev_priv) \ dev_priv 65 drivers/gpu/drm/i915/intel_pch.h (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \ dev_priv 66 drivers/gpu/drm/i915/intel_pch.h INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE) dev_priv 67 drivers/gpu/drm/i915/intel_pch.h #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) dev_priv 68 drivers/gpu/drm/i915/intel_pch.h #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) dev_priv 69 drivers/gpu/drm/i915/intel_pch.h #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) dev_priv 70 drivers/gpu/drm/i915/intel_pch.h #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) dev_priv 72 drivers/gpu/drm/i915/intel_pch.h void intel_detect_pch(struct drm_i915_private *dev_priv); dev_priv 68 drivers/gpu/drm/i915/intel_pm.c static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 70 drivers/gpu/drm/i915/intel_pm.c if (HAS_LLC(dev_priv)) { dev_priv 101 drivers/gpu/drm/i915/intel_pm.c if (IS_SKYLAKE(dev_priv)) { dev_priv 108 drivers/gpu/drm/i915/intel_pm.c static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 110 drivers/gpu/drm/i915/intel_pm.c gen9_init_clock_gating(dev_priv); dev_priv 139 drivers/gpu/drm/i915/intel_pm.c static void glk_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 141 drivers/gpu/drm/i915/intel_pm.c gen9_init_clock_gating(dev_priv); dev_priv 152 drivers/gpu/drm/i915/intel_pm.c if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) { dev_priv 162 drivers/gpu/drm/i915/intel_pm.c static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) dev_priv 170 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq = 533; /* 133*4 */ dev_priv 173 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq = 800; /* 200*4 */ dev_priv 176 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq = 667; /* 167*4 */ dev_priv 179 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq = 400; /* 100*4 */ dev_priv 185 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq = 533; dev_priv 188 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq = 667; dev_priv 191 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq = 800; dev_priv 197 drivers/gpu/drm/i915/intel_pm.c dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; dev_priv 200 drivers/gpu/drm/i915/intel_pm.c static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv) dev_priv 204 drivers/gpu/drm/i915/intel_pm.c ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); dev_priv 205 drivers/gpu/drm/i915/intel_pm.c csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0); dev_priv 209 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq = 800; dev_priv 212 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq = 1066; dev_priv 215 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq = 1333; dev_priv 218 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq = 1600; dev_priv 223 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq = 0; dev_priv 227 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.r_t = dev_priv->mem_freq; dev_priv 231 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq = 3200; dev_priv 234 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq = 3733; dev_priv 237 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq = 4266; dev_priv 240 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq = 4800; dev_priv 243 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq = 5333; dev_priv 246 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq = 5866; dev_priv 249 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq = 6400; dev_priv 254 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq = 0; dev_priv 258 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->fsb_freq == 3200) { dev_priv 259 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.c_m = 0; dev_priv 260 drivers/gpu/drm/i915/intel_pm.c } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { dev_priv 261 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.c_m = 1; dev_priv 263 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.c_m = 2; dev_priv 329 drivers/gpu/drm/i915/intel_pm.c static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) dev_priv 333 drivers/gpu/drm/i915/intel_pm.c vlv_punit_get(dev_priv); dev_priv 335 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); dev_priv 342 drivers/gpu/drm/i915/intel_pm.c vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); dev_priv 344 drivers/gpu/drm/i915/intel_pm.c if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & dev_priv 348 drivers/gpu/drm/i915/intel_pm.c vlv_punit_put(dev_priv); dev_priv 351 drivers/gpu/drm/i915/intel_pm.c static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) dev_priv 355 drivers/gpu/drm/i915/intel_pm.c vlv_punit_get(dev_priv); dev_priv 357 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); dev_priv 362 drivers/gpu/drm/i915/intel_pm.c vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); dev_priv 364 drivers/gpu/drm/i915/intel_pm.c vlv_punit_put(dev_priv); dev_priv 370 drivers/gpu/drm/i915/intel_pm.c static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) dev_priv 375 drivers/gpu/drm/i915/intel_pm.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 379 drivers/gpu/drm/i915/intel_pm.c } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) { dev_priv 383 drivers/gpu/drm/i915/intel_pm.c } else if (IS_PINEVIEW(dev_priv)) { dev_priv 392 drivers/gpu/drm/i915/intel_pm.c } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) { dev_priv 398 drivers/gpu/drm/i915/intel_pm.c } else if (IS_I915GM(dev_priv)) { dev_priv 413 drivers/gpu/drm/i915/intel_pm.c trace_intel_memory_cxsr(dev_priv, was_enabled, enable); dev_priv 459 drivers/gpu/drm/i915/intel_pm.c bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) dev_priv 463 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); dev_priv 464 drivers/gpu/drm/i915/intel_pm.c ret = _intel_set_memory_cxsr(dev_priv, enable); dev_priv 465 drivers/gpu/drm/i915/intel_pm.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 466 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.vlv.cxsr = enable; dev_priv 467 drivers/gpu/drm/i915/intel_pm.c else if (IS_G4X(dev_priv)) dev_priv 468 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.g4x.cxsr = enable; dev_priv 469 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); dev_priv 496 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 532 drivers/gpu/drm/i915/intel_pm.c static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, dev_priv 548 drivers/gpu/drm/i915/intel_pm.c static int i830_get_fifo_size(struct drm_i915_private *dev_priv, dev_priv 565 drivers/gpu/drm/i915/intel_pm.c static int i845_get_fifo_size(struct drm_i915_private *dev_priv, dev_priv 818 drivers/gpu/drm/i915/intel_pm.c static int intel_wm_num_levels(struct drm_i915_private *dev_priv) dev_priv 820 drivers/gpu/drm/i915/intel_pm.c return dev_priv->wm.max_level + 1; dev_priv 846 drivers/gpu/drm/i915/intel_pm.c static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv) dev_priv 850 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 863 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); dev_priv 869 drivers/gpu/drm/i915/intel_pm.c latency = intel_get_cxsr_latency(!IS_MOBILE(dev_priv), dev_priv 870 drivers/gpu/drm/i915/intel_pm.c dev_priv->is_ddr3, dev_priv 871 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq, dev_priv 872 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq); dev_priv 875 drivers/gpu/drm/i915/intel_pm.c intel_set_memory_cxsr(dev_priv, false); dev_priv 879 drivers/gpu/drm/i915/intel_pm.c crtc = single_enabled_crtc(dev_priv); dev_priv 926 drivers/gpu/drm/i915/intel_pm.c intel_set_memory_cxsr(dev_priv, true); dev_priv 928 drivers/gpu/drm/i915/intel_pm.c intel_set_memory_cxsr(dev_priv, false); dev_priv 949 drivers/gpu/drm/i915/intel_pm.c static void g4x_write_wm_values(struct drm_i915_private *dev_priv, dev_priv 954 drivers/gpu/drm/i915/intel_pm.c for_each_pipe(dev_priv, pipe) dev_priv 955 drivers/gpu/drm/i915/intel_pm.c trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); dev_priv 981 drivers/gpu/drm/i915/intel_pm.c static void vlv_write_wm_values(struct drm_i915_private *dev_priv, dev_priv 986 drivers/gpu/drm/i915/intel_pm.c for_each_pipe(dev_priv, pipe) { dev_priv 987 drivers/gpu/drm/i915/intel_pm.c trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); dev_priv 1019 drivers/gpu/drm/i915/intel_pm.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 1059 drivers/gpu/drm/i915/intel_pm.c static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv) dev_priv 1062 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5; dev_priv 1063 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12; dev_priv 1064 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35; dev_priv 1066 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL; dev_priv 1116 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1119 drivers/gpu/drm/i915/intel_pm.c unsigned int latency = dev_priv->wm.pri_latency[level] * 10; dev_priv 1141 drivers/gpu/drm/i915/intel_pm.c if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY && dev_priv 1178 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 1181 drivers/gpu/drm/i915/intel_pm.c for (; level < intel_wm_num_levels(dev_priv); level++) { dev_priv 1194 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 1200 drivers/gpu/drm/i915/intel_pm.c for (; level < intel_wm_num_levels(dev_priv); level++) { dev_priv 1296 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 1298 drivers/gpu/drm/i915/intel_pm.c if (level > dev_priv->wm.max_level) dev_priv 1497 drivers/gpu/drm/i915/intel_pm.c static void g4x_merge_wm(struct drm_i915_private *dev_priv, dev_priv 1507 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 1529 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 1541 drivers/gpu/drm/i915/intel_pm.c static void g4x_program_watermarks(struct drm_i915_private *dev_priv) dev_priv 1543 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_values *old_wm = &dev_priv->wm.g4x; dev_priv 1546 drivers/gpu/drm/i915/intel_pm.c g4x_merge_wm(dev_priv, &new_wm); dev_priv 1552 drivers/gpu/drm/i915/intel_pm.c _intel_set_memory_cxsr(dev_priv, false); dev_priv 1554 drivers/gpu/drm/i915/intel_pm.c g4x_write_wm_values(dev_priv, &new_wm); dev_priv 1557 drivers/gpu/drm/i915/intel_pm.c _intel_set_memory_cxsr(dev_priv, true); dev_priv 1565 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 1568 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); dev_priv 1570 drivers/gpu/drm/i915/intel_pm.c g4x_program_watermarks(dev_priv); dev_priv 1571 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); dev_priv 1577 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 1583 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); dev_priv 1585 drivers/gpu/drm/i915/intel_pm.c g4x_program_watermarks(dev_priv); dev_priv 1586 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); dev_priv 1605 drivers/gpu/drm/i915/intel_pm.c static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv) dev_priv 1608 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; dev_priv 1610 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; dev_priv 1612 drivers/gpu/drm/i915/intel_pm.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 1613 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; dev_priv 1614 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; dev_priv 1616 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; dev_priv 1625 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 1630 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->wm.pri_latency[level] == 0) dev_priv 1651 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[level] * 10); dev_priv 1749 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1751 drivers/gpu/drm/i915/intel_pm.c for (; level < intel_wm_num_levels(dev_priv); level++) { dev_priv 1777 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 1778 drivers/gpu/drm/i915/intel_pm.c int num_levels = intel_wm_num_levels(dev_priv); dev_priv 1853 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1910 drivers/gpu/drm/i915/intel_pm.c wm_state->num_levels = intel_wm_num_levels(dev_priv); dev_priv 1920 drivers/gpu/drm/i915/intel_pm.c const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1; dev_priv 1961 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 1962 drivers/gpu/drm/i915/intel_pm.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 2105 drivers/gpu/drm/i915/intel_pm.c static void vlv_merge_wm(struct drm_i915_private *dev_priv, dev_priv 2111 drivers/gpu/drm/i915/intel_pm.c wm->level = dev_priv->wm.max_level; dev_priv 2114 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 2133 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 2148 drivers/gpu/drm/i915/intel_pm.c static void vlv_program_watermarks(struct drm_i915_private *dev_priv) dev_priv 2150 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_values *old_wm = &dev_priv->wm.vlv; dev_priv 2153 drivers/gpu/drm/i915/intel_pm.c vlv_merge_wm(dev_priv, &new_wm); dev_priv 2159 drivers/gpu/drm/i915/intel_pm.c chv_set_memory_dvfs(dev_priv, false); dev_priv 2162 drivers/gpu/drm/i915/intel_pm.c chv_set_memory_pm5(dev_priv, false); dev_priv 2165 drivers/gpu/drm/i915/intel_pm.c _intel_set_memory_cxsr(dev_priv, false); dev_priv 2167 drivers/gpu/drm/i915/intel_pm.c vlv_write_wm_values(dev_priv, &new_wm); dev_priv 2170 drivers/gpu/drm/i915/intel_pm.c _intel_set_memory_cxsr(dev_priv, true); dev_priv 2173 drivers/gpu/drm/i915/intel_pm.c chv_set_memory_pm5(dev_priv, true); dev_priv 2176 drivers/gpu/drm/i915/intel_pm.c chv_set_memory_dvfs(dev_priv, true); dev_priv 2184 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 2187 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); dev_priv 2189 drivers/gpu/drm/i915/intel_pm.c vlv_program_watermarks(dev_priv); dev_priv 2190 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); dev_priv 2196 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 2202 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); dev_priv 2204 drivers/gpu/drm/i915/intel_pm.c vlv_program_watermarks(dev_priv); dev_priv 2205 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); dev_priv 2210 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); dev_priv 2217 drivers/gpu/drm/i915/intel_pm.c crtc = single_enabled_crtc(dev_priv); dev_priv 2259 drivers/gpu/drm/i915/intel_pm.c intel_set_memory_cxsr(dev_priv, false); dev_priv 2276 drivers/gpu/drm/i915/intel_pm.c intel_set_memory_cxsr(dev_priv, true); dev_priv 2283 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); dev_priv 2292 drivers/gpu/drm/i915/intel_pm.c if (IS_I945GM(dev_priv)) dev_priv 2294 drivers/gpu/drm/i915/intel_pm.c else if (!IS_GEN(dev_priv, 2)) dev_priv 2299 drivers/gpu/drm/i915/intel_pm.c fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A); dev_priv 2300 drivers/gpu/drm/i915/intel_pm.c crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A); dev_priv 2308 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 2)) dev_priv 2323 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 2)) dev_priv 2326 drivers/gpu/drm/i915/intel_pm.c fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B); dev_priv 2327 drivers/gpu/drm/i915/intel_pm.c crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B); dev_priv 2335 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 2)) dev_priv 2355 drivers/gpu/drm/i915/intel_pm.c if (IS_I915GM(dev_priv) && enabled) { dev_priv 2371 drivers/gpu/drm/i915/intel_pm.c intel_set_memory_cxsr(dev_priv, false); dev_priv 2374 drivers/gpu/drm/i915/intel_pm.c if (HAS_FW_BLC(dev_priv) && enabled) { dev_priv 2387 drivers/gpu/drm/i915/intel_pm.c if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) dev_priv 2400 drivers/gpu/drm/i915/intel_pm.c if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) dev_priv 2421 drivers/gpu/drm/i915/intel_pm.c intel_set_memory_cxsr(dev_priv, true); dev_priv 2426 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); dev_priv 2432 drivers/gpu/drm/i915/intel_pm.c crtc = single_enabled_crtc(dev_priv); dev_priv 2439 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.get_fifo_size(dev_priv, PLANE_A), dev_priv 2599 drivers/gpu/drm/i915/intel_pm.c ilk_display_fifo_size(const struct drm_i915_private *dev_priv) dev_priv 2601 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 2603 drivers/gpu/drm/i915/intel_pm.c else if (INTEL_GEN(dev_priv) >= 7) dev_priv 2610 drivers/gpu/drm/i915/intel_pm.c ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, dev_priv 2613 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 2616 drivers/gpu/drm/i915/intel_pm.c else if (INTEL_GEN(dev_priv) >= 7) dev_priv 2628 drivers/gpu/drm/i915/intel_pm.c ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) dev_priv 2630 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 7) dev_priv 2636 drivers/gpu/drm/i915/intel_pm.c static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) dev_priv 2638 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 2645 drivers/gpu/drm/i915/intel_pm.c static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv, dev_priv 2651 drivers/gpu/drm/i915/intel_pm.c unsigned int fifo_size = ilk_display_fifo_size(dev_priv); dev_priv 2659 drivers/gpu/drm/i915/intel_pm.c fifo_size /= INTEL_INFO(dev_priv)->num_pipes; dev_priv 2666 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) <= 6) dev_priv 2682 drivers/gpu/drm/i915/intel_pm.c return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite)); dev_priv 2686 drivers/gpu/drm/i915/intel_pm.c static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv, dev_priv 2695 drivers/gpu/drm/i915/intel_pm.c return ilk_cursor_wm_reg_max(dev_priv, level); dev_priv 2698 drivers/gpu/drm/i915/intel_pm.c static void ilk_compute_wm_maximums(const struct drm_i915_private *dev_priv, dev_priv 2704 drivers/gpu/drm/i915/intel_pm.c max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false); dev_priv 2705 drivers/gpu/drm/i915/intel_pm.c max->spr = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, true); dev_priv 2706 drivers/gpu/drm/i915/intel_pm.c max->cur = ilk_cursor_wm_max(dev_priv, level, config); dev_priv 2707 drivers/gpu/drm/i915/intel_pm.c max->fbc = ilk_fbc_wm_reg_max(dev_priv); dev_priv 2710 drivers/gpu/drm/i915/intel_pm.c static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv, dev_priv 2714 drivers/gpu/drm/i915/intel_pm.c max->pri = ilk_plane_wm_reg_max(dev_priv, level, false); dev_priv 2715 drivers/gpu/drm/i915/intel_pm.c max->spr = ilk_plane_wm_reg_max(dev_priv, level, true); dev_priv 2716 drivers/gpu/drm/i915/intel_pm.c max->cur = ilk_cursor_wm_reg_max(dev_priv, level); dev_priv 2717 drivers/gpu/drm/i915/intel_pm.c max->fbc = ilk_fbc_wm_reg_max(dev_priv); dev_priv 2761 drivers/gpu/drm/i915/intel_pm.c static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, dev_priv 2770 drivers/gpu/drm/i915/intel_pm.c u16 pri_latency = dev_priv->wm.pri_latency[level]; dev_priv 2771 drivers/gpu/drm/i915/intel_pm.c u16 spr_latency = dev_priv->wm.spr_latency[level]; dev_priv 2772 drivers/gpu/drm/i915/intel_pm.c u16 cur_latency = dev_priv->wm.cur_latency[level]; dev_priv 2824 drivers/gpu/drm/i915/intel_pm.c static void intel_read_wm_latency(struct drm_i915_private *dev_priv, dev_priv 2827 drivers/gpu/drm/i915/intel_pm.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 2829 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 2832 drivers/gpu/drm/i915/intel_pm.c int level, max_level = ilk_wm_max_level(dev_priv); dev_priv 2836 drivers/gpu/drm/i915/intel_pm.c ret = sandybridge_pcode_read(dev_priv, dev_priv 2855 drivers/gpu/drm/i915/intel_pm.c ret = sandybridge_pcode_read(dev_priv, dev_priv 2906 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->dram_info.is_16gb_dimm) dev_priv 2909 drivers/gpu/drm/i915/intel_pm.c } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { dev_priv 2919 drivers/gpu/drm/i915/intel_pm.c } else if (INTEL_GEN(dev_priv) >= 6) { dev_priv 2926 drivers/gpu/drm/i915/intel_pm.c } else if (INTEL_GEN(dev_priv) >= 5) { dev_priv 2934 drivers/gpu/drm/i915/intel_pm.c MISSING_CASE(INTEL_DEVID(dev_priv)); dev_priv 2938 drivers/gpu/drm/i915/intel_pm.c static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv, dev_priv 2942 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 5)) dev_priv 2946 drivers/gpu/drm/i915/intel_pm.c static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv, dev_priv 2950 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 5)) dev_priv 2954 drivers/gpu/drm/i915/intel_pm.c int ilk_wm_max_level(const struct drm_i915_private *dev_priv) dev_priv 2957 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 2959 drivers/gpu/drm/i915/intel_pm.c else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 2961 drivers/gpu/drm/i915/intel_pm.c else if (INTEL_GEN(dev_priv) >= 6) dev_priv 2967 drivers/gpu/drm/i915/intel_pm.c static void intel_print_wm_latency(struct drm_i915_private *dev_priv, dev_priv 2971 drivers/gpu/drm/i915/intel_pm.c int level, max_level = ilk_wm_max_level(dev_priv); dev_priv 2986 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 2997 drivers/gpu/drm/i915/intel_pm.c static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, dev_priv 3000 drivers/gpu/drm/i915/intel_pm.c int level, max_level = ilk_wm_max_level(dev_priv); dev_priv 3012 drivers/gpu/drm/i915/intel_pm.c static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv) dev_priv 3020 drivers/gpu/drm/i915/intel_pm.c changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | dev_priv 3021 drivers/gpu/drm/i915/intel_pm.c ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | dev_priv 3022 drivers/gpu/drm/i915/intel_pm.c ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); dev_priv 3028 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); dev_priv 3029 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); dev_priv 3030 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); dev_priv 3033 drivers/gpu/drm/i915/intel_pm.c static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv) dev_priv 3046 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->wm.pri_latency[3] == 0 && dev_priv 3047 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.spr_latency[3] == 0 && dev_priv 3048 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.cur_latency[3] == 0) dev_priv 3051 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[3] = 0; dev_priv 3052 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.spr_latency[3] = 0; dev_priv 3053 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.cur_latency[3] = 0; dev_priv 3056 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); dev_priv 3057 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); dev_priv 3058 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); dev_priv 3061 drivers/gpu/drm/i915/intel_pm.c static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv) dev_priv 3063 drivers/gpu/drm/i915/intel_pm.c intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency); dev_priv 3065 drivers/gpu/drm/i915/intel_pm.c memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, dev_priv 3066 drivers/gpu/drm/i915/intel_pm.c sizeof(dev_priv->wm.pri_latency)); dev_priv 3067 drivers/gpu/drm/i915/intel_pm.c memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, dev_priv 3068 drivers/gpu/drm/i915/intel_pm.c sizeof(dev_priv->wm.pri_latency)); dev_priv 3070 drivers/gpu/drm/i915/intel_pm.c intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency); dev_priv 3071 drivers/gpu/drm/i915/intel_pm.c intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency); dev_priv 3073 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); dev_priv 3074 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); dev_priv 3075 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); dev_priv 3077 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 6)) { dev_priv 3078 drivers/gpu/drm/i915/intel_pm.c snb_wm_latency_quirk(dev_priv); dev_priv 3079 drivers/gpu/drm/i915/intel_pm.c snb_wm_lp3_irq_quirk(dev_priv); dev_priv 3083 drivers/gpu/drm/i915/intel_pm.c static void skl_setup_wm_latency(struct drm_i915_private *dev_priv) dev_priv 3085 drivers/gpu/drm/i915/intel_pm.c intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency); dev_priv 3086 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency); dev_priv 3089 drivers/gpu/drm/i915/intel_pm.c static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv, dev_priv 3101 drivers/gpu/drm/i915/intel_pm.c ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max); dev_priv 3119 drivers/gpu/drm/i915/intel_pm.c const struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 3125 drivers/gpu/drm/i915/intel_pm.c int level, max_level = ilk_wm_max_level(dev_priv), usable_level; dev_priv 3152 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled) dev_priv 3160 drivers/gpu/drm/i915/intel_pm.c ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state, dev_priv 3163 drivers/gpu/drm/i915/intel_pm.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 3166 drivers/gpu/drm/i915/intel_pm.c if (!ilk_validate_pipe_wm(dev_priv, pipe_wm)) dev_priv 3169 drivers/gpu/drm/i915/intel_pm.c ilk_compute_wm_reg_maximums(dev_priv, 1, &max); dev_priv 3174 drivers/gpu/drm/i915/intel_pm.c ilk_compute_wm_level(dev_priv, intel_crtc, level, crtc_state, dev_priv 3199 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); dev_priv 3206 drivers/gpu/drm/i915/intel_pm.c int level, max_level = ilk_wm_max_level(dev_priv); dev_priv 3239 drivers/gpu/drm/i915/intel_pm.c if (!ilk_validate_pipe_wm(dev_priv, a)) dev_priv 3255 drivers/gpu/drm/i915/intel_pm.c static void ilk_merge_wm_level(struct drm_i915_private *dev_priv, dev_priv 3263 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, intel_crtc) { dev_priv 3288 drivers/gpu/drm/i915/intel_pm.c static void ilk_wm_merge(struct drm_i915_private *dev_priv, dev_priv 3293 drivers/gpu/drm/i915/intel_pm.c int level, max_level = ilk_wm_max_level(dev_priv); dev_priv 3297 drivers/gpu/drm/i915/intel_pm.c if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) && dev_priv 3302 drivers/gpu/drm/i915/intel_pm.c merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6; dev_priv 3308 drivers/gpu/drm/i915/intel_pm.c ilk_merge_wm_level(dev_priv, level, wm); dev_priv 3333 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled && dev_priv 3334 drivers/gpu/drm/i915/intel_pm.c intel_fbc_is_active(dev_priv)) { dev_priv 3350 drivers/gpu/drm/i915/intel_pm.c static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv, dev_priv 3353 drivers/gpu/drm/i915/intel_pm.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 3356 drivers/gpu/drm/i915/intel_pm.c return dev_priv->wm.pri_latency[level]; dev_priv 3359 drivers/gpu/drm/i915/intel_pm.c static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, dev_priv 3383 drivers/gpu/drm/i915/intel_pm.c (ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) | dev_priv 3390 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 8) dev_priv 3401 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) { dev_priv 3409 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, intel_crtc) { dev_priv 3429 drivers/gpu/drm/i915/intel_pm.c ilk_find_best_result(struct drm_i915_private *dev_priv, dev_priv 3433 drivers/gpu/drm/i915/intel_pm.c int level, max_level = ilk_wm_max_level(dev_priv); dev_priv 3463 drivers/gpu/drm/i915/intel_pm.c static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, dev_priv 3471 drivers/gpu/drm/i915/intel_pm.c for_each_pipe(dev_priv, pipe) { dev_priv 3515 drivers/gpu/drm/i915/intel_pm.c static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, dev_priv 3518 drivers/gpu/drm/i915/intel_pm.c struct ilk_wm_values *previous = &dev_priv->wm.hw; dev_priv 3549 drivers/gpu/drm/i915/intel_pm.c static void ilk_write_wm_values(struct drm_i915_private *dev_priv, dev_priv 3552 drivers/gpu/drm/i915/intel_pm.c struct ilk_wm_values *previous = &dev_priv->wm.hw; dev_priv 3556 drivers/gpu/drm/i915/intel_pm.c dirty = ilk_compute_wm_dirty(dev_priv, previous, results); dev_priv 3560 drivers/gpu/drm/i915/intel_pm.c _ilk_disable_lp_wm(dev_priv, dirty); dev_priv 3577 drivers/gpu/drm/i915/intel_pm.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { dev_priv 3607 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 7) { dev_priv 3621 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.hw = *results; dev_priv 3626 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 3628 drivers/gpu/drm/i915/intel_pm.c return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); dev_priv 3631 drivers/gpu/drm/i915/intel_pm.c static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv) dev_priv 3639 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) < 11) dev_priv 3657 drivers/gpu/drm/i915/intel_pm.c static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv) dev_priv 3659 drivers/gpu/drm/i915/intel_pm.c return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv); dev_priv 3663 drivers/gpu/drm/i915/intel_pm.c intel_has_sagv(struct drm_i915_private *dev_priv) dev_priv 3665 drivers/gpu/drm/i915/intel_pm.c return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) && dev_priv 3666 drivers/gpu/drm/i915/intel_pm.c dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED; dev_priv 3681 drivers/gpu/drm/i915/intel_pm.c intel_enable_sagv(struct drm_i915_private *dev_priv) dev_priv 3685 drivers/gpu/drm/i915/intel_pm.c if (!intel_has_sagv(dev_priv)) dev_priv 3688 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->sagv_status == I915_SAGV_ENABLED) dev_priv 3692 drivers/gpu/drm/i915/intel_pm.c ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL, dev_priv 3701 drivers/gpu/drm/i915/intel_pm.c if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { dev_priv 3703 drivers/gpu/drm/i915/intel_pm.c dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; dev_priv 3710 drivers/gpu/drm/i915/intel_pm.c dev_priv->sagv_status = I915_SAGV_ENABLED; dev_priv 3715 drivers/gpu/drm/i915/intel_pm.c intel_disable_sagv(struct drm_i915_private *dev_priv) dev_priv 3719 drivers/gpu/drm/i915/intel_pm.c if (!intel_has_sagv(dev_priv)) dev_priv 3722 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->sagv_status == I915_SAGV_DISABLED) dev_priv 3727 drivers/gpu/drm/i915/intel_pm.c ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL, dev_priv 3735 drivers/gpu/drm/i915/intel_pm.c if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { dev_priv 3737 drivers/gpu/drm/i915/intel_pm.c dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; dev_priv 3744 drivers/gpu/drm/i915/intel_pm.c dev_priv->sagv_status = I915_SAGV_DISABLED; dev_priv 3751 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 3759 drivers/gpu/drm/i915/intel_pm.c if (!intel_has_sagv(dev_priv)) dev_priv 3762 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 9)) dev_priv 3764 drivers/gpu/drm/i915/intel_pm.c else if (IS_GEN(dev_priv, 10)) dev_priv 3784 drivers/gpu/drm/i915/intel_pm.c crtc = intel_get_crtc_for_pipe(dev_priv, pipe); dev_priv 3799 drivers/gpu/drm/i915/intel_pm.c for (level = ilk_wm_max_level(dev_priv); dev_priv 3803 drivers/gpu/drm/i915/intel_pm.c latency = dev_priv->wm.skl_latency[level]; dev_priv 3805 drivers/gpu/drm/i915/intel_pm.c if (skl_needs_memory_bw_wa(dev_priv) && dev_priv 3822 drivers/gpu/drm/i915/intel_pm.c static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv, dev_priv 3830 drivers/gpu/drm/i915/intel_pm.c u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size; dev_priv 3834 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) < 11) dev_priv 3859 drivers/gpu/drm/i915/intel_pm.c skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, dev_priv 3878 drivers/gpu/drm/i915/intel_pm.c *num_active = hweight32(dev_priv->active_crtcs); dev_priv 3885 drivers/gpu/drm/i915/intel_pm.c *num_active = hweight32(dev_priv->active_crtcs); dev_priv 3887 drivers/gpu/drm/i915/intel_pm.c ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate, dev_priv 3949 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 3950 drivers/gpu/drm/i915/intel_pm.c int level, max_level = ilk_wm_max_level(dev_priv); dev_priv 3973 drivers/gpu/drm/i915/intel_pm.c static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv, dev_priv 3985 drivers/gpu/drm/i915/intel_pm.c skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv, dev_priv 3997 drivers/gpu/drm/i915/intel_pm.c skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); dev_priv 4009 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 11) { dev_priv 4011 drivers/gpu/drm/i915/intel_pm.c skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); dev_priv 4019 drivers/gpu/drm/i915/intel_pm.c skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); dev_priv 4020 drivers/gpu/drm/i915/intel_pm.c skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2); dev_priv 4028 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 4035 drivers/gpu/drm/i915/intel_pm.c wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); dev_priv 4040 drivers/gpu/drm/i915/intel_pm.c skl_ddb_get_hw_plane_state(dev_priv, pipe, dev_priv 4045 drivers/gpu/drm/i915/intel_pm.c intel_display_power_put(dev_priv, power_domain, wakeref); dev_priv 4048 drivers/gpu/drm/i915/intel_pm.c void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 4051 drivers/gpu/drm/i915/intel_pm.c ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv); dev_priv 4148 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); dev_priv 4188 drivers/gpu/drm/i915/intel_pm.c if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) dev_priv 4339 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->dev); dev_priv 4365 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 4376 drivers/gpu/drm/i915/intel_pm.c skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate, dev_priv 4396 drivers/gpu/drm/i915/intel_pm.c for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) { dev_priv 4482 drivers/gpu/drm/i915/intel_pm.c WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]); dev_priv 4504 drivers/gpu/drm/i915/intel_pm.c for (level++; level <= ilk_wm_max_level(dev_priv); level++) { dev_priv 4529 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 11) && dev_priv 4560 drivers/gpu/drm/i915/intel_pm.c skl_wm_method1(const struct drm_i915_private *dev_priv, u32 pixel_rate, dev_priv 4572 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 10) dev_priv 4646 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 4671 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 11 && dev_priv 4696 drivers/gpu/drm/i915/intel_pm.c if (skl_needs_memory_bw_wa(dev_priv)) dev_priv 4705 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 10) dev_priv 4710 drivers/gpu/drm/i915/intel_pm.c } else if (wp->x_tiled && IS_GEN(dev_priv, 9)) { dev_priv 4756 drivers/gpu/drm/i915/intel_pm.c static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level) dev_priv 4758 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv 4771 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 4772 drivers/gpu/drm/i915/intel_pm.c u32 latency = dev_priv->wm.skl_latency[level]; dev_priv 4787 drivers/gpu/drm/i915/intel_pm.c if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) && dev_priv 4788 drivers/gpu/drm/i915/intel_pm.c dev_priv->ipc_enabled) dev_priv 4791 drivers/gpu/drm/i915/intel_pm.c if (skl_needs_memory_bw_wa(dev_priv) && wp->x_tiled) dev_priv 4794 drivers/gpu/drm/i915/intel_pm.c method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate, dev_priv 4809 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 9) && dev_priv 4810 drivers/gpu/drm/i915/intel_pm.c !IS_GEMINILAKE(dev_priv)) dev_priv 4823 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) { dev_priv 4850 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 11) { dev_priv 4868 drivers/gpu/drm/i915/intel_pm.c if (!skl_wm_has_lines(dev_priv, level)) dev_priv 4895 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 4896 drivers/gpu/drm/i915/intel_pm.c int level, max_level = ilk_wm_max_level(dev_priv); dev_priv 4913 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(state->dev); dev_priv 4921 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) dev_priv 4932 drivers/gpu/drm/i915/intel_pm.c const struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 4938 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) <= 9) dev_priv 4942 drivers/gpu/drm/i915/intel_pm.c if (!dev_priv->ipc_enabled) dev_priv 4946 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 4972 drivers/gpu/drm/i915/intel_pm.c if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) dev_priv 5091 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 5108 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 5121 drivers/gpu/drm/i915/intel_pm.c static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, dev_priv 5131 drivers/gpu/drm/i915/intel_pm.c static void skl_write_wm_level(struct drm_i915_private *dev_priv, dev_priv 5150 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 5151 drivers/gpu/drm/i915/intel_pm.c int level, max_level = ilk_wm_max_level(dev_priv); dev_priv 5162 drivers/gpu/drm/i915/intel_pm.c skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level), dev_priv 5165 drivers/gpu/drm/i915/intel_pm.c skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id), dev_priv 5168 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 11) { dev_priv 5169 drivers/gpu/drm/i915/intel_pm.c skl_ddb_entry_write(dev_priv, dev_priv 5177 drivers/gpu/drm/i915/intel_pm.c skl_ddb_entry_write(dev_priv, dev_priv 5179 drivers/gpu/drm/i915/intel_pm.c skl_ddb_entry_write(dev_priv, dev_priv 5186 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); dev_priv 5187 drivers/gpu/drm/i915/intel_pm.c int level, max_level = ilk_wm_max_level(dev_priv); dev_priv 5196 drivers/gpu/drm/i915/intel_pm.c skl_write_wm_level(dev_priv, CUR_WM(pipe, level), dev_priv 5199 drivers/gpu/drm/i915/intel_pm.c skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm); dev_priv 5201 drivers/gpu/drm/i915/intel_pm.c skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb); dev_priv 5213 drivers/gpu/drm/i915/intel_pm.c static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv, dev_priv 5217 drivers/gpu/drm/i915/intel_pm.c int level, max_level = ilk_wm_max_level(dev_priv); dev_priv 5232 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 5236 drivers/gpu/drm/i915/intel_pm.c if (!skl_plane_wm_equals(dev_priv, dev_priv 5285 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 5288 drivers/gpu/drm/i915/intel_pm.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { dev_priv 5311 drivers/gpu/drm/i915/intel_pm.c const struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 5318 drivers/gpu/drm/i915/intel_pm.c memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb)); dev_priv 5343 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 5360 drivers/gpu/drm/i915/intel_pm.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { dev_priv 5376 drivers/gpu/drm/i915/intel_pm.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { dev_priv 5383 drivers/gpu/drm/i915/intel_pm.c if (skl_plane_wm_equals(dev_priv, old_wm, new_wm)) dev_priv 5458 drivers/gpu/drm/i915/intel_pm.c const struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 5468 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->wm.distrust_bios_wm) dev_priv 5491 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->wm.distrust_bios_wm) { dev_priv 5506 drivers/gpu/drm/i915/intel_pm.c state->active_crtcs = dev_priv->active_crtcs; dev_priv 5565 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 5572 drivers/gpu/drm/i915/intel_pm.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { dev_priv 5585 drivers/gpu/drm/i915/intel_pm.c skl_plane_wm_equals(dev_priv, dev_priv 5652 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); dev_priv 5667 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 5673 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); dev_priv 5678 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); dev_priv 5681 drivers/gpu/drm/i915/intel_pm.c static void ilk_compute_wm_config(struct drm_i915_private *dev_priv, dev_priv 5687 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 5699 drivers/gpu/drm/i915/intel_pm.c static void ilk_program_watermarks(struct drm_i915_private *dev_priv) dev_priv 5707 drivers/gpu/drm/i915/intel_pm.c ilk_compute_wm_config(dev_priv, &config); dev_priv 5709 drivers/gpu/drm/i915/intel_pm.c ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_1_2, &max); dev_priv 5710 drivers/gpu/drm/i915/intel_pm.c ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2); dev_priv 5713 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 7 && dev_priv 5715 drivers/gpu/drm/i915/intel_pm.c ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max); dev_priv 5716 drivers/gpu/drm/i915/intel_pm.c ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6); dev_priv 5718 drivers/gpu/drm/i915/intel_pm.c best_lp_wm = ilk_find_best_result(dev_priv, &lp_wm_1_2, &lp_wm_5_6); dev_priv 5726 drivers/gpu/drm/i915/intel_pm.c ilk_compute_wm_results(dev_priv, best_lp_wm, partitioning, &results); dev_priv 5728 drivers/gpu/drm/i915/intel_pm.c ilk_write_wm_values(dev_priv, &results); dev_priv 5734 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 5737 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); dev_priv 5739 drivers/gpu/drm/i915/intel_pm.c ilk_program_watermarks(dev_priv); dev_priv 5740 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); dev_priv 5746 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); dev_priv 5752 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); dev_priv 5754 drivers/gpu/drm/i915/intel_pm.c ilk_program_watermarks(dev_priv); dev_priv 5755 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); dev_priv 5771 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 5777 drivers/gpu/drm/i915/intel_pm.c max_level = ilk_wm_max_level(dev_priv); dev_priv 5805 drivers/gpu/drm/i915/intel_pm.c void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) dev_priv 5807 drivers/gpu/drm/i915/intel_pm.c struct skl_ddb_values *hw = &dev_priv->wm.skl_hw; dev_priv 5808 drivers/gpu/drm/i915/intel_pm.c struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; dev_priv 5812 drivers/gpu/drm/i915/intel_pm.c skl_ddb_get_hw_state(dev_priv, ddb); dev_priv 5813 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 5822 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->active_crtcs) { dev_priv 5824 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.distrust_bios_wm = true; dev_priv 5831 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(dev); dev_priv 5832 drivers/gpu/drm/i915/intel_pm.c struct ilk_wm_values *hw = &dev_priv->wm.hw; dev_priv 5843 drivers/gpu/drm/i915/intel_pm.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 5865 drivers/gpu/drm/i915/intel_pm.c int level, max_level = ilk_wm_max_level(dev_priv); dev_priv 5884 drivers/gpu/drm/i915/intel_pm.c static void g4x_read_wm_values(struct drm_i915_private *dev_priv, dev_priv 5910 drivers/gpu/drm/i915/intel_pm.c static void vlv_read_wm_values(struct drm_i915_private *dev_priv, dev_priv 5916 drivers/gpu/drm/i915/intel_pm.c for_each_pipe(dev_priv, pipe) { dev_priv 5943 drivers/gpu/drm/i915/intel_pm.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 5986 drivers/gpu/drm/i915/intel_pm.c void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv) dev_priv 5988 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_values *wm = &dev_priv->wm.g4x; dev_priv 5991 drivers/gpu/drm/i915/intel_pm.c g4x_read_wm_values(dev_priv, wm); dev_priv 5995 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 6070 drivers/gpu/drm/i915/intel_pm.c void g4x_wm_sanitize(struct drm_i915_private *dev_priv) dev_priv 6075 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); dev_priv 6077 drivers/gpu/drm/i915/intel_pm.c for_each_intel_plane(&dev_priv->drm, plane) { dev_priv 6079 drivers/gpu/drm/i915/intel_pm.c intel_get_crtc_for_pipe(dev_priv, plane->pipe); dev_priv 6112 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 6121 drivers/gpu/drm/i915/intel_pm.c g4x_program_watermarks(dev_priv); dev_priv 6123 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); dev_priv 6126 drivers/gpu/drm/i915/intel_pm.c void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv) dev_priv 6128 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_values *wm = &dev_priv->wm.vlv; dev_priv 6132 drivers/gpu/drm/i915/intel_pm.c vlv_read_wm_values(dev_priv, wm); dev_priv 6137 drivers/gpu/drm/i915/intel_pm.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 6138 drivers/gpu/drm/i915/intel_pm.c vlv_punit_get(dev_priv); dev_priv 6140 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); dev_priv 6153 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); dev_priv 6155 drivers/gpu/drm/i915/intel_pm.c vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); dev_priv 6157 drivers/gpu/drm/i915/intel_pm.c if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & dev_priv 6161 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; dev_priv 6163 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); dev_priv 6168 drivers/gpu/drm/i915/intel_pm.c vlv_punit_put(dev_priv); dev_priv 6171 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 6223 drivers/gpu/drm/i915/intel_pm.c void vlv_wm_sanitize(struct drm_i915_private *dev_priv) dev_priv 6228 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); dev_priv 6230 drivers/gpu/drm/i915/intel_pm.c for_each_intel_plane(&dev_priv->drm, plane) { dev_priv 6232 drivers/gpu/drm/i915/intel_pm.c intel_get_crtc_for_pipe(dev_priv, plane->pipe); dev_priv 6258 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { dev_priv 6267 drivers/gpu/drm/i915/intel_pm.c vlv_program_watermarks(dev_priv); dev_priv 6269 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); dev_priv 6276 drivers/gpu/drm/i915/intel_pm.c static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv) dev_priv 6288 drivers/gpu/drm/i915/intel_pm.c void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv) dev_priv 6290 drivers/gpu/drm/i915/intel_pm.c struct ilk_wm_values *hw = &dev_priv->wm.hw; dev_priv 6293 drivers/gpu/drm/i915/intel_pm.c ilk_init_lp_watermarks(dev_priv); dev_priv 6295 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) dev_priv 6303 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 7) { dev_priv 6308 drivers/gpu/drm/i915/intel_pm.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 6311 drivers/gpu/drm/i915/intel_pm.c else if (IS_IVYBRIDGE(dev_priv)) dev_priv 6354 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); dev_priv 6356 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->display.update_wm) dev_priv 6357 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.update_wm(crtc); dev_priv 6360 drivers/gpu/drm/i915/intel_pm.c void intel_enable_ipc(struct drm_i915_private *dev_priv) dev_priv 6364 drivers/gpu/drm/i915/intel_pm.c if (!HAS_IPC(dev_priv)) dev_priv 6369 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->ipc_enabled) dev_priv 6377 drivers/gpu/drm/i915/intel_pm.c static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv) dev_priv 6380 drivers/gpu/drm/i915/intel_pm.c if (IS_SKYLAKE(dev_priv)) dev_priv 6384 drivers/gpu/drm/i915/intel_pm.c if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) dev_priv 6385 drivers/gpu/drm/i915/intel_pm.c return dev_priv->dram_info.symmetric_memory; dev_priv 6390 drivers/gpu/drm/i915/intel_pm.c void intel_init_ipc(struct drm_i915_private *dev_priv) dev_priv 6392 drivers/gpu/drm/i915/intel_pm.c if (!HAS_IPC(dev_priv)) dev_priv 6395 drivers/gpu/drm/i915/intel_pm.c dev_priv->ipc_enabled = intel_can_enable_ipc(dev_priv); dev_priv 6397 drivers/gpu/drm/i915/intel_pm.c intel_enable_ipc(dev_priv); dev_priv 6429 drivers/gpu/drm/i915/intel_pm.c static void ironlake_enable_drps(struct drm_i915_private *dev_priv) dev_priv 6431 drivers/gpu/drm/i915/intel_pm.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 6462 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ dev_priv 6463 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.fstart = fstart; dev_priv 6465 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.max_delay = fstart; dev_priv 6466 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.min_delay = fmin; dev_priv 6467 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.cur_delay = fstart; dev_priv 6491 drivers/gpu/drm/i915/intel_pm.c ironlake_set_drps(dev_priv, fstart); dev_priv 6493 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.last_count1 = dev_priv 6497 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); dev_priv 6498 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.last_count2 = intel_uncore_read(uncore, GFXEC); dev_priv 6499 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.last_time2 = ktime_get_raw_ns(); dev_priv 6542 drivers/gpu/drm/i915/intel_pm.c static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) dev_priv 6544 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 6553 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 6566 drivers/gpu/drm/i915/intel_pm.c static void rps_set_power(struct drm_i915_private *dev_priv, int new_power) dev_priv 6568 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 6613 drivers/gpu/drm/i915/intel_pm.c if (IS_VALLEYVIEW(dev_priv)) dev_priv 6617 drivers/gpu/drm/i915/intel_pm.c GT_INTERVAL_FROM_US(dev_priv, ei_up)); dev_priv 6619 drivers/gpu/drm/i915/intel_pm.c GT_INTERVAL_FROM_US(dev_priv, dev_priv 6623 drivers/gpu/drm/i915/intel_pm.c GT_INTERVAL_FROM_US(dev_priv, ei_down)); dev_priv 6625 drivers/gpu/drm/i915/intel_pm.c GT_INTERVAL_FROM_US(dev_priv, dev_priv 6629 drivers/gpu/drm/i915/intel_pm.c (INTEL_GEN(dev_priv) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) | dev_priv 6642 drivers/gpu/drm/i915/intel_pm.c static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) dev_priv 6644 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 6679 drivers/gpu/drm/i915/intel_pm.c rps_set_power(dev_priv, new_power); dev_priv 6701 drivers/gpu/drm/i915/intel_pm.c static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) dev_priv 6703 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 6712 drivers/gpu/drm/i915/intel_pm.c mask &= dev_priv->pm_rps_events; dev_priv 6714 drivers/gpu/drm/i915/intel_pm.c return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); dev_priv 6720 drivers/gpu/drm/i915/intel_pm.c static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val) dev_priv 6722 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 6728 drivers/gpu/drm/i915/intel_pm.c gen6_set_rps_thresholds(dev_priv, val); dev_priv 6730 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 6733 drivers/gpu/drm/i915/intel_pm.c else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 6746 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); dev_priv 6747 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); dev_priv 6750 drivers/gpu/drm/i915/intel_pm.c trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); dev_priv 6755 drivers/gpu/drm/i915/intel_pm.c static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val) dev_priv 6759 drivers/gpu/drm/i915/intel_pm.c if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1), dev_priv 6763 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); dev_priv 6765 drivers/gpu/drm/i915/intel_pm.c if (val != dev_priv->gt_pm.rps.cur_freq) { dev_priv 6766 drivers/gpu/drm/i915/intel_pm.c vlv_punit_get(dev_priv); dev_priv 6767 drivers/gpu/drm/i915/intel_pm.c err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); dev_priv 6768 drivers/gpu/drm/i915/intel_pm.c vlv_punit_put(dev_priv); dev_priv 6772 drivers/gpu/drm/i915/intel_pm.c gen6_set_rps_thresholds(dev_priv, val); dev_priv 6775 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rps.cur_freq = val; dev_priv 6776 drivers/gpu/drm/i915/intel_pm.c trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); dev_priv 6788 drivers/gpu/drm/i915/intel_pm.c static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) dev_priv 6790 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 6809 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_MEDIA); dev_priv 6810 drivers/gpu/drm/i915/intel_pm.c err = valleyview_set_rps(dev_priv, val); dev_priv 6811 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_MEDIA); dev_priv 6817 drivers/gpu/drm/i915/intel_pm.c void gen6_rps_busy(struct drm_i915_private *dev_priv) dev_priv 6819 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 6825 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED) dev_priv 6826 drivers/gpu/drm/i915/intel_pm.c gen6_rps_reset_ei(dev_priv); dev_priv 6828 drivers/gpu/drm/i915/intel_pm.c gen6_rps_pm_mask(dev_priv, rps->cur_freq)); dev_priv 6830 drivers/gpu/drm/i915/intel_pm.c gen6_enable_rps_interrupts(dev_priv); dev_priv 6838 drivers/gpu/drm/i915/intel_pm.c if (intel_set_rps(dev_priv, dev_priv 6847 drivers/gpu/drm/i915/intel_pm.c void gen6_rps_idle(struct drm_i915_private *dev_priv) dev_priv 6849 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 6856 drivers/gpu/drm/i915/intel_pm.c gen6_disable_rps_interrupts(dev_priv); dev_priv 6860 drivers/gpu/drm/i915/intel_pm.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 6861 drivers/gpu/drm/i915/intel_pm.c vlv_set_rps_idle(dev_priv); dev_priv 6863 drivers/gpu/drm/i915/intel_pm.c gen6_set_rps(dev_priv, rps->idle_freq); dev_priv 6866 drivers/gpu/drm/i915/intel_pm.c gen6_sanitize_rps_pm_mask(dev_priv, ~0)); dev_priv 6904 drivers/gpu/drm/i915/intel_pm.c int intel_set_rps(struct drm_i915_private *dev_priv, u8 val) dev_priv 6906 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 6918 drivers/gpu/drm/i915/intel_pm.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv 6919 drivers/gpu/drm/i915/intel_pm.c err = valleyview_set_rps(dev_priv, val); dev_priv 6921 drivers/gpu/drm/i915/intel_pm.c err = gen6_set_rps(dev_priv, val); dev_priv 6926 drivers/gpu/drm/i915/intel_pm.c static void gen9_disable_rc6(struct drm_i915_private *dev_priv) dev_priv 6932 drivers/gpu/drm/i915/intel_pm.c static void gen9_disable_rps(struct drm_i915_private *dev_priv) dev_priv 6937 drivers/gpu/drm/i915/intel_pm.c static void gen6_disable_rc6(struct drm_i915_private *dev_priv) dev_priv 6942 drivers/gpu/drm/i915/intel_pm.c static void gen6_disable_rps(struct drm_i915_private *dev_priv) dev_priv 6948 drivers/gpu/drm/i915/intel_pm.c static void cherryview_disable_rc6(struct drm_i915_private *dev_priv) dev_priv 6953 drivers/gpu/drm/i915/intel_pm.c static void cherryview_disable_rps(struct drm_i915_private *dev_priv) dev_priv 6958 drivers/gpu/drm/i915/intel_pm.c static void valleyview_disable_rc6(struct drm_i915_private *dev_priv) dev_priv 6962 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 6966 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 6969 drivers/gpu/drm/i915/intel_pm.c static void valleyview_disable_rps(struct drm_i915_private *dev_priv) dev_priv 6974 drivers/gpu/drm/i915/intel_pm.c static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv) dev_priv 7000 drivers/gpu/drm/i915/intel_pm.c if (!((rc6_ctx_base >= dev_priv->dsm_reserved.start) && dev_priv 7001 drivers/gpu/drm/i915/intel_pm.c (rc6_ctx_base + PAGE_SIZE < dev_priv->dsm_reserved.end))) { dev_priv 7062 drivers/gpu/drm/i915/intel_pm.c static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) dev_priv 7064 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 7069 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN9_LP(dev_priv)) { dev_priv 7084 drivers/gpu/drm/i915/intel_pm.c if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || dev_priv 7085 drivers/gpu/drm/i915/intel_pm.c IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { dev_priv 7088 drivers/gpu/drm/i915/intel_pm.c if (sandybridge_pcode_read(dev_priv, dev_priv 7098 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { dev_priv 7110 drivers/gpu/drm/i915/intel_pm.c static void reset_rps(struct drm_i915_private *dev_priv, dev_priv 7113 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 7120 drivers/gpu/drm/i915/intel_pm.c if (set(dev_priv, freq)) dev_priv 7125 drivers/gpu/drm/i915/intel_pm.c static void gen9_enable_rps(struct drm_i915_private *dev_priv) dev_priv 7127 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7130 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 9)) dev_priv 7132 drivers/gpu/drm/i915/intel_pm.c GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq)); dev_priv 7136 drivers/gpu/drm/i915/intel_pm.c GT_INTERVAL_FROM_US(dev_priv, 1000000)); dev_priv 7143 drivers/gpu/drm/i915/intel_pm.c reset_rps(dev_priv, gen6_set_rps); dev_priv 7145 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7148 drivers/gpu/drm/i915/intel_pm.c static void gen11_enable_rc6(struct drm_i915_private *dev_priv) dev_priv 7160 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7171 drivers/gpu/drm/i915/intel_pm.c for_each_engine(engine, dev_priv, id) dev_priv 7174 drivers/gpu/drm/i915/intel_pm.c if (HAS_GT_UC(dev_priv)) dev_priv 7217 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7220 drivers/gpu/drm/i915/intel_pm.c static void gen9_enable_rc6(struct drm_i915_private *dev_priv) dev_priv 7231 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7237 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 10) { dev_priv 7240 drivers/gpu/drm/i915/intel_pm.c } else if (IS_SKYLAKE(dev_priv)) { dev_priv 7252 drivers/gpu/drm/i915/intel_pm.c for_each_engine(engine, dev_priv, id) dev_priv 7255 drivers/gpu/drm/i915/intel_pm.c if (HAS_GT_UC(dev_priv)) dev_priv 7288 drivers/gpu/drm/i915/intel_pm.c if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_C0)) dev_priv 7302 drivers/gpu/drm/i915/intel_pm.c if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) dev_priv 7308 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7311 drivers/gpu/drm/i915/intel_pm.c static void gen8_enable_rc6(struct drm_i915_private *dev_priv) dev_priv 7321 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7330 drivers/gpu/drm/i915/intel_pm.c for_each_engine(engine, dev_priv, id) dev_priv 7342 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7345 drivers/gpu/drm/i915/intel_pm.c static void gen8_enable_rps(struct drm_i915_private *dev_priv) dev_priv 7347 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 7349 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7380 drivers/gpu/drm/i915/intel_pm.c reset_rps(dev_priv, gen6_set_rps); dev_priv 7382 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7385 drivers/gpu/drm/i915/intel_pm.c static void gen6_enable_rc6(struct drm_i915_private *dev_priv) dev_priv 7402 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7413 drivers/gpu/drm/i915/intel_pm.c for_each_engine(engine, dev_priv, id) dev_priv 7418 drivers/gpu/drm/i915/intel_pm.c if (IS_IVYBRIDGE(dev_priv)) dev_priv 7427 drivers/gpu/drm/i915/intel_pm.c if (HAS_RC6p(dev_priv)) dev_priv 7429 drivers/gpu/drm/i915/intel_pm.c if (HAS_RC6pp(dev_priv)) dev_priv 7437 drivers/gpu/drm/i915/intel_pm.c ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, dev_priv 7439 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 6) && ret) { dev_priv 7441 drivers/gpu/drm/i915/intel_pm.c } else if (IS_GEN(dev_priv, 6) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { dev_priv 7446 drivers/gpu/drm/i915/intel_pm.c ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); dev_priv 7451 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7454 drivers/gpu/drm/i915/intel_pm.c static void gen6_enable_rps(struct drm_i915_private *dev_priv) dev_priv 7462 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7468 drivers/gpu/drm/i915/intel_pm.c reset_rps(dev_priv, gen6_set_rps); dev_priv 7470 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7473 drivers/gpu/drm/i915/intel_pm.c static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) dev_priv 7475 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 7509 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { dev_priv 7524 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { dev_priv 7530 drivers/gpu/drm/i915/intel_pm.c } else if (INTEL_GEN(dev_priv) >= 8) { dev_priv 7533 drivers/gpu/drm/i915/intel_pm.c } else if (IS_HASWELL(dev_priv)) { dev_priv 7552 drivers/gpu/drm/i915/intel_pm.c sandybridge_pcode_write(dev_priv, dev_priv 7560 drivers/gpu/drm/i915/intel_pm.c static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) dev_priv 7564 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); dev_priv 7566 drivers/gpu/drm/i915/intel_pm.c switch (RUNTIME_INFO(dev_priv)->sseu.eu_total) { dev_priv 7588 drivers/gpu/drm/i915/intel_pm.c static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) dev_priv 7592 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); dev_priv 7598 drivers/gpu/drm/i915/intel_pm.c static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) dev_priv 7602 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); dev_priv 7608 drivers/gpu/drm/i915/intel_pm.c static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv) dev_priv 7612 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE); dev_priv 7619 drivers/gpu/drm/i915/intel_pm.c static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) dev_priv 7623 drivers/gpu/drm/i915/intel_pm.c val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); dev_priv 7630 drivers/gpu/drm/i915/intel_pm.c static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) dev_priv 7634 drivers/gpu/drm/i915/intel_pm.c val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); dev_priv 7643 drivers/gpu/drm/i915/intel_pm.c static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) dev_priv 7647 drivers/gpu/drm/i915/intel_pm.c val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); dev_priv 7649 drivers/gpu/drm/i915/intel_pm.c val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); dev_priv 7655 drivers/gpu/drm/i915/intel_pm.c static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) dev_priv 7659 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; dev_priv 7671 drivers/gpu/drm/i915/intel_pm.c static void valleyview_check_pctx(struct drm_i915_private *dev_priv) dev_priv 7675 drivers/gpu/drm/i915/intel_pm.c WARN_ON(pctx_addr != dev_priv->dsm.start + dev_priv 7676 drivers/gpu/drm/i915/intel_pm.c dev_priv->vlv_pctx->stolen->start); dev_priv 7681 drivers/gpu/drm/i915/intel_pm.c static void cherryview_check_pctx(struct drm_i915_private *dev_priv) dev_priv 7688 drivers/gpu/drm/i915/intel_pm.c static void cherryview_setup_pctx(struct drm_i915_private *dev_priv) dev_priv 7697 drivers/gpu/drm/i915/intel_pm.c paddr = dev_priv->dsm.end + 1 - pctx_size; dev_priv 7707 drivers/gpu/drm/i915/intel_pm.c static void valleyview_setup_pctx(struct drm_i915_private *dev_priv) dev_priv 7719 drivers/gpu/drm/i915/intel_pm.c pcbr_offset = (pcbr & (~4095)) - dev_priv->dsm.start; dev_priv 7720 drivers/gpu/drm/i915/intel_pm.c pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv, dev_priv 7737 drivers/gpu/drm/i915/intel_pm.c pctx = i915_gem_object_create_stolen(dev_priv, pctx_size); dev_priv 7744 drivers/gpu/drm/i915/intel_pm.c dev_priv->dsm.start, dev_priv 7747 drivers/gpu/drm/i915/intel_pm.c pctx_paddr = dev_priv->dsm.start + pctx->stolen->start; dev_priv 7752 drivers/gpu/drm/i915/intel_pm.c dev_priv->vlv_pctx = pctx; dev_priv 7755 drivers/gpu/drm/i915/intel_pm.c static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv) dev_priv 7759 drivers/gpu/drm/i915/intel_pm.c pctx = fetch_and_zero(&dev_priv->vlv_pctx); dev_priv 7764 drivers/gpu/drm/i915/intel_pm.c static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv) dev_priv 7766 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rps.gpll_ref_freq = dev_priv 7767 drivers/gpu/drm/i915/intel_pm.c vlv_get_cck_clock(dev_priv, "GPLL ref", dev_priv 7769 drivers/gpu/drm/i915/intel_pm.c dev_priv->czclk_freq); dev_priv 7772 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rps.gpll_ref_freq); dev_priv 7775 drivers/gpu/drm/i915/intel_pm.c static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv) dev_priv 7777 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 7780 drivers/gpu/drm/i915/intel_pm.c valleyview_setup_pctx(dev_priv); dev_priv 7782 drivers/gpu/drm/i915/intel_pm.c vlv_iosf_sb_get(dev_priv, dev_priv 7787 drivers/gpu/drm/i915/intel_pm.c vlv_init_gpll_ref_freq(dev_priv); dev_priv 7789 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); dev_priv 7793 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq = 800; dev_priv 7796 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq = 1066; dev_priv 7799 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq = 1333; dev_priv 7802 drivers/gpu/drm/i915/intel_pm.c DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); dev_priv 7804 drivers/gpu/drm/i915/intel_pm.c rps->max_freq = valleyview_rps_max_freq(dev_priv); dev_priv 7807 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->max_freq), dev_priv 7810 drivers/gpu/drm/i915/intel_pm.c rps->efficient_freq = valleyview_rps_rpe_freq(dev_priv); dev_priv 7812 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->efficient_freq), dev_priv 7815 drivers/gpu/drm/i915/intel_pm.c rps->rp1_freq = valleyview_rps_guar_freq(dev_priv); dev_priv 7817 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->rp1_freq), dev_priv 7820 drivers/gpu/drm/i915/intel_pm.c rps->min_freq = valleyview_rps_min_freq(dev_priv); dev_priv 7822 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->min_freq), dev_priv 7825 drivers/gpu/drm/i915/intel_pm.c vlv_iosf_sb_put(dev_priv, dev_priv 7831 drivers/gpu/drm/i915/intel_pm.c static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv) dev_priv 7833 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 7836 drivers/gpu/drm/i915/intel_pm.c cherryview_setup_pctx(dev_priv); dev_priv 7838 drivers/gpu/drm/i915/intel_pm.c vlv_iosf_sb_get(dev_priv, dev_priv 7843 drivers/gpu/drm/i915/intel_pm.c vlv_init_gpll_ref_freq(dev_priv); dev_priv 7845 drivers/gpu/drm/i915/intel_pm.c val = vlv_cck_read(dev_priv, CCK_FUSE_REG); dev_priv 7849 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq = 2000; dev_priv 7852 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq = 1600; dev_priv 7855 drivers/gpu/drm/i915/intel_pm.c DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); dev_priv 7857 drivers/gpu/drm/i915/intel_pm.c rps->max_freq = cherryview_rps_max_freq(dev_priv); dev_priv 7860 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->max_freq), dev_priv 7863 drivers/gpu/drm/i915/intel_pm.c rps->efficient_freq = cherryview_rps_rpe_freq(dev_priv); dev_priv 7865 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->efficient_freq), dev_priv 7868 drivers/gpu/drm/i915/intel_pm.c rps->rp1_freq = cherryview_rps_guar_freq(dev_priv); dev_priv 7870 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->rp1_freq), dev_priv 7873 drivers/gpu/drm/i915/intel_pm.c rps->min_freq = cherryview_rps_min_freq(dev_priv); dev_priv 7875 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->min_freq), dev_priv 7878 drivers/gpu/drm/i915/intel_pm.c vlv_iosf_sb_put(dev_priv, dev_priv 7888 drivers/gpu/drm/i915/intel_pm.c static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv) dev_priv 7890 drivers/gpu/drm/i915/intel_pm.c valleyview_cleanup_pctx(dev_priv); dev_priv 7893 drivers/gpu/drm/i915/intel_pm.c static void cherryview_enable_rc6(struct drm_i915_private *dev_priv) dev_priv 7907 drivers/gpu/drm/i915/intel_pm.c cherryview_check_pctx(dev_priv); dev_priv 7911 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7921 drivers/gpu/drm/i915/intel_pm.c for_each_engine(engine, dev_priv, id) dev_priv 7943 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7946 drivers/gpu/drm/i915/intel_pm.c static void cherryview_enable_rps(struct drm_i915_private *dev_priv) dev_priv 7950 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7970 drivers/gpu/drm/i915/intel_pm.c vlv_punit_get(dev_priv); dev_priv 7973 drivers/gpu/drm/i915/intel_pm.c vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); dev_priv 7975 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); dev_priv 7977 drivers/gpu/drm/i915/intel_pm.c vlv_punit_put(dev_priv); dev_priv 7985 drivers/gpu/drm/i915/intel_pm.c reset_rps(dev_priv, valleyview_set_rps); dev_priv 7987 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 7990 drivers/gpu/drm/i915/intel_pm.c static void valleyview_enable_rc6(struct drm_i915_private *dev_priv) dev_priv 7996 drivers/gpu/drm/i915/intel_pm.c valleyview_check_pctx(dev_priv); dev_priv 8005 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 8014 drivers/gpu/drm/i915/intel_pm.c for_each_engine(engine, dev_priv, id) dev_priv 8030 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 8033 drivers/gpu/drm/i915/intel_pm.c static void valleyview_enable_rps(struct drm_i915_private *dev_priv) dev_priv 8037 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 8055 drivers/gpu/drm/i915/intel_pm.c vlv_punit_get(dev_priv); dev_priv 8059 drivers/gpu/drm/i915/intel_pm.c vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); dev_priv 8061 drivers/gpu/drm/i915/intel_pm.c val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); dev_priv 8063 drivers/gpu/drm/i915/intel_pm.c vlv_punit_put(dev_priv); dev_priv 8071 drivers/gpu/drm/i915/intel_pm.c reset_rps(dev_priv, valleyview_set_rps); dev_priv 8073 drivers/gpu/drm/i915/intel_pm.c intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); dev_priv 8105 drivers/gpu/drm/i915/intel_pm.c static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) dev_priv 8114 drivers/gpu/drm/i915/intel_pm.c diff1 = now - dev_priv->ips.last_time1; dev_priv 8122 drivers/gpu/drm/i915/intel_pm.c return dev_priv->ips.chipset_power; dev_priv 8131 drivers/gpu/drm/i915/intel_pm.c if (total_count < dev_priv->ips.last_count1) { dev_priv 8132 drivers/gpu/drm/i915/intel_pm.c diff = ~0UL - dev_priv->ips.last_count1; dev_priv 8135 drivers/gpu/drm/i915/intel_pm.c diff = total_count - dev_priv->ips.last_count1; dev_priv 8139 drivers/gpu/drm/i915/intel_pm.c if (cparams[i].i == dev_priv->ips.c_m && dev_priv 8140 drivers/gpu/drm/i915/intel_pm.c cparams[i].t == dev_priv->ips.r_t) { dev_priv 8151 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.last_count1 = total_count; dev_priv 8152 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.last_time1 = now; dev_priv 8154 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.chipset_power = ret; dev_priv 8159 drivers/gpu/drm/i915/intel_pm.c unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) dev_priv 8164 drivers/gpu/drm/i915/intel_pm.c if (!IS_GEN(dev_priv, 5)) dev_priv 8167 drivers/gpu/drm/i915/intel_pm.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { dev_priv 8169 drivers/gpu/drm/i915/intel_pm.c val = __i915_chipset_val(dev_priv); dev_priv 8202 drivers/gpu/drm/i915/intel_pm.c static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) dev_priv 8207 drivers/gpu/drm/i915/intel_pm.c if (INTEL_INFO(dev_priv)->is_mobile) dev_priv 8213 drivers/gpu/drm/i915/intel_pm.c static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) dev_priv 8221 drivers/gpu/drm/i915/intel_pm.c diffms = now - dev_priv->ips.last_time2; dev_priv 8230 drivers/gpu/drm/i915/intel_pm.c if (count < dev_priv->ips.last_count2) { dev_priv 8231 drivers/gpu/drm/i915/intel_pm.c diff = ~0UL - dev_priv->ips.last_count2; dev_priv 8234 drivers/gpu/drm/i915/intel_pm.c diff = count - dev_priv->ips.last_count2; dev_priv 8237 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.last_count2 = count; dev_priv 8238 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.last_time2 = now; dev_priv 8243 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.gfx_power = diff; dev_priv 8246 drivers/gpu/drm/i915/intel_pm.c void i915_update_gfx_val(struct drm_i915_private *dev_priv) dev_priv 8250 drivers/gpu/drm/i915/intel_pm.c if (!IS_GEN(dev_priv, 5)) dev_priv 8253 drivers/gpu/drm/i915/intel_pm.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { dev_priv 8255 drivers/gpu/drm/i915/intel_pm.c __i915_update_gfx_val(dev_priv); dev_priv 8260 drivers/gpu/drm/i915/intel_pm.c static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) dev_priv 8267 drivers/gpu/drm/i915/intel_pm.c pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq)); dev_priv 8269 drivers/gpu/drm/i915/intel_pm.c ext_v = pvid_to_extvid(dev_priv, pxvid); dev_priv 8273 drivers/gpu/drm/i915/intel_pm.c t = i915_mch_val(dev_priv); dev_priv 8287 drivers/gpu/drm/i915/intel_pm.c corr2 = (corr * dev_priv->ips.corr); dev_priv 8292 drivers/gpu/drm/i915/intel_pm.c __i915_update_gfx_val(dev_priv); dev_priv 8294 drivers/gpu/drm/i915/intel_pm.c return dev_priv->ips.gfx_power + state2; dev_priv 8297 drivers/gpu/drm/i915/intel_pm.c unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) dev_priv 8302 drivers/gpu/drm/i915/intel_pm.c if (!IS_GEN(dev_priv, 5)) dev_priv 8305 drivers/gpu/drm/i915/intel_pm.c with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { dev_priv 8307 drivers/gpu/drm/i915/intel_pm.c val = __i915_gfx_val(dev_priv); dev_priv 8471 drivers/gpu/drm/i915/intel_pm.c void intel_gpu_ips_init(struct drm_i915_private *dev_priv) dev_priv 8475 drivers/gpu/drm/i915/intel_pm.c rcu_assign_pointer(i915_mch_dev, dev_priv); dev_priv 8485 drivers/gpu/drm/i915/intel_pm.c static void intel_init_emon(struct drm_i915_private *dev_priv) dev_priv 8552 drivers/gpu/drm/i915/intel_pm.c dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); dev_priv 8555 drivers/gpu/drm/i915/intel_pm.c static bool i915_rc6_ctx_corrupted(struct drm_i915_private *dev_priv) dev_priv 8616 drivers/gpu/drm/i915/intel_pm.c static void intel_disable_rc6(struct drm_i915_private *dev_priv); dev_priv 8649 drivers/gpu/drm/i915/intel_pm.c void intel_init_gt_powersave(struct drm_i915_private *dev_priv) dev_priv 8651 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 8657 drivers/gpu/drm/i915/intel_pm.c if (!sanitize_rc6(dev_priv)) { dev_priv 8659 drivers/gpu/drm/i915/intel_pm.c pm_runtime_get(&dev_priv->drm.pdev->dev); dev_priv 8662 drivers/gpu/drm/i915/intel_pm.c i915_rc6_ctx_wa_init(dev_priv); dev_priv 8665 drivers/gpu/drm/i915/intel_pm.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 8666 drivers/gpu/drm/i915/intel_pm.c cherryview_init_gt_powersave(dev_priv); dev_priv 8667 drivers/gpu/drm/i915/intel_pm.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 8668 drivers/gpu/drm/i915/intel_pm.c valleyview_init_gt_powersave(dev_priv); dev_priv 8669 drivers/gpu/drm/i915/intel_pm.c else if (INTEL_GEN(dev_priv) >= 6) dev_priv 8670 drivers/gpu/drm/i915/intel_pm.c gen6_init_rps_frequencies(dev_priv); dev_priv 8677 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 6) || dev_priv 8678 drivers/gpu/drm/i915/intel_pm.c IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { dev_priv 8681 drivers/gpu/drm/i915/intel_pm.c sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, dev_priv 8697 drivers/gpu/drm/i915/intel_pm.c void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv) dev_priv 8699 drivers/gpu/drm/i915/intel_pm.c if (IS_VALLEYVIEW(dev_priv)) dev_priv 8700 drivers/gpu/drm/i915/intel_pm.c valleyview_cleanup_gt_powersave(dev_priv); dev_priv 8702 drivers/gpu/drm/i915/intel_pm.c i915_rc6_ctx_wa_cleanup(dev_priv); dev_priv 8704 drivers/gpu/drm/i915/intel_pm.c if (!HAS_RC6(dev_priv)) dev_priv 8705 drivers/gpu/drm/i915/intel_pm.c pm_runtime_put(&dev_priv->drm.pdev->dev); dev_priv 8708 drivers/gpu/drm/i915/intel_pm.c void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) dev_priv 8710 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */ dev_priv 8711 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */ dev_priv 8712 drivers/gpu/drm/i915/intel_pm.c intel_disable_gt_powersave(dev_priv); dev_priv 8714 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 11) dev_priv 8715 drivers/gpu/drm/i915/intel_pm.c gen11_reset_rps_interrupts(dev_priv); dev_priv 8716 drivers/gpu/drm/i915/intel_pm.c else if (INTEL_GEN(dev_priv) >= 6) dev_priv 8717 drivers/gpu/drm/i915/intel_pm.c gen6_reset_rps_interrupts(dev_priv); dev_priv 8732 drivers/gpu/drm/i915/intel_pm.c static void __intel_disable_rc6(struct drm_i915_private *dev_priv) dev_priv 8734 drivers/gpu/drm/i915/intel_pm.c lockdep_assert_held(&dev_priv->gt_pm.rps.lock); dev_priv 8736 drivers/gpu/drm/i915/intel_pm.c if (!dev_priv->gt_pm.rc6.enabled) dev_priv 8739 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 8740 drivers/gpu/drm/i915/intel_pm.c gen9_disable_rc6(dev_priv); dev_priv 8741 drivers/gpu/drm/i915/intel_pm.c else if (IS_CHERRYVIEW(dev_priv)) dev_priv 8742 drivers/gpu/drm/i915/intel_pm.c cherryview_disable_rc6(dev_priv); dev_priv 8743 drivers/gpu/drm/i915/intel_pm.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 8744 drivers/gpu/drm/i915/intel_pm.c valleyview_disable_rc6(dev_priv); dev_priv 8745 drivers/gpu/drm/i915/intel_pm.c else if (INTEL_GEN(dev_priv) >= 6) dev_priv 8746 drivers/gpu/drm/i915/intel_pm.c gen6_disable_rc6(dev_priv); dev_priv 8748 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rc6.enabled = false; dev_priv 8751 drivers/gpu/drm/i915/intel_pm.c static void intel_disable_rc6(struct drm_i915_private *dev_priv) dev_priv 8753 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 8756 drivers/gpu/drm/i915/intel_pm.c __intel_disable_rc6(dev_priv); dev_priv 8760 drivers/gpu/drm/i915/intel_pm.c static void intel_disable_rps(struct drm_i915_private *dev_priv) dev_priv 8762 drivers/gpu/drm/i915/intel_pm.c lockdep_assert_held(&dev_priv->gt_pm.rps.lock); dev_priv 8764 drivers/gpu/drm/i915/intel_pm.c if (!dev_priv->gt_pm.rps.enabled) dev_priv 8767 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 8768 drivers/gpu/drm/i915/intel_pm.c gen9_disable_rps(dev_priv); dev_priv 8769 drivers/gpu/drm/i915/intel_pm.c else if (IS_CHERRYVIEW(dev_priv)) dev_priv 8770 drivers/gpu/drm/i915/intel_pm.c cherryview_disable_rps(dev_priv); dev_priv 8771 drivers/gpu/drm/i915/intel_pm.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 8772 drivers/gpu/drm/i915/intel_pm.c valleyview_disable_rps(dev_priv); dev_priv 8773 drivers/gpu/drm/i915/intel_pm.c else if (INTEL_GEN(dev_priv) >= 6) dev_priv 8774 drivers/gpu/drm/i915/intel_pm.c gen6_disable_rps(dev_priv); dev_priv 8775 drivers/gpu/drm/i915/intel_pm.c else if (IS_IRONLAKE_M(dev_priv)) dev_priv 8776 drivers/gpu/drm/i915/intel_pm.c ironlake_disable_drps(dev_priv); dev_priv 8778 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rps.enabled = false; dev_priv 8781 drivers/gpu/drm/i915/intel_pm.c void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) dev_priv 8783 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->gt_pm.rps.lock); dev_priv 8785 drivers/gpu/drm/i915/intel_pm.c __intel_disable_rc6(dev_priv); dev_priv 8786 drivers/gpu/drm/i915/intel_pm.c intel_disable_rps(dev_priv); dev_priv 8787 drivers/gpu/drm/i915/intel_pm.c if (HAS_LLC(dev_priv)) dev_priv 8788 drivers/gpu/drm/i915/intel_pm.c intel_disable_llc_pstate(dev_priv); dev_priv 8790 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->gt_pm.rps.lock); dev_priv 8805 drivers/gpu/drm/i915/intel_pm.c static void intel_enable_rc6(struct drm_i915_private *dev_priv) dev_priv 8807 drivers/gpu/drm/i915/intel_pm.c lockdep_assert_held(&dev_priv->gt_pm.rps.lock); dev_priv 8809 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->gt_pm.rc6.enabled) dev_priv 8812 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->gt_pm.rc6.ctx_corrupted) dev_priv 8815 drivers/gpu/drm/i915/intel_pm.c if (IS_CHERRYVIEW(dev_priv)) dev_priv 8816 drivers/gpu/drm/i915/intel_pm.c cherryview_enable_rc6(dev_priv); dev_priv 8817 drivers/gpu/drm/i915/intel_pm.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 8818 drivers/gpu/drm/i915/intel_pm.c valleyview_enable_rc6(dev_priv); dev_priv 8819 drivers/gpu/drm/i915/intel_pm.c else if (INTEL_GEN(dev_priv) >= 11) dev_priv 8820 drivers/gpu/drm/i915/intel_pm.c gen11_enable_rc6(dev_priv); dev_priv 8821 drivers/gpu/drm/i915/intel_pm.c else if (INTEL_GEN(dev_priv) >= 9) dev_priv 8822 drivers/gpu/drm/i915/intel_pm.c gen9_enable_rc6(dev_priv); dev_priv 8823 drivers/gpu/drm/i915/intel_pm.c else if (IS_BROADWELL(dev_priv)) dev_priv 8824 drivers/gpu/drm/i915/intel_pm.c gen8_enable_rc6(dev_priv); dev_priv 8825 drivers/gpu/drm/i915/intel_pm.c else if (INTEL_GEN(dev_priv) >= 6) dev_priv 8826 drivers/gpu/drm/i915/intel_pm.c gen6_enable_rc6(dev_priv); dev_priv 8828 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rc6.enabled = true; dev_priv 8831 drivers/gpu/drm/i915/intel_pm.c static void intel_enable_rps(struct drm_i915_private *dev_priv) dev_priv 8833 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 8840 drivers/gpu/drm/i915/intel_pm.c if (IS_CHERRYVIEW(dev_priv)) { dev_priv 8841 drivers/gpu/drm/i915/intel_pm.c cherryview_enable_rps(dev_priv); dev_priv 8842 drivers/gpu/drm/i915/intel_pm.c } else if (IS_VALLEYVIEW(dev_priv)) { dev_priv 8843 drivers/gpu/drm/i915/intel_pm.c valleyview_enable_rps(dev_priv); dev_priv 8844 drivers/gpu/drm/i915/intel_pm.c } else if (INTEL_GEN(dev_priv) >= 9) { dev_priv 8845 drivers/gpu/drm/i915/intel_pm.c gen9_enable_rps(dev_priv); dev_priv 8846 drivers/gpu/drm/i915/intel_pm.c } else if (IS_BROADWELL(dev_priv)) { dev_priv 8847 drivers/gpu/drm/i915/intel_pm.c gen8_enable_rps(dev_priv); dev_priv 8848 drivers/gpu/drm/i915/intel_pm.c } else if (INTEL_GEN(dev_priv) >= 6) { dev_priv 8849 drivers/gpu/drm/i915/intel_pm.c gen6_enable_rps(dev_priv); dev_priv 8850 drivers/gpu/drm/i915/intel_pm.c } else if (IS_IRONLAKE_M(dev_priv)) { dev_priv 8851 drivers/gpu/drm/i915/intel_pm.c ironlake_enable_drps(dev_priv); dev_priv 8852 drivers/gpu/drm/i915/intel_pm.c intel_init_emon(dev_priv); dev_priv 8864 drivers/gpu/drm/i915/intel_pm.c void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) dev_priv 8867 drivers/gpu/drm/i915/intel_pm.c if (intel_vgpu_active(dev_priv)) dev_priv 8870 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->gt_pm.rps.lock); dev_priv 8872 drivers/gpu/drm/i915/intel_pm.c if (HAS_RC6(dev_priv)) dev_priv 8873 drivers/gpu/drm/i915/intel_pm.c intel_enable_rc6(dev_priv); dev_priv 8874 drivers/gpu/drm/i915/intel_pm.c if (HAS_RPS(dev_priv)) dev_priv 8875 drivers/gpu/drm/i915/intel_pm.c intel_enable_rps(dev_priv); dev_priv 8876 drivers/gpu/drm/i915/intel_pm.c if (HAS_LLC(dev_priv)) dev_priv 8877 drivers/gpu/drm/i915/intel_pm.c intel_enable_llc_pstate(dev_priv); dev_priv 8879 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->gt_pm.rps.lock); dev_priv 8882 drivers/gpu/drm/i915/intel_pm.c static void ibx_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 8892 drivers/gpu/drm/i915/intel_pm.c static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) dev_priv 8896 drivers/gpu/drm/i915/intel_pm.c for_each_pipe(dev_priv, pipe) { dev_priv 8906 drivers/gpu/drm/i915/intel_pm.c static void ilk_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 8946 drivers/gpu/drm/i915/intel_pm.c if (IS_IRONLAKE_M(dev_priv)) { dev_priv 8972 drivers/gpu/drm/i915/intel_pm.c g4x_disable_trickle_feed(dev_priv); dev_priv 8974 drivers/gpu/drm/i915/intel_pm.c ibx_init_clock_gating(dev_priv); dev_priv 8977 drivers/gpu/drm/i915/intel_pm.c static void cpt_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 8995 drivers/gpu/drm/i915/intel_pm.c for_each_pipe(dev_priv, pipe) { dev_priv 8999 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->vbt.fdi_rx_polarity_inverted) dev_priv 9007 drivers/gpu/drm/i915/intel_pm.c for_each_pipe(dev_priv, pipe) { dev_priv 9013 drivers/gpu/drm/i915/intel_pm.c static void gen6_check_mch_setup(struct drm_i915_private *dev_priv) dev_priv 9023 drivers/gpu/drm/i915/intel_pm.c static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9110 drivers/gpu/drm/i915/intel_pm.c g4x_disable_trickle_feed(dev_priv); dev_priv 9112 drivers/gpu/drm/i915/intel_pm.c cpt_init_clock_gating(dev_priv); dev_priv 9114 drivers/gpu/drm/i915/intel_pm.c gen6_check_mch_setup(dev_priv); dev_priv 9117 drivers/gpu/drm/i915/intel_pm.c static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) dev_priv 9135 drivers/gpu/drm/i915/intel_pm.c static void lpt_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9141 drivers/gpu/drm/i915/intel_pm.c if (HAS_PCH_LPT_LP(dev_priv)) dev_priv 9152 drivers/gpu/drm/i915/intel_pm.c static void lpt_suspend_hw(struct drm_i915_private *dev_priv) dev_priv 9154 drivers/gpu/drm/i915/intel_pm.c if (HAS_PCH_LPT_LP(dev_priv)) { dev_priv 9162 drivers/gpu/drm/i915/intel_pm.c static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, dev_priv 9188 drivers/gpu/drm/i915/intel_pm.c static void icl_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9202 drivers/gpu/drm/i915/intel_pm.c intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE, dev_priv 9206 drivers/gpu/drm/i915/intel_pm.c intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2, dev_priv 9210 drivers/gpu/drm/i915/intel_pm.c static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9212 drivers/gpu/drm/i915/intel_pm.c if (!HAS_PCH_CNP(dev_priv)) dev_priv 9220 drivers/gpu/drm/i915/intel_pm.c static void cnl_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9223 drivers/gpu/drm/i915/intel_pm.c cnp_init_clock_gating(dev_priv); dev_priv 9241 drivers/gpu/drm/i915/intel_pm.c if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) dev_priv 9257 drivers/gpu/drm/i915/intel_pm.c static void cfl_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9259 drivers/gpu/drm/i915/intel_pm.c cnp_init_clock_gating(dev_priv); dev_priv 9260 drivers/gpu/drm/i915/intel_pm.c gen9_init_clock_gating(dev_priv); dev_priv 9267 drivers/gpu/drm/i915/intel_pm.c static void kbl_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9269 drivers/gpu/drm/i915/intel_pm.c gen9_init_clock_gating(dev_priv); dev_priv 9272 drivers/gpu/drm/i915/intel_pm.c if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) dev_priv 9277 drivers/gpu/drm/i915/intel_pm.c if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) dev_priv 9286 drivers/gpu/drm/i915/intel_pm.c static void skl_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9288 drivers/gpu/drm/i915/intel_pm.c gen9_init_clock_gating(dev_priv); dev_priv 9299 drivers/gpu/drm/i915/intel_pm.c static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9311 drivers/gpu/drm/i915/intel_pm.c for_each_pipe(dev_priv, pipe) { dev_priv 9331 drivers/gpu/drm/i915/intel_pm.c gen8_set_l3sqc_credits(dev_priv, 30, 2); dev_priv 9337 drivers/gpu/drm/i915/intel_pm.c lpt_init_clock_gating(dev_priv); dev_priv 9348 drivers/gpu/drm/i915/intel_pm.c static void hsw_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9393 drivers/gpu/drm/i915/intel_pm.c lpt_init_clock_gating(dev_priv); dev_priv 9396 drivers/gpu/drm/i915/intel_pm.c static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9412 drivers/gpu/drm/i915/intel_pm.c if (IS_IVB_GT1(dev_priv)) dev_priv 9428 drivers/gpu/drm/i915/intel_pm.c if (IS_IVB_GT1(dev_priv)) dev_priv 9455 drivers/gpu/drm/i915/intel_pm.c g4x_disable_trickle_feed(dev_priv); dev_priv 9457 drivers/gpu/drm/i915/intel_pm.c gen7_setup_fixed_func_scheduler(dev_priv); dev_priv 9485 drivers/gpu/drm/i915/intel_pm.c if (!HAS_PCH_NOP(dev_priv)) dev_priv 9486 drivers/gpu/drm/i915/intel_pm.c cpt_init_clock_gating(dev_priv); dev_priv 9488 drivers/gpu/drm/i915/intel_pm.c gen6_check_mch_setup(dev_priv); dev_priv 9491 drivers/gpu/drm/i915/intel_pm.c static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9524 drivers/gpu/drm/i915/intel_pm.c gen7_setup_fixed_func_scheduler(dev_priv); dev_priv 9571 drivers/gpu/drm/i915/intel_pm.c static void chv_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9596 drivers/gpu/drm/i915/intel_pm.c gen8_set_l3sqc_credits(dev_priv, 38, 2); dev_priv 9599 drivers/gpu/drm/i915/intel_pm.c static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9611 drivers/gpu/drm/i915/intel_pm.c if (IS_GM45(dev_priv)) dev_priv 9622 drivers/gpu/drm/i915/intel_pm.c g4x_disable_trickle_feed(dev_priv); dev_priv 9625 drivers/gpu/drm/i915/intel_pm.c static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9627 drivers/gpu/drm/i915/intel_pm.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 9644 drivers/gpu/drm/i915/intel_pm.c static void i965g_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9659 drivers/gpu/drm/i915/intel_pm.c static void gen3_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9667 drivers/gpu/drm/i915/intel_pm.c if (IS_PINEVIEW(dev_priv)) dev_priv 9683 drivers/gpu/drm/i915/intel_pm.c static void i85x_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9695 drivers/gpu/drm/i915/intel_pm.c static void i830_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9702 drivers/gpu/drm/i915/intel_pm.c void intel_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9704 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating(dev_priv); dev_priv 9707 drivers/gpu/drm/i915/intel_pm.c void intel_suspend_hw(struct drm_i915_private *dev_priv) dev_priv 9709 drivers/gpu/drm/i915/intel_pm.c if (HAS_PCH_LPT(dev_priv)) dev_priv 9710 drivers/gpu/drm/i915/intel_pm.c lpt_suspend_hw(dev_priv); dev_priv 9713 drivers/gpu/drm/i915/intel_pm.c static void nop_init_clock_gating(struct drm_i915_private *dev_priv) dev_priv 9727 drivers/gpu/drm/i915/intel_pm.c void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) dev_priv 9729 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN(dev_priv, 12)) dev_priv 9730 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = nop_init_clock_gating; dev_priv 9731 drivers/gpu/drm/i915/intel_pm.c else if (IS_GEN(dev_priv, 11)) dev_priv 9732 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = icl_init_clock_gating; dev_priv 9733 drivers/gpu/drm/i915/intel_pm.c else if (IS_CANNONLAKE(dev_priv)) dev_priv 9734 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = cnl_init_clock_gating; dev_priv 9735 drivers/gpu/drm/i915/intel_pm.c else if (IS_COFFEELAKE(dev_priv)) dev_priv 9736 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = cfl_init_clock_gating; dev_priv 9737 drivers/gpu/drm/i915/intel_pm.c else if (IS_SKYLAKE(dev_priv)) dev_priv 9738 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = skl_init_clock_gating; dev_priv 9739 drivers/gpu/drm/i915/intel_pm.c else if (IS_KABYLAKE(dev_priv)) dev_priv 9740 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = kbl_init_clock_gating; dev_priv 9741 drivers/gpu/drm/i915/intel_pm.c else if (IS_BROXTON(dev_priv)) dev_priv 9742 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = bxt_init_clock_gating; dev_priv 9743 drivers/gpu/drm/i915/intel_pm.c else if (IS_GEMINILAKE(dev_priv)) dev_priv 9744 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = glk_init_clock_gating; dev_priv 9745 drivers/gpu/drm/i915/intel_pm.c else if (IS_BROADWELL(dev_priv)) dev_priv 9746 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = bdw_init_clock_gating; dev_priv 9747 drivers/gpu/drm/i915/intel_pm.c else if (IS_CHERRYVIEW(dev_priv)) dev_priv 9748 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = chv_init_clock_gating; dev_priv 9749 drivers/gpu/drm/i915/intel_pm.c else if (IS_HASWELL(dev_priv)) dev_priv 9750 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = hsw_init_clock_gating; dev_priv 9751 drivers/gpu/drm/i915/intel_pm.c else if (IS_IVYBRIDGE(dev_priv)) dev_priv 9752 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = ivb_init_clock_gating; dev_priv 9753 drivers/gpu/drm/i915/intel_pm.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 9754 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = vlv_init_clock_gating; dev_priv 9755 drivers/gpu/drm/i915/intel_pm.c else if (IS_GEN(dev_priv, 6)) dev_priv 9756 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = gen6_init_clock_gating; dev_priv 9757 drivers/gpu/drm/i915/intel_pm.c else if (IS_GEN(dev_priv, 5)) dev_priv 9758 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = ilk_init_clock_gating; dev_priv 9759 drivers/gpu/drm/i915/intel_pm.c else if (IS_G4X(dev_priv)) dev_priv 9760 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = g4x_init_clock_gating; dev_priv 9761 drivers/gpu/drm/i915/intel_pm.c else if (IS_I965GM(dev_priv)) dev_priv 9762 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = i965gm_init_clock_gating; dev_priv 9763 drivers/gpu/drm/i915/intel_pm.c else if (IS_I965G(dev_priv)) dev_priv 9764 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = i965g_init_clock_gating; dev_priv 9765 drivers/gpu/drm/i915/intel_pm.c else if (IS_GEN(dev_priv, 3)) dev_priv 9766 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = gen3_init_clock_gating; dev_priv 9767 drivers/gpu/drm/i915/intel_pm.c else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) dev_priv 9768 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = i85x_init_clock_gating; dev_priv 9769 drivers/gpu/drm/i915/intel_pm.c else if (IS_GEN(dev_priv, 2)) dev_priv 9770 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = i830_init_clock_gating; dev_priv 9772 drivers/gpu/drm/i915/intel_pm.c MISSING_CASE(INTEL_DEVID(dev_priv)); dev_priv 9773 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.init_clock_gating = nop_init_clock_gating; dev_priv 9778 drivers/gpu/drm/i915/intel_pm.c void intel_init_pm(struct drm_i915_private *dev_priv) dev_priv 9781 drivers/gpu/drm/i915/intel_pm.c if (IS_PINEVIEW(dev_priv)) dev_priv 9782 drivers/gpu/drm/i915/intel_pm.c i915_pineview_get_mem_freq(dev_priv); dev_priv 9783 drivers/gpu/drm/i915/intel_pm.c else if (IS_GEN(dev_priv, 5)) dev_priv 9784 drivers/gpu/drm/i915/intel_pm.c i915_ironlake_get_mem_freq(dev_priv); dev_priv 9787 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 9) { dev_priv 9788 drivers/gpu/drm/i915/intel_pm.c skl_setup_wm_latency(dev_priv); dev_priv 9789 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.initial_watermarks = skl_initial_wm; dev_priv 9790 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm; dev_priv 9791 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.compute_global_watermarks = skl_compute_wm; dev_priv 9792 drivers/gpu/drm/i915/intel_pm.c } else if (HAS_PCH_SPLIT(dev_priv)) { dev_priv 9793 drivers/gpu/drm/i915/intel_pm.c ilk_setup_wm_latency(dev_priv); dev_priv 9795 drivers/gpu/drm/i915/intel_pm.c if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] && dev_priv 9796 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || dev_priv 9797 drivers/gpu/drm/i915/intel_pm.c (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] && dev_priv 9798 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { dev_priv 9799 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; dev_priv 9800 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.compute_intermediate_wm = dev_priv 9802 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.initial_watermarks = dev_priv 9804 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.optimize_watermarks = dev_priv 9810 drivers/gpu/drm/i915/intel_pm.c } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 9811 drivers/gpu/drm/i915/intel_pm.c vlv_setup_wm_latency(dev_priv); dev_priv 9812 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm; dev_priv 9813 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm; dev_priv 9814 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.initial_watermarks = vlv_initial_watermarks; dev_priv 9815 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.optimize_watermarks = vlv_optimize_watermarks; dev_priv 9816 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo; dev_priv 9817 drivers/gpu/drm/i915/intel_pm.c } else if (IS_G4X(dev_priv)) { dev_priv 9818 drivers/gpu/drm/i915/intel_pm.c g4x_setup_wm_latency(dev_priv); dev_priv 9819 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm; dev_priv 9820 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm; dev_priv 9821 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.initial_watermarks = g4x_initial_watermarks; dev_priv 9822 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.optimize_watermarks = g4x_optimize_watermarks; dev_priv 9823 drivers/gpu/drm/i915/intel_pm.c } else if (IS_PINEVIEW(dev_priv)) { dev_priv 9824 drivers/gpu/drm/i915/intel_pm.c if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv), dev_priv 9825 drivers/gpu/drm/i915/intel_pm.c dev_priv->is_ddr3, dev_priv 9826 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq, dev_priv 9827 drivers/gpu/drm/i915/intel_pm.c dev_priv->mem_freq)) { dev_priv 9831 drivers/gpu/drm/i915/intel_pm.c (dev_priv->is_ddr3 == 1) ? "3" : "2", dev_priv 9832 drivers/gpu/drm/i915/intel_pm.c dev_priv->fsb_freq, dev_priv->mem_freq); dev_priv 9834 drivers/gpu/drm/i915/intel_pm.c intel_set_memory_cxsr(dev_priv, false); dev_priv 9835 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.update_wm = NULL; dev_priv 9837 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.update_wm = pineview_update_wm; dev_priv 9838 drivers/gpu/drm/i915/intel_pm.c } else if (IS_GEN(dev_priv, 4)) { dev_priv 9839 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.update_wm = i965_update_wm; dev_priv 9840 drivers/gpu/drm/i915/intel_pm.c } else if (IS_GEN(dev_priv, 3)) { dev_priv 9841 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.update_wm = i9xx_update_wm; dev_priv 9842 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.get_fifo_size = i9xx_get_fifo_size; dev_priv 9843 drivers/gpu/drm/i915/intel_pm.c } else if (IS_GEN(dev_priv, 2)) { dev_priv 9844 drivers/gpu/drm/i915/intel_pm.c if (INTEL_INFO(dev_priv)->num_pipes == 1) { dev_priv 9845 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.update_wm = i845_update_wm; dev_priv 9846 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.get_fifo_size = i845_get_fifo_size; dev_priv 9848 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.update_wm = i9xx_update_wm; dev_priv 9849 drivers/gpu/drm/i915/intel_pm.c dev_priv->display.get_fifo_size = i830_get_fifo_size; dev_priv 9856 drivers/gpu/drm/i915/intel_pm.c static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) dev_priv 9858 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 9867 drivers/gpu/drm/i915/intel_pm.c static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) dev_priv 9869 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 9874 drivers/gpu/drm/i915/intel_pm.c static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) dev_priv 9876 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 9885 drivers/gpu/drm/i915/intel_pm.c static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) dev_priv 9887 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; dev_priv 9893 drivers/gpu/drm/i915/intel_pm.c int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) dev_priv 9895 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 9898 drivers/gpu/drm/i915/intel_pm.c else if (IS_CHERRYVIEW(dev_priv)) dev_priv 9899 drivers/gpu/drm/i915/intel_pm.c return chv_gpu_freq(dev_priv, val); dev_priv 9900 drivers/gpu/drm/i915/intel_pm.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 9901 drivers/gpu/drm/i915/intel_pm.c return byt_gpu_freq(dev_priv, val); dev_priv 9906 drivers/gpu/drm/i915/intel_pm.c int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) dev_priv 9908 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 9911 drivers/gpu/drm/i915/intel_pm.c else if (IS_CHERRYVIEW(dev_priv)) dev_priv 9912 drivers/gpu/drm/i915/intel_pm.c return chv_freq_opcode(dev_priv, val); dev_priv 9913 drivers/gpu/drm/i915/intel_pm.c else if (IS_VALLEYVIEW(dev_priv)) dev_priv 9914 drivers/gpu/drm/i915/intel_pm.c return byt_freq_opcode(dev_priv, val); dev_priv 9919 drivers/gpu/drm/i915/intel_pm.c void intel_pm_setup(struct drm_i915_private *dev_priv) dev_priv 9921 drivers/gpu/drm/i915/intel_pm.c mutex_init(&dev_priv->gt_pm.rps.lock); dev_priv 9922 drivers/gpu/drm/i915/intel_pm.c mutex_init(&dev_priv->gt_pm.rps.power.mutex); dev_priv 9924 drivers/gpu/drm/i915/intel_pm.c atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0); dev_priv 9926 drivers/gpu/drm/i915/intel_pm.c dev_priv->runtime_pm.suspended = false; dev_priv 9927 drivers/gpu/drm/i915/intel_pm.c atomic_set(&dev_priv->runtime_pm.wakeref_count, 0); dev_priv 9930 drivers/gpu/drm/i915/intel_pm.c static u64 vlv_residency_raw(struct drm_i915_private *dev_priv, dev_priv 9940 drivers/gpu/drm/i915/intel_pm.c lockdep_assert_held(&dev_priv->uncore.lock); dev_priv 9976 drivers/gpu/drm/i915/intel_pm.c u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, dev_priv 9979 drivers/gpu/drm/i915/intel_pm.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 9986 drivers/gpu/drm/i915/intel_pm.c if (!HAS_RC6(dev_priv)) dev_priv 9998 drivers/gpu/drm/i915/intel_pm.c if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency))) dev_priv 10007 drivers/gpu/drm/i915/intel_pm.c if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv 10009 drivers/gpu/drm/i915/intel_pm.c div = dev_priv->czclk_freq; dev_priv 10011 drivers/gpu/drm/i915/intel_pm.c time_hw = vlv_residency_raw(dev_priv, reg); dev_priv 10014 drivers/gpu/drm/i915/intel_pm.c if (IS_GEN9_LP(dev_priv)) { dev_priv 10032 drivers/gpu/drm/i915/intel_pm.c prev_hw = dev_priv->gt_pm.rc6.prev_hw_residency[i]; dev_priv 10033 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rc6.prev_hw_residency[i] = time_hw; dev_priv 10042 drivers/gpu/drm/i915/intel_pm.c time_hw += dev_priv->gt_pm.rc6.cur_residency[i]; dev_priv 10043 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rc6.cur_residency[i] = time_hw; dev_priv 10051 drivers/gpu/drm/i915/intel_pm.c u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, dev_priv 10054 drivers/gpu/drm/i915/intel_pm.c return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000); dev_priv 10057 drivers/gpu/drm/i915/intel_pm.c u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat) dev_priv 10061 drivers/gpu/drm/i915/intel_pm.c if (INTEL_GEN(dev_priv) >= 9) dev_priv 10063 drivers/gpu/drm/i915/intel_pm.c else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dev_priv 25 drivers/gpu/drm/i915/intel_pm.h void intel_init_clock_gating(struct drm_i915_private *dev_priv); dev_priv 26 drivers/gpu/drm/i915/intel_pm.h void intel_suspend_hw(struct drm_i915_private *dev_priv); dev_priv 27 drivers/gpu/drm/i915/intel_pm.h int ilk_wm_max_level(const struct drm_i915_private *dev_priv); dev_priv 29 drivers/gpu/drm/i915/intel_pm.h void intel_init_pm(struct drm_i915_private *dev_priv); dev_priv 30 drivers/gpu/drm/i915/intel_pm.h void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); dev_priv 31 drivers/gpu/drm/i915/intel_pm.h void intel_pm_setup(struct drm_i915_private *dev_priv); dev_priv 32 drivers/gpu/drm/i915/intel_pm.h void intel_gpu_ips_init(struct drm_i915_private *dev_priv); dev_priv 34 drivers/gpu/drm/i915/intel_pm.h void intel_init_gt_powersave(struct drm_i915_private *dev_priv); dev_priv 35 drivers/gpu/drm/i915/intel_pm.h void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv); dev_priv 36 drivers/gpu/drm/i915/intel_pm.h void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv); dev_priv 37 drivers/gpu/drm/i915/intel_pm.h void intel_enable_gt_powersave(struct drm_i915_private *dev_priv); dev_priv 38 drivers/gpu/drm/i915/intel_pm.h void intel_disable_gt_powersave(struct drm_i915_private *dev_priv); dev_priv 42 drivers/gpu/drm/i915/intel_pm.h void gen6_rps_busy(struct drm_i915_private *dev_priv); dev_priv 43 drivers/gpu/drm/i915/intel_pm.h void gen6_rps_idle(struct drm_i915_private *dev_priv); dev_priv 45 drivers/gpu/drm/i915/intel_pm.h void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv); dev_priv 46 drivers/gpu/drm/i915/intel_pm.h void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv); dev_priv 47 drivers/gpu/drm/i915/intel_pm.h void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv); dev_priv 48 drivers/gpu/drm/i915/intel_pm.h void skl_wm_get_hw_state(struct drm_i915_private *dev_priv); dev_priv 52 drivers/gpu/drm/i915/intel_pm.h void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, dev_priv 56 drivers/gpu/drm/i915/intel_pm.h void g4x_wm_sanitize(struct drm_i915_private *dev_priv); dev_priv 57 drivers/gpu/drm/i915/intel_pm.h void vlv_wm_sanitize(struct drm_i915_private *dev_priv); dev_priv 59 drivers/gpu/drm/i915/intel_pm.h int intel_enable_sagv(struct drm_i915_private *dev_priv); dev_priv 60 drivers/gpu/drm/i915/intel_pm.h int intel_disable_sagv(struct drm_i915_private *dev_priv); dev_priv 73 drivers/gpu/drm/i915/intel_pm.h void intel_init_ipc(struct drm_i915_private *dev_priv); dev_priv 74 drivers/gpu/drm/i915/intel_pm.h void intel_enable_ipc(struct drm_i915_private *dev_priv); dev_priv 76 drivers/gpu/drm/i915/intel_pm.h int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); dev_priv 77 drivers/gpu/drm/i915/intel_pm.h int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); dev_priv 78 drivers/gpu/drm/i915/intel_pm.h u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg); dev_priv 79 drivers/gpu/drm/i915/intel_pm.h u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg); dev_priv 81 drivers/gpu/drm/i915/intel_pm.h u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1); dev_priv 83 drivers/gpu/drm/i915/intel_pm.h unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); dev_priv 84 drivers/gpu/drm/i915/intel_pm.h unsigned long i915_mch_val(struct drm_i915_private *dev_priv); dev_priv 85 drivers/gpu/drm/i915/intel_pm.h unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); dev_priv 86 drivers/gpu/drm/i915/intel_pm.h void i915_update_gfx_val(struct drm_i915_private *dev_priv); dev_priv 88 drivers/gpu/drm/i915/intel_pm.h bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); dev_priv 89 drivers/gpu/drm/i915/intel_pm.h int intel_set_rps(struct drm_i915_private *dev_priv, u8 val); dev_priv 91 drivers/gpu/drm/i915/intel_pm.h bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); dev_priv 881 drivers/gpu/drm/i915/intel_uncore.c #define HAS_FWTABLE(dev_priv) \ dev_priv 882 drivers/gpu/drm/i915/intel_uncore.c (INTEL_GEN(dev_priv) >= 9 || \ dev_priv 883 drivers/gpu/drm/i915/intel_uncore.c IS_CHERRYVIEW(dev_priv) || \ dev_priv 884 drivers/gpu/drm/i915/intel_uncore.c IS_VALLEYVIEW(dev_priv)) dev_priv 66 drivers/gpu/drm/i915/oa/i915_oa_bdw.c i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv) dev_priv 68 drivers/gpu/drm/i915/oa/i915_oa_bdw.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 70 drivers/gpu/drm/i915/oa/i915_oa_bdw.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 71 drivers/gpu/drm/i915/oa/i915_oa_bdw.c dev_priv->perf.test_config.id = 1; dev_priv 73 drivers/gpu/drm/i915/oa/i915_oa_bdw.c dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv 74 drivers/gpu/drm/i915/oa/i915_oa_bdw.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv 76 drivers/gpu/drm/i915/oa/i915_oa_bdw.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv 77 drivers/gpu/drm/i915/oa/i915_oa_bdw.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv 79 drivers/gpu/drm/i915/oa/i915_oa_bdw.c dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv 80 drivers/gpu/drm/i915/oa/i915_oa_bdw.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv 82 drivers/gpu/drm/i915/oa/i915_oa_bdw.c dev_priv->perf.test_config.sysfs_metric.name = "d6de6f55-e526-4f79-a6a6-d7315c09044e"; dev_priv 83 drivers/gpu/drm/i915/oa/i915_oa_bdw.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 85 drivers/gpu/drm/i915/oa/i915_oa_bdw.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 87 drivers/gpu/drm/i915/oa/i915_oa_bdw.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 88 drivers/gpu/drm/i915/oa/i915_oa_bdw.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 89 drivers/gpu/drm/i915/oa/i915_oa_bdw.c dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_bdw.h void i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv); dev_priv 64 drivers/gpu/drm/i915/oa/i915_oa_bxt.c i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv) dev_priv 66 drivers/gpu/drm/i915/oa/i915_oa_bxt.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 68 drivers/gpu/drm/i915/oa/i915_oa_bxt.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 69 drivers/gpu/drm/i915/oa/i915_oa_bxt.c dev_priv->perf.test_config.id = 1; dev_priv 71 drivers/gpu/drm/i915/oa/i915_oa_bxt.c dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv 72 drivers/gpu/drm/i915/oa/i915_oa_bxt.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv 74 drivers/gpu/drm/i915/oa/i915_oa_bxt.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv 75 drivers/gpu/drm/i915/oa/i915_oa_bxt.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv 77 drivers/gpu/drm/i915/oa/i915_oa_bxt.c dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv 78 drivers/gpu/drm/i915/oa/i915_oa_bxt.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv 80 drivers/gpu/drm/i915/oa/i915_oa_bxt.c dev_priv->perf.test_config.sysfs_metric.name = "5ee72f5c-092f-421e-8b70-225f7c3e9612"; dev_priv 81 drivers/gpu/drm/i915/oa/i915_oa_bxt.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 83 drivers/gpu/drm/i915/oa/i915_oa_bxt.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 85 drivers/gpu/drm/i915/oa/i915_oa_bxt.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 86 drivers/gpu/drm/i915/oa/i915_oa_bxt.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 87 drivers/gpu/drm/i915/oa/i915_oa_bxt.c dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_bxt.h void i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv); dev_priv 65 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c i915_perf_load_test_config_cflgt2(struct drm_i915_private *dev_priv) dev_priv 67 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 69 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 70 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c dev_priv->perf.test_config.id = 1; dev_priv 72 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv 73 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv 75 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv 76 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv 78 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv 79 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv 81 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c dev_priv->perf.test_config.sysfs_metric.name = "74fb4902-d3d3-4237-9e90-cbdc68d0a446"; dev_priv 82 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 84 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 86 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 87 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 88 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h void i915_perf_load_test_config_cflgt2(struct drm_i915_private *dev_priv); dev_priv 65 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c i915_perf_load_test_config_cflgt3(struct drm_i915_private *dev_priv) dev_priv 67 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 69 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 70 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c dev_priv->perf.test_config.id = 1; dev_priv 72 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv 73 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv 75 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv 76 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv 78 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv 79 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv 81 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c dev_priv->perf.test_config.sysfs_metric.name = "577e8e2c-3fa0-4875-8743-3538d585e3b0"; dev_priv 82 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 84 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 86 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 87 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 88 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h void i915_perf_load_test_config_cflgt3(struct drm_i915_private *dev_priv); dev_priv 65 drivers/gpu/drm/i915/oa/i915_oa_chv.c i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv) dev_priv 67 drivers/gpu/drm/i915/oa/i915_oa_chv.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 69 drivers/gpu/drm/i915/oa/i915_oa_chv.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 70 drivers/gpu/drm/i915/oa/i915_oa_chv.c dev_priv->perf.test_config.id = 1; dev_priv 72 drivers/gpu/drm/i915/oa/i915_oa_chv.c dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv 73 drivers/gpu/drm/i915/oa/i915_oa_chv.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv 75 drivers/gpu/drm/i915/oa/i915_oa_chv.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv 76 drivers/gpu/drm/i915/oa/i915_oa_chv.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv 78 drivers/gpu/drm/i915/oa/i915_oa_chv.c dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv 79 drivers/gpu/drm/i915/oa/i915_oa_chv.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv 81 drivers/gpu/drm/i915/oa/i915_oa_chv.c dev_priv->perf.test_config.sysfs_metric.name = "4a534b07-cba3-414d-8d60-874830e883aa"; dev_priv 82 drivers/gpu/drm/i915/oa/i915_oa_chv.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 84 drivers/gpu/drm/i915/oa/i915_oa_chv.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 86 drivers/gpu/drm/i915/oa/i915_oa_chv.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 87 drivers/gpu/drm/i915/oa/i915_oa_chv.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 88 drivers/gpu/drm/i915/oa/i915_oa_chv.c dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_chv.h void i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv); dev_priv 77 drivers/gpu/drm/i915/oa/i915_oa_cnl.c i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv) dev_priv 79 drivers/gpu/drm/i915/oa/i915_oa_cnl.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 81 drivers/gpu/drm/i915/oa/i915_oa_cnl.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 82 drivers/gpu/drm/i915/oa/i915_oa_cnl.c dev_priv->perf.test_config.id = 1; dev_priv 84 drivers/gpu/drm/i915/oa/i915_oa_cnl.c dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv 85 drivers/gpu/drm/i915/oa/i915_oa_cnl.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv 87 drivers/gpu/drm/i915/oa/i915_oa_cnl.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv 88 drivers/gpu/drm/i915/oa/i915_oa_cnl.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv 90 drivers/gpu/drm/i915/oa/i915_oa_cnl.c dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv 91 drivers/gpu/drm/i915/oa/i915_oa_cnl.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv 93 drivers/gpu/drm/i915/oa/i915_oa_cnl.c dev_priv->perf.test_config.sysfs_metric.name = "db41edd4-d8e7-4730-ad11-b9a2d6833503"; dev_priv 94 drivers/gpu/drm/i915/oa/i915_oa_cnl.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 96 drivers/gpu/drm/i915/oa/i915_oa_cnl.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 98 drivers/gpu/drm/i915/oa/i915_oa_cnl.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 99 drivers/gpu/drm/i915/oa/i915_oa_cnl.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 100 drivers/gpu/drm/i915/oa/i915_oa_cnl.c dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_cnl.h void i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv); dev_priv 64 drivers/gpu/drm/i915/oa/i915_oa_glk.c i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv) dev_priv 66 drivers/gpu/drm/i915/oa/i915_oa_glk.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 68 drivers/gpu/drm/i915/oa/i915_oa_glk.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 69 drivers/gpu/drm/i915/oa/i915_oa_glk.c dev_priv->perf.test_config.id = 1; dev_priv 71 drivers/gpu/drm/i915/oa/i915_oa_glk.c dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv 72 drivers/gpu/drm/i915/oa/i915_oa_glk.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv 74 drivers/gpu/drm/i915/oa/i915_oa_glk.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv 75 drivers/gpu/drm/i915/oa/i915_oa_glk.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv 77 drivers/gpu/drm/i915/oa/i915_oa_glk.c dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv 78 drivers/gpu/drm/i915/oa/i915_oa_glk.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv 80 drivers/gpu/drm/i915/oa/i915_oa_glk.c dev_priv->perf.test_config.sysfs_metric.name = "dd3fd789-e783-4204-8cd0-b671bbccb0cf"; dev_priv 81 drivers/gpu/drm/i915/oa/i915_oa_glk.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 83 drivers/gpu/drm/i915/oa/i915_oa_glk.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 85 drivers/gpu/drm/i915/oa/i915_oa_glk.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 86 drivers/gpu/drm/i915/oa/i915_oa_glk.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 87 drivers/gpu/drm/i915/oa/i915_oa_glk.c dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_glk.h void i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv); dev_priv 94 drivers/gpu/drm/i915/oa/i915_oa_hsw.c i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv) dev_priv 96 drivers/gpu/drm/i915/oa/i915_oa_hsw.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 98 drivers/gpu/drm/i915/oa/i915_oa_hsw.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 99 drivers/gpu/drm/i915/oa/i915_oa_hsw.c dev_priv->perf.test_config.id = 1; dev_priv 101 drivers/gpu/drm/i915/oa/i915_oa_hsw.c dev_priv->perf.test_config.mux_regs = mux_config_render_basic; dev_priv 102 drivers/gpu/drm/i915/oa/i915_oa_hsw.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_render_basic); dev_priv 104 drivers/gpu/drm/i915/oa/i915_oa_hsw.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_render_basic; dev_priv 105 drivers/gpu/drm/i915/oa/i915_oa_hsw.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_render_basic); dev_priv 107 drivers/gpu/drm/i915/oa/i915_oa_hsw.c dev_priv->perf.test_config.flex_regs = flex_eu_config_render_basic; dev_priv 108 drivers/gpu/drm/i915/oa/i915_oa_hsw.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_render_basic); dev_priv 110 drivers/gpu/drm/i915/oa/i915_oa_hsw.c dev_priv->perf.test_config.sysfs_metric.name = "403d8832-1a27-4aa6-a64e-f5389ce7b212"; dev_priv 111 drivers/gpu/drm/i915/oa/i915_oa_hsw.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 113 drivers/gpu/drm/i915/oa/i915_oa_hsw.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 115 drivers/gpu/drm/i915/oa/i915_oa_hsw.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 116 drivers/gpu/drm/i915/oa/i915_oa_hsw.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 117 drivers/gpu/drm/i915/oa/i915_oa_hsw.c dev_priv->perf.test_config.sysfs_metric_id.show = show_render_basic_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_hsw.h void i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv); dev_priv 74 drivers/gpu/drm/i915/oa/i915_oa_icl.c i915_perf_load_test_config_icl(struct drm_i915_private *dev_priv) dev_priv 76 drivers/gpu/drm/i915/oa/i915_oa_icl.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 78 drivers/gpu/drm/i915/oa/i915_oa_icl.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 79 drivers/gpu/drm/i915/oa/i915_oa_icl.c dev_priv->perf.test_config.id = 1; dev_priv 81 drivers/gpu/drm/i915/oa/i915_oa_icl.c dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv 82 drivers/gpu/drm/i915/oa/i915_oa_icl.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv 84 drivers/gpu/drm/i915/oa/i915_oa_icl.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv 85 drivers/gpu/drm/i915/oa/i915_oa_icl.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv 87 drivers/gpu/drm/i915/oa/i915_oa_icl.c dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv 88 drivers/gpu/drm/i915/oa/i915_oa_icl.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv 90 drivers/gpu/drm/i915/oa/i915_oa_icl.c dev_priv->perf.test_config.sysfs_metric.name = "a291665e-244b-4b76-9b9a-01de9d3c8068"; dev_priv 91 drivers/gpu/drm/i915/oa/i915_oa_icl.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 93 drivers/gpu/drm/i915/oa/i915_oa_icl.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 95 drivers/gpu/drm/i915/oa/i915_oa_icl.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 96 drivers/gpu/drm/i915/oa/i915_oa_icl.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 97 drivers/gpu/drm/i915/oa/i915_oa_icl.c dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_icl.h void i915_perf_load_test_config_icl(struct drm_i915_private *dev_priv); dev_priv 65 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv) dev_priv 67 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 69 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 70 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c dev_priv->perf.test_config.id = 1; dev_priv 72 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv 73 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv 75 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv 76 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv 78 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv 79 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv 81 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c dev_priv->perf.test_config.sysfs_metric.name = "baa3c7e4-52b6-4b85-801e-465a94b746dd"; dev_priv 82 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 84 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 86 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 87 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 88 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h void i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv); dev_priv 65 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv) dev_priv 67 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 69 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 70 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c dev_priv->perf.test_config.id = 1; dev_priv 72 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv 73 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv 75 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv 76 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv 78 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv 79 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv 81 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c dev_priv->perf.test_config.sysfs_metric.name = "f1792f32-6db2-4b50-b4b2-557128f1688d"; dev_priv 82 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 84 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 86 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 87 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 88 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.h void i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv); dev_priv 64 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv) dev_priv 66 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 68 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 69 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c dev_priv->perf.test_config.id = 1; dev_priv 71 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv 72 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv 74 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv 75 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv 77 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv 78 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv 80 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c dev_priv->perf.test_config.sysfs_metric.name = "1651949f-0ac0-4cb1-a06f-dafd74a407d1"; dev_priv 81 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 83 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 85 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 86 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 87 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.h void i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv); dev_priv 65 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv) dev_priv 67 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 69 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 70 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c dev_priv->perf.test_config.id = 1; dev_priv 72 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv 73 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv 75 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv 76 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv 78 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv 79 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv 81 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c dev_priv->perf.test_config.sysfs_metric.name = "2b985803-d3c9-4629-8a4f-634bfecba0e8"; dev_priv 82 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 84 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 86 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 87 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 88 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.h void i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv); dev_priv 65 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv) dev_priv 67 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c strlcpy(dev_priv->perf.test_config.uuid, dev_priv 69 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c sizeof(dev_priv->perf.test_config.uuid)); dev_priv 70 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c dev_priv->perf.test_config.id = 1; dev_priv 72 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c dev_priv->perf.test_config.mux_regs = mux_config_test_oa; dev_priv 73 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); dev_priv 75 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa; dev_priv 76 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); dev_priv 78 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa; dev_priv 79 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); dev_priv 81 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c dev_priv->perf.test_config.sysfs_metric.name = "882fa433-1f4a-4a67-a962-c741888fe5f5"; dev_priv 82 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs; dev_priv 84 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr; dev_priv 86 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id"; dev_priv 87 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444; dev_priv 88 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id; dev_priv 14 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.h void i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv); dev_priv 150 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c struct drm_i915_private *dev_priv = arg; dev_priv 157 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c if (!HAS_PPGTT(dev_priv)) dev_priv 160 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c ppgtt = __ppgtt_create(dev_priv); dev_priv 993 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c static int exercise_ppgtt(struct drm_i915_private *dev_priv, dev_priv 1004 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c if (!HAS_FULL_PPGTT(dev_priv)) dev_priv 1007 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c file = mock_file(dev_priv); dev_priv 1011 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c mutex_lock(&dev_priv->drm.struct_mutex); dev_priv 1012 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c ppgtt = i915_ppgtt_create(dev_priv); dev_priv 1020 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c err = func(dev_priv, &ppgtt->vm, 0, ppgtt->vm.total, end_time); dev_priv 1024 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv 1026 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c mock_file_free(dev_priv, file); dev_priv 257 drivers/gpu/drm/i915/selftests/intel_uncore.c struct drm_i915_private *dev_priv = arg; dev_priv 258 drivers/gpu/drm/i915/selftests/intel_uncore.c struct intel_uncore *uncore = &dev_priv->uncore; dev_priv 263 drivers/gpu/drm/i915/selftests/intel_uncore.c if (!HAS_FPGA_DBG_UNCLAIMED(dev_priv) && dev_priv 264 drivers/gpu/drm/i915/selftests/intel_uncore.c !IS_VALLEYVIEW(dev_priv) && dev_priv 265 drivers/gpu/drm/i915/selftests/intel_uncore.c !IS_CHERRYVIEW(dev_priv)) dev_priv 53 drivers/gpu/drm/mga/mga_dma.c int mga_do_wait_for_idle(drm_mga_private_t *dev_priv) dev_priv 59 drivers/gpu/drm/mga/mga_dma.c for (i = 0; i < dev_priv->usec_timeout; i++) { dev_priv 75 drivers/gpu/drm/mga/mga_dma.c static int mga_do_dma_reset(drm_mga_private_t *dev_priv) dev_priv 77 drivers/gpu/drm/mga/mga_dma.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 78 drivers/gpu/drm/mga/mga_dma.c drm_mga_primary_buffer_t *primary = &dev_priv->prim; dev_priv 103 drivers/gpu/drm/mga/mga_dma.c void mga_do_dma_flush(drm_mga_private_t *dev_priv) dev_priv 105 drivers/gpu/drm/mga/mga_dma.c drm_mga_primary_buffer_t *primary = &dev_priv->prim; dev_priv 113 drivers/gpu/drm/mga/mga_dma.c for (i = 0; i < dev_priv->usec_timeout; i++) { dev_priv 125 drivers/gpu/drm/mga/mga_dma.c tail = primary->tail + dev_priv->primary->offset; dev_priv 148 drivers/gpu/drm/mga/mga_dma.c DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset)); dev_priv 149 drivers/gpu/drm/mga/mga_dma.c DRM_DEBUG(" tail = 0x%06lx\n", (unsigned long)(tail - dev_priv->primary->offset)); dev_priv 153 drivers/gpu/drm/mga/mga_dma.c MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); dev_priv 158 drivers/gpu/drm/mga/mga_dma.c void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv) dev_priv 160 drivers/gpu/drm/mga/mga_dma.c drm_mga_primary_buffer_t *primary = &dev_priv->prim; dev_priv 173 drivers/gpu/drm/mga/mga_dma.c tail = primary->tail + dev_priv->primary->offset; dev_priv 181 drivers/gpu/drm/mga/mga_dma.c if (head == dev_priv->primary->offset) dev_priv 184 drivers/gpu/drm/mga/mga_dma.c primary->space = head - dev_priv->primary->offset; dev_priv 186 drivers/gpu/drm/mga/mga_dma.c DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset)); dev_priv 192 drivers/gpu/drm/mga/mga_dma.c MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); dev_priv 198 drivers/gpu/drm/mga/mga_dma.c void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv) dev_priv 200 drivers/gpu/drm/mga/mga_dma.c drm_mga_primary_buffer_t *primary = &dev_priv->prim; dev_priv 201 drivers/gpu/drm/mga/mga_dma.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 202 drivers/gpu/drm/mga/mga_dma.c u32 head = dev_priv->primary->offset; dev_priv 225 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 230 drivers/gpu/drm/mga/mga_dma.c dev_priv->sarea_priv->last_dispatch, dev_priv 232 drivers/gpu/drm/mga/mga_dma.c dev_priv->primary->offset)); dev_priv 235 drivers/gpu/drm/mga/mga_dma.c for (entry = dev_priv->head->next; entry; entry = entry->next) { dev_priv 238 drivers/gpu/drm/mga/mga_dma.c (unsigned long)(entry->age.head - dev_priv->primary->offset)); dev_priv 244 drivers/gpu/drm/mga/mga_dma.c static int mga_freelist_init(struct drm_device *dev, drm_mga_private_t *dev_priv) dev_priv 253 drivers/gpu/drm/mga/mga_dma.c dev_priv->head = kzalloc(sizeof(drm_mga_freelist_t), GFP_KERNEL); dev_priv 254 drivers/gpu/drm/mga/mga_dma.c if (dev_priv->head == NULL) dev_priv 257 drivers/gpu/drm/mga/mga_dma.c SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0); dev_priv 267 drivers/gpu/drm/mga/mga_dma.c entry->next = dev_priv->head->next; dev_priv 268 drivers/gpu/drm/mga/mga_dma.c entry->prev = dev_priv->head; dev_priv 272 drivers/gpu/drm/mga/mga_dma.c if (dev_priv->head->next != NULL) dev_priv 273 drivers/gpu/drm/mga/mga_dma.c dev_priv->head->next->prev = entry; dev_priv 275 drivers/gpu/drm/mga/mga_dma.c dev_priv->tail = entry; dev_priv 281 drivers/gpu/drm/mga/mga_dma.c dev_priv->head->next = entry; dev_priv 289 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 294 drivers/gpu/drm/mga/mga_dma.c entry = dev_priv->head; dev_priv 301 drivers/gpu/drm/mga/mga_dma.c dev_priv->head = dev_priv->tail = NULL; dev_priv 324 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 327 drivers/gpu/drm/mga/mga_dma.c drm_mga_freelist_t *tail = dev_priv->tail; dev_priv 332 drivers/gpu/drm/mga/mga_dma.c wrap = dev_priv->sarea_priv->last_wrap; dev_priv 336 drivers/gpu/drm/mga/mga_dma.c (unsigned long)(tail->age.head - dev_priv->primary->offset) : 0, dev_priv 339 drivers/gpu/drm/mga/mga_dma.c (unsigned long)(head - dev_priv->primary->offset), wrap); dev_priv 342 drivers/gpu/drm/mga/mga_dma.c prev = dev_priv->tail->prev; dev_priv 343 drivers/gpu/drm/mga/mga_dma.c next = dev_priv->tail; dev_priv 346 drivers/gpu/drm/mga/mga_dma.c dev_priv->tail = prev; dev_priv 357 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 363 drivers/gpu/drm/mga/mga_dma.c dev_priv->primary->offset), dev_priv 367 drivers/gpu/drm/mga/mga_dma.c head = dev_priv->head; dev_priv 371 drivers/gpu/drm/mga/mga_dma.c prev = dev_priv->tail; dev_priv 392 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *dev_priv; dev_priv 413 drivers/gpu/drm/mga/mga_dma.c dev_priv = kzalloc(sizeof(drm_mga_private_t), GFP_KERNEL); dev_priv 414 drivers/gpu/drm/mga/mga_dma.c if (!dev_priv) dev_priv 417 drivers/gpu/drm/mga/mga_dma.c dev->dev_private = (void *)dev_priv; dev_priv 419 drivers/gpu/drm/mga/mga_dma.c dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT; dev_priv 420 drivers/gpu/drm/mga/mga_dma.c dev_priv->chipset = flags; dev_priv 424 drivers/gpu/drm/mga/mga_dma.c dev_priv->mmio_base = pci_resource_start(dev->pdev, 1); dev_priv 425 drivers/gpu/drm/mga/mga_dma.c dev_priv->mmio_size = pci_resource_len(dev->pdev, 1); dev_priv 456 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *const dev_priv = dev_priv 494 drivers/gpu/drm/mga/mga_dma.c if (dev_priv->chipset == MGA_CARD_TYPE_G200) { dev_priv 506 drivers/gpu/drm/mga/mga_dma.c dev_priv->agp_size = 0; dev_priv 512 drivers/gpu/drm/mga/mga_dma.c dev_priv->agp_size = agp_size; dev_priv 513 drivers/gpu/drm/mga/mga_dma.c dev_priv->agp_handle = agp_req.handle; dev_priv 531 drivers/gpu/drm/mga/mga_dma.c _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp); dev_priv 539 drivers/gpu/drm/mga/mga_dma.c _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary); dev_priv 581 drivers/gpu/drm/mga/mga_dma.c _DRM_AGP, 0, &dev_priv->agp_textures); dev_priv 587 drivers/gpu/drm/mga/mga_dma.c drm_legacy_ioremap(dev_priv->warp, dev); dev_priv 588 drivers/gpu/drm/mga/mga_dma.c drm_legacy_ioremap(dev_priv->primary, dev); dev_priv 591 drivers/gpu/drm/mga/mga_dma.c if (!dev_priv->warp->handle || dev_priv 592 drivers/gpu/drm/mga/mga_dma.c !dev_priv->primary->handle || !dev->agp_buffer_map->handle) { dev_priv 594 drivers/gpu/drm/mga/mga_dma.c dev_priv->warp->handle, dev_priv->primary->handle, dev_priv 599 drivers/gpu/drm/mga/mga_dma.c dev_priv->dma_access = MGA_PAGPXFER; dev_priv 600 drivers/gpu/drm/mga/mga_dma.c dev_priv->wagp_enable = MGA_WAGP_ENABLE; dev_priv 630 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *const dev_priv = dev_priv 651 drivers/gpu/drm/mga/mga_dma.c _DRM_READ_ONLY, &dev_priv->warp); dev_priv 667 drivers/gpu/drm/mga/mga_dma.c _DRM_READ_ONLY, &dev_priv->primary); dev_priv 677 drivers/gpu/drm/mga/mga_dma.c if (dev_priv->primary->size != dma_bs->primary_size) { dev_priv 680 drivers/gpu/drm/mga/mga_dma.c (unsigned)dev_priv->primary->size); dev_priv 681 drivers/gpu/drm/mga/mga_dma.c dma_bs->primary_size = dev_priv->primary->size; dev_priv 707 drivers/gpu/drm/mga/mga_dma.c dev_priv->dma_access = 0; dev_priv 708 drivers/gpu/drm/mga/mga_dma.c dev_priv->wagp_enable = 0; dev_priv 721 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *const dev_priv = dev_priv 724 drivers/gpu/drm/mga/mga_dma.c dev_priv->used_new_dma_init = 1; dev_priv 729 drivers/gpu/drm/mga/mga_dma.c err = drm_legacy_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size, dev_priv 731 drivers/gpu/drm/mga/mga_dma.c &dev_priv->mmio); dev_priv 739 drivers/gpu/drm/mga/mga_dma.c &dev_priv->status); dev_priv 780 drivers/gpu/drm/mga/mga_dma.c const drm_mga_private_t *const dev_priv = dev_priv 789 drivers/gpu/drm/mga/mga_dma.c if (dev_priv->agp_textures != NULL) { dev_priv 790 drivers/gpu/drm/mga/mga_dma.c bootstrap->texture_handle = dev_priv->agp_textures->offset; dev_priv 791 drivers/gpu/drm/mga/mga_dma.c bootstrap->texture_size = dev_priv->agp_textures->size; dev_priv 804 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *dev_priv; dev_priv 808 drivers/gpu/drm/mga/mga_dma.c dev_priv = dev->dev_private; dev_priv 811 drivers/gpu/drm/mga/mga_dma.c dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK; dev_priv 813 drivers/gpu/drm/mga/mga_dma.c dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; dev_priv 814 drivers/gpu/drm/mga/mga_dma.c dev_priv->maccess = init->maccess; dev_priv 816 drivers/gpu/drm/mga/mga_dma.c dev_priv->fb_cpp = init->fb_cpp; dev_priv 817 drivers/gpu/drm/mga/mga_dma.c dev_priv->front_offset = init->front_offset; dev_priv 818 drivers/gpu/drm/mga/mga_dma.c dev_priv->front_pitch = init->front_pitch; dev_priv 819 drivers/gpu/drm/mga/mga_dma.c dev_priv->back_offset = init->back_offset; dev_priv 820 drivers/gpu/drm/mga/mga_dma.c dev_priv->back_pitch = init->back_pitch; dev_priv 822 drivers/gpu/drm/mga/mga_dma.c dev_priv->depth_cpp = init->depth_cpp; dev_priv 823 drivers/gpu/drm/mga/mga_dma.c dev_priv->depth_offset = init->depth_offset; dev_priv 824 drivers/gpu/drm/mga/mga_dma.c dev_priv->depth_pitch = init->depth_pitch; dev_priv 828 drivers/gpu/drm/mga/mga_dma.c dev_priv->texture_offset = init->texture_offset[0]; dev_priv 829 drivers/gpu/drm/mga/mga_dma.c dev_priv->texture_size = init->texture_size[0]; dev_priv 831 drivers/gpu/drm/mga/mga_dma.c dev_priv->sarea = drm_legacy_getsarea(dev); dev_priv 832 drivers/gpu/drm/mga/mga_dma.c if (!dev_priv->sarea) { dev_priv 837 drivers/gpu/drm/mga/mga_dma.c if (!dev_priv->used_new_dma_init) { dev_priv 839 drivers/gpu/drm/mga/mga_dma.c dev_priv->dma_access = MGA_PAGPXFER; dev_priv 840 drivers/gpu/drm/mga/mga_dma.c dev_priv->wagp_enable = MGA_WAGP_ENABLE; dev_priv 842 drivers/gpu/drm/mga/mga_dma.c dev_priv->status = drm_legacy_findmap(dev, init->status_offset); dev_priv 843 drivers/gpu/drm/mga/mga_dma.c if (!dev_priv->status) { dev_priv 847 drivers/gpu/drm/mga/mga_dma.c dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset); dev_priv 848 drivers/gpu/drm/mga/mga_dma.c if (!dev_priv->mmio) { dev_priv 852 drivers/gpu/drm/mga/mga_dma.c dev_priv->warp = drm_legacy_findmap(dev, init->warp_offset); dev_priv 853 drivers/gpu/drm/mga/mga_dma.c if (!dev_priv->warp) { dev_priv 857 drivers/gpu/drm/mga/mga_dma.c dev_priv->primary = drm_legacy_findmap(dev, init->primary_offset); dev_priv 858 drivers/gpu/drm/mga/mga_dma.c if (!dev_priv->primary) { dev_priv 870 drivers/gpu/drm/mga/mga_dma.c drm_legacy_ioremap(dev_priv->warp, dev); dev_priv 871 drivers/gpu/drm/mga/mga_dma.c drm_legacy_ioremap(dev_priv->primary, dev); dev_priv 875 drivers/gpu/drm/mga/mga_dma.c dev_priv->sarea_priv = dev_priv 876 drivers/gpu/drm/mga/mga_dma.c (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle + dev_priv 879 drivers/gpu/drm/mga/mga_dma.c if (!dev_priv->warp->handle || dev_priv 880 drivers/gpu/drm/mga/mga_dma.c !dev_priv->primary->handle || dev_priv 881 drivers/gpu/drm/mga/mga_dma.c ((dev_priv->dma_access != 0) && dev_priv 888 drivers/gpu/drm/mga/mga_dma.c ret = mga_warp_install_microcode(dev_priv); dev_priv 894 drivers/gpu/drm/mga/mga_dma.c ret = mga_warp_init(dev_priv); dev_priv 900 drivers/gpu/drm/mga/mga_dma.c dev_priv->prim.status = (u32 *) dev_priv->status->handle; dev_priv 902 drivers/gpu/drm/mga/mga_dma.c mga_do_wait_for_idle(dev_priv); dev_priv 906 drivers/gpu/drm/mga/mga_dma.c MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL); dev_priv 908 drivers/gpu/drm/mga/mga_dma.c MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */ dev_priv 912 drivers/gpu/drm/mga/mga_dma.c dev_priv->prim.start = (u8 *) dev_priv->primary->handle; dev_priv 913 drivers/gpu/drm/mga/mga_dma.c dev_priv->prim.end = ((u8 *) dev_priv->primary->handle dev_priv 914 drivers/gpu/drm/mga/mga_dma.c + dev_priv->primary->size); dev_priv 915 drivers/gpu/drm/mga/mga_dma.c dev_priv->prim.size = dev_priv->primary->size; dev_priv 917 drivers/gpu/drm/mga/mga_dma.c dev_priv->prim.tail = 0; dev_priv 918 drivers/gpu/drm/mga/mga_dma.c dev_priv->prim.space = dev_priv->prim.size; dev_priv 919 drivers/gpu/drm/mga/mga_dma.c dev_priv->prim.wrapped = 0; dev_priv 921 drivers/gpu/drm/mga/mga_dma.c dev_priv->prim.last_flush = 0; dev_priv 922 drivers/gpu/drm/mga/mga_dma.c dev_priv->prim.last_wrap = 0; dev_priv 924 drivers/gpu/drm/mga/mga_dma.c dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE; dev_priv 926 drivers/gpu/drm/mga/mga_dma.c dev_priv->prim.status[0] = dev_priv->primary->offset; dev_priv 927 drivers/gpu/drm/mga/mga_dma.c dev_priv->prim.status[1] = 0; dev_priv 929 drivers/gpu/drm/mga/mga_dma.c dev_priv->sarea_priv->last_wrap = 0; dev_priv 930 drivers/gpu/drm/mga/mga_dma.c dev_priv->sarea_priv->last_frame.head = 0; dev_priv 931 drivers/gpu/drm/mga/mga_dma.c dev_priv->sarea_priv->last_frame.wrap = 0; dev_priv 933 drivers/gpu/drm/mga/mga_dma.c if (mga_freelist_init(dev, dev_priv) < 0) { dev_priv 954 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 956 drivers/gpu/drm/mga/mga_dma.c if ((dev_priv->warp != NULL) dev_priv 957 drivers/gpu/drm/mga/mga_dma.c && (dev_priv->warp->type != _DRM_CONSISTENT)) dev_priv 958 drivers/gpu/drm/mga/mga_dma.c drm_legacy_ioremapfree(dev_priv->warp, dev); dev_priv 960 drivers/gpu/drm/mga/mga_dma.c if ((dev_priv->primary != NULL) dev_priv 961 drivers/gpu/drm/mga/mga_dma.c && (dev_priv->primary->type != _DRM_CONSISTENT)) dev_priv 962 drivers/gpu/drm/mga/mga_dma.c drm_legacy_ioremapfree(dev_priv->primary, dev); dev_priv 967 drivers/gpu/drm/mga/mga_dma.c if (dev_priv->used_new_dma_init) { dev_priv 969 drivers/gpu/drm/mga/mga_dma.c if (dev_priv->agp_handle != 0) { dev_priv 973 drivers/gpu/drm/mga/mga_dma.c unbind_req.handle = dev_priv->agp_handle; dev_priv 976 drivers/gpu/drm/mga/mga_dma.c free_req.handle = dev_priv->agp_handle; dev_priv 979 drivers/gpu/drm/mga/mga_dma.c dev_priv->agp_textures = NULL; dev_priv 980 drivers/gpu/drm/mga/mga_dma.c dev_priv->agp_size = 0; dev_priv 981 drivers/gpu/drm/mga/mga_dma.c dev_priv->agp_handle = 0; dev_priv 989 drivers/gpu/drm/mga/mga_dma.c dev_priv->warp = NULL; dev_priv 990 drivers/gpu/drm/mga/mga_dma.c dev_priv->primary = NULL; dev_priv 991 drivers/gpu/drm/mga/mga_dma.c dev_priv->sarea = NULL; dev_priv 992 drivers/gpu/drm/mga/mga_dma.c dev_priv->sarea_priv = NULL; dev_priv 996 drivers/gpu/drm/mga/mga_dma.c dev_priv->mmio = NULL; dev_priv 997 drivers/gpu/drm/mga/mga_dma.c dev_priv->status = NULL; dev_priv 998 drivers/gpu/drm/mga/mga_dma.c dev_priv->used_new_dma_init = 0; dev_priv 1001 drivers/gpu/drm/mga/mga_dma.c memset(&dev_priv->prim, 0, sizeof(dev_priv->prim)); dev_priv 1002 drivers/gpu/drm/mga/mga_dma.c dev_priv->warp_pipe = 0; dev_priv 1003 drivers/gpu/drm/mga/mga_dma.c memset(dev_priv->warp_pipe_phys, 0, dev_priv 1004 drivers/gpu/drm/mga/mga_dma.c sizeof(dev_priv->warp_pipe_phys)); dev_priv 1006 drivers/gpu/drm/mga/mga_dma.c if (dev_priv->head != NULL) dev_priv 1041 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; dev_priv 1051 drivers/gpu/drm/mga/mga_dma.c WRAP_WAIT_WITH_RETURN(dev_priv); dev_priv 1054 drivers/gpu/drm/mga/mga_dma.c mga_do_dma_flush(dev_priv); dev_priv 1058 drivers/gpu/drm/mga/mga_dma.c int ret = mga_do_wait_for_idle(dev_priv); dev_priv 1063 drivers/gpu/drm/mga/mga_dma.c return mga_do_wait_for_idle(dev_priv); dev_priv 1073 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; dev_priv 1077 drivers/gpu/drm/mga/mga_dma.c return mga_do_dma_reset(dev_priv); dev_priv 1113 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; dev_priv 1136 drivers/gpu/drm/mga/mga_dma.c WRAP_TEST_WITH_RETURN(dev_priv); dev_priv 1165 drivers/gpu/drm/mga/mga_dma.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 1166 drivers/gpu/drm/mga/mga_dma.c return mga_do_wait_for_idle(dev_priv); dev_priv 188 drivers/gpu/drm/mga/mga_drv.h extern int mga_do_wait_for_idle(drm_mga_private_t *dev_priv); dev_priv 190 drivers/gpu/drm/mga/mga_drv.h extern void mga_do_dma_flush(drm_mga_private_t *dev_priv); dev_priv 191 drivers/gpu/drm/mga/mga_drv.h extern void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv); dev_priv 192 drivers/gpu/drm/mga/mga_drv.h extern void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv); dev_priv 197 drivers/gpu/drm/mga/mga_drv.h extern int mga_warp_install_microcode(drm_mga_private_t *dev_priv); dev_priv 198 drivers/gpu/drm/mga/mga_drv.h extern int mga_warp_init(drm_mga_private_t *dev_priv); dev_priv 216 drivers/gpu/drm/mga/mga_drv.h readb(((void __iomem *)dev_priv->mmio->handle) + (reg)) dev_priv 218 drivers/gpu/drm/mga/mga_drv.h readl(((void __iomem *)dev_priv->mmio->handle) + (reg)) dev_priv 220 drivers/gpu/drm/mga/mga_drv.h writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) dev_priv 222 drivers/gpu/drm/mga/mga_drv.h writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) dev_priv 238 drivers/gpu/drm/mga/mga_drv.h #define MGA_EMIT_STATE(dev_priv, dirty) \ dev_priv 241 drivers/gpu/drm/mga/mga_drv.h if (dev_priv->chipset >= MGA_CARD_TYPE_G400) \ dev_priv 242 drivers/gpu/drm/mga/mga_drv.h mga_g400_emit_state(dev_priv); \ dev_priv 244 drivers/gpu/drm/mga/mga_drv.h mga_g200_emit_state(dev_priv); \ dev_priv 248 drivers/gpu/drm/mga/mga_drv.h #define WRAP_TEST_WITH_RETURN(dev_priv) \ dev_priv 250 drivers/gpu/drm/mga/mga_drv.h if (test_bit(0, &dev_priv->prim.wrapped)) { \ dev_priv 251 drivers/gpu/drm/mga/mga_drv.h if (mga_is_idle(dev_priv)) { \ dev_priv 252 drivers/gpu/drm/mga/mga_drv.h mga_do_dma_wrap_end(dev_priv); \ dev_priv 253 drivers/gpu/drm/mga/mga_drv.h } else if (dev_priv->prim.space < \ dev_priv 254 drivers/gpu/drm/mga/mga_drv.h dev_priv->prim.high_mark) { \ dev_priv 262 drivers/gpu/drm/mga/mga_drv.h #define WRAP_WAIT_WITH_RETURN(dev_priv) \ dev_priv 264 drivers/gpu/drm/mga/mga_drv.h if (test_bit(0, &dev_priv->prim.wrapped)) { \ dev_priv 265 drivers/gpu/drm/mga/mga_drv.h if (mga_do_wait_for_idle(dev_priv) < 0) { \ dev_priv 270 drivers/gpu/drm/mga/mga_drv.h mga_do_dma_wrap_end(dev_priv); \ dev_priv 289 drivers/gpu/drm/mga/mga_drv.h dev_priv->prim.space, (n) * DMA_BLOCK_SIZE); \ dev_priv 291 drivers/gpu/drm/mga/mga_drv.h prim = dev_priv->prim.start; \ dev_priv 292 drivers/gpu/drm/mga/mga_drv.h write = dev_priv->prim.tail; \ dev_priv 299 drivers/gpu/drm/mga/mga_drv.h DRM_INFO(" space=0x%x\n", dev_priv->prim.space); \ dev_priv 301 drivers/gpu/drm/mga/mga_drv.h prim = dev_priv->prim.start; \ dev_priv 302 drivers/gpu/drm/mga/mga_drv.h write = dev_priv->prim.tail; \ dev_priv 307 drivers/gpu/drm/mga/mga_drv.h dev_priv->prim.tail = write; \ dev_priv 310 drivers/gpu/drm/mga/mga_drv.h write, dev_priv->prim.space); \ dev_priv 318 drivers/gpu/drm/mga/mga_drv.h dev_priv->prim.tail, \ dev_priv 320 drivers/gpu/drm/mga/mga_drv.h dev_priv->primary->offset)); \ dev_priv 322 drivers/gpu/drm/mga/mga_drv.h if (!test_bit(0, &dev_priv->prim.wrapped)) { \ dev_priv 323 drivers/gpu/drm/mga/mga_drv.h if (dev_priv->prim.space < dev_priv->prim.high_mark) \ dev_priv 324 drivers/gpu/drm/mga/mga_drv.h mga_do_dma_wrap_start(dev_priv); \ dev_priv 326 drivers/gpu/drm/mga/mga_drv.h mga_do_dma_flush(dev_priv); \ dev_priv 370 drivers/gpu/drm/mga/mga_drv.h entry->age.head = (dev_priv->prim.tail + \ dev_priv 371 drivers/gpu/drm/mga/mga_drv.h dev_priv->primary->offset); \ dev_priv 372 drivers/gpu/drm/mga/mga_drv.h entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ dev_priv 681 drivers/gpu/drm/mga/mga_drv.h static __inline__ int mga_is_idle(drm_mga_private_t *dev_priv) dev_priv 38 drivers/gpu/drm/mga/mga_irq.c const drm_mga_private_t *const dev_priv = dev_priv 44 drivers/gpu/drm/mga/mga_irq.c return atomic_read(&dev_priv->vbl_received); dev_priv 51 drivers/gpu/drm/mga/mga_irq.c drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; dev_priv 60 drivers/gpu/drm/mga/mga_irq.c atomic_inc(&dev_priv->vbl_received); dev_priv 79 drivers/gpu/drm/mga/mga_irq.c atomic_inc(&dev_priv->last_fence_retired); dev_priv 80 drivers/gpu/drm/mga/mga_irq.c wake_up(&dev_priv->fence_queue); dev_priv 91 drivers/gpu/drm/mga/mga_irq.c drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; dev_priv 121 drivers/gpu/drm/mga/mga_irq.c drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; dev_priv 128 drivers/gpu/drm/mga/mga_irq.c wait_event_timeout(dev_priv->fence_queue, dev_priv 129 drivers/gpu/drm/mga/mga_irq.c (((cur_fence = atomic_read(&dev_priv->last_fence_retired)) dev_priv 138 drivers/gpu/drm/mga/mga_irq.c drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; dev_priv 148 drivers/gpu/drm/mga/mga_irq.c drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; dev_priv 150 drivers/gpu/drm/mga/mga_irq.c init_waitqueue_head(&dev_priv->fence_queue); dev_priv 161 drivers/gpu/drm/mga/mga_irq.c drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; dev_priv 162 drivers/gpu/drm/mga/mga_irq.c if (!dev_priv) dev_priv 41 drivers/gpu/drm/mga/mga_state.c static void mga_emit_clip_rect(drm_mga_private_t *dev_priv, dev_priv 44 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 46 drivers/gpu/drm/mga/mga_state.c unsigned int pitch = dev_priv->front_pitch; dev_priv 53 drivers/gpu/drm/mga/mga_state.c if (dev_priv->chipset >= MGA_CARD_TYPE_G400) { dev_priv 66 drivers/gpu/drm/mga/mga_state.c static __inline__ void mga_g200_emit_context(drm_mga_private_t *dev_priv) dev_priv 68 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 80 drivers/gpu/drm/mga/mga_state.c MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset); dev_priv 89 drivers/gpu/drm/mga/mga_state.c static __inline__ void mga_g400_emit_context(drm_mga_private_t *dev_priv) dev_priv 91 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 103 drivers/gpu/drm/mga/mga_state.c MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset); dev_priv 116 drivers/gpu/drm/mga/mga_state.c static __inline__ void mga_g200_emit_tex0(drm_mga_private_t *dev_priv) dev_priv 118 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 144 drivers/gpu/drm/mga/mga_state.c static __inline__ void mga_g400_emit_tex0(drm_mga_private_t *dev_priv) dev_priv 146 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 184 drivers/gpu/drm/mga/mga_state.c static __inline__ void mga_g400_emit_tex1(drm_mga_private_t *dev_priv) dev_priv 186 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 223 drivers/gpu/drm/mga/mga_state.c static __inline__ void mga_g200_emit_pipe(drm_mga_private_t *dev_priv) dev_priv 225 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 244 drivers/gpu/drm/mga/mga_state.c MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] | dev_priv 245 drivers/gpu/drm/mga/mga_state.c MGA_WMODE_START | dev_priv->wagp_enable)); dev_priv 250 drivers/gpu/drm/mga/mga_state.c static __inline__ void mga_g400_emit_pipe(drm_mga_private_t *dev_priv) dev_priv 252 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 274 drivers/gpu/drm/mga/mga_state.c if (dev_priv->warp_pipe & MGA_T2) { dev_priv 321 drivers/gpu/drm/mga/mga_state.c MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] | dev_priv 322 drivers/gpu/drm/mga/mga_state.c MGA_WMODE_START | dev_priv->wagp_enable)); dev_priv 327 drivers/gpu/drm/mga/mga_state.c static void mga_g200_emit_state(drm_mga_private_t *dev_priv) dev_priv 329 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 332 drivers/gpu/drm/mga/mga_state.c if (sarea_priv->warp_pipe != dev_priv->warp_pipe) { dev_priv 333 drivers/gpu/drm/mga/mga_state.c mga_g200_emit_pipe(dev_priv); dev_priv 334 drivers/gpu/drm/mga/mga_state.c dev_priv->warp_pipe = sarea_priv->warp_pipe; dev_priv 338 drivers/gpu/drm/mga/mga_state.c mga_g200_emit_context(dev_priv); dev_priv 343 drivers/gpu/drm/mga/mga_state.c mga_g200_emit_tex0(dev_priv); dev_priv 348 drivers/gpu/drm/mga/mga_state.c static void mga_g400_emit_state(drm_mga_private_t *dev_priv) dev_priv 350 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 354 drivers/gpu/drm/mga/mga_state.c if (sarea_priv->warp_pipe != dev_priv->warp_pipe) { dev_priv 355 drivers/gpu/drm/mga/mga_state.c mga_g400_emit_pipe(dev_priv); dev_priv 356 drivers/gpu/drm/mga/mga_state.c dev_priv->warp_pipe = sarea_priv->warp_pipe; dev_priv 360 drivers/gpu/drm/mga/mga_state.c mga_g400_emit_context(dev_priv); dev_priv 365 drivers/gpu/drm/mga/mga_state.c mga_g400_emit_tex0(dev_priv); dev_priv 370 drivers/gpu/drm/mga/mga_state.c mga_g400_emit_tex1(dev_priv); dev_priv 381 drivers/gpu/drm/mga/mga_state.c static int mga_verify_context(drm_mga_private_t *dev_priv) dev_priv 383 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 386 drivers/gpu/drm/mga/mga_state.c if (ctx->dstorg != dev_priv->front_offset && dev_priv 387 drivers/gpu/drm/mga/mga_state.c ctx->dstorg != dev_priv->back_offset) { dev_priv 389 drivers/gpu/drm/mga/mga_state.c ctx->dstorg, dev_priv->front_offset, dev_priv 390 drivers/gpu/drm/mga/mga_state.c dev_priv->back_offset); dev_priv 400 drivers/gpu/drm/mga/mga_state.c static int mga_verify_tex(drm_mga_private_t *dev_priv, int unit) dev_priv 402 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 417 drivers/gpu/drm/mga/mga_state.c static int mga_verify_state(drm_mga_private_t *dev_priv) dev_priv 419 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 427 drivers/gpu/drm/mga/mga_state.c ret |= mga_verify_context(dev_priv); dev_priv 430 drivers/gpu/drm/mga/mga_state.c ret |= mga_verify_tex(dev_priv, 0); dev_priv 432 drivers/gpu/drm/mga/mga_state.c if (dev_priv->chipset >= MGA_CARD_TYPE_G400) { dev_priv 434 drivers/gpu/drm/mga/mga_state.c ret |= mga_verify_tex(dev_priv, 1); dev_priv 446 drivers/gpu/drm/mga/mga_state.c static int mga_verify_iload(drm_mga_private_t *dev_priv, dev_priv 449 drivers/gpu/drm/mga/mga_state.c if (dstorg < dev_priv->texture_offset || dev_priv 450 drivers/gpu/drm/mga/mga_state.c dstorg + length > (dev_priv->texture_offset + dev_priv 451 drivers/gpu/drm/mga/mga_state.c dev_priv->texture_size)) { dev_priv 465 drivers/gpu/drm/mga/mga_state.c static int mga_verify_blit(drm_mga_private_t *dev_priv, dev_priv 482 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 483 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 516 drivers/gpu/drm/mga/mga_state.c MGA_DSTORG, dev_priv->front_offset, dev_priv 517 drivers/gpu/drm/mga/mga_state.c MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd); dev_priv 532 drivers/gpu/drm/mga/mga_state.c MGA_DSTORG, dev_priv->back_offset, dev_priv 533 drivers/gpu/drm/mga/mga_state.c MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd); dev_priv 548 drivers/gpu/drm/mga/mga_state.c MGA_DSTORG, dev_priv->depth_offset, dev_priv 549 drivers/gpu/drm/mga/mga_state.c MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd); dev_priv 570 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 571 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 579 drivers/gpu/drm/mga/mga_state.c sarea_priv->last_frame.head = dev_priv->prim.tail; dev_priv 580 drivers/gpu/drm/mga/mga_state.c sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap; dev_priv 588 drivers/gpu/drm/mga/mga_state.c DMA_BLOCK(MGA_DSTORG, dev_priv->front_offset, dev_priv 589 drivers/gpu/drm/mga/mga_state.c MGA_MACCESS, dev_priv->maccess, dev_priv 590 drivers/gpu/drm/mga/mga_state.c MGA_SRCORG, dev_priv->back_offset, dev_priv 591 drivers/gpu/drm/mga/mga_state.c MGA_AR5, dev_priv->front_pitch); dev_priv 600 drivers/gpu/drm/mga/mga_state.c u32 start = box->y1 * dev_priv->front_pitch; dev_priv 613 drivers/gpu/drm/mga/mga_state.c MGA_SRCORG, dev_priv->front_offset, MGA_DWGCTL, ctx->dwgctl); dev_priv 624 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 626 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 636 drivers/gpu/drm/mga/mga_state.c MGA_EMIT_STATE(dev_priv, sarea_priv->dirty); dev_priv 640 drivers/gpu/drm/mga/mga_state.c mga_emit_clip_rect(dev_priv, dev_priv 651 drivers/gpu/drm/mga/mga_state.c dev_priv->dma_access)); dev_priv 672 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 674 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 683 drivers/gpu/drm/mga/mga_state.c MGA_EMIT_STATE(dev_priv, sarea_priv->dirty); dev_priv 687 drivers/gpu/drm/mga/mga_state.c mga_emit_clip_rect(dev_priv, dev_priv 697 drivers/gpu/drm/mga/mga_state.c dev_priv->dma_access)); dev_priv 721 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 723 drivers/gpu/drm/mga/mga_state.c drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state; dev_priv 725 drivers/gpu/drm/mga/mga_state.c buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM; dev_priv 750 drivers/gpu/drm/mga/mga_state.c MGA_SRCORG, dev_priv->front_offset, dev_priv 751 drivers/gpu/drm/mga/mga_state.c MGA_PITCH, dev_priv->front_pitch, MGA_DWGSYNC, 0x00007000); dev_priv 768 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 769 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 788 drivers/gpu/drm/mga/mga_state.c MGA_MACCESS, dev_priv->maccess, dev_priv 818 drivers/gpu/drm/mga/mga_state.c MGA_PITCH, dev_priv->front_pitch, MGA_DWGCTL, ctx->dwgctl); dev_priv 829 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 830 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 838 drivers/gpu/drm/mga/mga_state.c WRAP_TEST_WITH_RETURN(dev_priv); dev_priv 844 drivers/gpu/drm/mga/mga_state.c dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; dev_priv 851 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 852 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 859 drivers/gpu/drm/mga/mga_state.c WRAP_TEST_WITH_RETURN(dev_priv); dev_priv 865 drivers/gpu/drm/mga/mga_state.c dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; dev_priv 872 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 888 drivers/gpu/drm/mga/mga_state.c if (!mga_verify_state(dev_priv)) { dev_priv 898 drivers/gpu/drm/mga/mga_state.c WRAP_TEST_WITH_RETURN(dev_priv); dev_priv 907 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 923 drivers/gpu/drm/mga/mga_state.c if (!mga_verify_state(dev_priv)) { dev_priv 933 drivers/gpu/drm/mga/mga_state.c WRAP_TEST_WITH_RETURN(dev_priv); dev_priv 943 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 952 drivers/gpu/drm/mga/mga_state.c if (mga_do_wait_for_idle(dev_priv) < 0) { dev_priv 964 drivers/gpu/drm/mga/mga_state.c if (mga_verify_iload(dev_priv, iload->dstorg, iload->length)) { dev_priv 969 drivers/gpu/drm/mga/mga_state.c WRAP_TEST_WITH_RETURN(dev_priv); dev_priv 975 drivers/gpu/drm/mga/mga_state.c dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; dev_priv 982 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 983 drivers/gpu/drm/mga/mga_state.c drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 992 drivers/gpu/drm/mga/mga_state.c if (mga_verify_blit(dev_priv, blit->srcorg, blit->dstorg)) dev_priv 995 drivers/gpu/drm/mga/mga_state.c WRAP_TEST_WITH_RETURN(dev_priv); dev_priv 1001 drivers/gpu/drm/mga/mga_state.c dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; dev_priv 1008 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 1012 drivers/gpu/drm/mga/mga_state.c if (!dev_priv) { dev_priv 1024 drivers/gpu/drm/mga/mga_state.c value = dev_priv->chipset; dev_priv 1040 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 1044 drivers/gpu/drm/mga/mga_state.c if (!dev_priv) { dev_priv 1055 drivers/gpu/drm/mga/mga_state.c *fence = dev_priv->next_fence_to_post; dev_priv 1056 drivers/gpu/drm/mga/mga_state.c dev_priv->next_fence_to_post++; dev_priv 1070 drivers/gpu/drm/mga/mga_state.c drm_mga_private_t *dev_priv = dev->dev_private; dev_priv 1073 drivers/gpu/drm/mga/mga_state.c if (!dev_priv) { dev_priv 47 drivers/gpu/drm/mga/mga_warp.c int mga_warp_install_microcode(drm_mga_private_t *dev_priv) dev_priv 49 drivers/gpu/drm/mga/mga_warp.c unsigned char *vcbase = dev_priv->warp->handle; dev_priv 50 drivers/gpu/drm/mga/mga_warp.c unsigned long pcbase = dev_priv->warp->offset; dev_priv 59 drivers/gpu/drm/mga/mga_warp.c switch (dev_priv->chipset) { dev_priv 102 drivers/gpu/drm/mga/mga_warp.c if (size > dev_priv->warp->size) { dev_priv 104 drivers/gpu/drm/mga/mga_warp.c size, dev_priv->warp->size); dev_priv 109 drivers/gpu/drm/mga/mga_warp.c memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); dev_priv 118 drivers/gpu/drm/mga/mga_warp.c dev_priv->warp_pipe_phys[where] = pcbase; dev_priv 134 drivers/gpu/drm/mga/mga_warp.c int mga_warp_init(drm_mga_private_t *dev_priv) dev_priv 140 drivers/gpu/drm/mga/mga_warp.c switch (dev_priv->chipset) { dev_priv 62 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct msm_drm_private *dev_priv = dev->dev_private; dev_priv 66 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \ dev_priv 76 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \ dev_priv 105 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct msm_drm_private *dev_priv = dev->dev_private; dev_priv 111 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ dev_priv 133 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct msm_drm_private *dev_priv = dev->dev_private; dev_priv 139 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ dev_priv 57 drivers/gpu/drm/r128/r128_cce.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 64 drivers/gpu/drm/r128/r128_cce.c static void r128_status(drm_r128_private_t *dev_priv) dev_priv 85 drivers/gpu/drm/r128/r128_cce.c static int r128_do_pixcache_flush(drm_r128_private_t *dev_priv) dev_priv 93 drivers/gpu/drm/r128/r128_cce.c for (i = 0; i < dev_priv->usec_timeout; i++) { dev_priv 105 drivers/gpu/drm/r128/r128_cce.c static int r128_do_wait_for_fifo(drm_r128_private_t *dev_priv, int entries) dev_priv 109 drivers/gpu/drm/r128/r128_cce.c for (i = 0; i < dev_priv->usec_timeout; i++) { dev_priv 122 drivers/gpu/drm/r128/r128_cce.c static int r128_do_wait_for_idle(drm_r128_private_t *dev_priv) dev_priv 126 drivers/gpu/drm/r128/r128_cce.c ret = r128_do_wait_for_fifo(dev_priv, 64); dev_priv 130 drivers/gpu/drm/r128/r128_cce.c for (i = 0; i < dev_priv->usec_timeout; i++) { dev_priv 132 drivers/gpu/drm/r128/r128_cce.c r128_do_pixcache_flush(dev_priv); dev_priv 149 drivers/gpu/drm/r128/r128_cce.c static int r128_cce_load_microcode(drm_r128_private_t *dev_priv) dev_priv 178 drivers/gpu/drm/r128/r128_cce.c r128_do_wait_for_idle(dev_priv); dev_priv 198 drivers/gpu/drm/r128/r128_cce.c static void r128_do_cce_flush(drm_r128_private_t *dev_priv) dev_priv 208 drivers/gpu/drm/r128/r128_cce.c int r128_do_cce_idle(drm_r128_private_t *dev_priv) dev_priv 212 drivers/gpu/drm/r128/r128_cce.c for (i = 0; i < dev_priv->usec_timeout; i++) { dev_priv 213 drivers/gpu/drm/r128/r128_cce.c if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) { dev_priv 216 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_fifo_size) && dev_priv 219 drivers/gpu/drm/r128/r128_cce.c return r128_do_pixcache_flush(dev_priv); dev_priv 227 drivers/gpu/drm/r128/r128_cce.c r128_status(dev_priv); dev_priv 234 drivers/gpu/drm/r128/r128_cce.c static void r128_do_cce_start(drm_r128_private_t *dev_priv) dev_priv 236 drivers/gpu/drm/r128/r128_cce.c r128_do_wait_for_idle(dev_priv); dev_priv 239 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_mode | dev_priv->ring.size_l2qw dev_priv 244 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_running = 1; dev_priv 251 drivers/gpu/drm/r128/r128_cce.c static void r128_do_cce_reset(drm_r128_private_t *dev_priv) dev_priv 255 drivers/gpu/drm/r128/r128_cce.c dev_priv->ring.tail = 0; dev_priv 262 drivers/gpu/drm/r128/r128_cce.c static void r128_do_cce_stop(drm_r128_private_t *dev_priv) dev_priv 268 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_running = 0; dev_priv 275 drivers/gpu/drm/r128/r128_cce.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 278 drivers/gpu/drm/r128/r128_cce.c r128_do_pixcache_flush(dev_priv); dev_priv 299 drivers/gpu/drm/r128/r128_cce.c r128_do_cce_reset(dev_priv); dev_priv 302 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_running = 0; dev_priv 311 drivers/gpu/drm/r128/r128_cce.c drm_r128_private_t *dev_priv) dev_priv 322 drivers/gpu/drm/r128/r128_cce.c if (!dev_priv->is_pci) dev_priv 323 drivers/gpu/drm/r128/r128_cce.c ring_start = dev_priv->cce_ring->offset - dev->agp->base; dev_priv 326 drivers/gpu/drm/r128/r128_cce.c ring_start = dev_priv->cce_ring->offset - dev_priv 351 drivers/gpu/drm/r128/r128_cce.c drm_r128_private_t *dev_priv; dev_priv 361 drivers/gpu/drm/r128/r128_cce.c dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL); dev_priv 362 drivers/gpu/drm/r128/r128_cce.c if (dev_priv == NULL) dev_priv 365 drivers/gpu/drm/r128/r128_cce.c dev_priv->is_pci = init->is_pci; dev_priv 367 drivers/gpu/drm/r128/r128_cce.c if (dev_priv->is_pci && !dev->sg) { dev_priv 369 drivers/gpu/drm/r128/r128_cce.c dev->dev_private = (void *)dev_priv; dev_priv 374 drivers/gpu/drm/r128/r128_cce.c dev_priv->usec_timeout = init->usec_timeout; dev_priv 375 drivers/gpu/drm/r128/r128_cce.c if (dev_priv->usec_timeout < 1 || dev_priv 376 drivers/gpu/drm/r128/r128_cce.c dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) { dev_priv 378 drivers/gpu/drm/r128/r128_cce.c dev->dev_private = (void *)dev_priv; dev_priv 383 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_mode = init->cce_mode; dev_priv 387 drivers/gpu/drm/r128/r128_cce.c atomic_set(&dev_priv->idle_count, 0); dev_priv 398 drivers/gpu/drm/r128/r128_cce.c dev->dev_private = (void *)dev_priv; dev_priv 405 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_fifo_size = 0; dev_priv 409 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_fifo_size = 192; dev_priv 413 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_fifo_size = 128; dev_priv 420 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_fifo_size = 64; dev_priv 426 drivers/gpu/drm/r128/r128_cce.c dev_priv->color_fmt = R128_DATATYPE_RGB565; dev_priv 430 drivers/gpu/drm/r128/r128_cce.c dev_priv->color_fmt = R128_DATATYPE_ARGB8888; dev_priv 433 drivers/gpu/drm/r128/r128_cce.c dev_priv->front_offset = init->front_offset; dev_priv 434 drivers/gpu/drm/r128/r128_cce.c dev_priv->front_pitch = init->front_pitch; dev_priv 435 drivers/gpu/drm/r128/r128_cce.c dev_priv->back_offset = init->back_offset; dev_priv 436 drivers/gpu/drm/r128/r128_cce.c dev_priv->back_pitch = init->back_pitch; dev_priv 440 drivers/gpu/drm/r128/r128_cce.c dev_priv->depth_fmt = R128_DATATYPE_RGB565; dev_priv 445 drivers/gpu/drm/r128/r128_cce.c dev_priv->depth_fmt = R128_DATATYPE_ARGB8888; dev_priv 448 drivers/gpu/drm/r128/r128_cce.c dev_priv->depth_offset = init->depth_offset; dev_priv 449 drivers/gpu/drm/r128/r128_cce.c dev_priv->depth_pitch = init->depth_pitch; dev_priv 450 drivers/gpu/drm/r128/r128_cce.c dev_priv->span_offset = init->span_offset; dev_priv 452 drivers/gpu/drm/r128/r128_cce.c dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) | dev_priv 453 drivers/gpu/drm/r128/r128_cce.c (dev_priv->front_offset >> 5)); dev_priv 454 drivers/gpu/drm/r128/r128_cce.c dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) | dev_priv 455 drivers/gpu/drm/r128/r128_cce.c (dev_priv->back_offset >> 5)); dev_priv 456 drivers/gpu/drm/r128/r128_cce.c dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | dev_priv 457 drivers/gpu/drm/r128/r128_cce.c (dev_priv->depth_offset >> 5) | dev_priv 459 drivers/gpu/drm/r128/r128_cce.c dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | dev_priv 460 drivers/gpu/drm/r128/r128_cce.c (dev_priv->span_offset >> 5)); dev_priv 462 drivers/gpu/drm/r128/r128_cce.c dev_priv->sarea = drm_legacy_getsarea(dev); dev_priv 463 drivers/gpu/drm/r128/r128_cce.c if (!dev_priv->sarea) { dev_priv 465 drivers/gpu/drm/r128/r128_cce.c dev->dev_private = (void *)dev_priv; dev_priv 470 drivers/gpu/drm/r128/r128_cce.c dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset); dev_priv 471 drivers/gpu/drm/r128/r128_cce.c if (!dev_priv->mmio) { dev_priv 473 drivers/gpu/drm/r128/r128_cce.c dev->dev_private = (void *)dev_priv; dev_priv 477 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_ring = drm_legacy_findmap(dev, init->ring_offset); dev_priv 478 drivers/gpu/drm/r128/r128_cce.c if (!dev_priv->cce_ring) { dev_priv 480 drivers/gpu/drm/r128/r128_cce.c dev->dev_private = (void *)dev_priv; dev_priv 484 drivers/gpu/drm/r128/r128_cce.c dev_priv->ring_rptr = drm_legacy_findmap(dev, init->ring_rptr_offset); dev_priv 485 drivers/gpu/drm/r128/r128_cce.c if (!dev_priv->ring_rptr) { dev_priv 487 drivers/gpu/drm/r128/r128_cce.c dev->dev_private = (void *)dev_priv; dev_priv 495 drivers/gpu/drm/r128/r128_cce.c dev->dev_private = (void *)dev_priv; dev_priv 500 drivers/gpu/drm/r128/r128_cce.c if (!dev_priv->is_pci) { dev_priv 501 drivers/gpu/drm/r128/r128_cce.c dev_priv->agp_textures = dev_priv 503 drivers/gpu/drm/r128/r128_cce.c if (!dev_priv->agp_textures) { dev_priv 505 drivers/gpu/drm/r128/r128_cce.c dev->dev_private = (void *)dev_priv; dev_priv 511 drivers/gpu/drm/r128/r128_cce.c dev_priv->sarea_priv = dev_priv 512 drivers/gpu/drm/r128/r128_cce.c (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle + dev_priv 516 drivers/gpu/drm/r128/r128_cce.c if (!dev_priv->is_pci) { dev_priv 517 drivers/gpu/drm/r128/r128_cce.c drm_legacy_ioremap_wc(dev_priv->cce_ring, dev); dev_priv 518 drivers/gpu/drm/r128/r128_cce.c drm_legacy_ioremap_wc(dev_priv->ring_rptr, dev); dev_priv 520 drivers/gpu/drm/r128/r128_cce.c if (!dev_priv->cce_ring->handle || dev_priv 521 drivers/gpu/drm/r128/r128_cce.c !dev_priv->ring_rptr->handle || dev_priv 524 drivers/gpu/drm/r128/r128_cce.c dev->dev_private = (void *)dev_priv; dev_priv 531 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_ring->handle = dev_priv 532 drivers/gpu/drm/r128/r128_cce.c (void *)(unsigned long)dev_priv->cce_ring->offset; dev_priv 533 drivers/gpu/drm/r128/r128_cce.c dev_priv->ring_rptr->handle = dev_priv 534 drivers/gpu/drm/r128/r128_cce.c (void *)(unsigned long)dev_priv->ring_rptr->offset; dev_priv 540 drivers/gpu/drm/r128/r128_cce.c if (!dev_priv->is_pci) dev_priv 541 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_buffers_offset = dev->agp->base; dev_priv 544 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual; dev_priv 546 drivers/gpu/drm/r128/r128_cce.c dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle; dev_priv 547 drivers/gpu/drm/r128/r128_cce.c dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle dev_priv 549 drivers/gpu/drm/r128/r128_cce.c dev_priv->ring.size = init->ring_size; dev_priv 550 drivers/gpu/drm/r128/r128_cce.c dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8); dev_priv 552 drivers/gpu/drm/r128/r128_cce.c dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv 554 drivers/gpu/drm/r128/r128_cce.c dev_priv->ring.high_mark = 128; dev_priv 556 drivers/gpu/drm/r128/r128_cce.c dev_priv->sarea_priv->last_frame = 0; dev_priv 557 drivers/gpu/drm/r128/r128_cce.c R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); dev_priv 559 drivers/gpu/drm/r128/r128_cce.c dev_priv->sarea_priv->last_dispatch = 0; dev_priv 560 drivers/gpu/drm/r128/r128_cce.c R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch); dev_priv 563 drivers/gpu/drm/r128/r128_cce.c if (dev_priv->is_pci) { dev_priv 565 drivers/gpu/drm/r128/r128_cce.c dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); dev_priv 566 drivers/gpu/drm/r128/r128_cce.c dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; dev_priv 567 drivers/gpu/drm/r128/r128_cce.c dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE; dev_priv 568 drivers/gpu/drm/r128/r128_cce.c dev_priv->gart_info.addr = NULL; dev_priv 569 drivers/gpu/drm/r128/r128_cce.c dev_priv->gart_info.bus_addr = 0; dev_priv 570 drivers/gpu/drm/r128/r128_cce.c dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; dev_priv 571 drivers/gpu/drm/r128/r128_cce.c rc = drm_ati_pcigart_init(dev, &dev_priv->gart_info); dev_priv 574 drivers/gpu/drm/r128/r128_cce.c dev->dev_private = (void *)dev_priv; dev_priv 578 drivers/gpu/drm/r128/r128_cce.c R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr); dev_priv 583 drivers/gpu/drm/r128/r128_cce.c r128_cce_init_ring_buffer(dev, dev_priv); dev_priv 584 drivers/gpu/drm/r128/r128_cce.c rc = r128_cce_load_microcode(dev_priv); dev_priv 586 drivers/gpu/drm/r128/r128_cce.c dev->dev_private = (void *)dev_priv; dev_priv 609 drivers/gpu/drm/r128/r128_cce.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 612 drivers/gpu/drm/r128/r128_cce.c if (!dev_priv->is_pci) { dev_priv 613 drivers/gpu/drm/r128/r128_cce.c if (dev_priv->cce_ring != NULL) dev_priv 614 drivers/gpu/drm/r128/r128_cce.c drm_legacy_ioremapfree(dev_priv->cce_ring, dev); dev_priv 615 drivers/gpu/drm/r128/r128_cce.c if (dev_priv->ring_rptr != NULL) dev_priv 616 drivers/gpu/drm/r128/r128_cce.c drm_legacy_ioremapfree(dev_priv->ring_rptr, dev); dev_priv 624 drivers/gpu/drm/r128/r128_cce.c if (dev_priv->gart_info.bus_addr) dev_priv 626 drivers/gpu/drm/r128/r128_cce.c &dev_priv->gart_info)) dev_priv 658 drivers/gpu/drm/r128/r128_cce.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 663 drivers/gpu/drm/r128/r128_cce.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 665 drivers/gpu/drm/r128/r128_cce.c if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) { dev_priv 670 drivers/gpu/drm/r128/r128_cce.c r128_do_cce_start(dev_priv); dev_priv 680 drivers/gpu/drm/r128/r128_cce.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 687 drivers/gpu/drm/r128/r128_cce.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 693 drivers/gpu/drm/r128/r128_cce.c r128_do_cce_flush(dev_priv); dev_priv 699 drivers/gpu/drm/r128/r128_cce.c ret = r128_do_cce_idle(dev_priv); dev_priv 708 drivers/gpu/drm/r128/r128_cce.c r128_do_cce_stop(dev_priv); dev_priv 720 drivers/gpu/drm/r128/r128_cce.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 725 drivers/gpu/drm/r128/r128_cce.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 727 drivers/gpu/drm/r128/r128_cce.c r128_do_cce_reset(dev_priv); dev_priv 730 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_running = 0; dev_priv 737 drivers/gpu/drm/r128/r128_cce.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 742 drivers/gpu/drm/r128/r128_cce.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 744 drivers/gpu/drm/r128/r128_cce.c if (dev_priv->cce_running) dev_priv 745 drivers/gpu/drm/r128/r128_cce.c r128_do_cce_flush(dev_priv); dev_priv 747 drivers/gpu/drm/r128/r128_cce.c return r128_do_cce_idle(dev_priv); dev_priv 776 drivers/gpu/drm/r128/r128_cce.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 782 drivers/gpu/drm/r128/r128_cce.c dev_priv->head = kzalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL); dev_priv 783 drivers/gpu/drm/r128/r128_cce.c if (dev_priv->head == NULL) dev_priv 786 drivers/gpu/drm/r128/r128_cce.c dev_priv->head->age = R128_BUFFER_USED; dev_priv 798 drivers/gpu/drm/r128/r128_cce.c entry->prev = dev_priv->head; dev_priv 799 drivers/gpu/drm/r128/r128_cce.c entry->next = dev_priv->head->next; dev_priv 801 drivers/gpu/drm/r128/r128_cce.c dev_priv->tail = entry; dev_priv 807 drivers/gpu/drm/r128/r128_cce.c dev_priv->head->next = entry; dev_priv 809 drivers/gpu/drm/r128/r128_cce.c if (dev_priv->head->next) dev_priv 810 drivers/gpu/drm/r128/r128_cce.c dev_priv->head->next->prev = entry; dev_priv 821 drivers/gpu/drm/r128/r128_cce.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 835 drivers/gpu/drm/r128/r128_cce.c for (t = 0; t < dev_priv->usec_timeout; t++) { dev_priv 872 drivers/gpu/drm/r128/r128_cce.c int r128_wait_ring(drm_r128_private_t *dev_priv, int n) dev_priv 874 drivers/gpu/drm/r128/r128_cce.c drm_r128_ring_buffer_t *ring = &dev_priv->ring; dev_priv 877 drivers/gpu/drm/r128/r128_cce.c for (i = 0; i < dev_priv->usec_timeout; i++) { dev_priv 878 drivers/gpu/drm/r128/r128_cce.c r128_update_ring_snapshot(dev_priv); dev_priv 65 drivers/gpu/drm/r128/r128_drv.h #define GET_RING_HEAD(dev_priv) R128_READ(R128_PM4_BUFFER_DL_RPTR) dev_priv 162 drivers/gpu/drm/r128/r128_drv.h extern int r128_wait_ring(drm_r128_private_t *dev_priv, int n); dev_priv 164 drivers/gpu/drm/r128/r128_drv.h extern int r128_do_cce_idle(drm_r128_private_t *dev_priv); dev_priv 406 drivers/gpu/drm/r128/r128_drv.h #define R128_READ(reg) readl(((void __iomem *)dev_priv->mmio->handle) + (reg)) dev_priv 407 drivers/gpu/drm/r128/r128_drv.h #define R128_WRITE(reg, val) writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) dev_priv 408 drivers/gpu/drm/r128/r128_drv.h #define R128_READ8(reg) readb(((void __iomem *)dev_priv->mmio->handle) + (reg)) dev_priv 409 drivers/gpu/drm/r128/r128_drv.h #define R128_WRITE8(reg, val) writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) dev_priv 426 drivers/gpu/drm/r128/r128_drv.h static __inline__ void r128_update_ring_snapshot(drm_r128_private_t *dev_priv) dev_priv 428 drivers/gpu/drm/r128/r128_drv.h drm_r128_ring_buffer_t *ring = &dev_priv->ring; dev_priv 429 drivers/gpu/drm/r128/r128_drv.h ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32); dev_priv 446 drivers/gpu/drm/r128/r128_drv.h #define RING_SPACE_TEST_WITH_RETURN(dev_priv) \ dev_priv 448 drivers/gpu/drm/r128/r128_drv.h drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ dev_priv 450 drivers/gpu/drm/r128/r128_drv.h for (i = 0 ; i < dev_priv->usec_timeout ; i++) { \ dev_priv 451 drivers/gpu/drm/r128/r128_drv.h r128_update_ring_snapshot(dev_priv); \ dev_priv 463 drivers/gpu/drm/r128/r128_drv.h #define VB_AGE_TEST_WITH_RETURN(dev_priv) \ dev_priv 465 drivers/gpu/drm/r128/r128_drv.h drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \ dev_priv 467 drivers/gpu/drm/r128/r128_drv.h int __ret = r128_do_cce_idle(dev_priv); \ dev_priv 492 drivers/gpu/drm/r128/r128_drv.h if (dev_priv->ring.space <= (n) * sizeof(u32)) { \ dev_priv 494 drivers/gpu/drm/r128/r128_drv.h r128_wait_ring(dev_priv, (n) * sizeof(u32)); \ dev_priv 496 drivers/gpu/drm/r128/r128_drv.h _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ dev_priv 497 drivers/gpu/drm/r128/r128_drv.h ring = dev_priv->ring.start; \ dev_priv 498 drivers/gpu/drm/r128/r128_drv.h write = dev_priv->ring.tail; \ dev_priv 499 drivers/gpu/drm/r128/r128_drv.h tail_mask = dev_priv->ring.tail_mask; \ dev_priv 512 drivers/gpu/drm/r128/r128_drv.h write, dev_priv->ring.tail); \ dev_priv 514 drivers/gpu/drm/r128/r128_drv.h memcpy(dev_priv->ring.end, \ dev_priv 515 drivers/gpu/drm/r128/r128_drv.h dev_priv->ring.start, \ dev_priv 517 drivers/gpu/drm/r128/r128_drv.h if (((dev_priv->ring.tail + _nr) & tail_mask) != write) \ dev_priv 520 drivers/gpu/drm/r128/r128_drv.h ((dev_priv->ring.tail + _nr) & tail_mask), \ dev_priv 523 drivers/gpu/drm/r128/r128_drv.h dev_priv->ring.tail = write; \ dev_priv 529 drivers/gpu/drm/r128/r128_drv.h dev_priv->ring.tail); \ dev_priv 531 drivers/gpu/drm/r128/r128_drv.h R128_WRITE(R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail); \ dev_priv 42 drivers/gpu/drm/r128/r128_irq.c const drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 47 drivers/gpu/drm/r128/r128_irq.c return atomic_read(&dev_priv->vbl_received); dev_priv 53 drivers/gpu/drm/r128/r128_irq.c drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; dev_priv 61 drivers/gpu/drm/r128/r128_irq.c atomic_inc(&dev_priv->vbl_received); dev_priv 70 drivers/gpu/drm/r128/r128_irq.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 97 drivers/gpu/drm/r128/r128_irq.c drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; dev_priv 112 drivers/gpu/drm/r128/r128_irq.c drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; dev_priv 113 drivers/gpu/drm/r128/r128_irq.c if (!dev_priv) dev_priv 46 drivers/gpu/drm/r128/r128_state.c static void r128_emit_clip_rects(drm_r128_private_t *dev_priv, dev_priv 89 drivers/gpu/drm/r128/r128_state.c static __inline__ void r128_emit_core(drm_r128_private_t *dev_priv) dev_priv 91 drivers/gpu/drm/r128/r128_state.c drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 104 drivers/gpu/drm/r128/r128_state.c static __inline__ void r128_emit_context(drm_r128_private_t *dev_priv) dev_priv 106 drivers/gpu/drm/r128/r128_state.c drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 130 drivers/gpu/drm/r128/r128_state.c static __inline__ void r128_emit_setup(drm_r128_private_t *dev_priv) dev_priv 132 drivers/gpu/drm/r128/r128_state.c drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 146 drivers/gpu/drm/r128/r128_state.c static __inline__ void r128_emit_masks(drm_r128_private_t *dev_priv) dev_priv 148 drivers/gpu/drm/r128/r128_state.c drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 165 drivers/gpu/drm/r128/r128_state.c static __inline__ void r128_emit_window(drm_r128_private_t *dev_priv) dev_priv 167 drivers/gpu/drm/r128/r128_state.c drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 180 drivers/gpu/drm/r128/r128_state.c static __inline__ void r128_emit_tex0(drm_r128_private_t *dev_priv) dev_priv 182 drivers/gpu/drm/r128/r128_state.c drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 206 drivers/gpu/drm/r128/r128_state.c static __inline__ void r128_emit_tex1(drm_r128_private_t *dev_priv) dev_priv 208 drivers/gpu/drm/r128/r128_state.c drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 228 drivers/gpu/drm/r128/r128_state.c static void r128_emit_state(drm_r128_private_t *dev_priv) dev_priv 230 drivers/gpu/drm/r128/r128_state.c drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 236 drivers/gpu/drm/r128/r128_state.c r128_emit_core(dev_priv); dev_priv 241 drivers/gpu/drm/r128/r128_state.c r128_emit_context(dev_priv); dev_priv 246 drivers/gpu/drm/r128/r128_state.c r128_emit_setup(dev_priv); dev_priv 251 drivers/gpu/drm/r128/r128_state.c r128_emit_masks(dev_priv); dev_priv 256 drivers/gpu/drm/r128/r128_state.c r128_emit_window(dev_priv); dev_priv 261 drivers/gpu/drm/r128/r128_state.c r128_emit_tex0(dev_priv); dev_priv 266 drivers/gpu/drm/r128/r128_state.c r128_emit_tex1(dev_priv); dev_priv 281 drivers/gpu/drm/r128/r128_state.c static void r128_clear_box(drm_r128_private_t *dev_priv, dev_priv 288 drivers/gpu/drm/r128/r128_state.c switch (dev_priv->fb_bpp) { dev_priv 306 drivers/gpu/drm/r128/r128_state.c offset = dev_priv->back_offset; dev_priv 307 drivers/gpu/drm/r128/r128_state.c pitch = dev_priv->back_pitch >> 3; dev_priv 328 drivers/gpu/drm/r128/r128_state.c static void r128_cce_performance_boxes(drm_r128_private_t *dev_priv) dev_priv 330 drivers/gpu/drm/r128/r128_state.c if (atomic_read(&dev_priv->idle_count) == 0) dev_priv 331 drivers/gpu/drm/r128/r128_state.c r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0); dev_priv 333 drivers/gpu/drm/r128/r128_state.c atomic_set(&dev_priv->idle_count, 0); dev_priv 361 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 362 drivers/gpu/drm/r128/r128_state.c drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 370 drivers/gpu/drm/r128/r128_state.c if (dev_priv->page_flipping && dev_priv->current_page == 1) { dev_priv 405 drivers/gpu/drm/r128/r128_state.c (dev_priv->color_fmt << 8) | dev_priv 411 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->front_pitch_offset_c); dev_priv 426 drivers/gpu/drm/r128/r128_state.c (dev_priv->color_fmt << 8) | dev_priv 432 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->back_pitch_offset_c); dev_priv 447 drivers/gpu/drm/r128/r128_state.c (dev_priv->depth_fmt << 8) | dev_priv 453 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->depth_pitch_offset_c); dev_priv 466 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 467 drivers/gpu/drm/r128/r128_state.c drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 477 drivers/gpu/drm/r128/r128_state.c r128_cce_performance_boxes(dev_priv); dev_priv 492 drivers/gpu/drm/r128/r128_state.c (dev_priv->color_fmt << 8) | dev_priv 501 drivers/gpu/drm/r128/r128_state.c if (dev_priv->current_page == 0) { dev_priv 502 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->back_pitch_offset_c); dev_priv 503 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->front_pitch_offset_c); dev_priv 505 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->front_pitch_offset_c); dev_priv 506 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->back_pitch_offset_c); dev_priv 520 drivers/gpu/drm/r128/r128_state.c dev_priv->sarea_priv->last_frame++; dev_priv 525 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->sarea_priv->last_frame); dev_priv 532 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 535 drivers/gpu/drm/r128/r128_state.c dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage); dev_priv 540 drivers/gpu/drm/r128/r128_state.c r128_cce_performance_boxes(dev_priv); dev_priv 548 drivers/gpu/drm/r128/r128_state.c if (dev_priv->current_page == 0) dev_priv 549 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->back_offset); dev_priv 551 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->front_offset); dev_priv 559 drivers/gpu/drm/r128/r128_state.c dev_priv->sarea_priv->last_frame++; dev_priv 560 drivers/gpu/drm/r128/r128_state.c dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = dev_priv 561 drivers/gpu/drm/r128/r128_state.c 1 - dev_priv->current_page; dev_priv 566 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->sarea_priv->last_frame); dev_priv 573 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 575 drivers/gpu/drm/r128/r128_state.c drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 591 drivers/gpu/drm/r128/r128_state.c r128_emit_state(dev_priv); dev_priv 596 drivers/gpu/drm/r128/r128_state.c r128_emit_clip_rects(dev_priv, dev_priv 618 drivers/gpu/drm/r128/r128_state.c buf_priv->age = dev_priv->sarea_priv->last_dispatch; dev_priv 634 drivers/gpu/drm/r128/r128_state.c dev_priv->sarea_priv->last_dispatch++; dev_priv 643 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 676 drivers/gpu/drm/r128/r128_state.c buf_priv->age = dev_priv->sarea_priv->last_dispatch; dev_priv 692 drivers/gpu/drm/r128/r128_state.c dev_priv->sarea_priv->last_dispatch++; dev_priv 699 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 701 drivers/gpu/drm/r128/r128_state.c drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 703 drivers/gpu/drm/r128/r128_state.c int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset; dev_priv 718 drivers/gpu/drm/r128/r128_state.c r128_emit_state(dev_priv); dev_priv 745 drivers/gpu/drm/r128/r128_state.c r128_emit_clip_rects(dev_priv, dev_priv 757 drivers/gpu/drm/r128/r128_state.c buf_priv->age = dev_priv->sarea_priv->last_dispatch; dev_priv 772 drivers/gpu/drm/r128/r128_state.c dev_priv->sarea_priv->last_dispatch++; dev_priv 782 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 893 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 930 drivers/gpu/drm/r128/r128_state.c (dev_priv->depth_fmt << 8) | dev_priv 936 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->depth_pitch_offset_c); dev_priv 954 drivers/gpu/drm/r128/r128_state.c (dev_priv->depth_fmt << 8) | dev_priv 960 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->depth_pitch_offset_c); dev_priv 978 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1025 drivers/gpu/drm/r128/r128_state.c (dev_priv->depth_fmt << 8) | dev_priv 1031 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->depth_pitch_offset_c); dev_priv 1049 drivers/gpu/drm/r128/r128_state.c (dev_priv->depth_fmt << 8) | dev_priv 1055 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->depth_pitch_offset_c); dev_priv 1075 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1095 drivers/gpu/drm/r128/r128_state.c (dev_priv->depth_fmt << 8) | dev_priv 1101 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->depth_pitch_offset_c); dev_priv 1102 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->span_pitch_offset_c); dev_priv 1116 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1126 drivers/gpu/drm/r128/r128_state.c if (count > dev_priv->depth_pitch) dev_priv 1127 drivers/gpu/drm/r128/r128_state.c count = dev_priv->depth_pitch; dev_priv 1157 drivers/gpu/drm/r128/r128_state.c (dev_priv->depth_fmt << 8) | dev_priv 1163 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->depth_pitch_offset_c); dev_priv 1164 drivers/gpu/drm/r128/r128_state.c OUT_RING(dev_priv->span_pitch_offset_c); dev_priv 1185 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1205 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1212 drivers/gpu/drm/r128/r128_state.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 1214 drivers/gpu/drm/r128/r128_state.c RING_SPACE_TEST_WITH_RETURN(dev_priv); dev_priv 1216 drivers/gpu/drm/r128/r128_state.c sarea_priv = dev_priv->sarea_priv; dev_priv 1226 drivers/gpu/drm/r128/r128_state.c dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS; dev_priv 1233 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1236 drivers/gpu/drm/r128/r128_state.c dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET); dev_priv 1237 drivers/gpu/drm/r128/r128_state.c dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL); dev_priv 1239 drivers/gpu/drm/r128/r128_state.c R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset); dev_priv 1241 drivers/gpu/drm/r128/r128_state.c dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL); dev_priv 1243 drivers/gpu/drm/r128/r128_state.c dev_priv->page_flipping = 1; dev_priv 1244 drivers/gpu/drm/r128/r128_state.c dev_priv->current_page = 0; dev_priv 1245 drivers/gpu/drm/r128/r128_state.c dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page; dev_priv 1252 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1255 drivers/gpu/drm/r128/r128_state.c R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset); dev_priv 1256 drivers/gpu/drm/r128/r128_state.c R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl); dev_priv 1258 drivers/gpu/drm/r128/r128_state.c if (dev_priv->current_page != 0) { dev_priv 1263 drivers/gpu/drm/r128/r128_state.c dev_priv->page_flipping = 0; dev_priv 1273 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1278 drivers/gpu/drm/r128/r128_state.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 1280 drivers/gpu/drm/r128/r128_state.c RING_SPACE_TEST_WITH_RETURN(dev_priv); dev_priv 1282 drivers/gpu/drm/r128/r128_state.c if (!dev_priv->page_flipping) dev_priv 1293 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1294 drivers/gpu/drm/r128/r128_state.c drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; dev_priv 1299 drivers/gpu/drm/r128/r128_state.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 1301 drivers/gpu/drm/r128/r128_state.c RING_SPACE_TEST_WITH_RETURN(dev_priv); dev_priv 1307 drivers/gpu/drm/r128/r128_state.c dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT | dev_priv 1316 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1324 drivers/gpu/drm/r128/r128_state.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 1340 drivers/gpu/drm/r128/r128_state.c RING_SPACE_TEST_WITH_RETURN(dev_priv); dev_priv 1341 drivers/gpu/drm/r128/r128_state.c VB_AGE_TEST_WITH_RETURN(dev_priv); dev_priv 1368 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1377 drivers/gpu/drm/r128/r128_state.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 1393 drivers/gpu/drm/r128/r128_state.c RING_SPACE_TEST_WITH_RETURN(dev_priv); dev_priv 1394 drivers/gpu/drm/r128/r128_state.c VB_AGE_TEST_WITH_RETURN(dev_priv); dev_priv 1434 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1440 drivers/gpu/drm/r128/r128_state.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 1450 drivers/gpu/drm/r128/r128_state.c RING_SPACE_TEST_WITH_RETURN(dev_priv); dev_priv 1451 drivers/gpu/drm/r128/r128_state.c VB_AGE_TEST_WITH_RETURN(dev_priv); dev_priv 1461 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1467 drivers/gpu/drm/r128/r128_state.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 1469 drivers/gpu/drm/r128/r128_state.c RING_SPACE_TEST_WITH_RETURN(dev_priv); dev_priv 1493 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1499 drivers/gpu/drm/r128/r128_state.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 1504 drivers/gpu/drm/r128/r128_state.c RING_SPACE_TEST_WITH_RETURN(dev_priv); dev_priv 1514 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1525 drivers/gpu/drm/r128/r128_state.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 1556 drivers/gpu/drm/r128/r128_state.c RING_SPACE_TEST_WITH_RETURN(dev_priv); dev_priv 1557 drivers/gpu/drm/r128/r128_state.c VB_AGE_TEST_WITH_RETURN(dev_priv); dev_priv 1583 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1587 drivers/gpu/drm/r128/r128_state.c DEV_INIT_TEST_WITH_RETURN(dev_priv); dev_priv 1610 drivers/gpu/drm/r128/r128_state.c drm_r128_private_t *dev_priv = dev->dev_private; dev_priv 1611 drivers/gpu/drm/r128/r128_state.c if (dev_priv->page_flipping) dev_priv 47 drivers/gpu/drm/savage/savage_bci.c savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n) dev_priv 49 drivers/gpu/drm/savage/savage_bci.c uint32_t mask = dev_priv->status_used_mask; dev_priv 50 drivers/gpu/drm/savage/savage_bci.c uint32_t threshold = dev_priv->bci_threshold_hi; dev_priv 55 drivers/gpu/drm/savage/savage_bci.c if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) dev_priv 62 drivers/gpu/drm/savage/savage_bci.c status = dev_priv->status_ptr[0]; dev_priv 76 drivers/gpu/drm/savage/savage_bci.c savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n) dev_priv 78 drivers/gpu/drm/savage/savage_bci.c uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; dev_priv 97 drivers/gpu/drm/savage/savage_bci.c savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n) dev_priv 99 drivers/gpu/drm/savage/savage_bci.c uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; dev_priv 129 drivers/gpu/drm/savage/savage_bci.c savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e) dev_priv 136 drivers/gpu/drm/savage/savage_bci.c status = dev_priv->status_ptr[1]; dev_priv 152 drivers/gpu/drm/savage/savage_bci.c savage_bci_wait_event_reg(drm_savage_private_t * dev_priv, uint16_t e) dev_priv 173 drivers/gpu/drm/savage/savage_bci.c uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv, dev_priv 179 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->status_ptr) { dev_priv 181 drivers/gpu/drm/savage/savage_bci.c count = dev_priv->status_ptr[1023]; dev_priv 182 drivers/gpu/drm/savage/savage_bci.c if (count < dev_priv->event_counter) dev_priv 183 drivers/gpu/drm/savage/savage_bci.c dev_priv->event_wrap++; dev_priv 185 drivers/gpu/drm/savage/savage_bci.c count = dev_priv->event_counter; dev_priv 190 drivers/gpu/drm/savage/savage_bci.c dev_priv->event_wrap++; dev_priv 192 drivers/gpu/drm/savage/savage_bci.c dev_priv->event_counter = count; dev_priv 193 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->status_ptr) dev_priv 194 drivers/gpu/drm/savage/savage_bci.c dev_priv->status_ptr[1023] = (uint32_t) count; dev_priv 217 drivers/gpu/drm/savage/savage_bci.c drm_savage_private_t *dev_priv = dev->dev_private; dev_priv 224 drivers/gpu/drm/savage/savage_bci.c dev_priv->head.next = &dev_priv->tail; dev_priv 225 drivers/gpu/drm/savage/savage_bci.c dev_priv->head.prev = NULL; dev_priv 226 drivers/gpu/drm/savage/savage_bci.c dev_priv->head.buf = NULL; dev_priv 228 drivers/gpu/drm/savage/savage_bci.c dev_priv->tail.next = NULL; dev_priv 229 drivers/gpu/drm/savage/savage_bci.c dev_priv->tail.prev = &dev_priv->head; dev_priv 230 drivers/gpu/drm/savage/savage_bci.c dev_priv->tail.buf = NULL; dev_priv 239 drivers/gpu/drm/savage/savage_bci.c entry->next = dev_priv->head.next; dev_priv 240 drivers/gpu/drm/savage/savage_bci.c entry->prev = &dev_priv->head; dev_priv 241 drivers/gpu/drm/savage/savage_bci.c dev_priv->head.next->prev = entry; dev_priv 242 drivers/gpu/drm/savage/savage_bci.c dev_priv->head.next = entry; dev_priv 250 drivers/gpu/drm/savage/savage_bci.c drm_savage_private_t *dev_priv = dev->dev_private; dev_priv 251 drivers/gpu/drm/savage/savage_bci.c drm_savage_buf_priv_t *tail = dev_priv->tail.prev; dev_priv 257 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->status_ptr) dev_priv 258 drivers/gpu/drm/savage/savage_bci.c event = dev_priv->status_ptr[1] & 0xffff; dev_priv 261 drivers/gpu/drm/savage/savage_bci.c wrap = dev_priv->event_wrap; dev_priv 262 drivers/gpu/drm/savage/savage_bci.c if (event > dev_priv->event_counter) dev_priv 283 drivers/gpu/drm/savage/savage_bci.c drm_savage_private_t *dev_priv = dev->dev_private; dev_priv 293 drivers/gpu/drm/savage/savage_bci.c prev = &dev_priv->head; dev_priv 304 drivers/gpu/drm/savage/savage_bci.c static int savage_dma_init(drm_savage_private_t * dev_priv) dev_priv 308 drivers/gpu/drm/savage/savage_bci.c dev_priv->nr_dma_pages = dev_priv->cmd_dma->size / dev_priv 310 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages = kmalloc_array(dev_priv->nr_dma_pages, dev_priv 313 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->dma_pages == NULL) dev_priv 316 drivers/gpu/drm/savage/savage_bci.c for (i = 0; i < dev_priv->nr_dma_pages; ++i) { dev_priv 317 drivers/gpu/drm/savage/savage_bci.c SET_AGE(&dev_priv->dma_pages[i].age, 0, 0); dev_priv 318 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[i].used = 0; dev_priv 319 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[i].flushed = 0; dev_priv 321 drivers/gpu/drm/savage/savage_bci.c SET_AGE(&dev_priv->last_dma_age, 0, 0); dev_priv 323 drivers/gpu/drm/savage/savage_bci.c dev_priv->first_dma_page = 0; dev_priv 324 drivers/gpu/drm/savage/savage_bci.c dev_priv->current_dma_page = 0; dev_priv 329 drivers/gpu/drm/savage/savage_bci.c void savage_dma_reset(drm_savage_private_t * dev_priv) dev_priv 333 drivers/gpu/drm/savage/savage_bci.c event = savage_bci_emit_event(dev_priv, 0); dev_priv 334 drivers/gpu/drm/savage/savage_bci.c wrap = dev_priv->event_wrap; dev_priv 335 drivers/gpu/drm/savage/savage_bci.c for (i = 0; i < dev_priv->nr_dma_pages; ++i) { dev_priv 336 drivers/gpu/drm/savage/savage_bci.c SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); dev_priv 337 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[i].used = 0; dev_priv 338 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[i].flushed = 0; dev_priv 340 drivers/gpu/drm/savage/savage_bci.c SET_AGE(&dev_priv->last_dma_age, event, wrap); dev_priv 341 drivers/gpu/drm/savage/savage_bci.c dev_priv->first_dma_page = dev_priv->current_dma_page = 0; dev_priv 344 drivers/gpu/drm/savage/savage_bci.c void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page) dev_priv 350 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->cmd_dma == &dev_priv->fake_dma) dev_priv 354 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->status_ptr) dev_priv 355 drivers/gpu/drm/savage/savage_bci.c event = dev_priv->status_ptr[1] & 0xffff; dev_priv 358 drivers/gpu/drm/savage/savage_bci.c wrap = dev_priv->event_wrap; dev_priv 359 drivers/gpu/drm/savage/savage_bci.c if (event > dev_priv->event_counter) dev_priv 362 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->dma_pages[page].age.wrap > wrap || dev_priv 363 drivers/gpu/drm/savage/savage_bci.c (dev_priv->dma_pages[page].age.wrap == wrap && dev_priv 364 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[page].age.event > event)) { dev_priv 365 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->wait_evnt(dev_priv, dev_priv 366 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[page].age.event) dev_priv 372 drivers/gpu/drm/savage/savage_bci.c uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n) dev_priv 374 drivers/gpu/drm/savage/savage_bci.c unsigned int cur = dev_priv->current_dma_page; dev_priv 376 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[cur].used; dev_priv 383 drivers/gpu/drm/savage/savage_bci.c cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages); dev_priv 385 drivers/gpu/drm/savage/savage_bci.c if (cur + nr_pages < dev_priv->nr_dma_pages) { dev_priv 386 drivers/gpu/drm/savage/savage_bci.c dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + dev_priv 387 drivers/gpu/drm/savage/savage_bci.c cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; dev_priv 390 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[cur].used += rest; dev_priv 394 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_flush(dev_priv); dev_priv 397 drivers/gpu/drm/savage/savage_bci.c for (i = cur; i < dev_priv->nr_dma_pages; ++i) { dev_priv 398 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[i].age = dev_priv->last_dma_age; dev_priv 399 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[i].used = 0; dev_priv 400 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[i].flushed = 0; dev_priv 402 drivers/gpu/drm/savage/savage_bci.c dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle; dev_priv 403 drivers/gpu/drm/savage/savage_bci.c dev_priv->first_dma_page = cur = 0; dev_priv 407 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->dma_pages[i].used) { dev_priv 409 drivers/gpu/drm/savage/savage_bci.c i, dev_priv->dma_pages[i].used); dev_priv 413 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE; dev_priv 415 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[i].used = n; dev_priv 418 drivers/gpu/drm/savage/savage_bci.c dev_priv->current_dma_page = --i; dev_priv 421 drivers/gpu/drm/savage/savage_bci.c i, dev_priv->dma_pages[i].used, n); dev_priv 423 drivers/gpu/drm/savage/savage_bci.c savage_dma_wait(dev_priv, dev_priv->current_dma_page); dev_priv 428 drivers/gpu/drm/savage/savage_bci.c static void savage_dma_flush(drm_savage_private_t * dev_priv) dev_priv 430 drivers/gpu/drm/savage/savage_bci.c unsigned int first = dev_priv->first_dma_page; dev_priv 431 drivers/gpu/drm/savage/savage_bci.c unsigned int cur = dev_priv->current_dma_page; dev_priv 438 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed) dev_priv 443 drivers/gpu/drm/savage/savage_bci.c pad = -dev_priv->dma_pages[cur].used & 1; dev_priv 444 drivers/gpu/drm/savage/savage_bci.c align = -(dev_priv->dma_pages[cur].used + pad) & 7; dev_priv 448 drivers/gpu/drm/savage/savage_bci.c first, cur, dev_priv->dma_pages[first].flushed, dev_priv 449 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[cur].used, pad, align); dev_priv 453 drivers/gpu/drm/savage/savage_bci.c uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + dev_priv 454 drivers/gpu/drm/savage/savage_bci.c cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; dev_priv 455 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[cur].used += pad; dev_priv 465 drivers/gpu/drm/savage/savage_bci.c phys_addr = dev_priv->cmd_dma->offset + dev_priv 467 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[first].flushed) * 4; dev_priv 469 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed; dev_priv 472 drivers/gpu/drm/savage/savage_bci.c phys_addr | dev_priv->dma_type, len); dev_priv 476 drivers/gpu/drm/savage/savage_bci.c BCI_WRITE(phys_addr | dev_priv->dma_type); dev_priv 480 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[cur].used += align; dev_priv 483 drivers/gpu/drm/savage/savage_bci.c event = savage_bci_emit_event(dev_priv, 0); dev_priv 484 drivers/gpu/drm/savage/savage_bci.c wrap = dev_priv->event_wrap; dev_priv 486 drivers/gpu/drm/savage/savage_bci.c SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); dev_priv 487 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[i].used = 0; dev_priv 488 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[i].flushed = 0; dev_priv 491 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) { dev_priv 492 drivers/gpu/drm/savage/savage_bci.c SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap); dev_priv 493 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[cur].used = 0; dev_priv 494 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[cur].flushed = 0; dev_priv 497 drivers/gpu/drm/savage/savage_bci.c if (cur == dev_priv->nr_dma_pages) dev_priv 499 drivers/gpu/drm/savage/savage_bci.c dev_priv->first_dma_page = dev_priv->current_dma_page = cur; dev_priv 501 drivers/gpu/drm/savage/savage_bci.c dev_priv->first_dma_page = cur; dev_priv 502 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used; dev_priv 504 drivers/gpu/drm/savage/savage_bci.c SET_AGE(&dev_priv->last_dma_age, event, wrap); dev_priv 507 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[cur].used, dev_priv 508 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[cur].flushed); dev_priv 511 drivers/gpu/drm/savage/savage_bci.c static void savage_fake_dma_flush(drm_savage_private_t * dev_priv) dev_priv 516 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->first_dma_page == dev_priv->current_dma_page && dev_priv 517 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[dev_priv->current_dma_page].used == 0) dev_priv 521 drivers/gpu/drm/savage/savage_bci.c dev_priv->first_dma_page, dev_priv->current_dma_page, dev_priv 522 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[dev_priv->current_dma_page].used); dev_priv 524 drivers/gpu/drm/savage/savage_bci.c for (i = dev_priv->first_dma_page; dev_priv 525 drivers/gpu/drm/savage/savage_bci.c i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used; dev_priv 527 drivers/gpu/drm/savage/savage_bci.c uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + dev_priv 531 drivers/gpu/drm/savage/savage_bci.c if (i < dev_priv->current_dma_page && dev_priv 532 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) { dev_priv 534 drivers/gpu/drm/savage/savage_bci.c i, dev_priv->dma_pages[i].used); dev_priv 537 drivers/gpu/drm/savage/savage_bci.c BEGIN_BCI(dev_priv->dma_pages[i].used); dev_priv 538 drivers/gpu/drm/savage/savage_bci.c for (j = 0; j < dev_priv->dma_pages[i].used; ++j) { dev_priv 541 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_pages[i].used = 0; dev_priv 545 drivers/gpu/drm/savage/savage_bci.c dev_priv->first_dma_page = dev_priv->current_dma_page = 0; dev_priv 550 drivers/gpu/drm/savage/savage_bci.c drm_savage_private_t *dev_priv; dev_priv 552 drivers/gpu/drm/savage/savage_bci.c dev_priv = kzalloc(sizeof(drm_savage_private_t), GFP_KERNEL); dev_priv 553 drivers/gpu/drm/savage/savage_bci.c if (dev_priv == NULL) dev_priv 556 drivers/gpu/drm/savage/savage_bci.c dev->dev_private = (void *)dev_priv; dev_priv 558 drivers/gpu/drm/savage/savage_bci.c dev_priv->chipset = (enum savage_family)chipset; dev_priv 574 drivers/gpu/drm/savage/savage_bci.c drm_savage_private_t *dev_priv = dev->dev_private; dev_priv 583 drivers/gpu/drm/savage/savage_bci.c if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { dev_priv 594 drivers/gpu/drm/savage/savage_bci.c dev_priv->mtrr_handles[0] = dev_priv 596 drivers/gpu/drm/savage/savage_bci.c dev_priv->mtrr_handles[1] = dev_priv 599 drivers/gpu/drm/savage/savage_bci.c dev_priv->mtrr_handles[2] = dev_priv 607 drivers/gpu/drm/savage/savage_bci.c } else if (dev_priv->chipset != S3_SUPERSAVAGE && dev_priv 608 drivers/gpu/drm/savage/savage_bci.c dev_priv->chipset != S3_SAVAGE2000) { dev_priv 619 drivers/gpu/drm/savage/savage_bci.c dev_priv->mtrr_handles[0] = dev_priv 639 drivers/gpu/drm/savage/savage_bci.c &dev_priv->mmio); dev_priv 644 drivers/gpu/drm/savage/savage_bci.c _DRM_WRITE_COMBINING, &dev_priv->fb); dev_priv 650 drivers/gpu/drm/savage/savage_bci.c &dev_priv->aperture); dev_priv 659 drivers/gpu/drm/savage/savage_bci.c drm_savage_private_t *dev_priv = dev->dev_private; dev_priv 663 drivers/gpu/drm/savage/savage_bci.c arch_phys_wc_del(dev_priv->mtrr_handles[i]); dev_priv 664 drivers/gpu/drm/savage/savage_bci.c dev_priv->mtrr_handles[i] = 0; dev_priv 670 drivers/gpu/drm/savage/savage_bci.c drm_savage_private_t *dev_priv = dev->dev_private; dev_priv 672 drivers/gpu/drm/savage/savage_bci.c kfree(dev_priv); dev_priv 677 drivers/gpu/drm/savage/savage_bci.c drm_savage_private_t *dev_priv = dev->dev_private; dev_priv 693 drivers/gpu/drm/savage/savage_bci.c dev_priv->cob_size = init->cob_size; dev_priv 694 drivers/gpu/drm/savage/savage_bci.c dev_priv->bci_threshold_lo = init->bci_threshold_lo; dev_priv 695 drivers/gpu/drm/savage/savage_bci.c dev_priv->bci_threshold_hi = init->bci_threshold_hi; dev_priv 696 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_type = init->dma_type; dev_priv 698 drivers/gpu/drm/savage/savage_bci.c dev_priv->fb_bpp = init->fb_bpp; dev_priv 699 drivers/gpu/drm/savage/savage_bci.c dev_priv->front_offset = init->front_offset; dev_priv 700 drivers/gpu/drm/savage/savage_bci.c dev_priv->front_pitch = init->front_pitch; dev_priv 701 drivers/gpu/drm/savage/savage_bci.c dev_priv->back_offset = init->back_offset; dev_priv 702 drivers/gpu/drm/savage/savage_bci.c dev_priv->back_pitch = init->back_pitch; dev_priv 703 drivers/gpu/drm/savage/savage_bci.c dev_priv->depth_bpp = init->depth_bpp; dev_priv 704 drivers/gpu/drm/savage/savage_bci.c dev_priv->depth_offset = init->depth_offset; dev_priv 705 drivers/gpu/drm/savage/savage_bci.c dev_priv->depth_pitch = init->depth_pitch; dev_priv 707 drivers/gpu/drm/savage/savage_bci.c dev_priv->texture_offset = init->texture_offset; dev_priv 708 drivers/gpu/drm/savage/savage_bci.c dev_priv->texture_size = init->texture_size; dev_priv 710 drivers/gpu/drm/savage/savage_bci.c dev_priv->sarea = drm_legacy_getsarea(dev); dev_priv 711 drivers/gpu/drm/savage/savage_bci.c if (!dev_priv->sarea) { dev_priv 717 drivers/gpu/drm/savage/savage_bci.c dev_priv->status = drm_legacy_findmap(dev, init->status_offset); dev_priv 718 drivers/gpu/drm/savage/savage_bci.c if (!dev_priv->status) { dev_priv 724 drivers/gpu/drm/savage/savage_bci.c dev_priv->status = NULL; dev_priv 726 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) { dev_priv 743 drivers/gpu/drm/savage/savage_bci.c dev_priv->agp_textures = dev_priv 745 drivers/gpu/drm/savage/savage_bci.c if (!dev_priv->agp_textures) { dev_priv 751 drivers/gpu/drm/savage/savage_bci.c dev_priv->agp_textures = NULL; dev_priv 755 drivers/gpu/drm/savage/savage_bci.c if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { dev_priv 767 drivers/gpu/drm/savage/savage_bci.c dev_priv->cmd_dma = drm_legacy_findmap(dev, init->cmd_dma_offset); dev_priv 768 drivers/gpu/drm/savage/savage_bci.c if (!dev_priv->cmd_dma) { dev_priv 773 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->dma_type == SAVAGE_DMA_AGP) { dev_priv 774 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->cmd_dma->type != _DRM_AGP) { dev_priv 780 drivers/gpu/drm/savage/savage_bci.c drm_legacy_ioremap(dev_priv->cmd_dma, dev); dev_priv 781 drivers/gpu/drm/savage/savage_bci.c if (!dev_priv->cmd_dma->handle) { dev_priv 787 drivers/gpu/drm/savage/savage_bci.c } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) { dev_priv 794 drivers/gpu/drm/savage/savage_bci.c dev_priv->cmd_dma = NULL; dev_priv 797 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_flush = savage_dma_flush; dev_priv 798 drivers/gpu/drm/savage/savage_bci.c if (!dev_priv->cmd_dma) { dev_priv 800 drivers/gpu/drm/savage/savage_bci.c dev_priv->fake_dma.offset = 0; dev_priv 801 drivers/gpu/drm/savage/savage_bci.c dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE; dev_priv 802 drivers/gpu/drm/savage/savage_bci.c dev_priv->fake_dma.type = _DRM_SHM; dev_priv 803 drivers/gpu/drm/savage/savage_bci.c dev_priv->fake_dma.handle = kmalloc(SAVAGE_FAKE_DMA_SIZE, dev_priv 805 drivers/gpu/drm/savage/savage_bci.c if (!dev_priv->fake_dma.handle) { dev_priv 810 drivers/gpu/drm/savage/savage_bci.c dev_priv->cmd_dma = &dev_priv->fake_dma; dev_priv 811 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_flush = savage_fake_dma_flush; dev_priv 814 drivers/gpu/drm/savage/savage_bci.c dev_priv->sarea_priv = dev_priv 815 drivers/gpu/drm/savage/savage_bci.c (drm_savage_sarea_t *) ((uint8_t *) dev_priv->sarea->handle + dev_priv 823 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->chipset <= S3_SAVAGE4) { dev_priv 824 drivers/gpu/drm/savage/savage_bci.c color_tile_format = dev_priv->fb_bpp == 16 ? dev_priv 826 drivers/gpu/drm/savage/savage_bci.c depth_tile_format = dev_priv->depth_bpp == 16 ? dev_priv 832 drivers/gpu/drm/savage/savage_bci.c front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8); dev_priv 833 drivers/gpu/drm/savage/savage_bci.c back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8); dev_priv 835 drivers/gpu/drm/savage/savage_bci.c dev_priv->depth_pitch / (dev_priv->depth_bpp / 8); dev_priv 837 drivers/gpu/drm/savage/savage_bci.c dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE | dev_priv 838 drivers/gpu/drm/savage/savage_bci.c (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | dev_priv 841 drivers/gpu/drm/savage/savage_bci.c dev_priv->back_bd = back_stride | SAVAGE_BD_BW_DISABLE | dev_priv 842 drivers/gpu/drm/savage/savage_bci.c (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | dev_priv 845 drivers/gpu/drm/savage/savage_bci.c dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE | dev_priv 846 drivers/gpu/drm/savage/savage_bci.c (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) | dev_priv 851 drivers/gpu/drm/savage/savage_bci.c dev_priv->event_counter = 0; dev_priv 852 drivers/gpu/drm/savage/savage_bci.c dev_priv->event_wrap = 0; dev_priv 853 drivers/gpu/drm/savage/savage_bci.c dev_priv->bci_ptr = (volatile uint32_t *) dev_priv 854 drivers/gpu/drm/savage/savage_bci.c ((uint8_t *) dev_priv->mmio->handle + SAVAGE_BCI_OFFSET); dev_priv 855 drivers/gpu/drm/savage/savage_bci.c if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { dev_priv 856 drivers/gpu/drm/savage/savage_bci.c dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D; dev_priv 858 drivers/gpu/drm/savage/savage_bci.c dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4; dev_priv 860 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->status != NULL) { dev_priv 861 drivers/gpu/drm/savage/savage_bci.c dev_priv->status_ptr = dev_priv 862 drivers/gpu/drm/savage/savage_bci.c (volatile uint32_t *)dev_priv->status->handle; dev_priv 863 drivers/gpu/drm/savage/savage_bci.c dev_priv->wait_fifo = savage_bci_wait_fifo_shadow; dev_priv 864 drivers/gpu/drm/savage/savage_bci.c dev_priv->wait_evnt = savage_bci_wait_event_shadow; dev_priv 865 drivers/gpu/drm/savage/savage_bci.c dev_priv->status_ptr[1023] = dev_priv->event_counter; dev_priv 867 drivers/gpu/drm/savage/savage_bci.c dev_priv->status_ptr = NULL; dev_priv 868 drivers/gpu/drm/savage/savage_bci.c if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { dev_priv 869 drivers/gpu/drm/savage/savage_bci.c dev_priv->wait_fifo = savage_bci_wait_fifo_s3d; dev_priv 871 drivers/gpu/drm/savage/savage_bci.c dev_priv->wait_fifo = savage_bci_wait_fifo_s4; dev_priv 873 drivers/gpu/drm/savage/savage_bci.c dev_priv->wait_evnt = savage_bci_wait_event_reg; dev_priv 877 drivers/gpu/drm/savage/savage_bci.c if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) dev_priv 878 drivers/gpu/drm/savage/savage_bci.c dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d; dev_priv 880 drivers/gpu/drm/savage/savage_bci.c dev_priv->emit_clip_rect = savage_emit_clip_rect_s4; dev_priv 888 drivers/gpu/drm/savage/savage_bci.c if (savage_dma_init(dev_priv) < 0) { dev_priv 899 drivers/gpu/drm/savage/savage_bci.c drm_savage_private_t *dev_priv = dev->dev_private; dev_priv 901 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->cmd_dma == &dev_priv->fake_dma) { dev_priv 902 drivers/gpu/drm/savage/savage_bci.c kfree(dev_priv->fake_dma.handle); dev_priv 903 drivers/gpu/drm/savage/savage_bci.c } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle && dev_priv 904 drivers/gpu/drm/savage/savage_bci.c dev_priv->cmd_dma->type == _DRM_AGP && dev_priv 905 drivers/gpu/drm/savage/savage_bci.c dev_priv->dma_type == SAVAGE_DMA_AGP) dev_priv 906 drivers/gpu/drm/savage/savage_bci.c drm_legacy_ioremapfree(dev_priv->cmd_dma, dev); dev_priv 908 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->dma_type == SAVAGE_DMA_AGP && dev_priv 917 drivers/gpu/drm/savage/savage_bci.c kfree(dev_priv->dma_pages); dev_priv 940 drivers/gpu/drm/savage/savage_bci.c drm_savage_private_t *dev_priv = dev->dev_private; dev_priv 947 drivers/gpu/drm/savage/savage_bci.c event->count = savage_bci_emit_event(dev_priv, event->flags); dev_priv 948 drivers/gpu/drm/savage/savage_bci.c event->count |= dev_priv->event_wrap << 16; dev_priv 955 drivers/gpu/drm/savage/savage_bci.c drm_savage_private_t *dev_priv = dev->dev_private; dev_priv 963 drivers/gpu/drm/savage/savage_bci.c if (dev_priv->status_ptr) dev_priv 964 drivers/gpu/drm/savage/savage_bci.c hw_e = dev_priv->status_ptr[1] & 0xffff; dev_priv 967 drivers/gpu/drm/savage/savage_bci.c hw_w = dev_priv->event_wrap; dev_priv 968 drivers/gpu/drm/savage/savage_bci.c if (hw_e > dev_priv->event_counter) dev_priv 981 drivers/gpu/drm/savage/savage_bci.c return dev_priv->wait_evnt(dev_priv, event_e); dev_priv 1050 drivers/gpu/drm/savage/savage_bci.c drm_savage_private_t *dev_priv = dev->dev_private; dev_priv 1056 drivers/gpu/drm/savage/savage_bci.c if (!dev_priv) dev_priv 1074 drivers/gpu/drm/savage/savage_bci.c event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D); dev_priv 1075 drivers/gpu/drm/savage/savage_bci.c SET_AGE(&buf_priv->age, event, dev_priv->event_wrap); dev_priv 193 drivers/gpu/drm/savage/savage_drv.h int (*wait_fifo) (struct drm_savage_private * dev_priv, unsigned int n); dev_priv 194 drivers/gpu/drm/savage/savage_drv.h int (*wait_evnt) (struct drm_savage_private * dev_priv, uint16_t e); dev_priv 197 drivers/gpu/drm/savage/savage_drv.h void (*emit_clip_rect) (struct drm_savage_private * dev_priv, dev_priv 199 drivers/gpu/drm/savage/savage_drv.h void (*dma_flush) (struct drm_savage_private * dev_priv); dev_priv 207 drivers/gpu/drm/savage/savage_drv.h extern uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv, dev_priv 210 drivers/gpu/drm/savage/savage_drv.h extern void savage_dma_reset(drm_savage_private_t * dev_priv); dev_priv 211 drivers/gpu/drm/savage/savage_drv.h extern void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page); dev_priv 212 drivers/gpu/drm/savage/savage_drv.h extern uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, dev_priv 222 drivers/gpu/drm/savage/savage_drv.h extern void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv, dev_priv 224 drivers/gpu/drm/savage/savage_drv.h extern void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv, dev_priv 492 drivers/gpu/drm/savage/savage_drv.h readl(((void __iomem *)dev_priv->mmio->handle) + (reg)) dev_priv 494 drivers/gpu/drm/savage/savage_drv.h writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) dev_priv 504 drivers/gpu/drm/savage/savage_drv.h dev_priv->wait_fifo(dev_priv, (n)); \ dev_priv 505 drivers/gpu/drm/savage/savage_drv.h bci_ptr = dev_priv->bci_ptr; \ dev_priv 518 drivers/gpu/drm/savage/savage_drv.h unsigned int cur = dev_priv->current_dma_page; \ dev_priv 520 drivers/gpu/drm/savage/savage_drv.h dev_priv->dma_pages[cur].used; \ dev_priv 522 drivers/gpu/drm/savage/savage_drv.h dma_ptr = savage_dma_alloc(dev_priv, (n)); \ dev_priv 524 drivers/gpu/drm/savage/savage_drv.h dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \ dev_priv 526 drivers/gpu/drm/savage/savage_drv.h dev_priv->dma_pages[cur].used; \ dev_priv 527 drivers/gpu/drm/savage/savage_drv.h if (dev_priv->dma_pages[cur].used == 0) \ dev_priv 528 drivers/gpu/drm/savage/savage_drv.h savage_dma_wait(dev_priv, cur); \ dev_priv 529 drivers/gpu/drm/savage/savage_drv.h dev_priv->dma_pages[cur].used += (n); \ dev_priv 542 drivers/gpu/drm/savage/savage_drv.h unsigned int cur = dev_priv->current_dma_page; \ dev_priv 543 drivers/gpu/drm/savage/savage_drv.h uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \ dev_priv 545 drivers/gpu/drm/savage/savage_drv.h dev_priv->dma_pages[cur].used; \ dev_priv 549 drivers/gpu/drm/savage/savage_drv.h savage_dma_reset(dev_priv); \ dev_priv 556 drivers/gpu/drm/savage/savage_drv.h #define DMA_FLUSH() dev_priv->dma_flush(dev_priv) dev_priv 562 drivers/gpu/drm/savage/savage_drv.h if (dev_priv->status_ptr) { \ dev_priv 565 drivers/gpu/drm/savage/savage_drv.h count = dev_priv->status_ptr[1023]; \ dev_priv 566 drivers/gpu/drm/savage/savage_drv.h if (count < dev_priv->event_counter) \ dev_priv 567 drivers/gpu/drm/savage/savage_drv.h dev_priv->event_wrap++; \ dev_priv 568 drivers/gpu/drm/savage/savage_drv.h dev_priv->event_counter = count; \ dev_priv 36 drivers/gpu/drm/savage/savage_state.c void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv, dev_priv 39 drivers/gpu/drm/savage/savage_state.c uint32_t scstart = dev_priv->state.s3d.new_scstart; dev_priv 40 drivers/gpu/drm/savage/savage_state.c uint32_t scend = dev_priv->state.s3d.new_scend; dev_priv 47 drivers/gpu/drm/savage/savage_state.c if (scstart != dev_priv->state.s3d.scstart || dev_priv 48 drivers/gpu/drm/savage/savage_state.c scend != dev_priv->state.s3d.scend) { dev_priv 55 drivers/gpu/drm/savage/savage_state.c dev_priv->state.s3d.scstart = scstart; dev_priv 56 drivers/gpu/drm/savage/savage_state.c dev_priv->state.s3d.scend = scend; dev_priv 57 drivers/gpu/drm/savage/savage_state.c dev_priv->waiting = 1; dev_priv 62 drivers/gpu/drm/savage/savage_state.c void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv, dev_priv 65 drivers/gpu/drm/savage/savage_state.c uint32_t drawctrl0 = dev_priv->state.s4.new_drawctrl0; dev_priv 66 drivers/gpu/drm/savage/savage_state.c uint32_t drawctrl1 = dev_priv->state.s4.new_drawctrl1; dev_priv 73 drivers/gpu/drm/savage/savage_state.c if (drawctrl0 != dev_priv->state.s4.drawctrl0 || dev_priv 74 drivers/gpu/drm/savage/savage_state.c drawctrl1 != dev_priv->state.s4.drawctrl1) { dev_priv 81 drivers/gpu/drm/savage/savage_state.c dev_priv->state.s4.drawctrl0 = drawctrl0; dev_priv 82 drivers/gpu/drm/savage/savage_state.c dev_priv->state.s4.drawctrl1 = drawctrl1; dev_priv 83 drivers/gpu/drm/savage/savage_state.c dev_priv->waiting = 1; dev_priv 88 drivers/gpu/drm/savage/savage_state.c static int savage_verify_texaddr(drm_savage_private_t * dev_priv, int unit, dev_priv 97 drivers/gpu/drm/savage/savage_state.c if (addr < dev_priv->texture_offset || dev_priv 98 drivers/gpu/drm/savage/savage_state.c addr >= dev_priv->texture_offset + dev_priv->texture_size) { dev_priv 105 drivers/gpu/drm/savage/savage_state.c if (!dev_priv->agp_textures) { dev_priv 111 drivers/gpu/drm/savage/savage_state.c if (addr < dev_priv->agp_textures->offset || dev_priv 112 drivers/gpu/drm/savage/savage_state.c addr >= (dev_priv->agp_textures->offset + dev_priv 113 drivers/gpu/drm/savage/savage_state.c dev_priv->agp_textures->size)) { dev_priv 125 drivers/gpu/drm/savage/savage_state.c dev_priv->state.where = regs[reg - start] dev_priv 130 drivers/gpu/drm/savage/savage_state.c dev_priv->state.where = (tmp & (mask)) | \ dev_priv 131 drivers/gpu/drm/savage/savage_state.c (dev_priv->state.where & ~(mask)); \ dev_priv 135 drivers/gpu/drm/savage/savage_state.c static int savage_verify_state_s3d(drm_savage_private_t * dev_priv, dev_priv 157 drivers/gpu/drm/savage/savage_state.c if (dev_priv->state.s3d.texctrl & SAVAGE_TEXCTRL_TEXEN_MASK) dev_priv 158 drivers/gpu/drm/savage/savage_state.c return savage_verify_texaddr(dev_priv, 0, dev_priv 159 drivers/gpu/drm/savage/savage_state.c dev_priv->state.s3d.texaddr); dev_priv 165 drivers/gpu/drm/savage/savage_state.c static int savage_verify_state_s4(drm_savage_private_t * dev_priv, dev_priv 190 drivers/gpu/drm/savage/savage_state.c if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX0EN_MASK) dev_priv 191 drivers/gpu/drm/savage/savage_state.c ret |= savage_verify_texaddr(dev_priv, 0, dev_priv 192 drivers/gpu/drm/savage/savage_state.c dev_priv->state.s4.texaddr0); dev_priv 193 drivers/gpu/drm/savage/savage_state.c if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX1EN_MASK) dev_priv 194 drivers/gpu/drm/savage/savage_state.c ret |= savage_verify_texaddr(dev_priv, 1, dev_priv 195 drivers/gpu/drm/savage/savage_state.c dev_priv->state.s4.texaddr1); dev_priv 204 drivers/gpu/drm/savage/savage_state.c static int savage_dispatch_state(drm_savage_private_t * dev_priv, dev_priv 218 drivers/gpu/drm/savage/savage_state.c if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { dev_priv 219 drivers/gpu/drm/savage/savage_state.c ret = savage_verify_state_s3d(dev_priv, start, count, regs); dev_priv 236 drivers/gpu/drm/savage/savage_state.c ret = savage_verify_state_s4(dev_priv, start, count, regs); dev_priv 260 drivers/gpu/drm/savage/savage_state.c dev_priv->waiting = 1; dev_priv 285 drivers/gpu/drm/savage/savage_state.c static int savage_dispatch_dma_prim(drm_savage_private_t * dev_priv, dev_priv 331 drivers/gpu/drm/savage/savage_state.c if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { dev_priv 361 drivers/gpu/drm/savage/savage_state.c if (dmabuf->bus_address != dev_priv->state.common.vbaddr) { dev_priv 364 drivers/gpu/drm/savage/savage_state.c BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type); dev_priv 365 drivers/gpu/drm/savage/savage_state.c dev_priv->state.common.vbaddr = dmabuf->bus_address; dev_priv 367 drivers/gpu/drm/savage/savage_state.c if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) { dev_priv 376 drivers/gpu/drm/savage/savage_state.c dev_priv->waiting = 0; dev_priv 399 drivers/gpu/drm/savage/savage_state.c } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { dev_priv 426 drivers/gpu/drm/savage/savage_state.c static int savage_dispatch_vb_prim(drm_savage_private_t * dev_priv, dev_priv 469 drivers/gpu/drm/savage/savage_state.c if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { dev_priv 545 drivers/gpu/drm/savage/savage_state.c static int savage_dispatch_dma_idx(drm_savage_private_t * dev_priv, dev_priv 589 drivers/gpu/drm/savage/savage_state.c if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { dev_priv 613 drivers/gpu/drm/savage/savage_state.c if (dmabuf->bus_address != dev_priv->state.common.vbaddr) { dev_priv 616 drivers/gpu/drm/savage/savage_state.c BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type); dev_priv 617 drivers/gpu/drm/savage/savage_state.c dev_priv->state.common.vbaddr = dmabuf->bus_address; dev_priv 619 drivers/gpu/drm/savage/savage_state.c if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) { dev_priv 628 drivers/gpu/drm/savage/savage_state.c dev_priv->waiting = 0; dev_priv 660 drivers/gpu/drm/savage/savage_state.c } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { dev_priv 687 drivers/gpu/drm/savage/savage_state.c static int savage_dispatch_vb_idx(drm_savage_private_t * dev_priv, dev_priv 728 drivers/gpu/drm/savage/savage_state.c if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { dev_priv 802 drivers/gpu/drm/savage/savage_state.c static int savage_dispatch_clear(drm_savage_private_t * dev_priv, dev_priv 845 drivers/gpu/drm/savage/savage_state.c DMA_WRITE(dev_priv->front_offset); dev_priv 846 drivers/gpu/drm/savage/savage_state.c DMA_WRITE(dev_priv->front_bd); dev_priv 849 drivers/gpu/drm/savage/savage_state.c DMA_WRITE(dev_priv->back_offset); dev_priv 850 drivers/gpu/drm/savage/savage_state.c DMA_WRITE(dev_priv->back_bd); dev_priv 853 drivers/gpu/drm/savage/savage_state.c DMA_WRITE(dev_priv->depth_offset); dev_priv 854 drivers/gpu/drm/savage/savage_state.c DMA_WRITE(dev_priv->depth_bd); dev_priv 874 drivers/gpu/drm/savage/savage_state.c static int savage_dispatch_swap(drm_savage_private_t * dev_priv, dev_priv 891 drivers/gpu/drm/savage/savage_state.c DMA_WRITE(dev_priv->back_offset); dev_priv 892 drivers/gpu/drm/savage/savage_state.c DMA_WRITE(dev_priv->back_bd); dev_priv 903 drivers/gpu/drm/savage/savage_state.c static int savage_dispatch_draw(drm_savage_private_t * dev_priv, dev_priv 917 drivers/gpu/drm/savage/savage_state.c dev_priv->emit_clip_rect(dev_priv, &boxes[i]); dev_priv 927 drivers/gpu/drm/savage/savage_state.c dev_priv, &cmd_header, dmabuf); dev_priv 931 drivers/gpu/drm/savage/savage_state.c dev_priv, &cmd_header, dev_priv 937 drivers/gpu/drm/savage/savage_state.c ret = savage_dispatch_dma_idx(dev_priv, dev_priv 945 drivers/gpu/drm/savage/savage_state.c ret = savage_dispatch_vb_idx(dev_priv, dev_priv 969 drivers/gpu/drm/savage/savage_state.c drm_savage_private_t *dev_priv = dev->dev_private; dev_priv 1045 drivers/gpu/drm/savage/savage_state.c dev_priv->waiting = 1; dev_priv 1080 drivers/gpu/drm/savage/savage_state.c dev_priv, first_draw_cmd, dev_priv 1103 drivers/gpu/drm/savage/savage_state.c ret = savage_dispatch_state(dev_priv, &cmd_header, dev_priv 1116 drivers/gpu/drm/savage/savage_state.c ret = savage_dispatch_clear(dev_priv, &cmd_header, dev_priv 1124 drivers/gpu/drm/savage/savage_state.c ret = savage_dispatch_swap(dev_priv, cmdbuf->nbox, dev_priv 1143 drivers/gpu/drm/savage/savage_state.c dev_priv, first_draw_cmd, cmdbuf->cmd_addr, dmabuf, dev_priv 1157 drivers/gpu/drm/savage/savage_state.c event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D); dev_priv 1158 drivers/gpu/drm/savage/savage_state.c SET_AGE(&buf_priv->age, event, dev_priv->event_wrap); dev_priv 44 drivers/gpu/drm/sis/sis_drv.c drm_sis_private_t *dev_priv; dev_priv 48 drivers/gpu/drm/sis/sis_drv.c dev_priv = kzalloc(sizeof(drm_sis_private_t), GFP_KERNEL); dev_priv 49 drivers/gpu/drm/sis/sis_drv.c if (dev_priv == NULL) dev_priv 52 drivers/gpu/drm/sis/sis_drv.c idr_init(&dev_priv->object_idr); dev_priv 53 drivers/gpu/drm/sis/sis_drv.c dev->dev_private = (void *)dev_priv; dev_priv 54 drivers/gpu/drm/sis/sis_drv.c dev_priv->chipset = chipset; dev_priv 61 drivers/gpu/drm/sis/sis_drv.c drm_sis_private_t *dev_priv = dev->dev_private; dev_priv 63 drivers/gpu/drm/sis/sis_drv.c idr_destroy(&dev_priv->object_idr); dev_priv 65 drivers/gpu/drm/sis/sis_drv.c kfree(dev_priv); dev_priv 51 drivers/gpu/drm/sis/sis_drv.h #define SIS_READ(reg) readl(((void __iomem *)dev_priv->mmio->handle) + (reg)) dev_priv 52 drivers/gpu/drm/sis/sis_drv.h #define SIS_WRITE(reg, val) writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) dev_priv 68 drivers/gpu/drm/sis/sis_mm.c drm_sis_private_t *dev_priv = dev->dev_private; dev_priv 74 drivers/gpu/drm/sis/sis_mm.c drm_mm_init(&dev_priv->vram_mm, 0, fb->size >> SIS_MM_ALIGN_SHIFT); dev_priv 76 drivers/gpu/drm/sis/sis_mm.c dev_priv->vram_initialized = 1; dev_priv 77 drivers/gpu/drm/sis/sis_mm.c dev_priv->vram_offset = fb->offset; dev_priv 88 drivers/gpu/drm/sis/sis_mm.c drm_sis_private_t *dev_priv = dev->dev_private; dev_priv 97 drivers/gpu/drm/sis/sis_mm.c if (0 == ((pool == 0) ? dev_priv->vram_initialized : dev_priv 98 drivers/gpu/drm/sis/sis_mm.c dev_priv->agp_initialized)) { dev_priv 113 drivers/gpu/drm/sis/sis_mm.c retval = drm_mm_insert_node(&dev_priv->agp_mm, dev_priv 125 drivers/gpu/drm/sis/sis_mm.c retval = drm_mm_insert_node(&dev_priv->vram_mm, dev_priv 134 drivers/gpu/drm/sis/sis_mm.c retval = idr_alloc(&dev_priv->object_idr, item, 1, 0, GFP_KERNEL); dev_priv 143 drivers/gpu/drm/sis/sis_mm.c dev_priv->vram_offset : dev_priv->agp_offset) + dev_priv 168 drivers/gpu/drm/sis/sis_mm.c drm_sis_private_t *dev_priv = dev->dev_private; dev_priv 173 drivers/gpu/drm/sis/sis_mm.c obj = idr_find(&dev_priv->object_idr, mem->free); dev_priv 179 drivers/gpu/drm/sis/sis_mm.c idr_remove(&dev_priv->object_idr, mem->free); dev_priv 203 drivers/gpu/drm/sis/sis_mm.c drm_sis_private_t *dev_priv = dev->dev_private; dev_priv 205 drivers/gpu/drm/sis/sis_mm.c dev_priv = dev->dev_private; dev_priv 208 drivers/gpu/drm/sis/sis_mm.c drm_mm_init(&dev_priv->agp_mm, 0, agp->size >> SIS_MM_ALIGN_SHIFT); dev_priv 210 drivers/gpu/drm/sis/sis_mm.c dev_priv->agp_initialized = 1; dev_priv 211 drivers/gpu/drm/sis/sis_mm.c dev_priv->agp_offset = agp->offset; dev_priv 242 drivers/gpu/drm/sis/sis_mm.c drm_sis_private_t *dev_priv = dev->dev_private; dev_priv 247 drivers/gpu/drm/sis/sis_mm.c if (dev_priv->idle_fault) dev_priv 250 drivers/gpu/drm/sis/sis_mm.c if (dev_priv->mmio == NULL) { dev_priv 251 drivers/gpu/drm/sis/sis_mm.c dev_priv->mmio = sis_reg_init(dev); dev_priv 252 drivers/gpu/drm/sis/sis_mm.c if (dev_priv->mmio == NULL) { dev_priv 262 drivers/gpu/drm/sis/sis_mm.c if (dev_priv->chipset != SIS_CHIP_315) dev_priv 282 drivers/gpu/drm/sis/sis_mm.c dev_priv->idle_fault = 1; dev_priv 296 drivers/gpu/drm/sis/sis_mm.c drm_sis_private_t *dev_priv = dev->dev_private; dev_priv 298 drivers/gpu/drm/sis/sis_mm.c if (!dev_priv) dev_priv 302 drivers/gpu/drm/sis/sis_mm.c if (dev_priv->vram_initialized) { dev_priv 303 drivers/gpu/drm/sis/sis_mm.c drm_mm_takedown(&dev_priv->vram_mm); dev_priv 304 drivers/gpu/drm/sis/sis_mm.c dev_priv->vram_initialized = 0; dev_priv 306 drivers/gpu/drm/sis/sis_mm.c if (dev_priv->agp_initialized) { dev_priv 307 drivers/gpu/drm/sis/sis_mm.c drm_mm_takedown(&dev_priv->agp_mm); dev_priv 308 drivers/gpu/drm/sis/sis_mm.c dev_priv->agp_initialized = 0; dev_priv 310 drivers/gpu/drm/sis/sis_mm.c dev_priv->mmio = NULL; dev_priv 68 drivers/gpu/drm/sti/sti_compositor.c struct sti_private *dev_priv = drm_dev->dev_private; dev_priv 74 drivers/gpu/drm/sti/sti_compositor.c dev_priv->compo = compo; dev_priv 284 drivers/gpu/drm/sti/sti_crtc.c struct sti_private *dev_priv = dev->dev_private; dev_priv 285 drivers/gpu/drm/sti/sti_crtc.c struct sti_compositor *compo = dev_priv->compo; dev_priv 67 drivers/gpu/drm/via/via_dma.c dev_priv->dma_low += 8; \ dev_priv 75 drivers/gpu/drm/via/via_dma.c dev_priv->dma_low += 8; \ dev_priv 78 drivers/gpu/drm/via/via_dma.c static void via_cmdbuf_start(drm_via_private_t *dev_priv); dev_priv 79 drivers/gpu/drm/via/via_dma.c static void via_cmdbuf_pause(drm_via_private_t *dev_priv); dev_priv 80 drivers/gpu/drm/via/via_dma.c static void via_cmdbuf_reset(drm_via_private_t *dev_priv); dev_priv 81 drivers/gpu/drm/via/via_dma.c static void via_cmdbuf_rewind(drm_via_private_t *dev_priv); dev_priv 82 drivers/gpu/drm/via/via_dma.c static int via_wait_idle(drm_via_private_t *dev_priv); dev_priv 83 drivers/gpu/drm/via/via_dma.c static void via_pad_cache(drm_via_private_t *dev_priv, int qwords); dev_priv 89 drivers/gpu/drm/via/via_dma.c static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv) dev_priv 91 drivers/gpu/drm/via/via_dma.c uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; dev_priv 92 drivers/gpu/drm/via/via_dma.c uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; dev_priv 94 drivers/gpu/drm/via/via_dma.c return ((hw_addr <= dev_priv->dma_low) ? dev_priv 95 drivers/gpu/drm/via/via_dma.c (dev_priv->dma_high + hw_addr - dev_priv->dma_low) : dev_priv 96 drivers/gpu/drm/via/via_dma.c (hw_addr - dev_priv->dma_low)); dev_priv 103 drivers/gpu/drm/via/via_dma.c static uint32_t via_cmdbuf_lag(drm_via_private_t *dev_priv) dev_priv 105 drivers/gpu/drm/via/via_dma.c uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; dev_priv 106 drivers/gpu/drm/via/via_dma.c uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; dev_priv 108 drivers/gpu/drm/via/via_dma.c return ((hw_addr <= dev_priv->dma_low) ? dev_priv 109 drivers/gpu/drm/via/via_dma.c (dev_priv->dma_low - hw_addr) : dev_priv 110 drivers/gpu/drm/via/via_dma.c (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr)); dev_priv 118 drivers/gpu/drm/via/via_dma.c via_cmdbuf_wait(drm_via_private_t *dev_priv, unsigned int size) dev_priv 120 drivers/gpu/drm/via/via_dma.c uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; dev_priv 124 drivers/gpu/drm/via/via_dma.c hw_addr_ptr = dev_priv->hw_addr_ptr; dev_priv 125 drivers/gpu/drm/via/via_dma.c cur_addr = dev_priv->dma_low; dev_priv 149 drivers/gpu/drm/via/via_dma.c static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv, dev_priv 152 drivers/gpu/drm/via/via_dma.c if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) > dev_priv 153 drivers/gpu/drm/via/via_dma.c dev_priv->dma_high) { dev_priv 154 drivers/gpu/drm/via/via_dma.c via_cmdbuf_rewind(dev_priv); dev_priv 156 drivers/gpu/drm/via/via_dma.c if (via_cmdbuf_wait(dev_priv, size) != 0) dev_priv 159 drivers/gpu/drm/via/via_dma.c return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); dev_priv 165 drivers/gpu/drm/via/via_dma.c drm_via_private_t *dev_priv = dev_priv 168 drivers/gpu/drm/via/via_dma.c if (dev_priv->ring.virtual_start) { dev_priv 169 drivers/gpu/drm/via/via_dma.c via_cmdbuf_reset(dev_priv); dev_priv 171 drivers/gpu/drm/via/via_dma.c drm_legacy_ioremapfree(&dev_priv->ring.map, dev); dev_priv 172 drivers/gpu/drm/via/via_dma.c dev_priv->ring.virtual_start = NULL; dev_priv 181 drivers/gpu/drm/via/via_dma.c drm_via_private_t *dev_priv, dev_priv 184 drivers/gpu/drm/via/via_dma.c if (!dev_priv || !dev_priv->mmio) { dev_priv 189 drivers/gpu/drm/via/via_dma.c if (dev_priv->ring.virtual_start != NULL) { dev_priv 199 drivers/gpu/drm/via/via_dma.c if (dev_priv->chipset == VIA_DX9_0) { dev_priv 204 drivers/gpu/drm/via/via_dma.c dev_priv->ring.map.offset = dev->agp->base + init->offset; dev_priv 205 drivers/gpu/drm/via/via_dma.c dev_priv->ring.map.size = init->size; dev_priv 206 drivers/gpu/drm/via/via_dma.c dev_priv->ring.map.type = 0; dev_priv 207 drivers/gpu/drm/via/via_dma.c dev_priv->ring.map.flags = 0; dev_priv 208 drivers/gpu/drm/via/via_dma.c dev_priv->ring.map.mtrr = 0; dev_priv 210 drivers/gpu/drm/via/via_dma.c drm_legacy_ioremap(&dev_priv->ring.map, dev); dev_priv 212 drivers/gpu/drm/via/via_dma.c if (dev_priv->ring.map.handle == NULL) { dev_priv 219 drivers/gpu/drm/via/via_dma.c dev_priv->ring.virtual_start = dev_priv->ring.map.handle; dev_priv 221 drivers/gpu/drm/via/via_dma.c dev_priv->dma_ptr = dev_priv->ring.virtual_start; dev_priv 222 drivers/gpu/drm/via/via_dma.c dev_priv->dma_low = 0; dev_priv 223 drivers/gpu/drm/via/via_dma.c dev_priv->dma_high = init->size; dev_priv 224 drivers/gpu/drm/via/via_dma.c dev_priv->dma_wrap = init->size; dev_priv 225 drivers/gpu/drm/via/via_dma.c dev_priv->dma_offset = init->offset; dev_priv 226 drivers/gpu/drm/via/via_dma.c dev_priv->last_pause_ptr = NULL; dev_priv 227 drivers/gpu/drm/via/via_dma.c dev_priv->hw_addr_ptr = dev_priv 228 drivers/gpu/drm/via/via_dma.c (volatile uint32_t *)((char *)dev_priv->mmio->handle + dev_priv 231 drivers/gpu/drm/via/via_dma.c via_cmdbuf_start(dev_priv); dev_priv 238 drivers/gpu/drm/via/via_dma.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 247 drivers/gpu/drm/via/via_dma.c retcode = via_initialize(dev, dev_priv, init); dev_priv 256 drivers/gpu/drm/via/via_dma.c retcode = (dev_priv->ring.virtual_start != NULL) ? dev_priv 269 drivers/gpu/drm/via/via_dma.c drm_via_private_t *dev_priv; dev_priv 273 drivers/gpu/drm/via/via_dma.c dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 275 drivers/gpu/drm/via/via_dma.c if (dev_priv->ring.virtual_start == NULL) { dev_priv 283 drivers/gpu/drm/via/via_dma.c if (copy_from_user(dev_priv->pci_buf, cmd->buf, cmd->size)) dev_priv 293 drivers/gpu/drm/via/via_dma.c via_verify_command_stream((uint32_t *) dev_priv->pci_buf, dev_priv 298 drivers/gpu/drm/via/via_dma.c vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size); dev_priv 302 drivers/gpu/drm/via/via_dma.c memcpy(vb, dev_priv->pci_buf, cmd->size); dev_priv 304 drivers/gpu/drm/via/via_dma.c dev_priv->dma_low += cmd->size; dev_priv 312 drivers/gpu/drm/via/via_dma.c via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3); dev_priv 313 drivers/gpu/drm/via/via_dma.c via_cmdbuf_pause(dev_priv); dev_priv 320 drivers/gpu/drm/via/via_dma.c drm_via_private_t *dev_priv = dev->dev_private; dev_priv 322 drivers/gpu/drm/via/via_dma.c if (!via_wait_idle(dev_priv)) dev_priv 351 drivers/gpu/drm/via/via_dma.c drm_via_private_t *dev_priv = dev->dev_private; dev_priv 356 drivers/gpu/drm/via/via_dma.c if (copy_from_user(dev_priv->pci_buf, cmd->buf, cmd->size)) dev_priv 360 drivers/gpu/drm/via/via_dma.c via_verify_command_stream((uint32_t *) dev_priv->pci_buf, dev_priv 366 drivers/gpu/drm/via/via_dma.c via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf, dev_priv 384 drivers/gpu/drm/via/via_dma.c static inline uint32_t *via_align_buffer(drm_via_private_t *dev_priv, dev_priv 397 drivers/gpu/drm/via/via_dma.c static inline uint32_t *via_get_dma(drm_via_private_t *dev_priv) dev_priv 399 drivers/gpu/drm/via/via_dma.c return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); dev_priv 407 drivers/gpu/drm/via/via_dma.c static int via_hook_segment(drm_via_private_t *dev_priv, dev_priv 412 drivers/gpu/drm/via/via_dma.c volatile uint32_t *paused_at = dev_priv->last_pause_ptr; dev_priv 418 drivers/gpu/drm/via/via_dma.c (void) *(volatile uint32_t *)(via_get_dma(dev_priv) - 1); dev_priv 424 drivers/gpu/drm/via/via_dma.c reader = *(dev_priv->hw_addr_ptr); dev_priv 425 drivers/gpu/drm/via/via_dma.c ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) + dev_priv 426 drivers/gpu/drm/via/via_dma.c dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; dev_priv 428 drivers/gpu/drm/via/via_dma.c dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1; dev_priv 437 drivers/gpu/drm/via/via_dma.c diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff; dev_priv 440 drivers/gpu/drm/via/via_dma.c paused = (via_read(dev_priv, 0x41c) & 0x80000000); dev_priv 443 drivers/gpu/drm/via/via_dma.c reader = *(dev_priv->hw_addr_ptr); dev_priv 444 drivers/gpu/drm/via/via_dma.c diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff; dev_priv 447 drivers/gpu/drm/via/via_dma.c paused = via_read(dev_priv, 0x41c) & 0x80000000; dev_priv 450 drivers/gpu/drm/via/via_dma.c reader = *(dev_priv->hw_addr_ptr); dev_priv 451 drivers/gpu/drm/via/via_dma.c diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff; dev_priv 452 drivers/gpu/drm/via/via_dma.c diff &= (dev_priv->dma_high - 1); dev_priv 453 drivers/gpu/drm/via/via_dma.c if (diff != 0 && diff < (dev_priv->dma_high >> 1)) { dev_priv 456 drivers/gpu/drm/via/via_dma.c ptr, reader, dev_priv->dma_diff); dev_priv 464 drivers/gpu/drm/via/via_dma.c via_write(dev_priv, VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); dev_priv 465 drivers/gpu/drm/via/via_dma.c via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_hi); dev_priv 466 drivers/gpu/drm/via/via_dma.c via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_lo); dev_priv 467 drivers/gpu/drm/via/via_dma.c via_read(dev_priv, VIA_REG_TRANSPACE); dev_priv 473 drivers/gpu/drm/via/via_dma.c static int via_wait_idle(drm_via_private_t *dev_priv) dev_priv 477 drivers/gpu/drm/via/via_dma.c while (!(via_read(dev_priv, VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && --count) dev_priv 480 drivers/gpu/drm/via/via_dma.c while (count && (via_read(dev_priv, VIA_REG_STATUS) & dev_priv 487 drivers/gpu/drm/via/via_dma.c static uint32_t *via_align_cmd(drm_via_private_t *dev_priv, uint32_t cmd_type, dev_priv 497 drivers/gpu/drm/via/via_dma.c via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE); dev_priv 499 drivers/gpu/drm/via/via_dma.c vb = via_get_dma(dev_priv); dev_priv 502 drivers/gpu/drm/via/via_dma.c agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; dev_priv 504 drivers/gpu/drm/via/via_dma.c ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3); dev_priv 507 drivers/gpu/drm/via/via_dma.c agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3); dev_priv 512 drivers/gpu/drm/via/via_dma.c vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1); dev_priv 517 drivers/gpu/drm/via/via_dma.c static void via_cmdbuf_start(drm_via_private_t *dev_priv) dev_priv 528 drivers/gpu/drm/via/via_dma.c dev_priv->dma_low = 0; dev_priv 530 drivers/gpu/drm/via/via_dma.c agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; dev_priv 532 drivers/gpu/drm/via/via_dma.c end_addr = agp_base + dev_priv->dma_high; dev_priv 539 drivers/gpu/drm/via/via_dma.c dev_priv->last_pause_ptr = dev_priv 540 drivers/gpu/drm/via/via_dma.c via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, dev_priv 544 drivers/gpu/drm/via/via_dma.c (void) *(volatile uint32_t *)dev_priv->last_pause_ptr; dev_priv 546 drivers/gpu/drm/via/via_dma.c via_write(dev_priv, VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); dev_priv 547 drivers/gpu/drm/via/via_dma.c via_write(dev_priv, VIA_REG_TRANSPACE, command); dev_priv 548 drivers/gpu/drm/via/via_dma.c via_write(dev_priv, VIA_REG_TRANSPACE, start_addr_lo); dev_priv 549 drivers/gpu/drm/via/via_dma.c via_write(dev_priv, VIA_REG_TRANSPACE, end_addr_lo); dev_priv 551 drivers/gpu/drm/via/via_dma.c via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_hi); dev_priv 552 drivers/gpu/drm/via/via_dma.c via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_lo); dev_priv 554 drivers/gpu/drm/via/via_dma.c via_write(dev_priv, VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK); dev_priv 555 drivers/gpu/drm/via/via_dma.c via_read(dev_priv, VIA_REG_TRANSPACE); dev_priv 557 drivers/gpu/drm/via/via_dma.c dev_priv->dma_diff = 0; dev_priv 560 drivers/gpu/drm/via/via_dma.c while (!(via_read(dev_priv, 0x41c) & 0x80000000) && count--); dev_priv 562 drivers/gpu/drm/via/via_dma.c reader = *(dev_priv->hw_addr_ptr); dev_priv 563 drivers/gpu/drm/via/via_dma.c ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) + dev_priv 564 drivers/gpu/drm/via/via_dma.c dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; dev_priv 573 drivers/gpu/drm/via/via_dma.c dev_priv->dma_diff = ptr - reader; dev_priv 576 drivers/gpu/drm/via/via_dma.c static void via_pad_cache(drm_via_private_t *dev_priv, int qwords) dev_priv 580 drivers/gpu/drm/via/via_dma.c via_cmdbuf_wait(dev_priv, qwords + 2); dev_priv 581 drivers/gpu/drm/via/via_dma.c vb = via_get_dma(dev_priv); dev_priv 583 drivers/gpu/drm/via/via_dma.c via_align_buffer(dev_priv, vb, qwords); dev_priv 586 drivers/gpu/drm/via/via_dma.c static inline void via_dummy_bitblt(drm_via_private_t *dev_priv) dev_priv 588 drivers/gpu/drm/via/via_dma.c uint32_t *vb = via_get_dma(dev_priv); dev_priv 594 drivers/gpu/drm/via/via_dma.c static void via_cmdbuf_jump(drm_via_private_t *dev_priv) dev_priv 602 drivers/gpu/drm/via/via_dma.c agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; dev_priv 603 drivers/gpu/drm/via/via_dma.c via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi, dev_priv 606 drivers/gpu/drm/via/via_dma.c dev_priv->dma_wrap = dev_priv->dma_low; dev_priv 612 drivers/gpu/drm/via/via_dma.c dev_priv->dma_low = 0; dev_priv 613 drivers/gpu/drm/via/via_dma.c if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) dev_priv 616 drivers/gpu/drm/via/via_dma.c via_dummy_bitblt(dev_priv); dev_priv 617 drivers/gpu/drm/via/via_dma.c via_dummy_bitblt(dev_priv); dev_priv 620 drivers/gpu/drm/via/via_dma.c via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, dev_priv 622 drivers/gpu/drm/via/via_dma.c via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, dev_priv 626 drivers/gpu/drm/via/via_dma.c dma_low_save1 = dev_priv->dma_low; dev_priv 638 drivers/gpu/drm/via/via_dma.c via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, dev_priv 640 drivers/gpu/drm/via/via_dma.c via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, dev_priv 644 drivers/gpu/drm/via/via_dma.c dma_low_save2 = dev_priv->dma_low; dev_priv 645 drivers/gpu/drm/via/via_dma.c dev_priv->dma_low = dma_low_save1; dev_priv 646 drivers/gpu/drm/via/via_dma.c via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0); dev_priv 647 drivers/gpu/drm/via/via_dma.c dev_priv->dma_low = dma_low_save2; dev_priv 648 drivers/gpu/drm/via/via_dma.c via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0); dev_priv 652 drivers/gpu/drm/via/via_dma.c static void via_cmdbuf_rewind(drm_via_private_t *dev_priv) dev_priv 654 drivers/gpu/drm/via/via_dma.c via_cmdbuf_jump(dev_priv); dev_priv 657 drivers/gpu/drm/via/via_dma.c static void via_cmdbuf_flush(drm_via_private_t *dev_priv, uint32_t cmd_type) dev_priv 661 drivers/gpu/drm/via/via_dma.c via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0); dev_priv 662 drivers/gpu/drm/via/via_dma.c via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0); dev_priv 665 drivers/gpu/drm/via/via_dma.c static void via_cmdbuf_pause(drm_via_private_t *dev_priv) dev_priv 667 drivers/gpu/drm/via/via_dma.c via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE); dev_priv 670 drivers/gpu/drm/via/via_dma.c static void via_cmdbuf_reset(drm_via_private_t *dev_priv) dev_priv 672 drivers/gpu/drm/via/via_dma.c via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP); dev_priv 673 drivers/gpu/drm/via/via_dma.c via_wait_idle(dev_priv); dev_priv 685 drivers/gpu/drm/via/via_dma.c drm_via_private_t *dev_priv; dev_priv 690 drivers/gpu/drm/via/via_dma.c dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 692 drivers/gpu/drm/via/via_dma.c if (dev_priv->ring.virtual_start == NULL) { dev_priv 701 drivers/gpu/drm/via/via_dma.c while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz->size) dev_priv 712 drivers/gpu/drm/via/via_dma.c while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz->size) dev_priv 212 drivers/gpu/drm/via/via_dmablit.c drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; dev_priv 214 drivers/gpu/drm/via/via_dmablit.c via_write(dev_priv, VIA_PCI_DMA_MAR0 + engine*0x10, 0); dev_priv 215 drivers/gpu/drm/via/via_dmablit.c via_write(dev_priv, VIA_PCI_DMA_DAR0 + engine*0x10, 0); dev_priv 216 drivers/gpu/drm/via/via_dmablit.c via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD | dev_priv 218 drivers/gpu/drm/via/via_dmablit.c via_write(dev_priv, VIA_PCI_DMA_MR0 + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE); dev_priv 219 drivers/gpu/drm/via/via_dmablit.c via_write(dev_priv, VIA_PCI_DMA_BCR0 + engine*0x10, 0); dev_priv 220 drivers/gpu/drm/via/via_dmablit.c via_write(dev_priv, VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start); dev_priv 222 drivers/gpu/drm/via/via_dmablit.c via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS); dev_priv 223 drivers/gpu/drm/via/via_dmablit.c via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04); dev_priv 289 drivers/gpu/drm/via/via_dmablit.c drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; dev_priv 291 drivers/gpu/drm/via/via_dmablit.c via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA); dev_priv 297 drivers/gpu/drm/via/via_dmablit.c drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; dev_priv 299 drivers/gpu/drm/via/via_dmablit.c via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD); dev_priv 314 drivers/gpu/drm/via/via_dmablit.c drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; dev_priv 315 drivers/gpu/drm/via/via_dmablit.c drm_via_blitq_t *blitq = dev_priv->blit_queues + engine; dev_priv 330 drivers/gpu/drm/via/via_dmablit.c ((status = via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD); dev_priv 349 drivers/gpu/drm/via/via_dmablit.c via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD); dev_priv 430 drivers/gpu/drm/via/via_dmablit.c drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; dev_priv 431 drivers/gpu/drm/via/via_dmablit.c drm_via_blitq_t *blitq = dev_priv->blit_queues + engine; dev_priv 542 drivers/gpu/drm/via/via_dmablit.c drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; dev_priv 548 drivers/gpu/drm/via/via_dmablit.c blitq = dev_priv->blit_queues + i; dev_priv 723 drivers/gpu/drm/via/via_dmablit.c drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private; dev_priv 730 drivers/gpu/drm/via/via_dmablit.c if (dev_priv == NULL) { dev_priv 736 drivers/gpu/drm/via/via_dmablit.c blitq = dev_priv->blit_queues + engine; dev_priv 124 drivers/gpu/drm/via/via_drv.h static inline u32 via_read(struct drm_via_private *dev_priv, u32 reg) dev_priv 126 drivers/gpu/drm/via/via_drv.h return readl((void __iomem *)(dev_priv->mmio->handle + reg)); dev_priv 129 drivers/gpu/drm/via/via_drv.h static inline void via_write(struct drm_via_private *dev_priv, u32 reg, dev_priv 132 drivers/gpu/drm/via/via_drv.h writel(val, (void __iomem *)(dev_priv->mmio->handle + reg)); dev_priv 135 drivers/gpu/drm/via/via_drv.h static inline void via_write8(struct drm_via_private *dev_priv, u32 reg, dev_priv 138 drivers/gpu/drm/via/via_drv.h writeb(val, (void __iomem *)(dev_priv->mmio->handle + reg)); dev_priv 141 drivers/gpu/drm/via/via_drv.h static inline void via_write8_mask(struct drm_via_private *dev_priv, dev_priv 146 drivers/gpu/drm/via/via_drv.h tmp = readb((void __iomem *)(dev_priv->mmio->handle + reg)); dev_priv 148 drivers/gpu/drm/via/via_drv.h writeb(tmp, (void __iomem *)(dev_priv->mmio->handle + reg)); dev_priv 218 drivers/gpu/drm/via/via_drv.h extern void via_init_futex(drm_via_private_t *dev_priv); dev_priv 219 drivers/gpu/drm/via/via_drv.h extern void via_cleanup_futex(drm_via_private_t *dev_priv); dev_priv 220 drivers/gpu/drm/via/via_drv.h extern void via_release_futex(drm_via_private_t *dev_priv, int context); dev_priv 95 drivers/gpu/drm/via/via_irq.c drm_via_private_t *dev_priv = dev->dev_private; dev_priv 100 drivers/gpu/drm/via/via_irq.c return atomic_read(&dev_priv->vbl_received); dev_priv 106 drivers/gpu/drm/via/via_irq.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 110 drivers/gpu/drm/via/via_irq.c drm_via_irq_t *cur_irq = dev_priv->via_irqs; dev_priv 113 drivers/gpu/drm/via/via_irq.c status = via_read(dev_priv, VIA_REG_INTERRUPT); dev_priv 115 drivers/gpu/drm/via/via_irq.c atomic_inc(&dev_priv->vbl_received); dev_priv 116 drivers/gpu/drm/via/via_irq.c if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) { dev_priv 118 drivers/gpu/drm/via/via_irq.c if (dev_priv->last_vblank_valid) { dev_priv 119 drivers/gpu/drm/via/via_irq.c dev_priv->nsec_per_vblank = dev_priv 121 drivers/gpu/drm/via/via_irq.c dev_priv->last_vblank) >> 4; dev_priv 123 drivers/gpu/drm/via/via_irq.c dev_priv->last_vblank = cur_vblank; dev_priv 124 drivers/gpu/drm/via/via_irq.c dev_priv->last_vblank_valid = 1; dev_priv 126 drivers/gpu/drm/via/via_irq.c if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) { dev_priv 128 drivers/gpu/drm/via/via_irq.c ktime_to_ns(dev_priv->nsec_per_vblank)); dev_priv 134 drivers/gpu/drm/via/via_irq.c for (i = 0; i < dev_priv->num_irqs; ++i) { dev_priv 139 drivers/gpu/drm/via/via_irq.c if (dev_priv->irq_map[drm_via_irq_dma0_td] == i) dev_priv 141 drivers/gpu/drm/via/via_irq.c else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i) dev_priv 148 drivers/gpu/drm/via/via_irq.c via_write(dev_priv, VIA_REG_INTERRUPT, status); dev_priv 157 drivers/gpu/drm/via/via_irq.c static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t *dev_priv) dev_priv 161 drivers/gpu/drm/via/via_irq.c if (dev_priv) { dev_priv 163 drivers/gpu/drm/via/via_irq.c status = via_read(dev_priv, VIA_REG_INTERRUPT); dev_priv 164 drivers/gpu/drm/via/via_irq.c via_write(dev_priv, VIA_REG_INTERRUPT, status | dev_priv 165 drivers/gpu/drm/via/via_irq.c dev_priv->irq_pending_mask); dev_priv 171 drivers/gpu/drm/via/via_irq.c drm_via_private_t *dev_priv = dev->dev_private; dev_priv 179 drivers/gpu/drm/via/via_irq.c status = via_read(dev_priv, VIA_REG_INTERRUPT); dev_priv 180 drivers/gpu/drm/via/via_irq.c via_write(dev_priv, VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE); dev_priv 182 drivers/gpu/drm/via/via_irq.c via_write8(dev_priv, 0x83d4, 0x11); dev_priv 183 drivers/gpu/drm/via/via_irq.c via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30); dev_priv 190 drivers/gpu/drm/via/via_irq.c drm_via_private_t *dev_priv = dev->dev_private; dev_priv 193 drivers/gpu/drm/via/via_irq.c status = via_read(dev_priv, VIA_REG_INTERRUPT); dev_priv 194 drivers/gpu/drm/via/via_irq.c via_write(dev_priv, VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE); dev_priv 196 drivers/gpu/drm/via/via_irq.c via_write8(dev_priv, 0x83d4, 0x11); dev_priv 197 drivers/gpu/drm/via/via_irq.c via_write8_mask(dev_priv, 0x83d5, 0x30, 0); dev_priv 207 drivers/gpu/drm/via/via_irq.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 216 drivers/gpu/drm/via/via_irq.c if (!dev_priv) { dev_priv 226 drivers/gpu/drm/via/via_irq.c real_irq = dev_priv->irq_map[irq]; dev_priv 234 drivers/gpu/drm/via/via_irq.c masks = dev_priv->irq_masks; dev_priv 235 drivers/gpu/drm/via/via_irq.c cur_irq = dev_priv->via_irqs + real_irq; dev_priv 239 drivers/gpu/drm/via/via_irq.c ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) == dev_priv 259 drivers/gpu/drm/via/via_irq.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 264 drivers/gpu/drm/via/via_irq.c DRM_DEBUG("dev_priv: %p\n", dev_priv); dev_priv 265 drivers/gpu/drm/via/via_irq.c if (dev_priv) { dev_priv 266 drivers/gpu/drm/via/via_irq.c cur_irq = dev_priv->via_irqs; dev_priv 268 drivers/gpu/drm/via/via_irq.c dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE; dev_priv 269 drivers/gpu/drm/via/via_irq.c dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING; dev_priv 271 drivers/gpu/drm/via/via_irq.c if (dev_priv->chipset == VIA_PRO_GROUP_A || dev_priv 272 drivers/gpu/drm/via/via_irq.c dev_priv->chipset == VIA_DX9_0) { dev_priv 273 drivers/gpu/drm/via/via_irq.c dev_priv->irq_masks = via_pro_group_a_irqs; dev_priv 274 drivers/gpu/drm/via/via_irq.c dev_priv->num_irqs = via_num_pro_group_a; dev_priv 275 drivers/gpu/drm/via/via_irq.c dev_priv->irq_map = via_irqmap_pro_group_a; dev_priv 277 drivers/gpu/drm/via/via_irq.c dev_priv->irq_masks = via_unichrome_irqs; dev_priv 278 drivers/gpu/drm/via/via_irq.c dev_priv->num_irqs = via_num_unichrome; dev_priv 279 drivers/gpu/drm/via/via_irq.c dev_priv->irq_map = via_irqmap_unichrome; dev_priv 282 drivers/gpu/drm/via/via_irq.c for (i = 0; i < dev_priv->num_irqs; ++i) { dev_priv 284 drivers/gpu/drm/via/via_irq.c cur_irq->enable_mask = dev_priv->irq_masks[i][0]; dev_priv 285 drivers/gpu/drm/via/via_irq.c cur_irq->pending_mask = dev_priv->irq_masks[i][1]; dev_priv 287 drivers/gpu/drm/via/via_irq.c dev_priv->irq_enable_mask |= cur_irq->enable_mask; dev_priv 288 drivers/gpu/drm/via/via_irq.c dev_priv->irq_pending_mask |= cur_irq->pending_mask; dev_priv 294 drivers/gpu/drm/via/via_irq.c dev_priv->last_vblank_valid = 0; dev_priv 297 drivers/gpu/drm/via/via_irq.c status = via_read(dev_priv, VIA_REG_INTERRUPT); dev_priv 298 drivers/gpu/drm/via/via_irq.c via_write(dev_priv, VIA_REG_INTERRUPT, status & dev_priv 299 drivers/gpu/drm/via/via_irq.c ~(dev_priv->irq_enable_mask)); dev_priv 302 drivers/gpu/drm/via/via_irq.c viadrv_acknowledge_irqs(dev_priv); dev_priv 308 drivers/gpu/drm/via/via_irq.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 312 drivers/gpu/drm/via/via_irq.c if (!dev_priv) dev_priv 315 drivers/gpu/drm/via/via_irq.c status = via_read(dev_priv, VIA_REG_INTERRUPT); dev_priv 316 drivers/gpu/drm/via/via_irq.c via_write(dev_priv, VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL dev_priv 317 drivers/gpu/drm/via/via_irq.c | dev_priv->irq_enable_mask); dev_priv 320 drivers/gpu/drm/via/via_irq.c via_write8(dev_priv, 0x83d4, 0x11); dev_priv 321 drivers/gpu/drm/via/via_irq.c via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30); dev_priv 328 drivers/gpu/drm/via/via_irq.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 332 drivers/gpu/drm/via/via_irq.c if (dev_priv) { dev_priv 336 drivers/gpu/drm/via/via_irq.c via_write8(dev_priv, 0x83d4, 0x11); dev_priv 337 drivers/gpu/drm/via/via_irq.c via_write8_mask(dev_priv, 0x83d5, 0x30, 0); dev_priv 339 drivers/gpu/drm/via/via_irq.c status = via_read(dev_priv, VIA_REG_INTERRUPT); dev_priv 340 drivers/gpu/drm/via/via_irq.c via_write(dev_priv, VIA_REG_INTERRUPT, status & dev_priv 341 drivers/gpu/drm/via/via_irq.c ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask)); dev_priv 350 drivers/gpu/drm/via/via_irq.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 351 drivers/gpu/drm/via/via_irq.c drm_via_irq_t *cur_irq = dev_priv->via_irqs; dev_priv 354 drivers/gpu/drm/via/via_irq.c if (irqwait->request.irq >= dev_priv->num_irqs) { dev_priv 34 drivers/gpu/drm/via/via_map.c drm_via_private_t *dev_priv = dev->dev_private; dev_priv 38 drivers/gpu/drm/via/via_map.c dev_priv->sarea = drm_legacy_getsarea(dev); dev_priv 39 drivers/gpu/drm/via/via_map.c if (!dev_priv->sarea) { dev_priv 41 drivers/gpu/drm/via/via_map.c dev->dev_private = (void *)dev_priv; dev_priv 46 drivers/gpu/drm/via/via_map.c dev_priv->fb = drm_legacy_findmap(dev, init->fb_offset); dev_priv 47 drivers/gpu/drm/via/via_map.c if (!dev_priv->fb) { dev_priv 49 drivers/gpu/drm/via/via_map.c dev->dev_private = (void *)dev_priv; dev_priv 53 drivers/gpu/drm/via/via_map.c dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset); dev_priv 54 drivers/gpu/drm/via/via_map.c if (!dev_priv->mmio) { dev_priv 56 drivers/gpu/drm/via/via_map.c dev->dev_private = (void *)dev_priv; dev_priv 61 drivers/gpu/drm/via/via_map.c dev_priv->sarea_priv = dev_priv 62 drivers/gpu/drm/via/via_map.c (drm_via_sarea_t *) ((u8 *) dev_priv->sarea->handle + dev_priv 65 drivers/gpu/drm/via/via_map.c dev_priv->agpAddr = init->agpAddr; dev_priv 67 drivers/gpu/drm/via/via_map.c via_init_futex(dev_priv); dev_priv 71 drivers/gpu/drm/via/via_map.c dev->dev_private = (void *)dev_priv; dev_priv 100 drivers/gpu/drm/via/via_map.c drm_via_private_t *dev_priv; dev_priv 103 drivers/gpu/drm/via/via_map.c dev_priv = kzalloc(sizeof(drm_via_private_t), GFP_KERNEL); dev_priv 104 drivers/gpu/drm/via/via_map.c if (dev_priv == NULL) dev_priv 107 drivers/gpu/drm/via/via_map.c idr_init(&dev_priv->object_idr); dev_priv 108 drivers/gpu/drm/via/via_map.c dev->dev_private = (void *)dev_priv; dev_priv 110 drivers/gpu/drm/via/via_map.c dev_priv->chipset = chipset; dev_priv 116 drivers/gpu/drm/via/via_map.c kfree(dev_priv); dev_priv 125 drivers/gpu/drm/via/via_map.c drm_via_private_t *dev_priv = dev->dev_private; dev_priv 127 drivers/gpu/drm/via/via_map.c idr_destroy(&dev_priv->object_idr); dev_priv 129 drivers/gpu/drm/via/via_map.c kfree(dev_priv); dev_priv 48 drivers/gpu/drm/via/via_mm.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 51 drivers/gpu/drm/via/via_mm.c drm_mm_init(&dev_priv->agp_mm, 0, agp->size >> VIA_MM_ALIGN_SHIFT); dev_priv 53 drivers/gpu/drm/via/via_mm.c dev_priv->agp_initialized = 1; dev_priv 54 drivers/gpu/drm/via/via_mm.c dev_priv->agp_offset = agp->offset; dev_priv 64 drivers/gpu/drm/via/via_mm.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 67 drivers/gpu/drm/via/via_mm.c drm_mm_init(&dev_priv->vram_mm, 0, fb->size >> VIA_MM_ALIGN_SHIFT); dev_priv 69 drivers/gpu/drm/via/via_mm.c dev_priv->vram_initialized = 1; dev_priv 70 drivers/gpu/drm/via/via_mm.c dev_priv->vram_offset = fb->offset; dev_priv 81 drivers/gpu/drm/via/via_mm.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 83 drivers/gpu/drm/via/via_mm.c via_release_futex(dev_priv, context); dev_priv 90 drivers/gpu/drm/via/via_mm.c via_cleanup_futex(dev_priv); dev_priv 98 drivers/gpu/drm/via/via_mm.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 100 drivers/gpu/drm/via/via_mm.c if (!dev_priv) dev_priv 104 drivers/gpu/drm/via/via_mm.c if (dev_priv->vram_initialized) { dev_priv 105 drivers/gpu/drm/via/via_mm.c drm_mm_takedown(&dev_priv->vram_mm); dev_priv 106 drivers/gpu/drm/via/via_mm.c dev_priv->vram_initialized = 0; dev_priv 108 drivers/gpu/drm/via/via_mm.c if (dev_priv->agp_initialized) { dev_priv 109 drivers/gpu/drm/via/via_mm.c drm_mm_takedown(&dev_priv->agp_mm); dev_priv 110 drivers/gpu/drm/via/via_mm.c dev_priv->agp_initialized = 0; dev_priv 121 drivers/gpu/drm/via/via_mm.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 130 drivers/gpu/drm/via/via_mm.c if (0 == ((mem->type == VIA_MEM_VIDEO) ? dev_priv->vram_initialized : dev_priv 131 drivers/gpu/drm/via/via_mm.c dev_priv->agp_initialized)) { dev_priv 146 drivers/gpu/drm/via/via_mm.c retval = drm_mm_insert_node(&dev_priv->agp_mm, dev_priv 150 drivers/gpu/drm/via/via_mm.c retval = drm_mm_insert_node(&dev_priv->vram_mm, dev_priv 156 drivers/gpu/drm/via/via_mm.c retval = idr_alloc(&dev_priv->object_idr, item, 1, 0, GFP_KERNEL); dev_priv 165 drivers/gpu/drm/via/via_mm.c dev_priv->vram_offset : dev_priv->agp_offset) + dev_priv 187 drivers/gpu/drm/via/via_mm.c drm_via_private_t *dev_priv = dev->dev_private; dev_priv 192 drivers/gpu/drm/via/via_mm.c obj = idr_find(&dev_priv->object_idr, mem->index); dev_priv 198 drivers/gpu/drm/via/via_mm.c idr_remove(&dev_priv->object_idr, mem->index); dev_priv 524 drivers/gpu/drm/via/via_verifier.c drm_via_private_t *dev_priv = dev_priv 582 drivers/gpu/drm/via/via_verifier.c if (dev_priv->num_fire_offsets >= dev_priv 588 drivers/gpu/drm/via/via_verifier.c dev_priv->fire_offsets[dev_priv-> dev_priv 717 drivers/gpu/drm/via/via_verifier.c via_parse_header2(drm_via_private_t *dev_priv, uint32_t const **buffer, dev_priv 725 drivers/gpu/drm/via/via_verifier.c next_fire = dev_priv->fire_offsets[*fire_count]; dev_priv 728 drivers/gpu/drm/via/via_verifier.c via_write(dev_priv, HC_REG_TRANS_SET + HC_REG_BASE, *buf++); dev_priv 732 drivers/gpu/drm/via/via_verifier.c (*fire_count < dev_priv->num_fire_offsets) && dev_priv 735 drivers/gpu/drm/via/via_verifier.c via_write(dev_priv, HC_REG_TRANS_SPACE + HC_REG_BASE + dev_priv 743 drivers/gpu/drm/via/via_verifier.c if (++(*fire_count) < dev_priv->num_fire_offsets) dev_priv 744 drivers/gpu/drm/via/via_verifier.c next_fire = dev_priv->fire_offsets[*fire_count]; dev_priv 756 drivers/gpu/drm/via/via_verifier.c via_write(dev_priv, HC_REG_TRANS_SPACE + HC_REG_BASE + dev_priv 836 drivers/gpu/drm/via/via_verifier.c via_parse_header1(drm_via_private_t *dev_priv, uint32_t const **buffer, dev_priv 846 drivers/gpu/drm/via/via_verifier.c via_write(dev_priv, (cmd & ~HALCYON_HEADER1MASK) << 2, *++buf); dev_priv 887 drivers/gpu/drm/via/via_verifier.c via_parse_vheader5(drm_via_private_t *dev_priv, uint32_t const **buffer, dev_priv 897 drivers/gpu/drm/via/via_verifier.c via_write(dev_priv, addr, *buf++); dev_priv 942 drivers/gpu/drm/via/via_verifier.c via_parse_vheader6(drm_via_private_t *dev_priv, uint32_t const **buffer, dev_priv 953 drivers/gpu/drm/via/via_verifier.c via_write(dev_priv, addr, *buf++); dev_priv 967 drivers/gpu/drm/via/via_verifier.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 968 drivers/gpu/drm/via/via_verifier.c drm_via_state_t *hc_state = &dev_priv->hc_state; dev_priv 976 drivers/gpu/drm/via/via_verifier.c cme_video = (dev_priv->chipset == VIA_PRO_GROUP_A || dev_priv 977 drivers/gpu/drm/via/via_verifier.c dev_priv->chipset == VIA_DX9_0); dev_priv 979 drivers/gpu/drm/via/via_verifier.c supported_3d = dev_priv->chipset != VIA_DX9_0; dev_priv 986 drivers/gpu/drm/via/via_verifier.c dev_priv->num_fire_offsets = 0; dev_priv 1043 drivers/gpu/drm/via/via_verifier.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 1054 drivers/gpu/drm/via/via_verifier.c via_parse_header2(dev_priv, &buf, buf_end, dev_priv 1058 drivers/gpu/drm/via/via_verifier.c state = via_parse_header1(dev_priv, &buf, buf_end); dev_priv 1061 drivers/gpu/drm/via/via_verifier.c state = via_parse_vheader5(dev_priv, &buf, buf_end); dev_priv 1064 drivers/gpu/drm/via/via_verifier.c state = via_parse_vheader6(dev_priv, &buf, buf_end); dev_priv 33 drivers/gpu/drm/via/via_video.c void via_init_futex(drm_via_private_t *dev_priv) dev_priv 40 drivers/gpu/drm/via/via_video.c init_waitqueue_head(&(dev_priv->decoder_queue[i])); dev_priv 41 drivers/gpu/drm/via/via_video.c XVMCLOCKPTR(dev_priv->sarea_priv, i)->lock = 0; dev_priv 45 drivers/gpu/drm/via/via_video.c void via_cleanup_futex(drm_via_private_t *dev_priv) dev_priv 49 drivers/gpu/drm/via/via_video.c void via_release_futex(drm_via_private_t *dev_priv, int context) dev_priv 54 drivers/gpu/drm/via/via_video.c if (!dev_priv->sarea_priv) dev_priv 58 drivers/gpu/drm/via/via_video.c lock = (volatile int *)XVMCLOCKPTR(dev_priv->sarea_priv, i); dev_priv 62 drivers/gpu/drm/via/via_video.c wake_up(&(dev_priv->decoder_queue[i])); dev_priv 73 drivers/gpu/drm/via/via_video.c drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; dev_priv 74 drivers/gpu/drm/via/via_video.c drm_via_sarea_t *sAPriv = dev_priv->sarea_priv; dev_priv 86 drivers/gpu/drm/via/via_video.c VIA_WAIT_ON(ret, dev_priv->decoder_queue[fx->lock], dev_priv 90 drivers/gpu/drm/via/via_video.c wake_up(&(dev_priv->decoder_queue[fx->lock])); dev_priv 93 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c struct vmw_private *dev_priv; dev_priv 496 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c struct vmw_private *dev_priv = bi->ctx->dev_priv; dev_priv 502 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 511 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 528 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c struct vmw_private *dev_priv = bi->ctx->dev_priv; dev_priv 534 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 545 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 564 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c struct vmw_private *dev_priv = bi->ctx->dev_priv; dev_priv 573 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 583 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 598 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c struct vmw_private *dev_priv = bi->ctx->dev_priv; dev_priv 604 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id); dev_priv 612 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 627 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c struct vmw_private *dev_priv = bi->ctx->dev_priv; dev_priv 633 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id); dev_priv 650 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 757 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id); dev_priv 768 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c vmw_fifo_commit(ctx->dev_priv, cmd_size); dev_priv 793 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id); dev_priv 807 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c vmw_fifo_commit(ctx->dev_priv, cmd_size); dev_priv 877 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id); dev_priv 885 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c vmw_fifo_commit(ctx->dev_priv, cmd_size); dev_priv 991 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c cmd = VMW_FIFO_RESERVE_DX(ctx->dev_priv, cmd_size, ctx->id); dev_priv 1001 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c vmw_fifo_commit(ctx->dev_priv, cmd_size); dev_priv 1138 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c struct vmw_private *dev_priv = bi->ctx->dev_priv; dev_priv 1144 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), bi->ctx->id); dev_priv 1160 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 1174 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c vmw_binding_state_alloc(struct vmw_private *dev_priv) dev_priv 1183 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), sizeof(*cbs), dev_priv 1190 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c ttm_mem_global_free(vmw_mem_glob(dev_priv), sizeof(*cbs)); dev_priv 1194 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c cbs->dev_priv = dev_priv; dev_priv 1208 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c struct vmw_private *dev_priv = cbs->dev_priv; dev_priv 1211 drivers/gpu/drm/vmwgfx/vmwgfx_binding.c ttm_mem_global_free(vmw_mem_glob(dev_priv), sizeof(*cbs)); dev_priv 204 drivers/gpu/drm/vmwgfx/vmwgfx_binding.h vmw_binding_state_alloc(struct vmw_private *dev_priv); dev_priv 89 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c int vmw_bo_pin_in_placement(struct vmw_private *dev_priv, dev_priv 99 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ret = ttm_write_lock(&dev_priv->reservation_sem, interruptible); dev_priv 103 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c vmw_execbuf_release_pinned_bo(dev_priv); dev_priv 121 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_write_unlock(&dev_priv->reservation_sem); dev_priv 139 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c int vmw_bo_pin_in_vram_or_gmr(struct vmw_private *dev_priv, dev_priv 148 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ret = ttm_write_lock(&dev_priv->reservation_sem, interruptible); dev_priv 152 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c vmw_execbuf_release_pinned_bo(dev_priv); dev_priv 176 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_write_unlock(&dev_priv->reservation_sem); dev_priv 193 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c int vmw_bo_pin_in_vram(struct vmw_private *dev_priv, dev_priv 197 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c return vmw_bo_pin_in_placement(dev_priv, buf, &vmw_vram_placement, dev_priv 214 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c int vmw_bo_pin_in_start_of_vram(struct vmw_private *dev_priv, dev_priv 232 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ret = ttm_write_lock(&dev_priv->reservation_sem, interruptible); dev_priv 236 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c vmw_execbuf_release_pinned_bo(dev_priv); dev_priv 267 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_write_unlock(&dev_priv->reservation_sem); dev_priv 284 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c int vmw_bo_unpin(struct vmw_private *dev_priv, dev_priv 291 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ret = ttm_read_lock(&dev_priv->reservation_sem, interruptible); dev_priv 304 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 430 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c static size_t vmw_bo_acc_size(struct vmw_private *dev_priv, size_t size, dev_priv 447 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c if (dev_priv->map_mode == vmw_dma_alloc_coherent) dev_priv 497 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c int vmw_bo_init(struct vmw_private *dev_priv, dev_priv 503 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct ttm_bo_device *bdev = &dev_priv->bdev; dev_priv 510 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c acc_size = vmw_bo_acc_size(dev_priv, size, user); dev_priv 590 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c int vmw_user_bo_alloc(struct vmw_private *dev_priv, dev_priv 607 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ret = vmw_bo_init(dev_priv, &user_bo->vbo, size, dev_priv 608 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c (dev_priv->has_mob) ? dev_priv 819 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 828 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ret = ttm_read_lock(&dev_priv->reservation_sem, true); dev_priv 832 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ret = vmw_user_bo_alloc(dev_priv, vmw_fpriv(file_priv)->tfile, dev_priv 846 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 1006 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct vmw_private *dev_priv = dev_priv 1010 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL); dev_priv 1034 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 1041 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ret = ttm_read_lock(&dev_priv->reservation_sem, true); dev_priv 1045 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ret = vmw_user_bo_alloc(dev_priv, vmw_fpriv(file_priv)->tfile, dev_priv 1053 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 114 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c struct vmw_private *dev_priv; dev_priv 307 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c vmw_write(man->dev_priv, SVGA_REG_COMMAND_HIGH, val); dev_priv 311 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c vmw_write(man->dev_priv, SVGA_REG_COMMAND_LOW, val); dev_priv 446 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c vmw_generic_waiter_remove(man->dev_priv, dev_priv 448 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c &man->dev_priv->cmdbuf_waiters); dev_priv 451 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c vmw_generic_waiter_add(man->dev_priv, dev_priv 453 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c &man->dev_priv->cmdbuf_waiters); dev_priv 613 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c vmw_fifo_send_fence(man->dev_priv, &dummy); dev_priv 724 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c vmw_generic_waiter_add(man->dev_priv, dev_priv 726 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c &man->dev_priv->cmdbuf_waiters); dev_priv 737 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c vmw_generic_waiter_remove(man->dev_priv, dev_priv 739 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c &man->dev_priv->cmdbuf_waiters); dev_priv 822 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c vmw_generic_waiter_add(man->dev_priv, dev_priv 824 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c &man->dev_priv->cmdbuf_waiters); dev_priv 833 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c (man->dev_priv, SVGA_IRQFLAG_COMMAND_BUFFER, dev_priv 834 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c &man->dev_priv->cmdbuf_waiters); dev_priv 841 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c vmw_generic_waiter_remove(man->dev_priv, dev_priv 843 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c &man->dev_priv->cmdbuf_waiters); dev_priv 1224 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c struct vmw_private *dev_priv = man->dev_priv; dev_priv 1233 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c man->map = dma_alloc_coherent(&dev_priv->dev->pdev->dev, size, dev_priv 1244 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c if (!(dev_priv->capabilities & SVGA_CAP_DX)) dev_priv 1247 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c ret = ttm_bo_create(&dev_priv->bdev, size, ttm_bo_type_device, dev_priv 1298 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c struct vmw_cmdbuf_man *vmw_cmdbuf_man_create(struct vmw_private *dev_priv) dev_priv 1305 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c if (!(dev_priv->capabilities & SVGA_CAP_COMMAND_BUFFERS)) dev_priv 1312 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c man->num_contexts = (dev_priv->capabilities & SVGA_CAP_HP_CMD_QUEUE) ? dev_priv 1315 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c &dev_priv->dev->pdev->dev, dev_priv 1324 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c &dev_priv->dev->pdev->dev, dev_priv 1343 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c man->dev_priv = dev_priv; dev_priv 1346 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ERROR, dev_priv 1347 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c &dev_priv->error_waiters); dev_priv 1389 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c dma_free_coherent(&man->dev_priv->dev->pdev->dev, dev_priv 1409 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c vmw_generic_waiter_remove(man->dev_priv, SVGA_IRQFLAG_ERROR, dev_priv 1410 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c &man->dev_priv->error_waiters); dev_priv 64 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c struct vmw_private *dev_priv; dev_priv 289 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c vmw_cmdbuf_res_man_create(struct vmw_private *dev_priv) dev_priv 298 drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c man->dev_priv = dev_priv; dev_priv 139 drivers/gpu/drm/vmwgfx/vmwgfx_context.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 148 drivers/gpu/drm/vmwgfx/vmwgfx_context.c mutex_lock(&dev_priv->cmdbuf_mutex); dev_priv 150 drivers/gpu/drm/vmwgfx/vmwgfx_context.c mutex_lock(&dev_priv->binding_mutex); dev_priv 153 drivers/gpu/drm/vmwgfx/vmwgfx_context.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 154 drivers/gpu/drm/vmwgfx/vmwgfx_context.c if (dev_priv->pinned_bo != NULL && dev_priv 155 drivers/gpu/drm/vmwgfx/vmwgfx_context.c !dev_priv->query_cid_valid) dev_priv 156 drivers/gpu/drm/vmwgfx/vmwgfx_context.c __vmw_execbuf_release_pinned_bo(dev_priv, NULL); dev_priv 157 drivers/gpu/drm/vmwgfx/vmwgfx_context.c mutex_unlock(&dev_priv->cmdbuf_mutex); dev_priv 162 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_execbuf_release_pinned_bo(dev_priv); dev_priv 163 drivers/gpu/drm/vmwgfx/vmwgfx_context.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 171 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 172 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_resource_dec(dev_priv); dev_priv 175 drivers/gpu/drm/vmwgfx/vmwgfx_context.c static int vmw_gb_context_init(struct vmw_private *dev_priv, dev_priv 186 drivers/gpu/drm/vmwgfx/vmwgfx_context.c ret = vmw_resource_init(dev_priv, res, true, dev_priv 193 drivers/gpu/drm/vmwgfx/vmwgfx_context.c if (dev_priv->has_mob) { dev_priv 194 drivers/gpu/drm/vmwgfx/vmwgfx_context.c uctx->man = vmw_cmdbuf_res_man_create(dev_priv); dev_priv 202 drivers/gpu/drm/vmwgfx/vmwgfx_context.c uctx->cbs = vmw_binding_state_alloc(dev_priv); dev_priv 212 drivers/gpu/drm/vmwgfx/vmwgfx_context.c uctx->cotables[i] = vmw_cotable_alloc(dev_priv, dev_priv 234 drivers/gpu/drm/vmwgfx/vmwgfx_context.c static int vmw_context_init(struct vmw_private *dev_priv, dev_priv 246 drivers/gpu/drm/vmwgfx/vmwgfx_context.c if (dev_priv->has_mob) dev_priv 247 drivers/gpu/drm/vmwgfx/vmwgfx_context.c return vmw_gb_context_init(dev_priv, dx, res, res_free); dev_priv 249 drivers/gpu/drm/vmwgfx/vmwgfx_context.c ret = vmw_resource_init(dev_priv, res, false, dev_priv 263 drivers/gpu/drm/vmwgfx/vmwgfx_context.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 273 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 274 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_resource_inc(dev_priv); dev_priv 293 drivers/gpu/drm/vmwgfx/vmwgfx_context.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 314 drivers/gpu/drm/vmwgfx/vmwgfx_context.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 323 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 324 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_resource_inc(dev_priv); dev_priv 337 drivers/gpu/drm/vmwgfx/vmwgfx_context.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 346 drivers/gpu/drm/vmwgfx/vmwgfx_context.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 356 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 365 drivers/gpu/drm/vmwgfx/vmwgfx_context.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 385 drivers/gpu/drm/vmwgfx/vmwgfx_context.c mutex_lock(&dev_priv->binding_mutex); dev_priv 390 drivers/gpu/drm/vmwgfx/vmwgfx_context.c cmd = VMW_FIFO_RESERVE(dev_priv, submit_size); dev_priv 392 drivers/gpu/drm/vmwgfx/vmwgfx_context.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 409 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_commit(dev_priv, submit_size); dev_priv 410 drivers/gpu/drm/vmwgfx/vmwgfx_context.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 416 drivers/gpu/drm/vmwgfx/vmwgfx_context.c (void) vmw_execbuf_fence_commands(NULL, dev_priv, dev_priv 429 drivers/gpu/drm/vmwgfx/vmwgfx_context.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 438 drivers/gpu/drm/vmwgfx/vmwgfx_context.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 445 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 446 drivers/gpu/drm/vmwgfx/vmwgfx_context.c if (dev_priv->query_cid == res->id) dev_priv 447 drivers/gpu/drm/vmwgfx/vmwgfx_context.c dev_priv->query_cid_valid = false; dev_priv 449 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_resource_dec(dev_priv); dev_priv 460 drivers/gpu/drm/vmwgfx/vmwgfx_context.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 481 drivers/gpu/drm/vmwgfx/vmwgfx_context.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 490 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 491 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_resource_inc(dev_priv); dev_priv 504 drivers/gpu/drm/vmwgfx/vmwgfx_context.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 513 drivers/gpu/drm/vmwgfx/vmwgfx_context.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 523 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 572 drivers/gpu/drm/vmwgfx/vmwgfx_context.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 592 drivers/gpu/drm/vmwgfx/vmwgfx_context.c mutex_lock(&dev_priv->binding_mutex); dev_priv 604 drivers/gpu/drm/vmwgfx/vmwgfx_context.c cmd = VMW_FIFO_RESERVE(dev_priv, submit_size); dev_priv 606 drivers/gpu/drm/vmwgfx/vmwgfx_context.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 623 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_commit(dev_priv, submit_size); dev_priv 624 drivers/gpu/drm/vmwgfx/vmwgfx_context.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 630 drivers/gpu/drm/vmwgfx/vmwgfx_context.c (void) vmw_execbuf_fence_commands(NULL, dev_priv, dev_priv 643 drivers/gpu/drm/vmwgfx/vmwgfx_context.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 652 drivers/gpu/drm/vmwgfx/vmwgfx_context.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 659 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 660 drivers/gpu/drm/vmwgfx/vmwgfx_context.c if (dev_priv->query_cid == res->id) dev_priv 661 drivers/gpu/drm/vmwgfx/vmwgfx_context.c dev_priv->query_cid_valid = false; dev_priv 663 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_fifo_resource_dec(dev_priv); dev_priv 682 drivers/gpu/drm/vmwgfx/vmwgfx_context.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 690 drivers/gpu/drm/vmwgfx/vmwgfx_context.c ttm_mem_global_free(vmw_mem_glob(dev_priv), dev_priv 722 drivers/gpu/drm/vmwgfx/vmwgfx_context.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 734 drivers/gpu/drm/vmwgfx/vmwgfx_context.c if (!dev_priv->has_dx && dx) { dev_priv 741 drivers/gpu/drm/vmwgfx/vmwgfx_context.c ((dev_priv->has_mob) ? vmw_cmdbuf_res_man_size() : 0) + dev_priv 744 drivers/gpu/drm/vmwgfx/vmwgfx_context.c ret = ttm_read_lock(&dev_priv->reservation_sem, true); dev_priv 748 drivers/gpu/drm/vmwgfx/vmwgfx_context.c ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), dev_priv 760 drivers/gpu/drm/vmwgfx/vmwgfx_context.c ttm_mem_global_free(vmw_mem_glob(dev_priv), dev_priv 774 drivers/gpu/drm/vmwgfx/vmwgfx_context.c ret = vmw_context_init(dev_priv, res, vmw_user_context_free, dx); dev_priv 791 drivers/gpu/drm/vmwgfx/vmwgfx_context.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 166 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 176 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 189 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c vmw_fifo_commit_flush(dev_priv, sizeof(*cmd)); dev_priv 241 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 257 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c co_info[vcotbl->type].unbind_func(dev_priv, dev_priv 264 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c cmd1 = VMW_FIFO_RESERVE(dev_priv, submit_size); dev_priv 284 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c vmw_fifo_commit_flush(dev_priv, submit_size); dev_priv 308 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 318 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c mutex_lock(&dev_priv->binding_mutex); dev_priv 321 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 322 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c (void) vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL); dev_priv 341 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 350 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 359 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 362 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c (void) vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL); dev_priv 384 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 411 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c ret = vmw_bo_init(dev_priv, buf, new_size, &vmw_mob_ne_placement, dev_priv 551 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 554 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c ttm_mem_global_free(vmw_mem_glob(dev_priv), cotable_acc_size); dev_priv 565 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c struct vmw_resource *vmw_cotable_alloc(struct vmw_private *dev_priv, dev_priv 580 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), dev_priv 591 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c ret = vmw_resource_init(dev_priv, &vcotbl->res, true, dev_priv 619 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c ttm_mem_global_free(vmw_mem_glob(dev_priv), cotable_acc_size); dev_priv 348 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) dev_priv 365 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, dev_priv 390 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->dummy_query_bo = vbo; dev_priv 405 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static int vmw_request_device_late(struct vmw_private *dev_priv) dev_priv 409 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->has_mob) { dev_priv 410 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = vmw_otables_setup(dev_priv); dev_priv 418 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->cman) { dev_priv 419 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, dev_priv 422 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c struct vmw_cmdbuf_man *man = dev_priv->cman; dev_priv 424 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->cman = NULL; dev_priv 432 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static int vmw_request_device(struct vmw_private *dev_priv) dev_priv 436 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); dev_priv 441 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fence_fifo_up(dev_priv->fman); dev_priv 442 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); dev_priv 443 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (IS_ERR(dev_priv->cman)) { dev_priv 444 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->cman = NULL; dev_priv 445 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->has_dx = false; dev_priv 448 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = vmw_request_device_late(dev_priv); dev_priv 452 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = vmw_dummy_query_bo_create(dev_priv); dev_priv 459 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->cman) dev_priv 460 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_cmdbuf_remove_pool(dev_priv->cman); dev_priv 461 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->has_mob) { dev_priv 462 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); dev_priv 463 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_otables_takedown(dev_priv); dev_priv 465 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->cman) dev_priv 466 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_cmdbuf_man_destroy(dev_priv->cman); dev_priv 468 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fence_fifo_down(dev_priv->fman); dev_priv 469 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fifo_release(dev_priv, &dev_priv->fifo); dev_priv 481 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static void vmw_release_device_early(struct vmw_private *dev_priv) dev_priv 488 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c BUG_ON(dev_priv->pinned_bo != NULL); dev_priv 490 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_bo_unreference(&dev_priv->dummy_query_bo); dev_priv 491 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->cman) dev_priv 492 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_cmdbuf_remove_pool(dev_priv->cman); dev_priv 494 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->has_mob) { dev_priv 495 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); dev_priv 496 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_otables_takedown(dev_priv); dev_priv 508 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static void vmw_release_device_late(struct vmw_private *dev_priv) dev_priv 510 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fence_fifo_down(dev_priv->fman); dev_priv 511 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->cman) dev_priv 512 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_cmdbuf_man_destroy(dev_priv->cman); dev_priv 514 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fifo_release(dev_priv, &dev_priv->fifo); dev_priv 526 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static void vmw_get_initial_size(struct vmw_private *dev_priv) dev_priv 531 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c width = vmw_read(dev_priv, SVGA_REG_WIDTH); dev_priv 532 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c height = vmw_read(dev_priv, SVGA_REG_HEIGHT); dev_priv 537 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (width > dev_priv->fb_max_width || dev_priv 538 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c height > dev_priv->fb_max_height) { dev_priv 548 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->initial_width = width; dev_priv 549 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->initial_height = height; dev_priv 564 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static int vmw_dma_select_mode(struct vmw_private *dev_priv) dev_priv 573 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->map_mode = vmw_dma_alloc_coherent; dev_priv 575 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->map_mode = vmw_dma_map_bind; dev_priv 577 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->map_mode = vmw_dma_map_populate; dev_priv 581 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (dev_priv->map_mode == vmw_dma_alloc_coherent)) dev_priv 584 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); dev_priv 596 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static int vmw_dma_masks(struct vmw_private *dev_priv) dev_priv 598 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c struct drm_device *dev = dev_priv->dev; dev_priv 602 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->map_mode != vmw_dma_phys && dev_priv 613 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c struct vmw_private *dev_priv; dev_priv 620 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); dev_priv 621 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (unlikely(!dev_priv)) { dev_priv 628 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->dev = dev; dev_priv 629 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->vmw_chipset = chipset; dev_priv 630 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->last_read_seqno = (uint32_t) -100; dev_priv 631 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c mutex_init(&dev_priv->cmdbuf_mutex); dev_priv 632 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c mutex_init(&dev_priv->release_mutex); dev_priv 633 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c mutex_init(&dev_priv->binding_mutex); dev_priv 634 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c mutex_init(&dev_priv->global_kms_state_mutex); dev_priv 635 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_lock_init(&dev_priv->reservation_sem); dev_priv 636 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_lock_init(&dev_priv->resource_lock); dev_priv 637 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_lock_init(&dev_priv->hw_lock); dev_priv 638 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_lock_init(&dev_priv->waiter_lock); dev_priv 639 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_lock_init(&dev_priv->cap_lock); dev_priv 640 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_lock_init(&dev_priv->svga_lock); dev_priv 641 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_lock_init(&dev_priv->cursor_lock); dev_priv 644 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c idr_init(&dev_priv->res_idr[i]); dev_priv 645 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c INIT_LIST_HEAD(&dev_priv->res_lru[i]); dev_priv 648 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c init_waitqueue_head(&dev_priv->fence_queue); dev_priv 649 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c init_waitqueue_head(&dev_priv->fifo_queue); dev_priv 650 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->fence_queue_waiters = 0; dev_priv 651 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->fifo_queue_waiters = 0; dev_priv 653 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->used_memory_size = 0; dev_priv 655 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->io_start = pci_resource_start(dev->pdev, 0); dev_priv 656 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->vram_start = pci_resource_start(dev->pdev, 1); dev_priv 657 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); dev_priv 659 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->assume_16bpp = !!vmw_assume_16bpp; dev_priv 661 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->enable_fb = enable_fbdev; dev_priv 663 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); dev_priv 664 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c svga_id = vmw_read(dev_priv, SVGA_REG_ID); dev_priv 671 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); dev_priv 673 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { dev_priv 674 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); dev_priv 678 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = vmw_dma_select_mode(dev_priv); dev_priv 684 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); dev_priv 685 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); dev_priv 686 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); dev_priv 687 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); dev_priv 689 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_get_initial_size(dev_priv); dev_priv 691 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->capabilities & SVGA_CAP_GMR2) { dev_priv 692 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->max_gmr_ids = dev_priv 693 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); dev_priv 694 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->max_gmr_pages = dev_priv 695 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); dev_priv 696 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->memory_size = dev_priv 697 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); dev_priv 698 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->memory_size -= dev_priv->vram_size; dev_priv 704 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->memory_size = 512*1024*1024; dev_priv 706 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->max_mob_pages = 0; dev_priv 707 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->max_mob_size = 0; dev_priv 708 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { dev_priv 710 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_read(dev_priv, dev_priv 717 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (!(dev_priv->capabilities & SVGA_CAP_3D)) dev_priv 720 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; dev_priv 721 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->prim_bb_mem = dev_priv 722 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_read(dev_priv, dev_priv 724 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->max_mob_size = dev_priv 725 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); dev_priv 726 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->stdu_max_width = dev_priv 727 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); dev_priv 728 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->stdu_max_height = dev_priv 729 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); dev_priv 731 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_write(dev_priv, SVGA_REG_DEV_CAP, dev_priv 733 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->texture_max_width = vmw_read(dev_priv, dev_priv 735 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_write(dev_priv, SVGA_REG_DEV_CAP, dev_priv 737 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->texture_max_height = vmw_read(dev_priv, dev_priv 740 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->texture_max_width = 8192; dev_priv 741 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->texture_max_height = 8192; dev_priv 742 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->prim_bb_mem = dev_priv->vram_size; dev_priv 745 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_print_capabilities(dev_priv->capabilities); dev_priv 746 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) dev_priv 747 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_print_capabilities2(dev_priv->capabilities2); dev_priv 749 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = vmw_dma_masks(dev_priv); dev_priv 756 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->capabilities & SVGA_CAP_GMR2) { dev_priv 758 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (unsigned)dev_priv->max_gmr_ids); dev_priv 760 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (unsigned)dev_priv->max_gmr_pages); dev_priv 762 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (unsigned)dev_priv->memory_size / 1024); dev_priv 765 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->prim_bb_mem / 1024); dev_priv 767 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->vram_start, dev_priv->vram_size / 1024); dev_priv 769 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->mmio_start, dev_priv->mmio_size / 1024); dev_priv 771 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->mmio_virt = memremap(dev_priv->mmio_start, dev_priv 772 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->mmio_size, MEMREMAP_WB); dev_priv 774 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (unlikely(dev_priv->mmio_virt == NULL)) { dev_priv 781 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && dev_priv 782 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && dev_priv 783 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c !vmw_fifo_have_pitchlock(dev_priv)) { dev_priv 789 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, dev_priv 792 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (unlikely(dev_priv->tdev == NULL)) { dev_priv 798 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev->dev_private = dev_priv; dev_priv 801 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->stealth = (ret != 0); dev_priv 802 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->stealth) { dev_priv 816 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { dev_priv 824 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->fman = vmw_fence_manager_init(dev_priv); dev_priv 825 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (unlikely(dev_priv->fman == NULL)) { dev_priv 830 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = ttm_bo_device_init(&dev_priv->bdev, dev_priv 843 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, dev_priv 844 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (dev_priv->vram_size >> PAGE_SHIFT)); dev_priv 849 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; dev_priv 851 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->has_gmr = true; dev_priv 852 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || dev_priv 853 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, dev_priv 857 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->has_gmr = false; dev_priv 860 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { dev_priv 861 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->has_mob = true; dev_priv 862 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, dev_priv 866 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->has_mob = false; dev_priv 870 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->has_mob) { dev_priv 871 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_lock(&dev_priv->cap_lock); dev_priv 872 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); dev_priv 873 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); dev_priv 874 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_unlock(&dev_priv->cap_lock); dev_priv 877 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); dev_priv 878 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = vmw_kms_init(dev_priv); dev_priv 881 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_overlay_init(dev_priv); dev_priv 883 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = vmw_request_device(dev_priv); dev_priv 887 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->has_dx) { dev_priv 892 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) { dev_priv 893 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_write(dev_priv, SVGA_REG_DEV_CAP, dev_priv 895 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->has_sm4_1 = vmw_read(dev_priv, dev_priv 900 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); dev_priv 903 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no."); dev_priv 915 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->enable_fb) { dev_priv 916 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fifo_resource_inc(dev_priv); dev_priv 917 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_svga_enable(dev_priv); dev_priv 918 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fb_init(dev_priv); dev_priv 921 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; dev_priv 922 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c register_pm_notifier(&dev_priv->pm_nb); dev_priv 927 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_overlay_close(dev_priv); dev_priv 928 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_kms_close(dev_priv); dev_priv 930 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->has_mob) dev_priv 931 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); dev_priv 932 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->has_gmr) dev_priv 933 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); dev_priv 934 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); dev_priv 936 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (void)ttm_bo_device_release(&dev_priv->bdev); dev_priv 938 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fence_manager_takedown(dev_priv->fman); dev_priv 940 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->capabilities & SVGA_CAP_IRQMASK) dev_priv 941 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_irq_uninstall(dev_priv->dev); dev_priv 943 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->stealth) dev_priv 948 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_object_device_release(&dev_priv->tdev); dev_priv 950 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c memunmap(dev_priv->mmio_virt); dev_priv 953 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c idr_destroy(&dev_priv->res_idr[i]); dev_priv 955 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->ctx.staged_bindings) dev_priv 956 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_binding_state_free(dev_priv->ctx.staged_bindings); dev_priv 957 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c kfree(dev_priv); dev_priv 963 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 966 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c unregister_pm_notifier(&dev_priv->pm_nb); dev_priv 968 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->ctx.res_ht_initialized) dev_priv 969 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c drm_ht_remove(&dev_priv->ctx.res_ht); dev_priv 970 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vfree(dev_priv->ctx.cmd_bounce); dev_priv 971 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->enable_fb) { dev_priv 972 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fb_off(dev_priv); dev_priv 973 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fb_close(dev_priv); dev_priv 974 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fifo_resource_dec(dev_priv); dev_priv 975 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_svga_disable(dev_priv); dev_priv 978 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_kms_close(dev_priv); dev_priv 979 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_overlay_close(dev_priv); dev_priv 981 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->has_gmr) dev_priv 982 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); dev_priv 983 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); dev_priv 985 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_release_device_early(dev_priv); dev_priv 986 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->has_mob) dev_priv 987 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); dev_priv 988 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (void) ttm_bo_device_release(&dev_priv->bdev); dev_priv 989 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_release_device_late(dev_priv); dev_priv 990 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fence_manager_takedown(dev_priv->fman); dev_priv 991 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->capabilities & SVGA_CAP_IRQMASK) dev_priv 992 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_irq_uninstall(dev_priv->dev); dev_priv 993 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->stealth) dev_priv 998 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_object_device_release(&dev_priv->tdev); dev_priv 999 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c memunmap(dev_priv->mmio_virt); dev_priv 1000 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->ctx.staged_bindings) dev_priv 1001 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_binding_state_free(dev_priv->ctx.staged_bindings); dev_priv 1004 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c idr_destroy(&dev_priv->res_idr[i]); dev_priv 1006 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c kfree(dev_priv); dev_priv 1020 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 1028 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); dev_priv 1115 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 1117 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_kms_legacy_hotspot_clear(dev_priv); dev_priv 1118 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (!dev_priv->enable_fb) dev_priv 1119 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_svga_disable(dev_priv); dev_priv 1128 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static void __vmw_svga_enable(struct vmw_private *dev_priv) dev_priv 1130 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_lock(&dev_priv->svga_lock); dev_priv 1131 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { dev_priv 1132 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); dev_priv 1133 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; dev_priv 1135 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_unlock(&dev_priv->svga_lock); dev_priv 1143 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c void vmw_svga_enable(struct vmw_private *dev_priv) dev_priv 1145 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (void) ttm_read_lock(&dev_priv->reservation_sem, false); dev_priv 1146 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c __vmw_svga_enable(dev_priv); dev_priv 1147 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 1157 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c static void __vmw_svga_disable(struct vmw_private *dev_priv) dev_priv 1159 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_lock(&dev_priv->svga_lock); dev_priv 1160 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { dev_priv 1161 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; dev_priv 1162 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_write(dev_priv, SVGA_REG_ENABLE, dev_priv 1166 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_unlock(&dev_priv->svga_lock); dev_priv 1176 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c void vmw_svga_disable(struct vmw_private *dev_priv) dev_priv 1190 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_kms_lost_device(dev_priv->dev); dev_priv 1191 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_write_lock(&dev_priv->reservation_sem, false); dev_priv 1192 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_lock(&dev_priv->svga_lock); dev_priv 1193 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { dev_priv 1194 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; dev_priv 1195 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_unlock(&dev_priv->svga_lock); dev_priv 1196 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) dev_priv 1198 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_write(dev_priv, SVGA_REG_ENABLE, dev_priv 1202 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c spin_unlock(&dev_priv->svga_lock); dev_priv 1203 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_write_unlock(&dev_priv->reservation_sem); dev_priv 1217 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c struct vmw_private *dev_priv = dev_priv 1230 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_suspend_lock(&dev_priv->reservation_sem); dev_priv 1231 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->suspend_locked = true; dev_priv 1235 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (READ_ONCE(dev_priv->suspend_locked)) { dev_priv 1236 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->suspend_locked = false; dev_priv 1237 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_suspend_unlock(&dev_priv->reservation_sem); dev_priv 1249 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 1251 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->refuse_hibernation) dev_priv 1288 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 1295 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_suspend_unlock(&dev_priv->reservation_sem); dev_priv 1296 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = vmw_kms_suspend(dev_priv->dev); dev_priv 1298 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_suspend_lock(&dev_priv->reservation_sem); dev_priv 1302 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->enable_fb) dev_priv 1303 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fb_off(dev_priv); dev_priv 1305 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_suspend_lock(&dev_priv->reservation_sem); dev_priv 1306 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_execbuf_release_pinned_bo(dev_priv); dev_priv 1307 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_resource_evict_all(dev_priv); dev_priv 1308 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_release_device_early(dev_priv); dev_priv 1309 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_bo_swapout_all(&dev_priv->bdev); dev_priv 1310 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->enable_fb) dev_priv 1311 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fifo_resource_dec(dev_priv); dev_priv 1312 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (atomic_read(&dev_priv->num_fifo_resources) != 0) { dev_priv 1314 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->enable_fb) dev_priv 1315 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fifo_resource_inc(dev_priv); dev_priv 1316 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c WARN_ON(vmw_request_device_late(dev_priv)); dev_priv 1317 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->suspend_locked = false; dev_priv 1318 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_suspend_unlock(&dev_priv->reservation_sem); dev_priv 1319 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->suspend_state) dev_priv 1321 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->enable_fb) dev_priv 1322 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fb_on(dev_priv); dev_priv 1326 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fence_fifo_down(dev_priv->fman); dev_priv 1327 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c __vmw_svga_disable(dev_priv); dev_priv 1329 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_release_device_late(dev_priv); dev_priv 1337 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 1340 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); dev_priv 1341 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c (void) vmw_read(dev_priv, SVGA_REG_ID); dev_priv 1343 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->enable_fb) dev_priv 1344 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fifo_resource_inc(dev_priv); dev_priv 1346 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = vmw_request_device(dev_priv); dev_priv 1350 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->enable_fb) dev_priv 1351 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c __vmw_svga_enable(dev_priv); dev_priv 1353 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fence_fifo_up(dev_priv->fman); dev_priv 1354 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c dev_priv->suspend_locked = false; dev_priv 1355 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_suspend_unlock(&dev_priv->reservation_sem); dev_priv 1356 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->suspend_state) dev_priv 1357 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_kms_resume(dev_priv->dev); dev_priv 1359 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c if (dev_priv->enable_fb) dev_priv 1360 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c vmw_fb_on(dev_priv); dev_priv 167 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h struct vmw_private *dev_priv; dev_priv 632 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h static inline void vmw_write(struct vmw_private *dev_priv, dev_priv 635 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h spin_lock(&dev_priv->hw_lock); dev_priv 636 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h outl(offset, dev_priv->io_start + VMWGFX_INDEX_PORT); dev_priv 637 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h outl(value, dev_priv->io_start + VMWGFX_VALUE_PORT); dev_priv 638 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h spin_unlock(&dev_priv->hw_lock); dev_priv 641 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h static inline uint32_t vmw_read(struct vmw_private *dev_priv, dev_priv 646 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h spin_lock(&dev_priv->hw_lock); dev_priv 647 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h outl(offset, dev_priv->io_start + VMWGFX_INDEX_PORT); dev_priv 648 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h val = inl(dev_priv->io_start + VMWGFX_VALUE_PORT); dev_priv 649 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h spin_unlock(&dev_priv->hw_lock); dev_priv 654 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_svga_enable(struct vmw_private *dev_priv); dev_priv 655 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_svga_disable(struct vmw_private *dev_priv); dev_priv 662 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_gmr_bind(struct vmw_private *dev_priv, dev_priv 666 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_gmr_unbind(struct vmw_private *dev_priv, int gmr_id); dev_priv 681 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_user_lookup_handle(struct vmw_private *dev_priv, dev_priv 687 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h struct vmw_private *dev_priv, dev_priv 693 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h vmw_user_resource_noref_lookup_handle(struct vmw_private *dev_priv, dev_priv 702 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_user_stream_lookup(struct vmw_private *dev_priv, dev_priv 715 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_resource_evict_all(struct vmw_private *dev_priv); dev_priv 747 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_bo_pin_in_vram(struct vmw_private *dev_priv, dev_priv 750 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_bo_pin_in_vram_or_gmr(struct vmw_private *dev_priv, dev_priv 763 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_bo_init(struct vmw_private *dev_priv, dev_priv 770 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_user_bo_alloc(struct vmw_private *dev_priv, dev_priv 878 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_fifo_init(struct vmw_private *dev_priv, dev_priv 880 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_fifo_release(struct vmw_private *dev_priv, dev_priv 883 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes, int ctx_id); dev_priv 884 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes); dev_priv 885 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes); dev_priv 886 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_fifo_send_fence(struct vmw_private *dev_priv, dev_priv 889 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason); dev_priv 890 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern bool vmw_fifo_have_3d(struct vmw_private *dev_priv); dev_priv 891 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv); dev_priv 892 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv, dev_priv 894 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_fifo_flush(struct vmw_private *dev_priv, dev_priv 915 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_validation_mem_init_ttm(struct vmw_private *dev_priv, dev_priv 987 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h struct vmw_private *dev_priv, dev_priv 997 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void __vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv, dev_priv 999 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv); dev_priv 1002 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h struct vmw_private *dev_priv, dev_priv 1005 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv, dev_priv 1020 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_wait_seqno(struct vmw_private *dev_priv, bool lazy, dev_priv 1025 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern bool vmw_seqno_passed(struct vmw_private *dev_priv, dev_priv 1027 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_fallback_wait(struct vmw_private *dev_priv, dev_priv 1033 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_update_seqno(struct vmw_private *dev_priv, dev_priv 1035 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_seqno_waiter_add(struct vmw_private *dev_priv); dev_priv 1036 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_seqno_waiter_remove(struct vmw_private *dev_priv); dev_priv 1037 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_goal_waiter_add(struct vmw_private *dev_priv); dev_priv 1038 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_goal_waiter_remove(struct vmw_private *dev_priv); dev_priv 1039 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_generic_waiter_add(struct vmw_private *dev_priv, u32 flag, dev_priv 1041 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_generic_waiter_remove(struct vmw_private *dev_priv, dev_priv 1055 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_wait_lag(struct vmw_private *dev_priv, dev_priv 1063 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_fb_close(struct vmw_private *dev_priv); dev_priv 1071 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_kms_init(struct vmw_private *dev_priv); dev_priv 1072 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_kms_close(struct vmw_private *dev_priv); dev_priv 1077 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv); dev_priv 1085 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv, dev_priv 1091 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_kms_present(struct vmw_private *dev_priv, dev_priv 1100 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h void vmw_kms_legacy_hotspot_clear(struct vmw_private *dev_priv); dev_priv 1123 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_overlay_init(struct vmw_private *dev_priv); dev_priv 1124 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_overlay_close(struct vmw_private *dev_priv); dev_priv 1127 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_overlay_stop_all(struct vmw_private *dev_priv); dev_priv 1128 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_overlay_resume_all(struct vmw_private *dev_priv); dev_priv 1129 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_overlay_pause_all(struct vmw_private *dev_priv); dev_priv 1130 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_overlay_claim(struct vmw_private *dev_priv, uint32_t *out); dev_priv 1131 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_overlay_unref(struct vmw_private *dev_priv, uint32_t stream_id); dev_priv 1132 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_overlay_num_overlays(struct vmw_private *dev_priv); dev_priv 1133 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h int vmw_overlay_num_free_overlays(struct vmw_private *dev_priv); dev_priv 1158 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_mob_bind(struct vmw_private *dev_priv, struct vmw_mob *mob, dev_priv 1161 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_mob_unbind(struct vmw_private *dev_priv, dev_priv 1165 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_otables_setup(struct vmw_private *dev_priv); dev_priv 1166 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_otables_takedown(struct vmw_private *dev_priv); dev_priv 1174 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_context_check(struct vmw_private *dev_priv, dev_priv 1218 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_surface_check(struct vmw_private *dev_priv, dev_priv 1221 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_surface_validate(struct vmw_private *dev_priv, dev_priv 1252 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern int vmw_compat_shader_add(struct vmw_private *dev_priv, dev_priv 1266 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern void vmw_dx_shader_cotable_list_scrub(struct vmw_private *dev_priv, dev_priv 1279 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h vmw_cmdbuf_res_man_create(struct vmw_private *dev_priv); dev_priv 1303 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h extern struct vmw_resource *vmw_cotable_alloc(struct vmw_private *dev_priv, dev_priv 1318 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h vmw_cmdbuf_man_create(struct vmw_private *dev_priv); dev_priv 1450 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h static inline struct ttm_mem_global *vmw_mem_glob(struct vmw_private *dev_priv) dev_priv 1455 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h static inline void vmw_fifo_resource_inc(struct vmw_private *dev_priv) dev_priv 1457 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h atomic_inc(&dev_priv->num_fifo_resources); dev_priv 1460 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h static inline void vmw_fifo_resource_dec(struct vmw_private *dev_priv) dev_priv 1462 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h atomic_dec(&dev_priv->num_fifo_resources); dev_priv 142 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_resource_context_res_add(struct vmw_private *dev_priv, dev_priv 145 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_translate_mob_ptr(struct vmw_private *dev_priv, dev_priv 208 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_ctx_first_setup(struct vmw_private *dev_priv, dev_priv 215 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_resource_context_res_add(dev_priv, sw_context, res); dev_priv 220 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c sw_context->staged_bindings = vmw_binding_state_alloc(dev_priv); dev_priv 229 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c node->staged = vmw_binding_state_alloc(dev_priv); dev_priv 262 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static unsigned int vmw_execbuf_res_size(struct vmw_private *dev_priv, dev_priv 266 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c (res_type == vmw_res_context && dev_priv->has_mob)) ? dev_priv 303 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 320 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c priv_size = vmw_execbuf_res_size(dev_priv, res_type); dev_priv 329 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_ctx_first_setup(dev_priv, sw_context, res, dev_priv 453 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_resource_context_res_add(struct vmw_private *dev_priv, dev_priv 464 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->has_dx && vmw_res_type(ctx) == vmw_res_dx_context) { dev_priv 478 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c mutex_lock(&dev_priv->binding_mutex); dev_priv 492 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->has_dx && vmw_res_type(ctx) == vmw_res_dx_context) { dev_priv 501 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 581 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_invalid(struct vmw_private *dev_priv, dev_priv 588 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_ok(struct vmw_private *dev_priv, dev_priv 642 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_cmd_res_check(struct vmw_private *dev_priv, dev_priv 671 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c unsigned int size = vmw_execbuf_res_size(dev_priv, res_type); dev_priv 678 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c (dev_priv, sw_context->fp->tfile, *id_loc, converter); dev_priv 714 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c struct vmw_private *dev_priv = ctx_res->dev_priv; dev_priv 723 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), ctx_res->id); dev_priv 731 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 828 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_cid_check(struct vmw_private *dev_priv, dev_priv 835 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, dev_priv 868 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_set_render_target_check(struct vmw_private *dev_priv, dev_priv 885 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, dev_priv 891 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 897 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->has_mob) { dev_priv 915 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_surface_copy_check(struct vmw_private *dev_priv, dev_priv 924 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 930 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 935 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_buffer_copy_check(struct vmw_private *dev_priv, dev_priv 943 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 949 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 954 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_pred_copy_check(struct vmw_private *dev_priv, dev_priv 962 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 968 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 973 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_stretch_blt_check(struct vmw_private *dev_priv, dev_priv 981 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 987 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 992 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_blt_surf_screen_check(struct vmw_private *dev_priv, dev_priv 999 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 1004 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_present_check(struct vmw_private *dev_priv, dev_priv 1011 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 1028 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_query_bo_switch_prepare(struct vmw_private *dev_priv, dev_priv 1050 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c dev_priv->has_mob, false); dev_priv 1057 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c dev_priv->dummy_query_bo, dev_priv 1058 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c dev_priv->has_mob, false); dev_priv 1083 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static void vmw_query_bo_switch_commit(struct vmw_private *dev_priv, dev_priv 1099 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_fifo_emit_dummy_query(dev_priv, ctx->id); dev_priv 1105 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->pinned_bo != sw_context->cur_query_bo) { dev_priv 1106 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->pinned_bo) { dev_priv 1107 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_bo_pin_reserved(dev_priv->pinned_bo, false); dev_priv 1108 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_bo_unreference(&dev_priv->pinned_bo); dev_priv 1119 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (!dev_priv->dummy_query_bo_pinned) { dev_priv 1120 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_bo_pin_reserved(dev_priv->dummy_query_bo, dev_priv 1122 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c dev_priv->dummy_query_bo_pinned = true; dev_priv 1126 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c dev_priv->query_cid = sw_context->last_query_ctx->id; dev_priv 1127 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c dev_priv->query_cid_valid = true; dev_priv 1128 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c dev_priv->pinned_bo = dev_priv 1154 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_translate_mob_ptr(struct vmw_private *dev_priv, dev_priv 1209 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_translate_guest_ptr(struct vmw_private *dev_priv, dev_priv 1252 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_define_query(struct vmw_private *dev_priv, dev_priv 1287 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_bind_query(struct vmw_private *dev_priv, dev_priv 1301 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_translate_mob_ptr(dev_priv, sw_context, &cmd->body.mobid, dev_priv 1319 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_begin_gb_query(struct vmw_private *dev_priv, dev_priv 1326 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, dev_priv 1338 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_begin_query(struct vmw_private *dev_priv, dev_priv 1345 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (unlikely(dev_priv->has_mob)) { dev_priv 1356 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_begin_gb_query(dev_priv, sw_context, header); dev_priv 1359 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, dev_priv 1371 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_end_gb_query(struct vmw_private *dev_priv, dev_priv 1380 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_cid_check(dev_priv, sw_context, header); dev_priv 1384 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_translate_mob_ptr(dev_priv, sw_context, &cmd->body.mobid, dev_priv 1389 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_query_bo_switch_prepare(dev_priv, vmw_bo, sw_context); dev_priv 1401 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_end_query(struct vmw_private *dev_priv, dev_priv 1410 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->has_mob) { dev_priv 1423 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_end_gb_query(dev_priv, sw_context, header); dev_priv 1426 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_cid_check(dev_priv, sw_context, header); dev_priv 1430 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_translate_guest_ptr(dev_priv, sw_context, dev_priv 1435 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_query_bo_switch_prepare(dev_priv, vmw_bo, sw_context); dev_priv 1447 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_wait_gb_query(struct vmw_private *dev_priv, dev_priv 1456 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_cid_check(dev_priv, sw_context, header); dev_priv 1460 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_translate_mob_ptr(dev_priv, sw_context, &cmd->body.mobid, dev_priv 1475 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_wait_query(struct vmw_private *dev_priv, dev_priv 1484 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->has_mob) { dev_priv 1497 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_wait_gb_query(dev_priv, sw_context, header); dev_priv 1500 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_cid_check(dev_priv, sw_context, header); dev_priv 1504 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_translate_guest_ptr(dev_priv, sw_context, dev_priv 1512 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dma(struct vmw_private *dev_priv, dev_priv 1534 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_translate_guest_ptr(dev_priv, sw_context, dev_priv 1552 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 1568 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_draw(struct vmw_private *dev_priv, dev_priv 1580 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_cid_check(dev_priv, sw_context, header); dev_priv 1593 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 1610 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 1620 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_tex_state(struct vmw_private *dev_priv, dev_priv 1635 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, dev_priv 1651 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 1658 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->has_mob) { dev_priv 1678 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_check_define_gmrfb(struct vmw_private *dev_priv, dev_priv 1689 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_translate_guest_ptr(dev_priv, sw_context, &cmd->body.ptr, dev_priv 1708 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_res_switch_backup(struct vmw_private *dev_priv, dev_priv 1721 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_translate_mob_ptr(dev_priv, sw_context, buf_id, &vbo); dev_priv 1746 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_switch_backup(struct vmw_private *dev_priv, dev_priv 1756 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, res_type, dev_priv 1761 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_switch_backup(dev_priv, sw_context, res, buf_id, dev_priv 1772 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_bind_gb_surface(struct vmw_private *dev_priv, dev_priv 1779 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_switch_backup(dev_priv, sw_context, vmw_res_surface, dev_priv 1791 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_update_gb_image(struct vmw_private *dev_priv, dev_priv 1798 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 1810 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_update_gb_surface(struct vmw_private *dev_priv, dev_priv 1817 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 1829 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_readback_gb_image(struct vmw_private *dev_priv, dev_priv 1836 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 1849 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_readback_gb_surface(struct vmw_private *dev_priv, dev_priv 1856 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 1869 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_invalidate_gb_image(struct vmw_private *dev_priv, dev_priv 1876 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 1889 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_invalidate_gb_surface(struct vmw_private *dev_priv, dev_priv 1896 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 1908 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_shader_define(struct vmw_private *dev_priv, dev_priv 1919 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, dev_priv 1925 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (unlikely(!dev_priv->has_mob)) dev_priv 1929 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_compat_shader_add(dev_priv, vmw_context_res_man(ctx), dev_priv 1948 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_shader_destroy(struct vmw_private *dev_priv, dev_priv 1958 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, dev_priv 1964 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (unlikely(!dev_priv->has_mob)) dev_priv 1985 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_set_shader(struct vmw_private *dev_priv, dev_priv 2003 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, dev_priv 2009 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (!dev_priv->has_mob) dev_priv 2037 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_shader, dev_priv 2065 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_set_shader_const(struct vmw_private *dev_priv, dev_priv 2074 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, dev_priv 2080 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->has_mob) dev_priv 2093 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_bind_gb_shader(struct vmw_private *dev_priv, dev_priv 2100 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_switch_backup(dev_priv, sw_context, vmw_res_shader, dev_priv 2114 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_cmd_dx_set_single_constant_buffer(struct vmw_private *dev_priv, dev_priv 2128 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 2164 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_set_shader_res(struct vmw_private *dev_priv, dev_priv 2194 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_set_shader(struct vmw_private *dev_priv, dev_priv 2247 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_set_vertex_buffers(struct vmw_private *dev_priv, dev_priv 2274 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 2302 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_set_index_buffer(struct vmw_private *dev_priv, dev_priv 2316 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 2341 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_set_rendertargets(struct vmw_private *dev_priv, dev_priv 2374 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_clear_rendertarget_view(struct vmw_private *dev_priv, dev_priv 2393 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_clear_depthstencil_view(struct vmw_private *dev_priv, dev_priv 2404 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_view_define(struct vmw_private *dev_priv, dev_priv 2435 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 2459 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_set_so_targets(struct vmw_private *dev_priv, dev_priv 2485 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 2505 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_so_define(struct vmw_private *dev_priv, dev_priv 2541 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_check_subresource(struct vmw_private *dev_priv, dev_priv 2564 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 2569 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_cid_check(struct vmw_private *dev_priv, dev_priv 2592 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_view_remove(struct vmw_private *dev_priv, dev_priv 2632 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_define_shader(struct vmw_private *dev_priv, dev_priv 2662 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_destroy_shader(struct vmw_private *dev_priv, dev_priv 2687 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_bind_shader(struct vmw_private *dev_priv, dev_priv 2698 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context, dev_priv 2727 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_switch_backup(dev_priv, sw_context, res, dev_priv 2739 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_genmips(struct vmw_private *dev_priv, dev_priv 2758 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_dx_transfer_from_buffer(struct vmw_private *dev_priv, dev_priv 2766 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 2772 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 2784 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_intra_surface_copy(struct vmw_private *dev_priv, dev_priv 2791 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (!(dev_priv->capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY)) dev_priv 2794 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface, dev_priv 2799 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv, dev_priv 2837 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_check_define_gmrfb(dev_priv, sw_context, buf); dev_priv 3201 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_check(struct vmw_private *dev_priv, dev_priv 3210 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c bool gb = dev_priv->capabilities & SVGA_CAP_GBOBJECTS; dev_priv 3215 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c return vmw_cmd_check_not_3d(dev_priv, sw_context, buf, size); dev_priv 3241 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = entry->func(dev_priv, sw_context, header); dev_priv 3267 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_cmd_check_all(struct vmw_private *dev_priv, dev_priv 3278 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_check(dev_priv, sw_context, buf, &size); dev_priv 3363 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c struct vmw_private *dev_priv, dev_priv 3374 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_fifo_send_fence(dev_priv, &sequence); dev_priv 3381 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_user_fence_create(file_priv, dev_priv->fman, dev_priv 3384 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_fence_create(dev_priv->fman, sequence, p_fence); dev_priv 3387 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c (void) vmw_fallback_wait(dev_priv, false, false, sequence, dev_priv 3417 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv, dev_priv 3437 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_update_seqno(dev_priv, &dev_priv->fifo); dev_priv 3438 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c fence_rep.passed_seqno = dev_priv->last_read_seqno; dev_priv 3481 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_execbuf_submit_fifo(struct vmw_private *dev_priv, dev_priv 3488 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c cmd = VMW_FIFO_RESERVE_DX(dev_priv, command_size, dev_priv 3491 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c cmd = VMW_FIFO_RESERVE(dev_priv, command_size); dev_priv 3500 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_fifo_commit(dev_priv, command_size); dev_priv 3517 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_execbuf_submit_cmdbuf(struct vmw_private *dev_priv, dev_priv 3524 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c void *cmd = vmw_cmdbuf_reserve(dev_priv->cman, command_size, id, false, dev_priv 3530 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_cmdbuf_commit(dev_priv->cman, command_size, header, false); dev_priv 3559 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static void *vmw_execbuf_cmdbuf(struct vmw_private *dev_priv, dev_priv 3573 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (!dev_priv->cman || kernel_commands) dev_priv 3579 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c kernel_commands = vmw_cmdbuf_alloc(dev_priv->cman, cmdbuf_size, true, dev_priv 3595 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static int vmw_execbuf_tie_context(struct vmw_private *dev_priv, dev_priv 3606 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c size = vmw_execbuf_res_size(dev_priv, vmw_res_dx_context); dev_priv 3612 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c (dev_priv, sw_context->fp->tfile, handle, dev_priv 3631 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c struct vmw_private *dev_priv, dev_priv 3638 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c struct vmw_sw_context *sw_context = &dev_priv->ctx; dev_priv 3647 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_validation_set_val_mem(&val_ctx, &dev_priv->vvm); dev_priv 3658 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_wait_lag(dev_priv, &dev_priv->fifo.marker_queue, dev_priv 3665 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c kernel_commands = vmw_execbuf_cmdbuf(dev_priv, user_commands, dev_priv 3673 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex); dev_priv 3700 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c sw_context->cur_query_bo = dev_priv->pinned_bo; dev_priv 3723 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_execbuf_tie_context(dev_priv, sw_context, dx_context_handle); dev_priv 3727 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_cmd_check_all(dev_priv, sw_context, kernel_commands, dev_priv 3750 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = mutex_lock_interruptible(&dev_priv->binding_mutex); dev_priv 3756 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->has_mob) { dev_priv 3763 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_execbuf_submit_fifo(dev_priv, kernel_commands, dev_priv 3766 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_execbuf_submit_cmdbuf(dev_priv, header, command_size, dev_priv 3770 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 3774 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_query_bo_switch_commit(dev_priv, sw_context); dev_priv 3775 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_execbuf_fence_commands(file_priv, dev_priv, &fence, dev_priv 3791 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (unlikely(dev_priv->pinned_bo != NULL && !dev_priv->query_cid_valid)) dev_priv 3792 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c __vmw_execbuf_release_pinned_bo(dev_priv, fence); dev_priv 3815 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_execbuf_copy_fence_user(dev_priv, vmw_fpriv(file_priv), ret, dev_priv 3828 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c mutex_unlock(&dev_priv->cmdbuf_mutex); dev_priv 3839 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 3847 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (unlikely(dev_priv->pinned_bo != NULL && !dev_priv->query_cid_valid)) dev_priv 3848 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c __vmw_execbuf_release_pinned_bo(dev_priv, NULL); dev_priv 3853 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c mutex_unlock(&dev_priv->cmdbuf_mutex); dev_priv 3879 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c static void vmw_execbuf_unpin_panic(struct vmw_private *dev_priv) dev_priv 3883 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c (void) vmw_fallback_wait(dev_priv, false, true, 0, false, 10*HZ); dev_priv 3884 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_bo_pin_reserved(dev_priv->pinned_bo, false); dev_priv 3885 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->dummy_query_bo_pinned) { dev_priv 3886 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_bo_pin_reserved(dev_priv->dummy_query_bo, false); dev_priv 3887 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c dev_priv->dummy_query_bo_pinned = false; dev_priv 3915 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c void __vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv, dev_priv 3922 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->pinned_bo == NULL) dev_priv 3925 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_validation_add_bo(&val_ctx, dev_priv->pinned_bo, false, dev_priv 3930 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_validation_add_bo(&val_ctx, dev_priv->dummy_query_bo, false, dev_priv 3939 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->query_cid_valid) { dev_priv 3941 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_fifo_emit_dummy_query(dev_priv, dev_priv->query_cid); dev_priv 3944 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c dev_priv->query_cid_valid = false; dev_priv 3947 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_bo_pin_reserved(dev_priv->pinned_bo, false); dev_priv 3948 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->dummy_query_bo_pinned) { dev_priv 3949 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_bo_pin_reserved(dev_priv->dummy_query_bo, false); dev_priv 3950 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c dev_priv->dummy_query_bo_pinned = false; dev_priv 3953 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c (void) vmw_execbuf_fence_commands(NULL, dev_priv, &lfence, dev_priv 3962 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_bo_unreference(&dev_priv->pinned_bo); dev_priv 3970 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_execbuf_unpin_panic(dev_priv); dev_priv 3971 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_bo_unreference(&dev_priv->pinned_bo); dev_priv 3990 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c void vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv) dev_priv 3992 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c mutex_lock(&dev_priv->cmdbuf_mutex); dev_priv 3993 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (dev_priv->query_cid_valid) dev_priv 3994 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c __vmw_execbuf_release_pinned_bo(dev_priv, NULL); dev_priv 3995 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c mutex_unlock(&dev_priv->cmdbuf_mutex); dev_priv 4001 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 4038 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_wait_dma_fence(dev_priv->fman, in_fence); dev_priv 4043 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = ttm_read_lock(&dev_priv->reservation_sem, true); dev_priv 4047 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ret = vmw_execbuf_process(file_priv, dev_priv, dev_priv 4054 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 4058 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_kms_cursor_post_execbuf(dev_priv); dev_priv 36 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct vmw_private *dev_priv; dev_priv 142 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct vmw_private *dev_priv = fman->dev_priv; dev_priv 144 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c u32 *fifo_mem = dev_priv->mmio_virt; dev_priv 149 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); dev_priv 176 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct vmw_private *dev_priv = fman->dev_priv; dev_priv 183 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); dev_priv 184 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c vmw_seqno_waiter_add(dev_priv); dev_priv 240 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c vmw_seqno_waiter_remove(dev_priv); dev_priv 279 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c vmw_goal_waiter_remove(fman->dev_priv); dev_priv 300 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct vmw_fence_manager *vmw_fence_manager_init(struct vmw_private *dev_priv) dev_priv 307 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c fman->dev_priv = dev_priv; dev_priv 410 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c fifo_mem = fman->dev_priv->mmio_virt; dev_priv 453 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c fifo_mem = fman->dev_priv->mmio_virt; dev_priv 471 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c u32 *fifo_mem = fman->dev_priv->mmio_virt; dev_priv 540 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct vmw_private *dev_priv = fman_from_fence(fence)->dev_priv; dev_priv 542 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); dev_priv 585 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c ttm_mem_global_free(vmw_mem_glob(fman->dev_priv), dev_priv 609 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct ttm_mem_global *mem_glob = vmw_mem_glob(fman->dev_priv); dev_priv 864 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 877 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c arg->passed_seqno = dev_priv->last_read_seqno; dev_priv 992 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c vmw_goal_waiter_add(fman->dev_priv); dev_priv 1036 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c eaction->dev = fman->dev_priv->dev; dev_priv 1058 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct drm_device *dev = fman->dev_priv->dev; dev_priv 1106 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 1151 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c ret = vmw_execbuf_fence_commands(file_priv, dev_priv, dev_priv 1173 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c vmw_execbuf_copy_fence_user(dev_priv, vmw_fp, 0, user_fence_rep, fence, dev_priv 67 drivers/gpu/drm/vmwgfx/vmwgfx_fence.h vmw_fence_manager_init(struct vmw_private *dev_priv); dev_priv 39 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c bool vmw_fifo_have_3d(struct vmw_private *dev_priv) dev_priv 41 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c u32 *fifo_mem = dev_priv->mmio_virt; dev_priv 43 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c const struct vmw_fifo_state *fifo = &dev_priv->fifo; dev_priv 45 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (!(dev_priv->capabilities & SVGA_CAP_3D)) dev_priv 48 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { dev_priv 51 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (!dev_priv->has_mob) dev_priv 54 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c spin_lock(&dev_priv->cap_lock); dev_priv 55 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D); dev_priv 56 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c result = vmw_read(dev_priv, SVGA_REG_DEV_CAP); dev_priv 57 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c spin_unlock(&dev_priv->cap_lock); dev_priv 62 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) dev_priv 82 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (dev_priv->active_display_unit == vmw_du_legacy) dev_priv 88 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv) dev_priv 90 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c u32 *fifo_mem = dev_priv->mmio_virt; dev_priv 93 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) dev_priv 103 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) dev_priv 105 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c u32 *fifo_mem = dev_priv->mmio_virt; dev_priv 122 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH)); dev_priv 123 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT)); dev_priv 124 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL)); dev_priv 126 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); dev_priv 127 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); dev_priv 128 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); dev_priv 130 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | dev_priv 132 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_write(dev_priv, SVGA_REG_TRACES, 0); dev_priv 135 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO) dev_priv 136 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); dev_priv 143 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_mmio_write(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX); dev_priv 150 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); dev_priv 161 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); dev_priv 162 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_mmio_write(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE); dev_priv 168 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason) dev_priv 170 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c u32 *fifo_mem = dev_priv->mmio_virt; dev_priv 174 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_write(dev_priv, SVGA_REG_SYNC, reason); dev_priv 178 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) dev_priv 180 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c u32 *fifo_mem = dev_priv->mmio_virt; dev_priv 182 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); dev_priv 183 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) dev_priv 186 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c dev_priv->last_read_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE); dev_priv 188 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, dev_priv 189 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c dev_priv->config_done_state); dev_priv 190 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_write(dev_priv, SVGA_REG_ENABLE, dev_priv 191 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c dev_priv->enable_state); dev_priv 192 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_write(dev_priv, SVGA_REG_TRACES, dev_priv 193 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c dev_priv->traces_state); dev_priv 208 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes) dev_priv 210 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c u32 *fifo_mem = dev_priv->mmio_virt; dev_priv 219 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv, dev_priv 230 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c prepare_to_wait(&dev_priv->fifo_queue, &__wait, dev_priv 233 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (!vmw_fifo_is_full(dev_priv, bytes)) dev_priv 246 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c finish_wait(&dev_priv->fifo_queue, &__wait); dev_priv 247 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c wake_up_all(&dev_priv->fifo_queue); dev_priv 252 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c static int vmw_fifo_wait(struct vmw_private *dev_priv, dev_priv 258 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (likely(!vmw_fifo_is_full(dev_priv, bytes))) dev_priv 261 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL); dev_priv 262 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) dev_priv 263 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c return vmw_fifo_wait_noirq(dev_priv, bytes, dev_priv 266 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS, dev_priv 267 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c &dev_priv->fifo_queue_waiters); dev_priv 271 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c (dev_priv->fifo_queue, dev_priv 272 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c !vmw_fifo_is_full(dev_priv, bytes), timeout); dev_priv 275 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c (dev_priv->fifo_queue, dev_priv 276 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c !vmw_fifo_is_full(dev_priv, bytes), timeout); dev_priv 283 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS, dev_priv 284 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c &dev_priv->fifo_queue_waiters); dev_priv 299 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv, dev_priv 302 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c struct vmw_fifo_state *fifo_state = &dev_priv->fifo; dev_priv 303 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c u32 *fifo_mem = dev_priv->mmio_virt; dev_priv 333 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c else if (vmw_fifo_is_full(dev_priv, bytes)) { dev_priv 334 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c ret = vmw_fifo_wait(dev_priv, bytes, dev_priv 346 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c ret = vmw_fifo_wait(dev_priv, bytes, dev_priv 386 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c void *vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes, dev_priv 391 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (dev_priv->cman) dev_priv 392 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c ret = vmw_cmdbuf_reserve(dev_priv->cman, bytes, dev_priv 395 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c ret = vmw_local_fifo_reserve(dev_priv, bytes); dev_priv 447 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) dev_priv 449 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c struct vmw_fifo_state *fifo_state = &dev_priv->fifo; dev_priv 450 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c u32 *fifo_mem = dev_priv->mmio_virt; dev_priv 493 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); dev_priv 497 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) dev_priv 499 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (dev_priv->cman) dev_priv 500 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false); dev_priv 502 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_local_fifo_commit(dev_priv, bytes); dev_priv 512 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes) dev_priv 514 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (dev_priv->cman) dev_priv 515 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true); dev_priv 517 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_local_fifo_commit(dev_priv, bytes); dev_priv 527 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible) dev_priv 531 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (dev_priv->cman) dev_priv 532 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c return vmw_cmdbuf_cur_flush(dev_priv->cman, interruptible); dev_priv 537 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno) dev_priv 539 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c struct vmw_fifo_state *fifo_state = &dev_priv->fifo; dev_priv 545 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c fm = VMW_FIFO_RESERVE(dev_priv, bytes); dev_priv 547 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c *seqno = atomic_read(&dev_priv->marker_seq); dev_priv 549 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c (void)vmw_fallback_wait(dev_priv, false, true, *seqno, dev_priv 555 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c *seqno = atomic_add_return(1, &dev_priv->marker_seq); dev_priv 565 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_fifo_commit(dev_priv, 0); dev_priv 572 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_fifo_commit_flush(dev_priv, bytes); dev_priv 574 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_update_seqno(dev_priv, fifo_state); dev_priv 589 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv, dev_priv 598 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base; dev_priv 604 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 621 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 635 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv, dev_priv 644 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base; dev_priv 650 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 662 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 686 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv, dev_priv 689 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (dev_priv->has_mob) dev_priv 690 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c return vmw_fifo_emit_dummy_gb_query(dev_priv, cid); dev_priv 692 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid); dev_priv 38 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c static int vmw_gmr2_bind(struct vmw_private *dev_priv, dev_priv 54 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c cmd_orig = cmd = VMW_FIFO_RESERVE(dev_priv, cmd_size); dev_priv 101 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c vmw_fifo_commit(dev_priv, cmd_size); dev_priv 106 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c static void vmw_gmr2_unbind(struct vmw_private *dev_priv, dev_priv 113 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c cmd = VMW_FIFO_RESERVE(dev_priv, define_size); dev_priv 123 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c vmw_fifo_commit(dev_priv, define_size); dev_priv 127 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c int vmw_gmr_bind(struct vmw_private *dev_priv, dev_priv 139 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c if (unlikely(!(dev_priv->capabilities & SVGA_CAP_GMR2))) dev_priv 142 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c return vmw_gmr2_bind(dev_priv, &data_iter, num_pages, gmr_id); dev_priv 146 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c void vmw_gmr_unbind(struct vmw_private *dev_priv, int gmr_id) dev_priv 148 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c if (likely(dev_priv->capabilities & SVGA_CAP_GMR2)) dev_priv 149 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c vmw_gmr2_unbind(dev_priv, gmr_id); dev_priv 102 drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c struct vmw_private *dev_priv = dev_priv 116 drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c gman->max_gmr_ids = dev_priv->max_gmr_ids; dev_priv 117 drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c gman->max_gmr_pages = dev_priv->max_gmr_pages; dev_priv 121 drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c gman->max_gmr_pages = dev_priv->max_mob_pages; dev_priv 41 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 48 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = vmw_overlay_num_overlays(dev_priv); dev_priv 51 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = vmw_overlay_num_free_overlays(dev_priv); dev_priv 54 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = vmw_fifo_have_3d(dev_priv) ? 1 : 0; dev_priv 57 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = dev_priv->capabilities; dev_priv 60 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = dev_priv->capabilities2; dev_priv 63 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = dev_priv->fifo.capabilities; dev_priv 66 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = dev_priv->prim_bb_mem; dev_priv 70 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c u32 *fifo_mem = dev_priv->mmio_virt; dev_priv 71 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c const struct vmw_fifo_state *fifo = &dev_priv->fifo; dev_priv 73 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS)) { dev_priv 87 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS) && dev_priv 89 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = dev_priv->max_mob_pages * PAGE_SIZE / 2; dev_priv 91 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = dev_priv->memory_size; dev_priv 94 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS) && dev_priv 97 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c else if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) dev_priv 107 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = dev_priv->max_mob_pages * PAGE_SIZE; dev_priv 110 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = dev_priv->max_mob_size; dev_priv 114 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c (dev_priv->active_display_unit == vmw_du_screen_target); dev_priv 117 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = dev_priv->has_dx; dev_priv 120 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c param->value = dev_priv->has_sm4_1; dev_priv 142 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c static int vmw_fill_compat_cap(struct vmw_private *dev_priv, void *bounce, dev_priv 163 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c spin_lock(&dev_priv->cap_lock); dev_priv 165 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c vmw_write(dev_priv, SVGA_REG_DEV_CAP, i); dev_priv 168 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c (i, vmw_read(dev_priv, SVGA_REG_DEV_CAP)); dev_priv 170 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c spin_unlock(&dev_priv->cap_lock); dev_priv 181 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 187 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c bool gb_objects = !!(dev_priv->capabilities & SVGA_CAP_GBOBJECTS); dev_priv 220 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c spin_lock(&dev_priv->cap_lock); dev_priv 222 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c vmw_write(dev_priv, SVGA_REG_DEV_CAP, i); dev_priv 224 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c (i, vmw_read(dev_priv, SVGA_REG_DEV_CAP)); dev_priv 226 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c spin_unlock(&dev_priv->cap_lock); dev_priv 228 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c ret = vmw_fill_compat_cap(dev_priv, bounce, size); dev_priv 232 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c fifo_mem = dev_priv->mmio_virt; dev_priv 252 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 300 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c ret = ttm_read_lock(&dev_priv->reservation_sem, true); dev_priv 304 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c ret = vmw_user_resource_lookup_handle(dev_priv, tfile, arg->sid, dev_priv 311 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c ret = vmw_kms_present(dev_priv, file_priv, dev_priv 320 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 334 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 389 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c ret = ttm_read_lock(&dev_priv->reservation_sem, true); dev_priv 393 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c ret = vmw_kms_readback(dev_priv, file_priv, dev_priv 397 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 421 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c struct vmw_private *dev_priv = dev_priv 424 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); dev_priv 444 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c struct vmw_private *dev_priv = dev_priv 447 drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); dev_priv 48 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 52 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c dev_priv->irqthread_pending)) { dev_priv 53 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_fences_update(dev_priv->fman); dev_priv 54 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c wake_up_all(&dev_priv->fence_queue); dev_priv 59 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c dev_priv->irqthread_pending)) { dev_priv 60 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_cmdbuf_irqthread(dev_priv->cman); dev_priv 81 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 85 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); dev_priv 86 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c masked_status = status & READ_ONCE(dev_priv->irq_mask); dev_priv 89 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); dev_priv 95 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c wake_up_all(&dev_priv->fifo_queue); dev_priv 99 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c !test_and_set_bit(VMW_IRQTHREAD_FENCE, dev_priv->irqthread_pending)) dev_priv 105 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c dev_priv->irqthread_pending)) dev_priv 111 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno) dev_priv 114 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0); dev_priv 117 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c void vmw_update_seqno(struct vmw_private *dev_priv, dev_priv 120 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c u32 *fifo_mem = dev_priv->mmio_virt; dev_priv 123 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c if (dev_priv->last_read_seqno != seqno) { dev_priv 124 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c dev_priv->last_read_seqno = seqno; dev_priv 126 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_fences_update(dev_priv->fman); dev_priv 130 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c bool vmw_seqno_passed(struct vmw_private *dev_priv, dev_priv 136 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) dev_priv 139 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c fifo_state = &dev_priv->fifo; dev_priv 140 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_update_seqno(dev_priv, fifo_state); dev_priv 141 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) dev_priv 145 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_fifo_idle(dev_priv, seqno)) dev_priv 153 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c ret = ((atomic_read(&dev_priv->marker_seq) - seqno) dev_priv 159 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c int vmw_fallback_wait(struct vmw_private *dev_priv, dev_priv 166 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c struct vmw_fifo_state *fifo_state = &dev_priv->fifo; dev_priv 184 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c if (dev_priv->cman) { dev_priv 185 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c ret = vmw_cmdbuf_idle(dev_priv->cman, interruptible, dev_priv 192 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c signal_seq = atomic_read(&dev_priv->marker_seq); dev_priv 196 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c prepare_to_wait(&dev_priv->fence_queue, &__wait, dev_priv 199 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c if (wait_condition(dev_priv, seqno)) dev_priv 224 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c finish_wait(&dev_priv->fence_queue, &__wait); dev_priv 226 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c u32 *fifo_mem = dev_priv->mmio_virt; dev_priv 230 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c wake_up_all(&dev_priv->fence_queue); dev_priv 238 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c void vmw_generic_waiter_add(struct vmw_private *dev_priv, dev_priv 241 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c spin_lock_bh(&dev_priv->waiter_lock); dev_priv 243 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c outl(flag, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); dev_priv 244 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c dev_priv->irq_mask |= flag; dev_priv 245 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); dev_priv 247 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c spin_unlock_bh(&dev_priv->waiter_lock); dev_priv 250 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c void vmw_generic_waiter_remove(struct vmw_private *dev_priv, dev_priv 253 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c spin_lock_bh(&dev_priv->waiter_lock); dev_priv 255 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c dev_priv->irq_mask &= ~flag; dev_priv 256 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); dev_priv 258 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c spin_unlock_bh(&dev_priv->waiter_lock); dev_priv 261 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c void vmw_seqno_waiter_add(struct vmw_private *dev_priv) dev_priv 263 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ANY_FENCE, dev_priv 264 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c &dev_priv->fence_queue_waiters); dev_priv 267 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c void vmw_seqno_waiter_remove(struct vmw_private *dev_priv) dev_priv 269 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_ANY_FENCE, dev_priv 270 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c &dev_priv->fence_queue_waiters); dev_priv 273 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c void vmw_goal_waiter_add(struct vmw_private *dev_priv) dev_priv 275 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FENCE_GOAL, dev_priv 276 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c &dev_priv->goal_queue_waiters); dev_priv 279 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c void vmw_goal_waiter_remove(struct vmw_private *dev_priv) dev_priv 281 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FENCE_GOAL, dev_priv 282 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c &dev_priv->goal_queue_waiters); dev_priv 285 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c int vmw_wait_seqno(struct vmw_private *dev_priv, dev_priv 290 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c struct vmw_fifo_state *fifo = &dev_priv->fifo; dev_priv 292 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) dev_priv 295 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c if (likely(vmw_seqno_passed(dev_priv, seqno))) dev_priv 298 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); dev_priv 301 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c return vmw_fallback_wait(dev_priv, lazy, true, seqno, dev_priv 304 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) dev_priv 305 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c return vmw_fallback_wait(dev_priv, lazy, false, seqno, dev_priv 308 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_seqno_waiter_add(dev_priv); dev_priv 312 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c (dev_priv->fence_queue, dev_priv 313 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_seqno_passed(dev_priv, seqno), dev_priv 317 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c (dev_priv->fence_queue, dev_priv 318 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_seqno_passed(dev_priv, seqno), dev_priv 321 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_seqno_waiter_remove(dev_priv); dev_priv 333 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 336 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); dev_priv 337 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); dev_priv 342 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 345 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) dev_priv 351 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_write(dev_priv, SVGA_REG_IRQMASK, 0); dev_priv 353 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); dev_priv 354 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); dev_priv 57 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c static int vmw_cursor_update_image(struct vmw_private *dev_priv, dev_priv 71 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c cmd = VMW_FIFO_RESERVE(dev_priv, cmd_size); dev_priv 86 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_fifo_commit_flush(dev_priv, cmd_size); dev_priv 91 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c static int vmw_cursor_update_bo(struct vmw_private *dev_priv, dev_priv 117 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_cursor_update_image(dev_priv, virtual, width, height, dev_priv 128 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c static void vmw_cursor_update_position(struct vmw_private *dev_priv, dev_priv 131 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c u32 *fifo_mem = dev_priv->mmio_virt; dev_priv 134 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c spin_lock(&dev_priv->cursor_lock); dev_priv 140 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c spin_unlock(&dev_priv->cursor_lock); dev_priv 237 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c void vmw_kms_legacy_hotspot_clear(struct vmw_private *dev_priv) dev_priv 239 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct drm_device *dev = dev_priv->dev; dev_priv 253 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv) dev_priv 255 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct drm_device *dev = dev_priv->dev; dev_priv 268 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_cursor_update_image(dev_priv, dev_priv 380 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(crtc->dev); dev_priv 401 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_cursor_update_image(dev_priv, dev_priv 406 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_cursor_update_bo(dev_priv, vps->bo, dev_priv 411 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_cursor_update_position(dev_priv, false, 0, 0); dev_priv 419 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_cursor_update_position(dev_priv, true, dev_priv 855 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c int vmw_kms_readback(struct vmw_private *dev_priv, dev_priv 862 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c switch (dev_priv->active_display_unit) { dev_priv 864 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c return vmw_kms_sou_readback(dev_priv, file_priv, vfb, dev_priv 868 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c return vmw_kms_stdu_dma(dev_priv, file_priv, vfb, dev_priv 885 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv, dev_priv 893 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct drm_device *dev = dev_priv->dev; dev_priv 900 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (dev_priv->active_display_unit == vmw_du_legacy) dev_priv 944 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (!dev_priv->has_dx && format != surface->format) { dev_priv 999 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(framebuffer->dev); dev_priv 1005 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_modeset_lock_all(dev_priv->dev); dev_priv 1007 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = ttm_read_lock(&dev_priv->reservation_sem, true); dev_priv 1009 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_modeset_unlock_all(dev_priv->dev); dev_priv 1024 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c switch (dev_priv->active_display_unit) { dev_priv 1026 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_kms_ldu_do_bo_dirty(dev_priv, &vfbd->base, 0, 0, dev_priv 1035 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_fifo_flush(dev_priv, false); dev_priv 1036 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 1038 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_modeset_unlock_all(dev_priv->dev); dev_priv 1049 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(framebuffer->dev); dev_priv 1051 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (dev_priv->active_display_unit == vmw_du_legacy) dev_priv 1070 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(vfb->base.dev); dev_priv 1081 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c switch (dev_priv->active_display_unit) { dev_priv 1083 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_overlay_pause_all(dev_priv); dev_priv 1084 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_bo_pin_in_start_of_vram(dev_priv, buf, false); dev_priv 1085 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_overlay_resume_all(dev_priv); dev_priv 1090 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (dev_priv->capabilities & SVGA_CAP_3D) { dev_priv 1105 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c return vmw_bo_pin_in_placement(dev_priv, buf, placement, false); dev_priv 1115 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(vfb->base.dev); dev_priv 1124 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c return vmw_bo_unpin(dev_priv, buf, false); dev_priv 1202 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c mutex_lock(&res->dev_priv->cmdbuf_mutex); dev_priv 1208 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c mutex_unlock(&res->dev_priv->cmdbuf_mutex); dev_priv 1215 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c static int vmw_kms_new_framebuffer_bo(struct vmw_private *dev_priv, dev_priv 1222 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct drm_device *dev = dev_priv->dev; dev_priv 1236 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (dev_priv->active_display_unit == vmw_du_screen_object) { dev_priv 1287 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_kms_srf_ok(struct vmw_private *dev_priv, uint32_t width, uint32_t height) dev_priv 1289 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (width > dev_priv->texture_max_width || dev_priv 1290 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c height > dev_priv->texture_max_height) dev_priv 1309 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_kms_new_framebuffer(struct vmw_private *dev_priv, dev_priv 1324 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (vmw_kms_srf_ok(dev_priv, mode_cmd->width, mode_cmd->height) && dev_priv 1327 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c dev_priv->active_display_unit == vmw_du_screen_target) { dev_priv 1328 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_create_bo_proxy(dev_priv->dev, mode_cmd, dev_priv 1338 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_kms_new_framebuffer_surface(dev_priv, surface, &vfb, dev_priv 1349 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_kms_new_framebuffer_bo(dev_priv, bo, &vfb, dev_priv 1372 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 1400 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_user_lookup_handle(dev_priv, tfile, dev_priv 1408 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c !vmw_kms_srf_ok(dev_priv, mode_cmd->width, mode_cmd->height)) { dev_priv 1410 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c dev_priv->texture_max_width, dev_priv 1411 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c dev_priv->texture_max_height); dev_priv 1416 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vfb = vmw_kms_new_framebuffer(dev_priv, bo, surface, dev_priv 1417 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c !(dev_priv->capabilities & SVGA_CAP_3D), dev_priv 1456 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 1466 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (dev_priv->active_display_unit == vmw_du_screen_target && dev_priv 1467 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c (drm_rect_width(&rects[i]) > dev_priv->stdu_max_width || dev_priv 1468 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_rect_height(&rects[i]) > dev_priv->stdu_max_height)) { dev_priv 1492 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (pixel_mem > dev_priv->prim_bb_mem) { dev_priv 1498 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (dev_priv->active_display_unit != vmw_du_screen_target || dev_priv 1499 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c !(dev_priv->capabilities & SVGA_CAP_NO_BB_RESTRICTION)) { dev_priv 1502 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (bb_mem > dev_priv->prim_bb_mem) { dev_priv 1731 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c static int vmw_kms_generic_present(struct vmw_private *dev_priv, dev_priv 1740 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c return vmw_kms_sou_do_surface_dirty(dev_priv, vfb, NULL, clips, dev_priv 1746 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c int vmw_kms_present(struct vmw_private *dev_priv, dev_priv 1757 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c switch (dev_priv->active_display_unit) { dev_priv 1759 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_kms_stdu_surface_dirty(dev_priv, vfb, NULL, clips, dev_priv 1764 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_kms_generic_present(dev_priv, file_priv, vfb, surface, dev_priv 1777 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_fifo_flush(dev_priv, false); dev_priv 1783 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_kms_create_hotplug_mode_update_property(struct vmw_private *dev_priv) dev_priv 1785 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (dev_priv->hotplug_mode_update_property) dev_priv 1788 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c dev_priv->hotplug_mode_update_property = dev_priv 1789 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_property_create_range(dev_priv->dev, dev_priv 1793 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (!dev_priv->hotplug_mode_update_property) dev_priv 1798 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c int vmw_kms_init(struct vmw_private *dev_priv) dev_priv 1800 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct drm_device *dev = dev_priv->dev; dev_priv 1807 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c dev->mode_config.max_width = dev_priv->texture_max_width; dev_priv 1808 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c dev->mode_config.max_height = dev_priv->texture_max_height; dev_priv 1811 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_kms_create_hotplug_mode_update_property(dev_priv); dev_priv 1813 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_kms_stdu_init_display(dev_priv); dev_priv 1815 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_kms_sou_init_display(dev_priv); dev_priv 1817 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_kms_ldu_init_display(dev_priv); dev_priv 1823 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c int vmw_kms_close(struct vmw_private *dev_priv) dev_priv 1832 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_mode_config_cleanup(dev_priv->dev); dev_priv 1833 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (dev_priv->active_display_unit == vmw_du_legacy) dev_priv 1834 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_kms_ldu_close_display(dev_priv); dev_priv 1981 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv, dev_priv 1986 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ((dev_priv->active_display_unit == vmw_du_screen_target) ? dev_priv 1987 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c dev_priv->prim_bb_mem : dev_priv->vram_size); dev_priv 2021 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c static int vmw_du_update_layout(struct vmw_private *dev_priv, dev_priv 2024 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct drm_device *dev = dev_priv->dev; dev_priv 2100 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(crtc->dev); dev_priv 2106 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8); dev_priv 2107 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8); dev_priv 2108 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8); dev_priv 2124 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 2127 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS); dev_priv 2238 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 2249 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (dev_priv->assume_16bpp) dev_priv 2252 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c max_width = min(max_width, dev_priv->texture_max_width); dev_priv 2253 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c max_height = min(max_height, dev_priv->texture_max_height); dev_priv 2259 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (dev_priv->active_display_unit == vmw_du_screen_target) { dev_priv 2260 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c max_width = min(max_width, dev_priv->stdu_max_width); dev_priv 2261 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c max_height = min(max_height, dev_priv->stdu_max_height); dev_priv 2272 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (vmw_kms_validate_mode_vram(dev_priv, dev_priv 2295 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (!vmw_kms_validate_mode_vram(dev_priv, dev_priv 2337 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 2352 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_du_update_layout(dev_priv, 1, &def_rect); dev_priv 2414 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_du_update_layout(dev_priv, arg->num_outputs, drm_rects); dev_priv 2438 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c int vmw_kms_helper_dirty(struct vmw_private *dev_priv, dev_priv 2452 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c dirty->dev_priv = dev_priv; dev_priv 2458 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, dev_priv 2478 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c dirty->cmd = VMW_FIFO_RESERVE(dev_priv, dev_priv 2554 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c void vmw_kms_helper_validation_finish(struct vmw_private *dev_priv, dev_priv 2567 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_execbuf_fence_commands(file_priv, dev_priv, &fence, dev_priv 2571 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_execbuf_copy_fence_user(dev_priv, vmw_fpriv(file_priv), dev_priv 2599 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 2612 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd) * num_clips); dev_priv 2641 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_fifo_commit(dev_priv, copy_size); dev_priv 2646 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c int vmw_kms_fbdev_init_data(struct vmw_private *dev_priv, dev_priv 2660 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c mutex_lock(&dev_priv->dev->mode_config.mutex); dev_priv 2661 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c list_for_each_entry(con, &dev_priv->dev->mode_config.connector_list, dev_priv 2703 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c mutex_unlock(&dev_priv->dev->mode_config.mutex); dev_priv 2717 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_kms_create_implicit_placement_property(struct vmw_private *dev_priv) dev_priv 2719 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (dev_priv->implicit_placement_property) dev_priv 2722 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c dev_priv->implicit_placement_property = dev_priv 2723 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_property_create_range(dev_priv->dev, dev_priv 2736 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 2738 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c dev_priv->suspend_state = drm_atomic_helper_suspend(dev); dev_priv 2739 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (IS_ERR(dev_priv->suspend_state)) { dev_priv 2740 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c int ret = PTR_ERR(dev_priv->suspend_state); dev_priv 2743 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c dev_priv->suspend_state = NULL; dev_priv 2763 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 2766 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (WARN_ON(!dev_priv->suspend_state)) dev_priv 2769 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = drm_atomic_helper_resume(dev, dev_priv->suspend_state); dev_priv 2770 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c dev_priv->suspend_state = NULL; dev_priv 2844 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c cmd_start = VMW_FIFO_RESERVE(update->dev_priv, reserved_size); dev_priv 2893 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_fifo_commit(update->dev_priv, submit_size); dev_priv 2895 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_kms_helper_validation_finish(update->dev_priv, NULL, &val_ctx, dev_priv 123 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h struct vmw_private *dev_priv; dev_priv 188 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h struct vmw_private *dev_priv; dev_priv 415 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h int vmw_kms_helper_dirty(struct vmw_private *dev_priv, dev_priv 424 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h void vmw_kms_helper_validation_finish(struct vmw_private *dev_priv, dev_priv 430 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h int vmw_kms_readback(struct vmw_private *dev_priv, dev_priv 437 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h vmw_kms_new_framebuffer(struct vmw_private *dev_priv, dev_priv 442 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h int vmw_kms_fbdev_init_data(struct vmw_private *dev_priv, dev_priv 450 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h void vmw_kms_update_implicit_fb(struct vmw_private *dev_priv); dev_priv 451 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h void vmw_kms_create_implicit_placement_property(struct vmw_private *dev_priv); dev_priv 495 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h int vmw_kms_ldu_init_display(struct vmw_private *dev_priv); dev_priv 496 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h int vmw_kms_ldu_close_display(struct vmw_private *dev_priv); dev_priv 497 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h int vmw_kms_ldu_do_bo_dirty(struct vmw_private *dev_priv, dev_priv 510 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h int vmw_kms_sou_init_display(struct vmw_private *dev_priv); dev_priv 511 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h int vmw_kms_sou_do_surface_dirty(struct vmw_private *dev_priv, dev_priv 521 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h int vmw_kms_sou_do_bo_dirty(struct vmw_private *dev_priv, dev_priv 529 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h int vmw_kms_sou_readback(struct vmw_private *dev_priv, dev_priv 540 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h int vmw_kms_stdu_init_display(struct vmw_private *dev_priv); dev_priv 541 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h int vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv, dev_priv 551 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h int vmw_kms_stdu_dma(struct vmw_private *dev_priv, dev_priv 78 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c static int vmw_ldu_commit_list(struct vmw_private *dev_priv) dev_priv 80 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c struct vmw_legacy_display *lds = dev_priv->ldu_priv; dev_priv 89 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)) { dev_priv 102 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c return vmw_kms_write_svga(dev_priv, w, h, fb->pitches[0], dev_priv 111 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_kms_write_svga(dev_priv, fb->width, fb->height, fb->pitches[0], dev_priv 116 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_write(dev_priv, SVGA_REG_NUM_GUEST_DISPLAYS, dev_priv 123 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, i); dev_priv 124 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_write(dev_priv, SVGA_REG_DISPLAY_IS_PRIMARY, !i); dev_priv 125 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_X, crtc->x); dev_priv 126 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_Y, crtc->y); dev_priv 127 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_write(dev_priv, SVGA_REG_DISPLAY_WIDTH, crtc->mode.hdisplay); dev_priv 128 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_write(dev_priv, SVGA_REG_DISPLAY_HEIGHT, crtc->mode.vdisplay); dev_priv 129 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID); dev_priv 286 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c struct vmw_private *dev_priv; dev_priv 294 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c dev_priv = vmw_priv(plane->dev); dev_priv 300 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_ldu_add_active(dev_priv, ldu, vfb); dev_priv 302 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_ldu_del_active(dev_priv, ldu); dev_priv 304 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_ldu_commit_list(dev_priv); dev_priv 353 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c static int vmw_ldu_init(struct vmw_private *dev_priv, unsigned unit) dev_priv 356 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c struct drm_device *dev = dev_priv->dev; dev_priv 377 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c ldu->base.pref_width = dev_priv->initial_width; dev_priv 378 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c ldu->base.pref_height = dev_priv->initial_height; dev_priv 460 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c dev_priv->hotplug_mode_update_property, 1); dev_priv 465 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c if (dev_priv->implicit_placement_property) dev_priv 468 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c dev_priv->implicit_placement_property, dev_priv 484 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c int vmw_kms_ldu_init_display(struct vmw_private *dev_priv) dev_priv 486 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c struct drm_device *dev = dev_priv->dev; dev_priv 489 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c if (dev_priv->ldu_priv) { dev_priv 494 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c dev_priv->ldu_priv = kmalloc(sizeof(*dev_priv->ldu_priv), GFP_KERNEL); dev_priv 495 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c if (!dev_priv->ldu_priv) dev_priv 498 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c INIT_LIST_HEAD(&dev_priv->ldu_priv->active); dev_priv 499 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c dev_priv->ldu_priv->num_active = 0; dev_priv 500 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c dev_priv->ldu_priv->last_num_active = 0; dev_priv 501 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c dev_priv->ldu_priv->fb = NULL; dev_priv 504 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c if (dev_priv->capabilities & SVGA_CAP_MULTIMON) dev_priv 511 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_kms_create_implicit_placement_property(dev_priv); dev_priv 513 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c if (dev_priv->capabilities & SVGA_CAP_MULTIMON) dev_priv 515 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_ldu_init(dev_priv, i); dev_priv 517 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_ldu_init(dev_priv, 0); dev_priv 519 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c dev_priv->active_display_unit = vmw_du_legacy; dev_priv 526 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c kfree(dev_priv->ldu_priv); dev_priv 527 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c dev_priv->ldu_priv = NULL; dev_priv 531 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c int vmw_kms_ldu_close_display(struct vmw_private *dev_priv) dev_priv 533 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c if (!dev_priv->ldu_priv) dev_priv 536 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c BUG_ON(!list_empty(&dev_priv->ldu_priv->active)); dev_priv 538 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c kfree(dev_priv->ldu_priv); dev_priv 544 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c int vmw_kms_ldu_do_bo_dirty(struct vmw_private *dev_priv, dev_priv 559 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c cmd = VMW_FIFO_RESERVE(dev_priv, fifo_size); dev_priv 572 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_fifo_commit(dev_priv, fifo_size); dev_priv 128 drivers/gpu/drm/vmwgfx/vmwgfx_marker.c int vmw_wait_lag(struct vmw_private *dev_priv, dev_priv 138 drivers/gpu/drm/vmwgfx/vmwgfx_marker.c seqno = atomic_read(&dev_priv->marker_seq); dev_priv 146 drivers/gpu/drm/vmwgfx/vmwgfx_marker.c ret = vmw_wait_seqno(dev_priv, false, seqno, true, dev_priv 91 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c static int vmw_mob_pt_populate(struct vmw_private *dev_priv, dev_priv 109 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c static int vmw_setup_otable_base(struct vmw_private *dev_priv, dev_priv 143 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c ret = vmw_mob_pt_populate(dev_priv, mob); dev_priv 151 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 173 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 192 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c static void vmw_takedown_otable_base(struct vmw_private *dev_priv, dev_priv 206 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 218 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 235 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c static int vmw_otable_batch_setup(struct vmw_private *dev_priv, dev_priv 258 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c ret = ttm_bo_create(&dev_priv->bdev, bo_size, dev_priv 282 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c ret = vmw_setup_otable_base(dev_priv, i, batch->otable_bo, dev_priv 297 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c vmw_takedown_otable_base(dev_priv, i, dev_priv 318 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c int vmw_otables_setup(struct vmw_private *dev_priv) dev_priv 320 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c struct vmw_otable **otables = &dev_priv->otable_batch.otables; dev_priv 323 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c if (dev_priv->has_dx) { dev_priv 328 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c dev_priv->otable_batch.num_otables = ARRAY_SIZE(dx_tables); dev_priv 335 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c dev_priv->otable_batch.num_otables = ARRAY_SIZE(pre_dx_tables); dev_priv 338 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c ret = vmw_otable_batch_setup(dev_priv, &dev_priv->otable_batch); dev_priv 349 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c static void vmw_otable_batch_takedown(struct vmw_private *dev_priv, dev_priv 358 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c vmw_takedown_otable_base(dev_priv, i, dev_priv 378 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c void vmw_otables_takedown(struct vmw_private *dev_priv) dev_priv 380 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c vmw_otable_batch_takedown(dev_priv, &dev_priv->otable_batch); dev_priv 381 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c kfree(dev_priv->otable_batch.otables); dev_priv 432 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c static int vmw_mob_pt_populate(struct vmw_private *dev_priv, dev_priv 443 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c ret = ttm_bo_create(&dev_priv->bdev, mob->num_pages * PAGE_SIZE, dev_priv 597 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c void vmw_mob_unbind(struct vmw_private *dev_priv, dev_priv 615 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 620 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 627 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c vmw_fifo_resource_dec(dev_priv); dev_priv 645 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c int vmw_mob_bind(struct vmw_private *dev_priv, dev_priv 671 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c ret = vmw_mob_pt_populate(dev_priv, mob); dev_priv 680 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c vmw_fifo_resource_inc(dev_priv); dev_priv 682 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 693 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 698 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c vmw_fifo_resource_dec(dev_priv); dev_priv 58 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 59 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c return dev_priv ? dev_priv->overlay_priv : NULL; dev_priv 94 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c static int vmw_overlay_send_put(struct vmw_private *dev_priv, dev_priv 101 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c bool have_so = (dev_priv->active_display_unit == vmw_du_screen_object); dev_priv 125 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c cmds = VMW_FIFO_RESERVE(dev_priv, fifo_size); dev_priv 172 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c vmw_fifo_commit(dev_priv, fifo_size); dev_priv 183 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c static int vmw_overlay_send_stop(struct vmw_private *dev_priv, dev_priv 195 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c cmds = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmds)); dev_priv 199 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ret = vmw_fallback_wait(dev_priv, false, true, 0, dev_priv 214 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c vmw_fifo_commit(dev_priv, sizeof(*cmds)); dev_priv 225 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c static int vmw_overlay_move_buffer(struct vmw_private *dev_priv, dev_priv 230 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c return vmw_bo_unpin(dev_priv, buf, inter); dev_priv 232 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c if (dev_priv->active_display_unit == vmw_du_legacy) dev_priv 233 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c return vmw_bo_pin_in_vram(dev_priv, buf, inter); dev_priv 235 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c return vmw_bo_pin_in_vram_or_gmr(dev_priv, buf, inter); dev_priv 250 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c static int vmw_overlay_stop(struct vmw_private *dev_priv, dev_priv 254 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c struct vmw_overlay *overlay = dev_priv->overlay_priv; dev_priv 264 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ret = vmw_overlay_send_stop(dev_priv, stream_id, dev_priv 270 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ret = vmw_overlay_move_buffer(dev_priv, stream->buf, false, dev_priv 297 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c static int vmw_overlay_update_stream(struct vmw_private *dev_priv, dev_priv 302 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c struct vmw_overlay *overlay = dev_priv->overlay_priv; dev_priv 313 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ret = vmw_overlay_stop(dev_priv, arg->stream_id, dev_priv 321 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ret = vmw_overlay_send_put(dev_priv, buf, arg, interruptible); dev_priv 333 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ret = vmw_overlay_move_buffer(dev_priv, buf, true, interruptible); dev_priv 337 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ret = vmw_overlay_send_put(dev_priv, buf, arg, interruptible); dev_priv 342 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c BUG_ON(vmw_overlay_move_buffer(dev_priv, buf, false, false) dev_priv 363 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c int vmw_overlay_stop_all(struct vmw_private *dev_priv) dev_priv 365 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c struct vmw_overlay *overlay = dev_priv->overlay_priv; dev_priv 378 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ret = vmw_overlay_stop(dev_priv, i, false, false); dev_priv 394 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c int vmw_overlay_resume_all(struct vmw_private *dev_priv) dev_priv 396 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c struct vmw_overlay *overlay = dev_priv->overlay_priv; dev_priv 409 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ret = vmw_overlay_update_stream(dev_priv, stream->buf, dev_priv 428 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c int vmw_overlay_pause_all(struct vmw_private *dev_priv) dev_priv 430 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c struct vmw_overlay *overlay = dev_priv->overlay_priv; dev_priv 442 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ret = vmw_overlay_stop(dev_priv, i, true, false); dev_priv 452 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c static bool vmw_overlay_available(const struct vmw_private *dev_priv) dev_priv 454 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c return (dev_priv->overlay_priv != NULL && dev_priv 455 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ((dev_priv->fifo.capabilities & VMW_OVERLAY_CAP_MASK) == dev_priv 463 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 464 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c struct vmw_overlay *overlay = dev_priv->overlay_priv; dev_priv 471 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c if (!vmw_overlay_available(dev_priv)) dev_priv 474 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ret = vmw_user_stream_lookup(dev_priv, tfile, &arg->stream_id, &res); dev_priv 481 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ret = vmw_overlay_stop(dev_priv, arg->stream_id, false, true); dev_priv 489 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c ret = vmw_overlay_update_stream(dev_priv, buf, arg, true); dev_priv 500 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c int vmw_overlay_num_overlays(struct vmw_private *dev_priv) dev_priv 502 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c if (!vmw_overlay_available(dev_priv)) dev_priv 508 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c int vmw_overlay_num_free_overlays(struct vmw_private *dev_priv) dev_priv 510 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c struct vmw_overlay *overlay = dev_priv->overlay_priv; dev_priv 513 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c if (!vmw_overlay_available(dev_priv)) dev_priv 527 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c int vmw_overlay_claim(struct vmw_private *dev_priv, uint32_t *out) dev_priv 529 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c struct vmw_overlay *overlay = dev_priv->overlay_priv; dev_priv 552 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c int vmw_overlay_unref(struct vmw_private *dev_priv, uint32_t stream_id) dev_priv 554 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c struct vmw_overlay *overlay = dev_priv->overlay_priv; dev_priv 564 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c vmw_overlay_stop(dev_priv, stream_id, false, false); dev_priv 571 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c int vmw_overlay_init(struct vmw_private *dev_priv) dev_priv 576 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c if (dev_priv->overlay_priv) dev_priv 590 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c dev_priv->overlay_priv = overlay; dev_priv 595 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c int vmw_overlay_close(struct vmw_private *dev_priv) dev_priv 597 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c struct vmw_overlay *overlay = dev_priv->overlay_priv; dev_priv 607 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c vmw_overlay_stop(dev_priv, i, false, false); dev_priv 613 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c dev_priv->overlay_priv = NULL; dev_priv 87 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 88 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct idr *idr = &dev_priv->res_idr[res->func->res_type]; dev_priv 90 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_lock(&dev_priv->resource_lock); dev_priv 94 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_unlock(&dev_priv->resource_lock); dev_priv 101 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 103 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct idr *idr = &dev_priv->res_idr[res->func->res_type]; dev_priv 105 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_lock(&dev_priv->resource_lock); dev_priv 107 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_unlock(&dev_priv->resource_lock); dev_priv 127 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c mutex_lock(&dev_priv->binding_mutex); dev_priv 129 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 139 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_lock(&dev_priv->resource_lock); dev_priv 142 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_unlock(&dev_priv->resource_lock); dev_priv 164 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 166 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct idr *idr = &dev_priv->res_idr[res->func->res_type]; dev_priv 171 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_lock(&dev_priv->resource_lock); dev_priv 177 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_unlock(&dev_priv->resource_lock); dev_priv 193 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c int vmw_resource_init(struct vmw_private *dev_priv, struct vmw_resource *res, dev_priv 201 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c res->dev_priv = dev_priv; dev_priv 233 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c int vmw_user_resource_lookup_handle(struct vmw_private *dev_priv, dev_priv 278 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c vmw_user_resource_noref_lookup_handle(struct vmw_private *dev_priv, dev_priv 303 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c int vmw_user_lookup_handle(struct vmw_private *dev_priv, dev_priv 314 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c ret = vmw_user_resource_lookup_handle(dev_priv, tfile, handle, dev_priv 351 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c ret = vmw_bo_init(res->dev_priv, backup, res->backup_size, dev_priv 428 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 455 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_lock(&dev_priv->resource_lock); dev_priv 457 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c &res->dev_priv->res_lru[res->func->res_type]); dev_priv 458 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_unlock(&dev_priv->resource_lock); dev_priv 537 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 540 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_lock(&dev_priv->resource_lock); dev_priv 542 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_unlock(&dev_priv->resource_lock); dev_priv 639 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 640 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct list_head *lru_list = &dev_priv->res_lru[res->func->res_type]; dev_priv 656 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_lock(&dev_priv->resource_lock); dev_priv 661 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_unlock(&dev_priv->resource_lock); dev_priv 670 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_unlock(&dev_priv->resource_lock); dev_priv 675 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_lock(&dev_priv->resource_lock); dev_priv 677 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_unlock(&dev_priv->resource_lock); dev_priv 748 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct vmw_private *dev_priv; dev_priv 760 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c dev_priv = dx_query_ctx->dev_priv; dev_priv 762 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), dx_query_ctx->id); dev_priv 770 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 794 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct vmw_private *dev_priv; dev_priv 797 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c dev_priv = container_of(bdev, struct vmw_private, bdev); dev_priv 799 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c mutex_lock(&dev_priv->binding_mutex); dev_priv 803 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 812 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 815 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c (void) vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL); dev_priv 823 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 846 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c static void vmw_resource_evict_type(struct vmw_private *dev_priv, dev_priv 849 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct list_head *lru_list = &dev_priv->res_lru[type]; dev_priv 856 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_lock(&dev_priv->resource_lock); dev_priv 865 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_unlock(&dev_priv->resource_lock); dev_priv 870 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_lock(&dev_priv->resource_lock); dev_priv 872 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_unlock(&dev_priv->resource_lock); dev_priv 883 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c spin_unlock(&dev_priv->resource_lock); dev_priv 896 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c void vmw_resource_evict_all(struct vmw_private *dev_priv) dev_priv 900 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c mutex_lock(&dev_priv->cmdbuf_mutex); dev_priv 903 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c vmw_resource_evict_type(dev_priv, type); dev_priv 905 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c mutex_unlock(&dev_priv->cmdbuf_mutex); dev_priv 921 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 924 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c ttm_write_lock(&dev_priv->reservation_sem, interruptible); dev_priv 925 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c mutex_lock(&dev_priv->cmdbuf_mutex); dev_priv 962 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c mutex_unlock(&dev_priv->cmdbuf_mutex); dev_priv 963 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c ttm_write_unlock(&dev_priv->reservation_sem); dev_priv 978 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 981 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c (void) ttm_read_lock(&dev_priv->reservation_sem, false); dev_priv 982 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c mutex_lock(&dev_priv->cmdbuf_mutex); dev_priv 998 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c mutex_unlock(&dev_priv->cmdbuf_mutex); dev_priv 999 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 126 drivers/gpu/drm/vmwgfx/vmwgfx_resource_priv.h int vmw_resource_init(struct vmw_private *dev_priv, struct vmw_resource *res, dev_priv 118 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static int vmw_sou_fifo_create(struct vmw_private *dev_priv, dev_priv 135 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c cmd = VMW_FIFO_RESERVE(dev_priv, fifo_size); dev_priv 156 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_fifo_commit(dev_priv, fifo_size); dev_priv 166 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static int vmw_sou_fifo_destroy(struct vmw_private *dev_priv, dev_priv 184 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c cmd = VMW_FIFO_RESERVE(dev_priv, fifo_size); dev_priv 192 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_fifo_commit(dev_priv, fifo_size); dev_priv 195 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ); dev_priv 214 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c struct vmw_private *dev_priv; dev_priv 223 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c dev_priv = vmw_priv(crtc->dev); dev_priv 231 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = vmw_sou_fifo_destroy(dev_priv, sou); dev_priv 252 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = vmw_sou_fifo_create(dev_priv, sou, x, y, &crtc->mode); dev_priv 294 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c struct vmw_private *dev_priv; dev_priv 305 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c dev_priv = vmw_priv(crtc->dev); dev_priv 308 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = vmw_sou_fifo_destroy(dev_priv, sou); dev_priv 411 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c struct vmw_private *dev_priv; dev_priv 424 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c dev_priv = vmw_priv(crtc->dev); dev_priv 432 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c return vmw_bo_pin_in_vram(dev_priv, vps->bo, dev_priv 444 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_svga_enable(dev_priv); dev_priv 449 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_overlay_pause_all(dev_priv); dev_priv 450 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = vmw_bo_init(dev_priv, vps->bo, size, dev_priv 453 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_overlay_resume_all(dev_priv); dev_priv 465 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c return vmw_bo_pin_in_vram(dev_priv, vps->bo, true); dev_priv 537 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static int vmw_sou_plane_update_bo(struct vmw_private *dev_priv, dev_priv 548 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.dev_priv = dev_priv; dev_priv 698 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static int vmw_sou_plane_update_surface(struct vmw_private *dev_priv, dev_priv 709 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.dev_priv = dev_priv; dev_priv 713 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.mutex = &dev_priv->cmdbuf_mutex; dev_priv 737 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c struct vmw_private *dev_priv = vmw_priv(crtc->dev); dev_priv 742 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = vmw_sou_plane_update_bo(dev_priv, plane, dev_priv 745 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = vmw_sou_plane_update_surface(dev_priv, plane, dev_priv 826 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static int vmw_sou_init(struct vmw_private *dev_priv, unsigned unit) dev_priv 829 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c struct drm_device *dev = dev_priv->dev; dev_priv 848 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sou->base.pref_width = dev_priv->initial_width; dev_priv 849 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sou->base.pref_height = dev_priv->initial_height; dev_priv 933 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c dev_priv->hotplug_mode_update_property, 1); dev_priv 951 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c int vmw_kms_sou_init_display(struct vmw_private *dev_priv) dev_priv 953 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c struct drm_device *dev = dev_priv->dev; dev_priv 956 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c if (!(dev_priv->capabilities & SVGA_CAP_SCREEN_OBJECT_2)) { dev_priv 969 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_sou_init(dev_priv, i); dev_priv 971 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c dev_priv->active_display_unit = vmw_du_screen_object; dev_priv 978 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c static int do_bo_define_gmrfb(struct vmw_private *dev_priv, dev_priv 997 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 1008 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 1034 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_fifo_commit(dirty->dev_priv, 0); dev_priv 1066 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_fifo_commit(dirty->dev_priv, region_size + sizeof(*cmd)); dev_priv 1125 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c int vmw_kms_sou_do_surface_dirty(struct vmw_private *dev_priv, dev_priv 1150 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = vmw_validation_prepare(&val_ctx, &dev_priv->cmdbuf_mutex, true); dev_priv 1156 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sdirty.base.dev_priv = dev_priv; dev_priv 1167 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips, dev_priv 1170 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence, dev_priv 1190 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_fifo_commit(dirty->dev_priv, 0); dev_priv 1194 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_fifo_commit(dirty->dev_priv, dev_priv 1241 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c int vmw_kms_sou_do_bo_dirty(struct vmw_private *dev_priv, dev_priv 1265 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = do_bo_define_gmrfb(dev_priv, framebuffer); dev_priv 1274 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips, dev_priv 1276 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence, dev_priv 1300 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_fifo_commit(dirty->dev_priv, 0); dev_priv 1304 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_fifo_commit(dirty->dev_priv, dev_priv 1349 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c int vmw_kms_sou_readback(struct vmw_private *dev_priv, dev_priv 1371 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = do_bo_define_gmrfb(dev_priv, vfb); dev_priv 1380 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = vmw_kms_helper_dirty(dev_priv, vfb, NULL, vclips, dev_priv 1382 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_kms_helper_validation_finish(dev_priv, file_priv, &val_ctx, NULL, dev_priv 159 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c static int vmw_gb_shader_init(struct vmw_private *dev_priv, dev_priv 172 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = vmw_resource_init(dev_priv, res, true, res_free, dev_priv 203 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 225 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 236 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 237 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c vmw_fifo_resource_inc(dev_priv); dev_priv 250 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 259 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 269 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 278 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 287 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 296 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 302 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c (void) vmw_execbuf_fence_commands(NULL, dev_priv, dev_priv 315 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 324 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c mutex_lock(&dev_priv->binding_mutex); dev_priv 327 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 329 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 336 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 337 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 339 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c vmw_fifo_resource_dec(dev_priv); dev_priv 360 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 363 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c mutex_lock(&dev_priv->binding_mutex); dev_priv 368 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 370 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c mutex_lock(&dev_priv->binding_mutex); dev_priv 374 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 388 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 397 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), shader->ctx->id); dev_priv 407 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 424 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 431 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c mutex_lock(&dev_priv->binding_mutex); dev_priv 433 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 450 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 454 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c mutex_lock(&dev_priv->binding_mutex); dev_priv 456 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 474 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 484 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 494 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 512 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 518 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c mutex_lock(&dev_priv->binding_mutex); dev_priv 520 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 525 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c (void) vmw_execbuf_fence_commands(NULL, dev_priv, dev_priv 546 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c void vmw_dx_shader_cotable_list_scrub(struct vmw_private *dev_priv, dev_priv 552 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c lockdep_assert_held_once(&dev_priv->binding_mutex); dev_priv 570 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 575 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ttm_mem_global_free(vmw_mem_glob(dev_priv), vmw_shader_dx_size); dev_priv 596 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = ctx->dev_priv; dev_priv 609 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), vmw_shader_dx_size, dev_priv 620 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ttm_mem_global_free(vmw_mem_glob(dev_priv), vmw_shader_dx_size); dev_priv 631 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = vmw_resource_init(dev_priv, res, true, dev_priv 672 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 675 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ttm_mem_global_free(vmw_mem_glob(dev_priv), dev_priv 682 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 685 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ttm_mem_global_free(vmw_mem_glob(dev_priv), dev_priv 713 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c static int vmw_user_shader_alloc(struct vmw_private *dev_priv, dev_priv 736 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), dev_priv 748 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ttm_mem_global_free(vmw_mem_glob(dev_priv), dev_priv 762 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = vmw_gb_shader_init(dev_priv, res, shader_size, dev_priv 788 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c static struct vmw_resource *vmw_shader_alloc(struct vmw_private *dev_priv, dev_priv 807 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), dev_priv 819 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ttm_mem_global_free(vmw_mem_glob(dev_priv), dev_priv 830 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = vmw_gb_shader_init(dev_priv, res, shader_size, dev_priv 845 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 880 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = ttm_read_lock(&dev_priv->reservation_sem, true); dev_priv 884 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = vmw_user_shader_alloc(dev_priv, buffer, size, offset, dev_priv 888 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 959 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c int vmw_compat_shader_add(struct vmw_private *dev_priv, dev_priv 981 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = vmw_bo_init(dev_priv, buf, size, &vmw_sys_ne_placement, dev_priv 1006 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c res = vmw_shader_alloc(dev_priv, buf, size, 0, shader_type); dev_priv 62 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c static int vmw_simple_resource_init(struct vmw_private *dev_priv, dev_priv 70 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c ret = vmw_resource_init(dev_priv, res, false, res_free, dev_priv 101 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 105 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c ttm_mem_global_free(vmw_mem_glob(dev_priv), size); dev_priv 147 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 165 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c ret = ttm_read_lock(&dev_priv->reservation_sem, true); dev_priv 169 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), account_size, dev_priv 171 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 182 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c ttm_mem_global_free(vmw_mem_glob(dev_priv), dev_priv 197 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c ret = vmw_simple_resource_init(dev_priv, &usimple->simple, dev_priv 129 drivers/gpu/drm/vmwgfx/vmwgfx_so.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 131 drivers/gpu/drm/vmwgfx/vmwgfx_so.c mutex_lock(&dev_priv->binding_mutex); dev_priv 146 drivers/gpu/drm/vmwgfx/vmwgfx_so.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 161 drivers/gpu/drm/vmwgfx/vmwgfx_so.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 167 drivers/gpu/drm/vmwgfx/vmwgfx_so.c mutex_lock(&dev_priv->binding_mutex); dev_priv 169 drivers/gpu/drm/vmwgfx/vmwgfx_so.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 173 drivers/gpu/drm/vmwgfx/vmwgfx_so.c cmd = VMW_FIFO_RESERVE_DX(res->dev_priv, view->cmd_size, view->ctx->id); dev_priv 175 drivers/gpu/drm/vmwgfx/vmwgfx_so.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 184 drivers/gpu/drm/vmwgfx/vmwgfx_so.c vmw_fifo_commit(res->dev_priv, view->cmd_size); dev_priv 188 drivers/gpu/drm/vmwgfx/vmwgfx_so.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 203 drivers/gpu/drm/vmwgfx/vmwgfx_so.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 210 drivers/gpu/drm/vmwgfx/vmwgfx_so.c lockdep_assert_held_once(&dev_priv->binding_mutex); dev_priv 216 drivers/gpu/drm/vmwgfx/vmwgfx_so.c cmd = VMW_FIFO_RESERVE_DX(dev_priv, sizeof(*cmd), view->ctx->id); dev_priv 223 drivers/gpu/drm/vmwgfx/vmwgfx_so.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 240 drivers/gpu/drm/vmwgfx/vmwgfx_so.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 242 drivers/gpu/drm/vmwgfx/vmwgfx_so.c mutex_lock(&dev_priv->binding_mutex); dev_priv 245 drivers/gpu/drm/vmwgfx/vmwgfx_so.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 287 drivers/gpu/drm/vmwgfx/vmwgfx_so.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 292 drivers/gpu/drm/vmwgfx/vmwgfx_so.c ttm_mem_global_free(vmw_mem_glob(dev_priv), size); dev_priv 325 drivers/gpu/drm/vmwgfx/vmwgfx_so.c struct vmw_private *dev_priv = ctx->dev_priv; dev_priv 348 drivers/gpu/drm/vmwgfx/vmwgfx_so.c ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), size, &ttm_opt_ctx); dev_priv 357 drivers/gpu/drm/vmwgfx/vmwgfx_so.c ttm_mem_global_free(vmw_mem_glob(dev_priv), size); dev_priv 373 drivers/gpu/drm/vmwgfx/vmwgfx_so.c ret = vmw_resource_init(dev_priv, res, true, dev_priv 432 drivers/gpu/drm/vmwgfx/vmwgfx_so.c void vmw_view_cotable_list_destroy(struct vmw_private *dev_priv, dev_priv 438 drivers/gpu/drm/vmwgfx/vmwgfx_so.c lockdep_assert_held_once(&dev_priv->binding_mutex); dev_priv 453 drivers/gpu/drm/vmwgfx/vmwgfx_so.c void vmw_view_surface_list_destroy(struct vmw_private *dev_priv, dev_priv 458 drivers/gpu/drm/vmwgfx/vmwgfx_so.c lockdep_assert_held_once(&dev_priv->binding_mutex); dev_priv 151 drivers/gpu/drm/vmwgfx/vmwgfx_so.h extern void vmw_view_surface_list_destroy(struct vmw_private *dev_priv, dev_priv 153 drivers/gpu/drm/vmwgfx/vmwgfx_so.h extern void vmw_view_cotable_list_destroy(struct vmw_private *dev_priv, dev_priv 163 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static int vmw_stdu_define_st(struct vmw_private *dev_priv, dev_priv 173 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 191 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 211 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static int vmw_stdu_bind_st(struct vmw_private *dev_priv, dev_priv 232 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 242 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 286 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static int vmw_stdu_update_st(struct vmw_private *dev_priv, dev_priv 296 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 304 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 317 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static int vmw_stdu_destroy_st(struct vmw_private *dev_priv, dev_priv 332 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 341 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 344 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ); dev_priv 366 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c struct vmw_private *dev_priv; dev_priv 373 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c dev_priv = vmw_priv(crtc->dev); dev_priv 378 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_stdu_bind_st(dev_priv, stdu, NULL); dev_priv 382 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c (void) vmw_stdu_update_st(dev_priv, stdu); dev_priv 384 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_stdu_destroy_st(dev_priv, stdu); dev_priv 397 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_svga_enable(dev_priv); dev_priv 398 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_stdu_define_st(dev_priv, stdu, &crtc->mode, x, y); dev_priv 418 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c struct vmw_private *dev_priv; dev_priv 429 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c dev_priv = vmw_priv(crtc->dev); dev_priv 432 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_stdu_bind_st(dev_priv, stdu, NULL); dev_priv 436 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c (void) vmw_stdu_update_st(dev_priv, stdu); dev_priv 438 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_stdu_destroy_st(dev_priv, stdu); dev_priv 502 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_fifo_commit(dirty->dev_priv, 0); dev_priv 525 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_fifo_commit(dirty->dev_priv, sizeof(*cmd) + blit_size); dev_priv 614 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c struct vmw_private *dev_priv; dev_priv 630 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c dev_priv = vmw_priv(stdu->base.crtc.dev); dev_priv 631 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 639 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 671 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c int vmw_kms_stdu_dma(struct vmw_private *dev_priv, dev_priv 687 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bool cpu_blit = !(dev_priv->capabilities & SVGA_CAP_3D); dev_priv 727 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_kms_helper_dirty(dev_priv, vfb, clips, vclips, dev_priv 730 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_kms_helper_validation_finish(dev_priv, file_priv, &val_ctx, NULL, dev_priv 798 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_fifo_commit(dirty->dev_priv, 0); dev_priv 820 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_fifo_commit(dirty->dev_priv, commit_size); dev_priv 848 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c int vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv, dev_priv 873 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_validation_prepare(&val_ctx, &dev_priv->cmdbuf_mutex, true); dev_priv 893 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips, dev_priv 897 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence, dev_priv 1035 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c struct vmw_private *dev_priv = vmw_priv(plane->dev); dev_priv 1174 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c !(dev_priv->capabilities & SVGA_CAP_3D)) dev_priv 1362 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static int vmw_stdu_plane_update_bo(struct vmw_private *dev_priv, dev_priv 1373 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.dev_priv = dev_priv; dev_priv 1378 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.cpu_blit = !(dev_priv->capabilities & SVGA_CAP_3D); dev_priv 1537 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static int vmw_stdu_plane_update_surface(struct vmw_private *dev_priv, dev_priv 1553 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c srf_update.dev_priv = dev_priv; dev_priv 1557 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c srf_update.mutex = &dev_priv->cmdbuf_mutex; dev_priv 1597 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c struct vmw_private *dev_priv; dev_priv 1605 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c dev_priv = vmw_priv(crtc->dev); dev_priv 1611 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_stdu_bind_st(dev_priv, stdu, &stdu->display_srf->res); dev_priv 1616 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_stdu_plane_update_bo(dev_priv, plane, dev_priv 1619 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_stdu_plane_update_surface(dev_priv, plane, dev_priv 1627 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c dev_priv = vmw_priv(crtc->dev); dev_priv 1633 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_stdu_bind_st(dev_priv, stdu, NULL); dev_priv 1637 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_stdu_update_st(dev_priv, stdu); dev_priv 1725 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c static int vmw_stdu_init(struct vmw_private *dev_priv, unsigned unit) dev_priv 1728 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c struct drm_device *dev = dev_priv->dev; dev_priv 1748 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu->base.pref_width = dev_priv->initial_width; dev_priv 1749 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu->base.pref_height = dev_priv->initial_height; dev_priv 1827 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c dev_priv->hotplug_mode_update_property, 1); dev_priv 1881 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c int vmw_kms_stdu_init_display(struct vmw_private *dev_priv) dev_priv 1883 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c struct drm_device *dev = dev_priv->dev; dev_priv 1891 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c if (!(dev_priv->capabilities & SVGA_CAP_GBOBJECTS)) dev_priv 1898 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c dev_priv->active_display_unit = vmw_du_screen_target; dev_priv 1901 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = vmw_stdu_init(dev_priv, i); dev_priv 338 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 349 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c cmd = VMW_FIFO_RESERVE(dev_priv, vmw_surface_destroy_size()); dev_priv 354 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_fifo_commit(dev_priv, vmw_surface_destroy_size()); dev_priv 362 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c mutex_lock(&dev_priv->cmdbuf_mutex); dev_priv 364 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c dev_priv->used_memory_size -= res->backup_size; dev_priv 365 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c mutex_unlock(&dev_priv->cmdbuf_mutex); dev_priv 384 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 394 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (unlikely(dev_priv->used_memory_size + res->backup_size >= dev_priv 395 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c dev_priv->memory_size)) dev_priv 418 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c cmd = VMW_FIFO_RESERVE(dev_priv, submit_size); dev_priv 425 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_fifo_commit(dev_priv, submit_size); dev_priv 426 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_fifo_resource_inc(dev_priv); dev_priv 432 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c dev_priv->used_memory_size += res->backup_size; dev_priv 466 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 470 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c cmd = VMW_FIFO_RESERVE(dev_priv, submit_size); dev_priv 477 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_fifo_commit(dev_priv, submit_size); dev_priv 483 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c (void) vmw_execbuf_fence_commands(NULL, dev_priv, dev_priv 545 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 556 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c cmd = VMW_FIFO_RESERVE(dev_priv, submit_size); dev_priv 561 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_fifo_commit(dev_priv, submit_size); dev_priv 567 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c dev_priv->used_memory_size -= res->backup_size; dev_priv 574 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_fifo_resource_dec(dev_priv); dev_priv 588 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c static int vmw_surface_init(struct vmw_private *dev_priv, dev_priv 596 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = vmw_resource_init(dev_priv, res, true, res_free, dev_priv 597 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c (dev_priv->has_mob) ? &vmw_gb_surface_func : dev_priv 641 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = srf->res.dev_priv; dev_priv 650 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ttm_mem_global_free(vmw_mem_glob(dev_priv), size); dev_priv 703 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 752 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = ttm_read_lock(&dev_priv->reservation_sem, true); dev_priv 756 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), dev_priv 847 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = vmw_surface_init(dev_priv, srf, vmw_user_surface_free); dev_priv 855 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (dev_priv->has_mob && req->shareable) { dev_priv 858 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = vmw_user_bo_alloc(dev_priv, tfile, dev_priv 884 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 893 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ttm_mem_global_free(vmw_mem_glob(dev_priv), size); dev_priv 895 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 901 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_surface_handle_reference(struct vmw_private *dev_priv, dev_priv 926 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c base = ttm_base_object_lookup_for_ref(dev_priv->tdev, handle); dev_priv 980 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 992 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = vmw_surface_handle_reference(dev_priv, file_priv, req->sid, dev_priv 1030 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 1050 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_fifo_resource_inc(dev_priv); dev_priv 1062 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (dev_priv->has_sm4_1 && srf->array_size > 0) { dev_priv 1077 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c cmd = VMW_FIFO_RESERVE(dev_priv, submit_len); dev_priv 1085 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (dev_priv->has_sm4_1 && srf->array_size > 0) { dev_priv 1127 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_fifo_commit(dev_priv, submit_len); dev_priv 1134 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_fifo_resource_dec(dev_priv); dev_priv 1142 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 1158 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c cmd1 = VMW_FIFO_RESERVE(dev_priv, submit_size); dev_priv 1173 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_fifo_commit(dev_priv, submit_size); dev_priv 1182 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 1205 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c cmd = VMW_FIFO_RESERVE(dev_priv, submit_size); dev_priv 1228 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_fifo_commit(dev_priv, submit_size); dev_priv 1234 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c (void) vmw_execbuf_fence_commands(NULL, dev_priv, dev_priv 1247 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 1257 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c mutex_lock(&dev_priv->binding_mutex); dev_priv 1258 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_view_surface_list_destroy(dev_priv, &srf->view_list); dev_priv 1261 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); dev_priv 1263 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 1270 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_fifo_commit(dev_priv, sizeof(*cmd)); dev_priv 1271 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c mutex_unlock(&dev_priv->binding_mutex); dev_priv 1273 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_fifo_resource_dec(dev_priv); dev_priv 1369 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 1388 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (size.width > dev_priv->texture_max_width || dev_priv 1389 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c size.height > dev_priv->texture_max_height) { dev_priv 1392 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c dev_priv->texture_max_width, dev_priv 1393 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c dev_priv->texture_max_height); dev_priv 1407 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (array_size > 0 && !dev_priv->has_dx) { dev_priv 1412 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = ttm_read_lock(&dev_priv->reservation_sem, true); dev_priv 1416 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), dev_priv 1477 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (dev_priv->active_display_unit == vmw_du_screen_target && dev_priv 1478 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c for_scanout && size.width <= dev_priv->stdu_max_width && dev_priv 1479 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c size.height <= dev_priv->stdu_max_height) dev_priv 1486 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = vmw_surface_init(dev_priv, srf, vmw_user_surface_free); dev_priv 1488 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 1492 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ttm_mem_global_free(vmw_mem_glob(dev_priv), user_accounting_size); dev_priv 1495 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 1552 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 1565 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (!dev_priv->has_sm4_1) { dev_priv 1617 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = ttm_read_lock(&dev_priv->reservation_sem, true); dev_priv 1640 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = vmw_user_bo_alloc(dev_priv, tfile, dev_priv 1682 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ttm_read_unlock(&dev_priv->reservation_sem); dev_priv 1701 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct vmw_private *dev_priv = vmw_priv(dev); dev_priv 1709 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = vmw_surface_handle_reference(dev_priv, file_priv, req->sid, dev_priv 1721 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c mutex_lock(&dev_priv->cmdbuf_mutex); /* Protect res->backup */ dev_priv 1723 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c mutex_unlock(&dev_priv->cmdbuf_mutex); dev_priv 241 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c struct vmw_private *dev_priv; dev_priv 363 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c struct device *dev = vmw_tt->dev_priv->dev->dev; dev_priv 385 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c struct device *dev = vmw_tt->dev_priv->dev->dev; dev_priv 410 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c struct vmw_private *dev_priv = vmw_tt->dev_priv; dev_priv 411 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c struct ttm_mem_global *glob = vmw_mem_glob(dev_priv); dev_priv 426 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c vsgt->mode = dev_priv->map_mode; dev_priv 432 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c switch (dev_priv->map_mode) { dev_priv 447 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c dma_get_max_seg_size(dev_priv->dev->dev), dev_priv 502 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c struct vmw_private *dev_priv = vmw_tt->dev_priv; dev_priv 507 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c switch (dev_priv->map_mode) { dev_priv 513 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c ttm_mem_global_free(vmw_mem_glob(dev_priv), dev_priv 594 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c return vmw_gmr_bind(vmw_be->dev_priv, &vmw_be->vsgt, dev_priv 604 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c return vmw_mob_bind(vmw_be->dev_priv, vmw_be->mob, dev_priv 620 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c vmw_gmr_unbind(vmw_be->dev_priv, vmw_be->gmr_id); dev_priv 623 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c vmw_mob_unbind(vmw_be->dev_priv, vmw_be->mob); dev_priv 629 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c if (vmw_be->dev_priv->map_mode == vmw_dma_map_bind) dev_priv 642 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c if (vmw_be->dev_priv->map_mode == vmw_dma_alloc_coherent) dev_priv 658 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c struct vmw_private *dev_priv = vmw_tt->dev_priv; dev_priv 659 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c struct ttm_mem_global *glob = vmw_mem_glob(dev_priv); dev_priv 665 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c if (dev_priv->map_mode == vmw_dma_alloc_coherent) { dev_priv 672 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c ret = ttm_dma_populate(&vmw_tt->dma_ttm, dev_priv->dev->dev, dev_priv 686 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c struct vmw_private *dev_priv = vmw_tt->dev_priv; dev_priv 687 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c struct ttm_mem_global *glob = vmw_mem_glob(dev_priv); dev_priv 696 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c if (dev_priv->map_mode == vmw_dma_alloc_coherent) { dev_priv 700 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c ttm_dma_unpopulate(&vmw_tt->dma_ttm, dev_priv->dev->dev); dev_priv 723 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c vmw_be->dev_priv = container_of(bo->bdev, struct vmw_private, bdev); dev_priv 726 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c if (vmw_be->dev_priv->map_mode == vmw_dma_alloc_coherent) dev_priv 800 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c struct vmw_private *dev_priv = container_of(bdev, struct vmw_private, bdev); dev_priv 816 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c mem->bus.base = dev_priv->vram_start; dev_priv 33 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev); dev_priv 35 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c return ttm_bo_mmap(filp, vma, &dev_priv->bdev); dev_priv 43 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c struct vmw_private *dev_priv = container_of(m, struct vmw_private, vvm); dev_priv 45 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c return ttm_mem_global_alloc(vmw_mem_glob(dev_priv), size, &ctx); dev_priv 51 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c struct vmw_private *dev_priv = container_of(m, struct vmw_private, vvm); dev_priv 53 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c return ttm_mem_global_free(vmw_mem_glob(dev_priv), size); dev_priv 65 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c void vmw_validation_mem_init_ttm(struct vmw_private *dev_priv, size_t gran) dev_priv 67 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c struct vmw_validation_mem *vvm = &dev_priv->vvm; dev_priv 58 drivers/gpu/drm/vmwgfx/vmwgfx_va.c struct vmw_private *dev_priv = res->dev_priv; dev_priv 62 drivers/gpu/drm/vmwgfx/vmwgfx_va.c ret = vmw_overlay_unref(dev_priv, stream->stream_id); dev_priv 70 drivers/gpu/drm/vmwgfx/vmwgfx_va.c return vmw_overlay_claim(res->dev_priv, &stream->stream_id); dev_priv 152 drivers/gpu/drm/vmwgfx/vmwgfx_va.c int vmw_user_stream_lookup(struct vmw_private *dev_priv, dev_priv 346 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c if (!res->dev_priv->has_mob) { dev_priv 786 drivers/media/v4l2-core/v4l2-subdev.c sd->dev_priv = NULL; dev_priv 233 drivers/net/ethernet/amd/am79c961a.c struct dev_priv *priv = netdev_priv(dev); dev_priv 304 drivers/net/ethernet/amd/am79c961a.c struct dev_priv *priv = from_timer(priv, t, timer); dev_priv 331 drivers/net/ethernet/amd/am79c961a.c struct dev_priv *priv = netdev_priv(dev); dev_priv 356 drivers/net/ethernet/amd/am79c961a.c struct dev_priv *priv = netdev_priv(dev); dev_priv 379 drivers/net/ethernet/amd/am79c961a.c struct dev_priv *priv = netdev_priv(dev); dev_priv 443 drivers/net/ethernet/amd/am79c961a.c struct dev_priv *priv = netdev_priv(dev); dev_priv 481 drivers/net/ethernet/amd/am79c961a.c am79c961_rx(struct net_device *dev, struct dev_priv *priv) dev_priv 538 drivers/net/ethernet/amd/am79c961a.c am79c961_tx(struct net_device *dev, struct dev_priv *priv) dev_priv 588 drivers/net/ethernet/amd/am79c961a.c struct dev_priv *priv = netdev_priv(dev); dev_priv 636 drivers/net/ethernet/amd/am79c961a.c struct dev_priv *priv = netdev_priv(dev); dev_priv 673 drivers/net/ethernet/amd/am79c961a.c struct dev_priv *priv; dev_priv 680 drivers/net/ethernet/amd/am79c961a.c dev = alloc_etherdev(sizeof(struct dev_priv)); dev_priv 4631 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 4829 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 4903 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 4984 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5153 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5237 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5310 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5350 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5437 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5468 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5489 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5594 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5650 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5676 drivers/net/ethernet/micrel/ksz884x.c static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv, dev_priv 5711 drivers/net/ethernet/micrel/ksz884x.c static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw, dev_priv 5738 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5786 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5826 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5888 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5908 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5946 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 5973 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6043 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6063 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6080 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6133 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6171 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6191 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6219 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6233 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6266 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6294 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6328 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6361 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6406 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6469 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6489 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6512 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6581 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6628 drivers/net/ethernet/micrel/ksz884x.c static void update_link(struct net_device *dev, struct dev_priv *priv, dev_priv 6710 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = from_timer(priv, t, monitor_timer_info.timer); dev_priv 6777 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv = netdev_priv(dev); dev_priv 6916 drivers/net/ethernet/micrel/ksz884x.c struct dev_priv *priv; dev_priv 7060 drivers/net/ethernet/micrel/ksz884x.c dev = alloc_etherdev(sizeof(struct dev_priv)); dev_priv 295 drivers/net/ethernet/netronome/nfp/bpf/cmsg.c struct nfp_bpf_map *nfp_map = offmap->dev_priv; dev_priv 4418 drivers/net/ethernet/netronome/nfp/bpf/jit.c nfp_map = map_to_offmap(map)->dev_priv; dev_priv 195 drivers/net/ethernet/netronome/nfp/bpf/offload.c prog->aux->offload->dev_priv = nfp_prog; dev_priv 218 drivers/net/ethernet/netronome/nfp/bpf/offload.c struct nfp_prog *nfp_prog = prog->aux->offload->dev_priv; dev_priv 245 drivers/net/ethernet/netronome/nfp/bpf/offload.c struct nfp_prog *nfp_prog = prog->aux->offload->dev_priv; dev_priv 290 drivers/net/ethernet/netronome/nfp/bpf/offload.c nfp_map_bpf_byte_swap(offmap->dev_priv, value); dev_priv 298 drivers/net/ethernet/netronome/nfp/bpf/offload.c nfp_map_bpf_byte_swap(offmap->dev_priv, value); dev_priv 299 drivers/net/ethernet/netronome/nfp/bpf/offload.c nfp_map_bpf_byte_swap_record(offmap->dev_priv, value); dev_priv 385 drivers/net/ethernet/netronome/nfp/bpf/offload.c offmap->dev_priv = nfp_map; dev_priv 408 drivers/net/ethernet/netronome/nfp/bpf/offload.c struct nfp_bpf_map *nfp_map = offmap->dev_priv; dev_priv 484 drivers/net/ethernet/netronome/nfp/bpf/offload.c struct nfp_prog *nfp_prog = prog->aux->offload->dev_priv; dev_priv 100 drivers/net/ethernet/netronome/nfp/bpf/verifier.c nfp_map = offmap->dev_priv; dev_priv 434 drivers/net/ethernet/netronome/nfp/bpf/verifier.c nfp_map = offmap->dev_priv; dev_priv 629 drivers/net/ethernet/netronome/nfp/bpf/verifier.c struct nfp_prog *nfp_prog = env->prog->aux->offload->dev_priv; dev_priv 766 drivers/net/ethernet/netronome/nfp/bpf/verifier.c nfp_prog = env->prog->aux->offload->dev_priv; dev_priv 805 drivers/net/ethernet/netronome/nfp/bpf/verifier.c struct nfp_prog *nfp_prog = env->prog->aux->offload->dev_priv; dev_priv 838 drivers/net/ethernet/netronome/nfp/bpf/verifier.c struct nfp_prog *nfp_prog = env->prog->aux->offload->dev_priv; dev_priv 173 drivers/net/ethernet/seeq/ether3.c struct dev_priv *private = from_timer(private, t, timer); dev_priv 762 drivers/net/ethernet/seeq/ether3.c dev = alloc_etherdev(sizeof(struct dev_priv)); dev_priv 22 drivers/net/ethernet/seeq/ether3.h #define priv(dev) ((struct dev_priv *)netdev_priv(dev)) dev_priv 67 drivers/net/netdevsim/bpf.c state = env->prog->aux->offload->dev_priv; dev_priv 94 drivers/net/netdevsim/bpf.c state = prog->aux->offload->dev_priv; dev_priv 245 drivers/net/netdevsim/bpf.c prog->aux->offload->dev_priv = state; dev_priv 263 drivers/net/netdevsim/bpf.c struct nsim_bpf_bound_prog *state = prog->aux->offload->dev_priv; dev_priv 273 drivers/net/netdevsim/bpf.c state = prog->aux->offload->dev_priv; dev_priv 319 drivers/net/netdevsim/bpf.c state = bpf->prog->aux->offload->dev_priv; dev_priv 335 drivers/net/netdevsim/bpf.c struct nsim_bpf_bound_map *nmap = offmap->dev_priv; dev_priv 348 drivers/net/netdevsim/bpf.c struct nsim_bpf_bound_map *nmap = offmap->dev_priv; dev_priv 367 drivers/net/netdevsim/bpf.c struct nsim_bpf_bound_map *nmap = offmap->dev_priv; dev_priv 397 drivers/net/netdevsim/bpf.c struct nsim_bpf_bound_map *nmap = offmap->dev_priv; dev_priv 415 drivers/net/netdevsim/bpf.c struct nsim_bpf_bound_map *nmap = offmap->dev_priv; dev_priv 454 drivers/net/netdevsim/bpf.c struct nsim_bpf_bound_map *nmap = offmap->dev_priv; dev_priv 499 drivers/net/netdevsim/bpf.c offmap->dev_priv = nmap; dev_priv 532 drivers/net/netdevsim/bpf.c struct nsim_bpf_bound_map *nmap = offmap->dev_priv; dev_priv 270 drivers/usb/cdns3/trace.h TP_PROTO(struct cdns3_device *dev_priv, struct usb_request *request), dev_priv 271 drivers/usb/cdns3/trace.h TP_ARGS(dev_priv, request), dev_priv 277 drivers/usb/cdns3/trace.h __entry->dir = dev_priv->ep0_data_dir; dev_priv 155 include/linux/bpf.h void *dev_priv; dev_priv 346 include/linux/bpf.h void *dev_priv; dev_priv 862 include/media/v4l2-subdev.h void *dev_priv; dev_priv 990 include/media/v4l2-subdev.h sd->dev_priv = p; dev_priv 1002 include/media/v4l2-subdev.h return sd->dev_priv; dev_priv 78 include/rdma/opa_vnic.h char *dev_priv[0]; dev_priv 92 include/rdma/opa_vnic.h return oparn->dev_priv;