ddc_clk_regs       97 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c static const struct ddc_registers ddc_clk_regs[] = {
ddc_clk_regs       98 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c 	ddc_clk_regs(1),
ddc_clk_regs       99 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c 	ddc_clk_regs(2),
ddc_clk_regs      100 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c 	ddc_clk_regs(3),
ddc_clk_regs      101 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c 	ddc_clk_regs(4),
ddc_clk_regs      102 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c 	ddc_clk_regs(5),
ddc_clk_regs      103 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c 	ddc_clk_regs(6),
ddc_clk_regs      128 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c 		ddc->regs = &ddc_clk_regs[en];
ddc_clk_regs      129 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c 		ddc->base.regs = &ddc_clk_regs[en].gpio;
ddc_clk_regs      110 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c static const struct ddc_registers ddc_clk_regs[] = {
ddc_clk_regs      111 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c 	ddc_clk_regs(1),
ddc_clk_regs      112 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c 	ddc_clk_regs(2),
ddc_clk_regs      113 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c 	ddc_clk_regs(3),
ddc_clk_regs      114 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c 	ddc_clk_regs(4),
ddc_clk_regs      115 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c 	ddc_clk_regs(5),
ddc_clk_regs      116 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c 	ddc_clk_regs(6),
ddc_clk_regs      141 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c 		ddc->regs = &ddc_clk_regs[en];
ddc_clk_regs      142 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c 		ddc->base.regs = &ddc_clk_regs[en].gpio;
ddc_clk_regs       97 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c static const struct ddc_registers ddc_clk_regs[] = {
ddc_clk_regs       98 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c 	ddc_clk_regs(1),
ddc_clk_regs       99 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c 	ddc_clk_regs(2),
ddc_clk_regs      100 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c 	ddc_clk_regs(3),
ddc_clk_regs      101 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c 	ddc_clk_regs(4),
ddc_clk_regs      102 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c 	ddc_clk_regs(5),
ddc_clk_regs      103 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c 	ddc_clk_regs(6),
ddc_clk_regs      128 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c 		ddc->regs = &ddc_clk_regs[en];
ddc_clk_regs      129 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c 		ddc->base.regs = &ddc_clk_regs[en].gpio;
ddc_clk_regs      106 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c static const struct ddc_registers ddc_clk_regs[] = {
ddc_clk_regs      107 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c 	ddc_clk_regs(1),
ddc_clk_regs      108 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c 	ddc_clk_regs(2),
ddc_clk_regs      109 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c 	ddc_clk_regs(3),
ddc_clk_regs      110 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c 	ddc_clk_regs(4),
ddc_clk_regs      111 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c 	ddc_clk_regs(5),
ddc_clk_regs      112 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c 	ddc_clk_regs(6),
ddc_clk_regs      173 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c 		ddc->regs = &ddc_clk_regs[en];
ddc_clk_regs      174 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c 		ddc->base.regs = &ddc_clk_regs[en].gpio;