ddc 298 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c &amdgpu_connector->ddc_bus->aux.ddc); ddc 307 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c &amdgpu_connector->ddc_bus->aux.ddc); ddc 1508 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c struct i2c_adapter *ddc = NULL; ddc 1580 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc = &amdgpu_connector->ddc_bus->adapter; ddc 1592 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc); ddc 1613 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc); ddc 1657 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc); ddc 1676 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc = &amdgpu_connector->ddc_bus->adapter; ddc 1681 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc); ddc 1701 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc = &amdgpu_connector->ddc_bus->adapter; ddc 1706 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc); ddc 1731 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc = &amdgpu_connector->ddc_bus->adapter; ddc 1736 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc); ddc 1786 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc = &amdgpu_connector->ddc_bus->adapter; ddc 1791 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc); ddc 1832 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc = &amdgpu_connector->ddc_bus->adapter; ddc 1840 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc); ddc 1879 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc = &amdgpu_connector->ddc_bus->adapter; ddc 1887 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc); ddc 1906 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc = &amdgpu_connector->ddc_bus->adapter; ddc 1911 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ddc); ddc 473 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); ddc 5201 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c i2c = create_i2c(link->ddc, link->link_index, &res); ddc 574 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c struct i2c_adapter *ddc; ddc 580 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c ddc = &aconnector->dm_dp_aux.aux.ddc; ddc 582 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c ddc = &aconnector->i2c->base; ddc 589 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c edid = drm_get_edid(&aconnector->base, ddc); ddc 416 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; ddc 2398 drivers/gpu/drm/amd/display/dc/core/dc.c struct ddc_service *ddc = link->ddc; ddc 2401 drivers/gpu/drm/amd/display/dc/core/dc.c ddc->ddc_pin, ddc 87 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (link->ddc) ddc 88 drivers/gpu/drm/amd/display/dc/core/dc_link.c dal_ddc_service_destroy(&link->ddc); ddc 353 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct ddc *ddc; ddc 362 drivers/gpu/drm/amd/display/dc/core/dc_link.c ddc = dal_ddc_service_get_ddc_pin(link->ddc); ddc 364 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (!ddc) { ddc 375 drivers/gpu/drm/amd/display/dc/core/dc_link.c ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) { ddc 376 drivers/gpu/drm/amd/display/dc/core/dc_link.c dal_ddc_close(ddc); ddc 390 drivers/gpu/drm/amd/display/dc/core/dc_link.c gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin); ddc 400 drivers/gpu/drm/amd/display/dc/core/dc_link.c dal_ddc_close(ddc); ddc 495 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct ddc_service *ddc, ddc 500 drivers/gpu/drm/amd/display/dc/core/dc_link.c ddc, sink_cap); ddc 604 drivers/gpu/drm/amd/display/dc/core/dc_link.c link->ddc, ddc 664 drivers/gpu/drm/amd/display/dc/core/dc_link.c sink_caps->signal = dp_passive_dongle_detection(link->ddc, ddc 892 drivers/gpu/drm/amd/display/dc/core/dc_link.c link->ddc, ddc 896 drivers/gpu/drm/amd/display/dc/core/dc_link.c link->ddc); ddc 1103 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct ddc *ddc; ddc 1106 drivers/gpu/drm/amd/display/dc/core/dc_link.c ddc = dal_ddc_service_get_ddc_pin(link->ddc); ddc 1108 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (ddc) { ddc 1109 drivers/gpu/drm/amd/display/dc/core/dc_link.c switch (dal_ddc_get_line(ddc)) { ddc 1299 drivers/gpu/drm/amd/display/dc/core/dc_link.c link->ddc = dal_ddc_service_create(&ddc_service_init_data); ddc 1301 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (link->ddc == NULL) { ddc 1308 drivers/gpu/drm/amd/display/dc/core/dc_link.c dal_ddc_service_get_ddc_pin(link->ddc)); ddc 1387 drivers/gpu/drm/amd/display/dc/core/dc_link.c dal_ddc_service_destroy(&link->ddc); ddc 1752 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->link->ddc, ddc 1805 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->stream->link->ddc, ddc 2065 drivers/gpu/drm/amd/display/dc/core/dc_link.c stream->link->ddc, ddc 2084 drivers/gpu/drm/amd/display/dc/core/dc_link.c dal_ddc_service_read_scdc_data(link->ddc); ddc 2827 drivers/gpu/drm/amd/display/dc/core/dc_link.c link->ddc, ddc 243 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c static void destruct(struct ddc_service *ddc) ddc 245 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c if (ddc->ddc_pin) ddc 246 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c dal_gpio_destroy_ddc(&ddc->ddc_pin); ddc 249 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c void dal_ddc_service_destroy(struct ddc_service **ddc) ddc 251 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c if (!ddc || !*ddc) { ddc 255 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c destruct(*ddc); ddc 256 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c kfree(*ddc); ddc 257 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c *ddc = NULL; ddc 260 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc) ddc 266 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c struct ddc_service *ddc, ddc 269 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c ddc->transaction_type = type; ddc 272 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc) ddc 274 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c switch (ddc->transaction_type) { ddc 285 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c void ddc_service_set_dongle_type(struct ddc_service *ddc, ddc 288 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c ddc->dongle_type = dongle_type; ddc 292 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c struct ddc_service *ddc, ddc 295 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c struct dc_link *link = ddc->link; ddc 309 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t get_defer_delay(struct ddc_service *ddc) ddc 313 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c switch (ddc->transaction_type) { ddc 315 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) || ddc 316 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c (DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) || ddc 318 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c ddc->dongle_type)) { ddc 323 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c defer_delay_converter_wa(ddc, defer_delay); ddc 338 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c struct ddc_service *ddc, ddc 360 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c .speed = ddc->ctx->dc->caps.i2c_speed_in_khz }; ddc 363 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c ddc->ctx, ddc 364 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c ddc->link, ddc 369 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c struct ddc_service *ddc, ddc 386 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c ddc, ddc 392 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c if (i2c_read(ddc, ddc 403 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf), ddc 450 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c CONN_DATA_DETECT(ddc->link, type2_dongle_buf, ddc 458 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c CONN_DATA_DETECT(ddc->link, type2_dongle_buf, ddc 465 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c CONN_DATA_DETECT(ddc->link, type2_dongle_buf, ddc 481 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c CONN_DATA_DETECT(ddc->link, type2_dongle_buf, ddc 488 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c CONN_DATA_DETECT(ddc->link, type2_dongle_buf, ddc 504 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c struct ddc_service *ddc, ddc 513 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c dal_ddc_service_is_in_aux_transaction_mode(ddc) ? ddc 529 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) { ddc 538 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c .defer_delay = get_defer_delay(ddc), ddc 549 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c .defer_delay = get_defer_delay(ddc), ddc 552 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c ret = dc_link_aux_transfer_with_retries(ddc, &write_payload); ddc 557 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c ret = dc_link_aux_transfer_with_retries(ddc, &read_payload); ddc 560 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c dal_ddc_i2c_payloads_create(ddc->ctx, payloads_num); ddc 566 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c .speed = ddc->ctx->dc->caps.i2c_speed_in_khz }; ddc 578 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c ddc->ctx, ddc 579 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c ddc->link, ddc 595 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c int dc_link_aux_transfer_raw(struct ddc_service *ddc, ddc 599 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c return dce_aux_transfer_raw(ddc, payload, operation_result); ddc 610 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc, ddc 613 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c return dce_aux_transfer_with_retries(ddc, payload); ddc 619 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c struct ddc *ddc) ddc 621 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c ddc_service->ddc_pin = ddc; ddc 624 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service) ddc 2553 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c ddc_service_set_dongle_type(link->ddc, ddc 2645 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type); ddc 163 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h struct ddc *ddc_pin; ddc 110 drivers/gpu/drm/amd/display/dc/dc_link.h struct ddc_service *ddc; ddc 63 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c dal_ddc_close(engine->ddc); ddc 65 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c engine->ddc = NULL; ddc 256 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE, ddc 385 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c struct ddc *ddc) ddc 392 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE, ddc 399 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c dal_ddc_close(ddc); ddc 403 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c engine->ddc = ddc; ddc 423 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c aux_engine110->base.ddc = NULL; ddc 451 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c int dce_aux_transfer_raw(struct ddc_service *ddc, ddc 455 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c struct ddc *ddc_pin = ddc->ddc_pin; ddc 466 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; ddc 490 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c EVENT_LOG_AUX_REP(aux_engine->ddc->pin_data->en, ddc 508 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c bool dce_aux_transfer_with_retries(struct ddc_service *ddc, ddc 527 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c ret = dce_aux_transfer_raw(ddc, payload, &operation_result); ddc 93 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h struct ddc *ddc; ddc 134 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h struct ddc *ddc); ddc 136 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h int dce_aux_transfer_raw(struct ddc_service *ddc, ddc 140 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h bool dce_aux_transfer_with_retries(struct ddc_service *ddc, ddc 30 drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c struct ddc *ddc, ddc 36 drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c if (!ddc) { ddc 47 drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c dce_i2c_sw = dce_i2c_acquire_i2c_sw_engine(pool, ddc); ddc 50 drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c dce_i2c_hw = acquire_i2c_hw_engine(pool, ddc); ddc 55 drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c return dce_i2c_submit_command_hw(pool, ddc, cmd, dce_i2c_hw); ddc 58 drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c return dce_i2c_submit_command_sw(pool, ddc, cmd, dce_i2c_sw); ddc 35 drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h struct ddc *ddc, ddc 381 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct ddc *ddc) ddc 388 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (!ddc) ddc 391 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (ddc->hw_info.hw_supported) { ddc 392 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c enum gpio_ddc_line line = dal_ddc_get_line(ddc); ddc 405 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE, ddc 421 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->ddc = ddc; ddc 578 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct ddc *ddc, ddc 608 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dal_ddc_close(dce_i2c_hw->ddc); ddc 610 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->ddc = NULL; ddc 264 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h struct ddc *ddc; ddc 327 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h struct ddc *ddc, ddc 333 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h struct ddc *ddc); ddc 42 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc, ddc 48 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c dal_gpio_get_value(ddc->pin_data, &value); ddc 50 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c dal_gpio_get_value(ddc->pin_clock, &value); ddc 56 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc, ddc 63 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c dal_gpio_set_value(ddc->pin_data, value); ddc 65 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c dal_gpio_set_value(ddc->pin_clock, value); ddc 72 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c dal_ddc_close(dce_i2c_sw->ddc); ddc 73 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c dce_i2c_sw->ddc = NULL; ddc 77 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc, ddc 84 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c if (!ddc) { ddc 89 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c if (!ddc->hw_info.hw_supported) ddc 92 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c line_found = dal_ddc_get_line(ddc); ddc 103 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc, ddc 112 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c if (read_bit_from_ddc(ddc, SCL)) ddc 124 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc_handle, ddc 181 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc_handle, ddc 241 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc_handle, ddc 278 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc_handle, ddc 300 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc_handle, ddc 325 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc_handle, ddc 383 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc) ddc 387 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c result = dal_ddc_open(ddc, GPIO_MODE_FAST_OUTPUT, ddc 393 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c engine->ddc = ddc; ddc 399 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc_handle) ddc 429 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc = engine->ddc; ddc 434 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c bool result = start_sync_sw(engine->ctx, ddc, clock_delay_div_4); ddc 442 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c result = i2c_write_sw(engine->ctx, ddc, clock_delay_div_4, ddc 447 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c result = i2c_read_sw(engine->ctx, ddc, clock_delay_div_4, ddc 461 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c if (!stop_sync_sw(engine->ctx, ddc, clock_delay_div_4)) ddc 498 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc, ddc 529 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c struct ddc *ddc) ddc 534 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c if (get_hw_supported_ddc_line(ddc, &line)) ddc 540 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c if (!dce_i2c_engine_acquire_sw(engine, ddc)) ddc 36 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h struct ddc *ddc; ddc 48 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h struct ddc *ddc, ddc 54 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h struct ddc *ddc); ddc 2829 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c stream->link->ddc->dongle_type; ddc 34 drivers/gpu/drm/amd/display/dc/dm_event_log.h #define EVENT_LOG_AUX_REQ(ddc, type, action, address, len, data) ddc 35 drivers/gpu/drm/amd/display/dc/dm_event_log.h #define EVENT_LOG_AUX_REP(ddc, type, replyStatus, len, data) ddc 120 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); ddc 124 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c ddc->regs = &ddc_data_regs[en]; ddc 125 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c ddc->base.regs = &ddc_data_regs[en].gpio; ddc 128 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c ddc->regs = &ddc_clk_regs[en]; ddc 129 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c ddc->base.regs = &ddc_clk_regs[en].gpio; ddc 136 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c ddc->shifts = &ddc_shift; ddc 137 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c ddc->masks = &ddc_mask; ddc 133 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); ddc 137 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c ddc->regs = &ddc_data_regs[en]; ddc 138 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c ddc->base.regs = &ddc_data_regs[en].gpio; ddc 141 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c ddc->regs = &ddc_clk_regs[en]; ddc 142 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c ddc->base.regs = &ddc_clk_regs[en].gpio; ddc 149 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c ddc->shifts = &ddc_shift; ddc 150 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c ddc->masks = &ddc_mask; ddc 120 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); ddc 124 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c ddc->regs = &ddc_data_regs[en]; ddc 125 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c ddc->base.regs = &ddc_data_regs[en].gpio; ddc 128 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c ddc->regs = &ddc_clk_regs[en]; ddc 129 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c ddc->base.regs = &ddc_clk_regs[en].gpio; ddc 136 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c ddc->shifts = &ddc_shift; ddc 137 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c ddc->masks = &ddc_mask; ddc 165 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); ddc 169 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c ddc->regs = &ddc_data_regs[en]; ddc 170 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c ddc->base.regs = &ddc_data_regs[en].gpio; ddc 173 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c ddc->regs = &ddc_clk_regs[en]; ddc 174 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c ddc->base.regs = &ddc_clk_regs[en].gpio; ddc 181 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c ddc->shifts = &ddc_shift; ddc 182 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c ddc->masks = &ddc_mask; ddc 172 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); ddc 176 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c ddc->regs = &ddc_data_regs_dcn[en]; ddc 177 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c ddc->base.regs = &ddc_data_regs_dcn[en].gpio; ddc 180 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c ddc->regs = &ddc_clk_regs_dcn[en]; ddc 181 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; ddc 188 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c ddc->shifts = &ddc_shift[en]; ddc 189 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c ddc->masks = &ddc_mask[en]; ddc 174 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); ddc 178 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c ddc->regs = &ddc_data_regs_dcn[en]; ddc 179 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c ddc->base.regs = &ddc_data_regs_dcn[en].gpio; ddc 182 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c ddc->regs = &ddc_clk_regs_dcn[en]; ddc 183 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; ddc 190 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c ddc->shifts = &ddc_shift[en]; ddc 191 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c ddc->masks = &ddc_mask[en]; ddc 71 drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c if (!gpio->hw_container.ddc) { ddc 240 drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c return gpio->hw_container.ddc; ddc 292 drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en); ddc 295 drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en); ddc 328 drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c kfree((*gpio)->hw_container.ddc); ddc 329 drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c (*gpio)->hw_container.ddc = NULL; ddc 333 drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c kfree((*gpio)->hw_container.ddc); ddc 334 drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c (*gpio)->hw_container.ddc = NULL; ddc 470 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c struct ddc *dal_gpio_create_ddc( ddc 478 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c struct ddc *ddc; ddc 483 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c ddc = kzalloc(sizeof(struct ddc), GFP_KERNEL); ddc 485 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c if (!ddc) { ddc 490 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c ddc->pin_data = dal_gpio_create( ddc 493 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c if (!ddc->pin_data) { ddc 498 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c ddc->pin_clock = dal_gpio_create( ddc 501 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c if (!ddc->pin_clock) { ddc 506 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c ddc->hw_info = *info; ddc 508 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c ddc->ctx = service->ctx; ddc 510 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c return ddc; ddc 513 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c dal_gpio_destroy(&ddc->pin_data); ddc 516 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c kfree(ddc); ddc 522 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c struct ddc **ddc) ddc 524 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c if (!ddc || !*ddc) { ddc 529 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c dal_ddc_close(*ddc); ddc 530 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c dal_gpio_destroy(&(*ddc)->pin_data); ddc 531 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c dal_gpio_destroy(&(*ddc)->pin_clock); ddc 532 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c kfree(*ddc); ddc 534 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c *ddc = NULL; ddc 538 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c struct ddc *ddc, ddc 548 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c result = dal_gpio_open_ex(ddc->pin_data, mode); ddc 555 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c result = dal_gpio_open_ex(ddc->pin_clock, mode); ddc 573 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c config_data.config.ddc.type = config_type; ddc 575 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c hw_data = FROM_HW_GPIO_PIN(ddc->pin_data->pin); ddc 576 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c hw_clock = FROM_HW_GPIO_PIN(ddc->pin_clock->pin); ddc 578 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c config_data.config.ddc.data_en_bit_present = hw_data->store.en != 0; ddc 579 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c config_data.config.ddc.clock_en_bit_present = hw_clock->store.en != 0; ddc 581 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c result = dal_gpio_set_config(ddc->pin_data, &config_data); ddc 588 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c dal_gpio_close(ddc->pin_clock); ddc 591 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c dal_gpio_close(ddc->pin_data); ddc 597 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c struct ddc *ddc, ddc 603 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c dal_gpio_get_mode(ddc->pin_data); ddc 605 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c result = dal_gpio_change_mode(ddc->pin_data, mode); ddc 615 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c result = dal_gpio_change_mode(ddc->pin_clock, mode); ddc 620 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c dal_gpio_change_mode(ddc->pin_clock, original_mode); ddc 623 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c dal_gpio_change_mode(ddc->pin_data, original_mode); ddc 629 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c const struct ddc *ddc) ddc 631 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c return (enum gpio_ddc_line)dal_gpio_get_enum(ddc->pin_data); ddc 635 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c struct ddc *ddc, ddc 642 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c config_data.config.ddc.type = config_type; ddc 643 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c config_data.config.ddc.data_en_bit_present = false; ddc 644 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c config_data.config.ddc.clock_en_bit_present = false; ddc 646 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c return dal_gpio_set_config(ddc->pin_data, &config_data); ddc 650 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c struct ddc *ddc) ddc 652 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c dal_gpio_close(ddc->pin_clock); ddc 653 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c dal_gpio_close(ddc->pin_data); ddc 42 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c ddc->shifts->field_name, ddc->masks->field_name ddc 45 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c ddc->base.base.ctx ddc 47 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c (ddc->regs->reg) ddc 73 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr); ddc 80 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c hw_gpio = &ddc->base; ddc 92 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c switch (config_data->config.ddc.type) { ddc 140 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c if (config_data->config.ddc.data_en_bit_present || ddc 141 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c config_data->config.ddc.clock_en_bit_present) ddc 154 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { ddc 158 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c if (ddc->regs->phy_aux_cntl != 0) { ddc 170 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { ddc 224 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c struct hw_ddc *ddc, ddc 229 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c dal_hw_gpio_construct(&ddc->base, id, en, ctx); ddc 230 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c ddc->base.base.funcs = &funcs; ddc 76 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h void dal_ddc_service_destroy(struct ddc_service **ddc); ddc 78 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc); ddc 81 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h struct ddc_service *ddc, ddc 84 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc); ddc 87 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h struct ddc_service *ddc, ddc 91 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h struct ddc_service *ddc, ddc 98 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h int dc_link_aux_transfer_raw(struct ddc_service *ddc, ddc 102 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc, ddc 113 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h void ddc_service_set_dongle_type(struct ddc_service *ddc, ddc 118 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h struct ddc *ddc); ddc 120 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service); ddc 122 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h uint32_t get_defer_delay(struct ddc_service *ddc); ddc 86 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h struct ddc *ddc; ddc 170 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h struct ddc *ddc); ddc 33 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h struct hw_ddc *ddc; ddc 71 drivers/gpu/drm/amd/display/include/gpio_service_interface.h struct ddc *dal_gpio_create_ddc( ddc 78 drivers/gpu/drm/amd/display/include/gpio_service_interface.h struct ddc **ddc); ddc 103 drivers/gpu/drm/amd/display/include/gpio_service_interface.h struct ddc *ddc, ddc 108 drivers/gpu/drm/amd/display/include/gpio_service_interface.h struct ddc *ddc, ddc 112 drivers/gpu/drm/amd/display/include/gpio_service_interface.h const struct ddc *ddc); ddc 115 drivers/gpu/drm/amd/display/include/gpio_service_interface.h struct ddc *ddc, ddc 119 drivers/gpu/drm/amd/display/include/gpio_service_interface.h struct ddc *ddc); ddc 325 drivers/gpu/drm/amd/display/include/gpio_types.h struct gpio_ddc_config ddc; ddc 34 drivers/gpu/drm/amd/display/include/link_service_types.h struct ddc; ddc 958 drivers/gpu/drm/bridge/analogix-anx78xx.c anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc); ddc 1122 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c edid = drm_get_edid(connector, &dp->aux.ddc); ddc 23 drivers/gpu/drm/bridge/dumb-vga-dac.c struct i2c_adapter *ddc; ddc 45 drivers/gpu/drm/bridge/dumb-vga-dac.c if (!vga->ddc) ddc 48 drivers/gpu/drm/bridge/dumb-vga-dac.c edid = drm_get_edid(connector, vga->ddc); ddc 87 drivers/gpu/drm/bridge/dumb-vga-dac.c if (vga->ddc && drm_probe_ddc(vga->ddc)) ddc 117 drivers/gpu/drm/bridge/dumb-vga-dac.c vga->ddc); ddc 158 drivers/gpu/drm/bridge/dumb-vga-dac.c struct i2c_adapter *ddc; ddc 169 drivers/gpu/drm/bridge/dumb-vga-dac.c ddc = of_get_i2c_adapter_by_node(phandle); ddc 171 drivers/gpu/drm/bridge/dumb-vga-dac.c if (!ddc) ddc 174 drivers/gpu/drm/bridge/dumb-vga-dac.c return ddc; ddc 195 drivers/gpu/drm/bridge/dumb-vga-dac.c vga->ddc = dumb_vga_retrieve_ddc(&pdev->dev); ddc 196 drivers/gpu/drm/bridge/dumb-vga-dac.c if (IS_ERR(vga->ddc)) { ddc 197 drivers/gpu/drm/bridge/dumb-vga-dac.c if (PTR_ERR(vga->ddc) == -ENODEV) { ddc 200 drivers/gpu/drm/bridge/dumb-vga-dac.c vga->ddc = NULL; ddc 203 drivers/gpu/drm/bridge/dumb-vga-dac.c return PTR_ERR(vga->ddc); ddc 222 drivers/gpu/drm/bridge/dumb-vga-dac.c if (vga->ddc) ddc 223 drivers/gpu/drm/bridge/dumb-vga-dac.c i2c_put_adapter(vga->ddc); ddc 164 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c struct i2c_adapter *ddc; ddc 1182 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if (!hdmi->ddc) ddc 1221 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1); ddc 1223 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0); ddc 1829 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, ddc 1831 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, ddc 1835 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c drm_scdc_set_scrambling(hdmi->ddc, 1); ddc 1851 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c drm_scdc_set_scrambling(hdmi->ddc, 0); ddc 2197 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if (!hdmi->ddc) ddc 2200 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c edid = drm_get_edid(connector, hdmi->ddc); ddc 2260 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi->ddc); ddc 2646 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); ddc 2648 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if (!hdmi->ddc) { ddc 2781 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if (!hdmi->ddc) { ddc 2800 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); ddc 2801 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if (IS_ERR(hdmi->ddc)) ddc 2802 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi->ddc = NULL; ddc 2869 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi->ddc = NULL; ddc 2878 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c i2c_put_adapter(hdmi->ddc); ddc 2901 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c i2c_put_adapter(hdmi->ddc); ddc 1333 drivers/gpu/drm/bridge/tc358767.c edid = drm_get_edid(connector, &tc->aux.ddc); ddc 29 drivers/gpu/drm/bridge/ti-tfp410.c struct i2c_adapter *ddc; ddc 58 drivers/gpu/drm/bridge/ti-tfp410.c if (!dvi->ddc) ddc 61 drivers/gpu/drm/bridge/ti-tfp410.c edid = drm_get_edid(connector, dvi->ddc); ddc 101 drivers/gpu/drm/bridge/ti-tfp410.c if (dvi->ddc) { ddc 102 drivers/gpu/drm/bridge/ti-tfp410.c if (drm_probe_ddc(dvi->ddc)) ddc 140 drivers/gpu/drm/bridge/ti-tfp410.c dvi->ddc); ddc 302 drivers/gpu/drm/bridge/ti-tfp410.c dvi->ddc = of_get_i2c_adapter_by_node(ddc_phandle); ddc 303 drivers/gpu/drm/bridge/ti-tfp410.c if (dvi->ddc) ddc 372 drivers/gpu/drm/bridge/ti-tfp410.c i2c_put_adapter(dvi->ddc); ddc 387 drivers/gpu/drm/bridge/ti-tfp410.c if (dvi->ddc) ddc 388 drivers/gpu/drm/bridge/ti-tfp410.c i2c_put_adapter(dvi->ddc); ddc 320 drivers/gpu/drm/drm_connector.c struct i2c_adapter *ddc) ddc 329 drivers/gpu/drm/drm_connector.c connector->ddc = ddc; ddc 988 drivers/gpu/drm/drm_dp_helper.c return container_of(i2c, struct drm_dp_aux, ddc); ddc 1099 drivers/gpu/drm/drm_dp_helper.c aux->ddc.algo = &drm_dp_i2c_algo; ddc 1100 drivers/gpu/drm/drm_dp_helper.c aux->ddc.algo_data = aux; ddc 1101 drivers/gpu/drm/drm_dp_helper.c aux->ddc.retries = 3; ddc 1103 drivers/gpu/drm/drm_dp_helper.c aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; ddc 1119 drivers/gpu/drm/drm_dp_helper.c if (!aux->ddc.algo) ddc 1122 drivers/gpu/drm/drm_dp_helper.c aux->ddc.class = I2C_CLASS_DDC; ddc 1123 drivers/gpu/drm/drm_dp_helper.c aux->ddc.owner = THIS_MODULE; ddc 1124 drivers/gpu/drm/drm_dp_helper.c aux->ddc.dev.parent = aux->dev; ddc 1126 drivers/gpu/drm/drm_dp_helper.c strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), ddc 1127 drivers/gpu/drm/drm_dp_helper.c sizeof(aux->ddc.name)); ddc 1133 drivers/gpu/drm/drm_dp_helper.c ret = i2c_add_adapter(&aux->ddc); ddc 1150 drivers/gpu/drm/drm_dp_helper.c i2c_del_adapter(&aux->ddc); ddc 1714 drivers/gpu/drm/drm_dp_mst_topology.c &port->aux.ddc); ddc 3101 drivers/gpu/drm/drm_dp_mst_topology.c port->cached_edid = drm_get_edid(connector, &port->aux.ddc); ddc 3158 drivers/gpu/drm/drm_dp_mst_topology.c edid = drm_get_edid(connector, &port->aux.ddc); ddc 4125 drivers/gpu/drm/drm_dp_mst_topology.c aux->ddc.algo = &drm_dp_mst_i2c_algo; ddc 4126 drivers/gpu/drm/drm_dp_mst_topology.c aux->ddc.algo_data = aux; ddc 4127 drivers/gpu/drm/drm_dp_mst_topology.c aux->ddc.retries = 3; ddc 4129 drivers/gpu/drm/drm_dp_mst_topology.c aux->ddc.class = I2C_CLASS_DDC; ddc 4130 drivers/gpu/drm/drm_dp_mst_topology.c aux->ddc.owner = THIS_MODULE; ddc 4131 drivers/gpu/drm/drm_dp_mst_topology.c aux->ddc.dev.parent = aux->dev; ddc 4132 drivers/gpu/drm/drm_dp_mst_topology.c aux->ddc.dev.of_node = aux->dev->of_node; ddc 4134 drivers/gpu/drm/drm_dp_mst_topology.c strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), ddc 4135 drivers/gpu/drm/drm_dp_mst_topology.c sizeof(aux->ddc.name)); ddc 4137 drivers/gpu/drm/drm_dp_mst_topology.c return i2c_add_adapter(&aux->ddc); ddc 4146 drivers/gpu/drm/drm_dp_mst_topology.c i2c_del_adapter(&aux->ddc); ddc 299 drivers/gpu/drm/drm_sysfs.c if (connector->ddc) ddc 301 drivers/gpu/drm/drm_sysfs.c &connector->ddc->dev.kobj, "ddc"); ddc 310 drivers/gpu/drm/drm_sysfs.c if (connector->ddc) ddc 73 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct i2c_adapter ddc; ddc 1311 drivers/gpu/drm/gma500/psb_intel_sdvo.c return drm_get_edid(connector, &sdvo->ddc); ddc 1334 drivers/gpu/drm/gma500/psb_intel_sdvo.c u8 ddc, saved_ddc = psb_intel_sdvo->ddc_bus; ddc 1340 drivers/gpu/drm/gma500/psb_intel_sdvo.c for (ddc = psb_intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { ddc 1341 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo->ddc_bus = ddc; ddc 1867 drivers/gpu/drm/gma500/psb_intel_sdvo.c i2c_del_adapter(&psb_intel_sdvo->ddc); ddc 2504 drivers/gpu/drm/gma500/psb_intel_sdvo.c sdvo->ddc.owner = THIS_MODULE; ddc 2505 drivers/gpu/drm/gma500/psb_intel_sdvo.c sdvo->ddc.class = I2C_CLASS_DDC; ddc 2506 drivers/gpu/drm/gma500/psb_intel_sdvo.c snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); ddc 2507 drivers/gpu/drm/gma500/psb_intel_sdvo.c sdvo->ddc.dev.parent = &dev->pdev->dev; ddc 2508 drivers/gpu/drm/gma500/psb_intel_sdvo.c sdvo->ddc.algo_data = sdvo; ddc 2509 drivers/gpu/drm/gma500/psb_intel_sdvo.c sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy; ddc 2511 drivers/gpu/drm/gma500/psb_intel_sdvo.c return i2c_add_adapter(&sdvo->ddc) == 0; ddc 2599 drivers/gpu/drm/gma500/psb_intel_sdvo.c i2c_del_adapter(&psb_intel_sdvo->ddc); ddc 5023 drivers/gpu/drm/i915/display/intel_dp.c if (drm_probe_ddc(&intel_dp->aux.ddc)) ddc 5316 drivers/gpu/drm/i915/display/intel_dp.c &intel_dp->aux.ddc); ddc 7046 drivers/gpu/drm/i915/display/intel_dp.c edid = drm_get_edid(connector, &intel_dp->aux.ddc); ddc 110 drivers/gpu/drm/i915/display/intel_lspcon.c struct i2c_adapter *adapter = &lspcon_to_intel_dp(lspcon)->aux.ddc; ddc 147 drivers/gpu/drm/i915/display/intel_lspcon.c struct i2c_adapter *adapter = &lspcon_to_intel_dp(lspcon)->aux.ddc; ddc 206 drivers/gpu/drm/i915/display/intel_lspcon.c struct i2c_adapter *adapter = &lspcon_to_intel_dp(lspcon)->aux.ddc; ddc 84 drivers/gpu/drm/i915/display/intel_sdvo.c struct i2c_adapter ddc; ddc 1945 drivers/gpu/drm/i915/display/intel_sdvo.c return drm_get_edid(connector, &sdvo->ddc); ddc 1971 drivers/gpu/drm/i915/display/intel_sdvo.c u8 ddc, saved_ddc = intel_sdvo->ddc_bus; ddc 1977 drivers/gpu/drm/i915/display/intel_sdvo.c for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { ddc 1978 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo->ddc_bus = ddc; ddc 2245 drivers/gpu/drm/i915/display/intel_sdvo.c intel_ddc_get_modes(connector, &intel_sdvo->ddc); ddc 2390 drivers/gpu/drm/i915/display/intel_sdvo.c &sdvo->ddc.dev.kobj, ddc 2391 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo->ddc.dev.kobj.name); ddc 2400 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo->ddc.dev.kobj.name); ddc 2464 drivers/gpu/drm/i915/display/intel_sdvo.c i2c_del_adapter(&intel_sdvo->ddc); ddc 3218 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo->ddc.owner = THIS_MODULE; ddc 3219 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo->ddc.class = I2C_CLASS_DDC; ddc 3220 drivers/gpu/drm/i915/display/intel_sdvo.c snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); ddc 3221 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo->ddc.dev.parent = &pdev->dev; ddc 3222 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo->ddc.algo_data = sdvo; ddc 3223 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo->ddc.algo = &intel_sdvo_ddc_proxy; ddc 3224 drivers/gpu/drm/i915/display/intel_sdvo.c sdvo->ddc.lock_ops = &proxy_lock_ops; ddc 3226 drivers/gpu/drm/i915/display/intel_sdvo.c return i2c_add_adapter(&sdvo->ddc) == 0; ddc 3358 drivers/gpu/drm/i915/display/intel_sdvo.c i2c_del_adapter(&intel_sdvo->ddc); ddc 60 drivers/gpu/drm/imx/imx-ldb.c struct i2c_adapter *ddc; ddc 133 drivers/gpu/drm/imx/imx-ldb.c if (!imx_ldb_ch->edid && imx_ldb_ch->ddc) ddc 134 drivers/gpu/drm/imx/imx-ldb.c imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc); ddc 465 drivers/gpu/drm/imx/imx-ldb.c imx_ldb_ch->ddc); ddc 553 drivers/gpu/drm/imx/imx-ldb.c channel->ddc = of_find_i2c_adapter_by_node(ddc_node); ddc 555 drivers/gpu/drm/imx/imx-ldb.c if (!channel->ddc) { ddc 561 drivers/gpu/drm/imx/imx-ldb.c if (!channel->ddc) { ddc 728 drivers/gpu/drm/imx/imx-ldb.c i2c_put_adapter(channel->ddc); ddc 114 drivers/gpu/drm/imx/imx-tve.c struct i2c_adapter *ddc; ddc 227 drivers/gpu/drm/imx/imx-tve.c if (!tve->ddc) ddc 230 drivers/gpu/drm/imx/imx-tve.c edid = drm_get_edid(connector, tve->ddc); ddc 490 drivers/gpu/drm/imx/imx-tve.c tve->ddc); ddc 558 drivers/gpu/drm/imx/imx-tve.c tve->ddc = of_find_i2c_adapter_by_node(ddc_node); ddc 62 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, ddc 65 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c writel(readl(ddc->regs + offset) | val, ddc->regs + offset); ddc 68 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, ddc 71 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset); ddc 74 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset, ddc 77 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c return (readl(ddc->regs + offset) & val) == val; ddc 80 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset, ddc 86 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c tmp = readl(ddc->regs + offset); ddc 89 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c writel(tmp, ddc->regs + offset); ddc 92 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc, ddc 96 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c return (readl(ddc->regs + offset) & mask) >> shift; ddc 99 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c static void ddcm_trigger_mode(struct mtk_hdmi_ddc *ddc, int mode) ddc 103 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK, ddc 105 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI); ddc 106 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val, ddc 110 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c static int mtk_hdmi_ddc_read_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg) ddc 112 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c struct device *dev = ddc->adap.dev.parent; ddc 118 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddcm_trigger_mode(ddc, DDCM_START); ddc 119 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01); ddc 120 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET, ddc 122 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddcm_trigger_mode(ddc, DDCM_WRITE_DATA); ddc 123 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET); ddc 144 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, ddc 146 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddcm_trigger_mode(ddc, (ack_final == 1) ? ddc 150 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, ddc 173 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c msg->buf[index + i - 1] = sif_read_mask(ddc, offset, ddc 185 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c static int mtk_hdmi_ddc_write_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg) ddc 187 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c struct device *dev = ddc->adap.dev.parent; ddc 190 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddcm_trigger_mode(ddc, DDCM_START); ddc 191 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1); ddc 192 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]); ddc 193 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET, ddc 195 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddcm_trigger_mode(ddc, DDCM_WRITE_DATA); ddc 197 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET); ddc 211 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c struct mtk_hdmi_ddc *ddc = adapter->algo_data; ddc 216 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c if (!ddc) { ddc 221 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SCL_STRECH); ddc 222 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SM0EN); ddc 223 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c sif_clr_bit(ddc, DDC_DDCMCTL0, DDCM_ODRAIN); ddc 225 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) { ddc 230 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK, ddc 240 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ret = mtk_hdmi_ddc_read_msg(ddc, msg); ddc 242 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ret = mtk_hdmi_ddc_write_msg(ddc, msg); ddc 247 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddcm_trigger_mode(ddc, DDCM_STOP); ddc 252 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddcm_trigger_mode(ddc, DDCM_STOP); ddc 270 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c struct mtk_hdmi_ddc *ddc; ddc 274 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddc = devm_kzalloc(dev, sizeof(struct mtk_hdmi_ddc), GFP_KERNEL); ddc 275 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c if (!ddc) ddc 278 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddc->clk = devm_clk_get(dev, "ddc-i2c"); ddc 279 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c if (IS_ERR(ddc->clk)) { ddc 280 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c dev_err(dev, "get ddc_clk failed: %p ,\n", ddc->clk); ddc 281 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c return PTR_ERR(ddc->clk); ddc 285 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddc->regs = devm_ioremap_resource(&pdev->dev, mem); ddc 286 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c if (IS_ERR(ddc->regs)) ddc 287 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c return PTR_ERR(ddc->regs); ddc 289 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ret = clk_prepare_enable(ddc->clk); ddc 295 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c strlcpy(ddc->adap.name, "mediatek-hdmi-ddc", sizeof(ddc->adap.name)); ddc 296 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddc->adap.owner = THIS_MODULE; ddc 297 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddc->adap.class = I2C_CLASS_DDC; ddc 298 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddc->adap.algo = &mtk_hdmi_ddc_algorithm; ddc 299 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddc->adap.retries = 3; ddc 300 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddc->adap.dev.of_node = dev->of_node; ddc 301 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddc->adap.algo_data = ddc; ddc 302 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ddc->adap.dev.parent = &pdev->dev; ddc 304 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c ret = i2c_add_adapter(&ddc->adap); ddc 310 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c platform_set_drvdata(pdev, ddc); ddc 312 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c dev_dbg(dev, "ddc->adap: %p\n", &ddc->adap); ddc 313 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c dev_dbg(dev, "ddc->clk: %p\n", ddc->clk); ddc 320 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c clk_disable_unprepare(ddc->clk); ddc 326 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c struct mtk_hdmi_ddc *ddc = platform_get_drvdata(pdev); ddc 328 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c i2c_del_adapter(&ddc->adap); ddc 329 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c clk_disable_unprepare(ddc->clk); ddc 1237 drivers/gpu/drm/msm/edp/edp_ctrl.c ctrl->edid = drm_get_edid(connector, &ctrl->drm_aux->ddc); ddc 1621 drivers/gpu/drm/nouveau/dispnv50/disp.c nv_encoder->i2c = &nv_connector->aux.ddc; ddc 1732 drivers/gpu/drm/nouveau/dispnv50/disp.c struct i2c_adapter *ddc; ddc 1740 drivers/gpu/drm/nouveau/dispnv50/disp.c ddc = bus ? &bus->i2c : NULL; ddc 1745 drivers/gpu/drm/nouveau/dispnv50/disp.c ddc = aux ? &aux->i2c : NULL; ddc 1756 drivers/gpu/drm/nouveau/dispnv50/disp.c nv_encoder->i2c = ddc; ddc 109 drivers/gpu/drm/panel/panel-simple.c struct i2c_adapter *ddc; ddc 326 drivers/gpu/drm/panel/panel-simple.c if (p->ddc) { ddc 327 drivers/gpu/drm/panel/panel-simple.c struct edid *edid = drm_get_edid(panel->connector, p->ddc); ddc 416 drivers/gpu/drm/panel/panel-simple.c struct device_node *backlight, *ddc; ddc 453 drivers/gpu/drm/panel/panel-simple.c ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); ddc 454 drivers/gpu/drm/panel/panel-simple.c if (ddc) { ddc 455 drivers/gpu/drm/panel/panel-simple.c panel->ddc = of_find_i2c_adapter_by_node(ddc); ddc 456 drivers/gpu/drm/panel/panel-simple.c of_node_put(ddc); ddc 458 drivers/gpu/drm/panel/panel-simple.c if (!panel->ddc) { ddc 480 drivers/gpu/drm/panel/panel-simple.c if (panel->ddc) ddc 481 drivers/gpu/drm/panel/panel-simple.c put_device(&panel->ddc->dev); ddc 498 drivers/gpu/drm/panel/panel-simple.c if (panel->ddc) ddc 499 drivers/gpu/drm/panel/panel-simple.c put_device(&panel->ddc->dev); ddc 418 drivers/gpu/drm/radeon/radeon_combios.c enum radeon_combios_ddc ddc, ddc 447 drivers/gpu/drm/radeon/radeon_combios.c switch (ddc) { ddc 472 drivers/gpu/drm/radeon/radeon_combios.c ddc = DDC_DVI; ddc 481 drivers/gpu/drm/radeon/radeon_combios.c ddc = DDC_DVI; ddc 488 drivers/gpu/drm/radeon/radeon_combios.c ddc = DDC_MONID; ddc 634 drivers/gpu/drm/radeon/radeon_combios.c i2c.i2c_id = ddc; ddc 314 drivers/gpu/drm/radeon/radeon_connectors.c &radeon_connector->ddc_bus->aux.ddc); ddc 323 drivers/gpu/drm/radeon/radeon_connectors.c &radeon_connector->ddc_bus->aux.ddc); ddc 70 drivers/gpu/drm/radeon/radeon_i2c.c ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2); ddc 61 drivers/gpu/drm/rockchip/inno_hdmi.c struct i2c_adapter *ddc; ddc 554 drivers/gpu/drm/rockchip/inno_hdmi.c if (!hdmi->ddc) ddc 557 drivers/gpu/drm/rockchip/inno_hdmi.c edid = drm_get_edid(connector, hdmi->ddc); ddc 852 drivers/gpu/drm/rockchip/inno_hdmi.c hdmi->ddc = inno_hdmi_i2c_adapter(hdmi); ddc 853 drivers/gpu/drm/rockchip/inno_hdmi.c if (IS_ERR(hdmi->ddc)) { ddc 854 drivers/gpu/drm/rockchip/inno_hdmi.c ret = PTR_ERR(hdmi->ddc); ddc 855 drivers/gpu/drm/rockchip/inno_hdmi.c hdmi->ddc = NULL; ddc 888 drivers/gpu/drm/rockchip/inno_hdmi.c i2c_put_adapter(hdmi->ddc); ddc 902 drivers/gpu/drm/rockchip/inno_hdmi.c i2c_put_adapter(hdmi->ddc); ddc 52 drivers/gpu/drm/rockchip/rk3066_hdmi.c struct i2c_adapter *ddc; ddc 473 drivers/gpu/drm/rockchip/rk3066_hdmi.c if (!hdmi->ddc) ddc 476 drivers/gpu/drm/rockchip/rk3066_hdmi.c edid = drm_get_edid(connector, hdmi->ddc); ddc 792 drivers/gpu/drm/rockchip/rk3066_hdmi.c hdmi->ddc = rk3066_hdmi_i2c_adapter(hdmi); ddc 793 drivers/gpu/drm/rockchip/rk3066_hdmi.c if (IS_ERR(hdmi->ddc)) { ddc 794 drivers/gpu/drm/rockchip/rk3066_hdmi.c ret = PTR_ERR(hdmi->ddc); ddc 795 drivers/gpu/drm/rockchip/rk3066_hdmi.c hdmi->ddc = NULL; ddc 827 drivers/gpu/drm/rockchip/rk3066_hdmi.c i2c_put_adapter(hdmi->ddc); ddc 842 drivers/gpu/drm/rockchip/rk3066_hdmi.c i2c_put_adapter(hdmi->ddc); ddc 1357 drivers/gpu/drm/sti/sti_hdmi.c struct device_node *ddc; ddc 1366 drivers/gpu/drm/sti/sti_hdmi.c ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0); ddc 1367 drivers/gpu/drm/sti/sti_hdmi.c if (ddc) { ddc 1368 drivers/gpu/drm/sti/sti_hdmi.c hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc); ddc 1369 drivers/gpu/drm/sti/sti_hdmi.c of_node_put(ddc); ddc 65 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c struct sun4i_ddc *ddc = hw_to_ddc(hw); ddc 67 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c return sun4i_ddc_calc_divider(rate, *prate, ddc->pre_div, ddc 68 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c ddc->m_offset, NULL, NULL); ddc 74 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c struct sun4i_ddc *ddc = hw_to_ddc(hw); ddc 78 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c regmap_field_read(ddc->reg, ®); ddc 82 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c return (((parent_rate / ddc->pre_div) / 10) >> n) / ddc 83 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c (m + ddc->m_offset); ddc 89 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c struct sun4i_ddc *ddc = hw_to_ddc(hw); ddc 92 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c sun4i_ddc_calc_divider(rate, parent_rate, ddc->pre_div, ddc 93 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c ddc->m_offset, &div_m, &div_n); ddc 95 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c regmap_field_write(ddc->reg, ddc 111 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c struct sun4i_ddc *ddc; ddc 118 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL); ddc 119 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c if (!ddc) ddc 122 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c ddc->reg = devm_regmap_field_alloc(hdmi->dev, hdmi->regmap, ddc 124 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c if (IS_ERR(ddc->reg)) ddc 125 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c return PTR_ERR(ddc->reg); ddc 132 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c ddc->hdmi = hdmi; ddc 133 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c ddc->hw.init = &init; ddc 134 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c ddc->pre_div = hdmi->variant->ddc_clk_pre_divider; ddc 135 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c ddc->m_offset = hdmi->variant->ddc_clk_m_offset; ddc 137 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c hdmi->ddc_clk = devm_clk_register(hdmi->dev, &ddc->hw); ddc 236 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c struct i2c_adapter *ddc; ddc 247 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c ddc = of_get_i2c_adapter_by_node(phandle); ddc 249 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c if (!ddc) ddc 252 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c return ddc; ddc 122 drivers/gpu/drm/tegra/drm.h struct i2c_adapter *ddc; ddc 33 drivers/gpu/drm/tegra/output.c else if (output->ddc) ddc 34 drivers/gpu/drm/tegra/output.c edid = drm_get_edid(connector, output->ddc); ddc 94 drivers/gpu/drm/tegra/output.c struct device_node *ddc, *panel; ddc 112 drivers/gpu/drm/tegra/output.c ddc = of_parse_phandle(output->of_node, "nvidia,ddc-i2c-bus", 0); ddc 113 drivers/gpu/drm/tegra/output.c if (ddc) { ddc 114 drivers/gpu/drm/tegra/output.c output->ddc = of_find_i2c_adapter_by_node(ddc); ddc 115 drivers/gpu/drm/tegra/output.c if (!output->ddc) { ddc 117 drivers/gpu/drm/tegra/output.c of_node_put(ddc); ddc 121 drivers/gpu/drm/tegra/output.c of_node_put(ddc); ddc 181 drivers/gpu/drm/tegra/output.c if (output->ddc) ddc 182 drivers/gpu/drm/tegra/output.c put_device(&output->ddc->dev); ddc 2317 drivers/gpu/drm/tegra/sor.c struct i2c_adapter *ddc = sor->output.ddc; ddc 2319 drivers/gpu/drm/tegra/sor.c drm_scdc_set_high_tmds_clock_ratio(ddc, false); ddc 2320 drivers/gpu/drm/tegra/sor.c drm_scdc_set_scrambling(ddc, false); ddc 2345 drivers/gpu/drm/tegra/sor.c struct i2c_adapter *ddc = sor->output.ddc; ddc 2347 drivers/gpu/drm/tegra/sor.c drm_scdc_set_high_tmds_clock_ratio(ddc, true); ddc 2348 drivers/gpu/drm/tegra/sor.c drm_scdc_set_scrambling(ddc, true); ddc 2356 drivers/gpu/drm/tegra/sor.c struct i2c_adapter *ddc = sor->output.ddc; ddc 2358 drivers/gpu/drm/tegra/sor.c if (!drm_scdc_get_scrambling_status(ddc)) { ddc 79 drivers/gpu/drm/vc4/vc4_hdmi.c struct i2c_adapter *ddc; ddc 210 drivers/gpu/drm/vc4/vc4_hdmi.c if (drm_probe_ddc(vc4->hdmi->ddc)) ddc 236 drivers/gpu/drm/vc4/vc4_hdmi.c edid = drm_get_edid(connector, vc4->hdmi->ddc); ddc 1356 drivers/gpu/drm/vc4/vc4_hdmi.c hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); ddc 1358 drivers/gpu/drm/vc4/vc4_hdmi.c if (!hdmi->ddc) { ddc 1472 drivers/gpu/drm/vc4/vc4_hdmi.c put_device(&hdmi->ddc->dev); ddc 1491 drivers/gpu/drm/vc4/vc4_hdmi.c put_device(&hdmi->ddc->dev); ddc 40 drivers/gpu/drm/zte/zx_hdmi.c struct zx_hdmi_i2c *ddc; ddc 267 drivers/gpu/drm/zte/zx_hdmi.c edid = drm_get_edid(connector, &hdmi->ddc->adap); ddc 565 drivers/gpu/drm/zte/zx_hdmi.c struct zx_hdmi_i2c *ddc = hdmi->ddc; ddc 568 drivers/gpu/drm/zte/zx_hdmi.c mutex_lock(&ddc->lock); ddc 593 drivers/gpu/drm/zte/zx_hdmi.c mutex_unlock(&ddc->lock); ddc 611 drivers/gpu/drm/zte/zx_hdmi.c struct zx_hdmi_i2c *ddc; ddc 614 drivers/gpu/drm/zte/zx_hdmi.c ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL); ddc 615 drivers/gpu/drm/zte/zx_hdmi.c if (!ddc) ddc 618 drivers/gpu/drm/zte/zx_hdmi.c hdmi->ddc = ddc; ddc 619 drivers/gpu/drm/zte/zx_hdmi.c mutex_init(&ddc->lock); ddc 621 drivers/gpu/drm/zte/zx_hdmi.c adap = &ddc->adap; ddc 36 drivers/gpu/drm/zte/zx_vga.c struct zx_vga_i2c *ddc; ddc 91 drivers/gpu/drm/zte/zx_vga.c edid = drm_get_edid(connector, &vga->ddc->adap); ddc 287 drivers/gpu/drm/zte/zx_vga.c struct zx_vga_i2c *ddc = vga->ddc; ddc 291 drivers/gpu/drm/zte/zx_vga.c mutex_lock(&ddc->lock); ddc 306 drivers/gpu/drm/zte/zx_vga.c mutex_unlock(&ddc->lock); ddc 325 drivers/gpu/drm/zte/zx_vga.c struct zx_vga_i2c *ddc; ddc 328 drivers/gpu/drm/zte/zx_vga.c ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL); ddc 329 drivers/gpu/drm/zte/zx_vga.c if (!ddc) ddc 332 drivers/gpu/drm/zte/zx_vga.c vga->ddc = ddc; ddc 333 drivers/gpu/drm/zte/zx_vga.c mutex_init(&ddc->lock); ddc 335 drivers/gpu/drm/zte/zx_vga.c adap = &ddc->adap; ddc 618 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c NPCM7XX_GRP(ddc), \ ddc 761 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c NPCM7XX_SFUNC(ddc); ddc 879 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c NPCM7XX_MKFUNC(ddc), ddc 1135 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), ddc 1136 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), ddc 1137 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)), ddc 1138 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)), ddc 1813 drivers/pinctrl/tegra/pinctrl-tegra114.c DRV_PINGROUP(ddc, 0x8fc, 2, 3, -1, 12, 5, 20, 5, 28, 2, 30, 2, N), ddc 2020 drivers/pinctrl/tegra/pinctrl-tegra124.c DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), ddc 2062 drivers/pinctrl/tegra/pinctrl-tegra20.c MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28), ddc 2204 drivers/pinctrl/tegra/pinctrl-tegra20.c DRV_PG(ddc, 0x8f0), ddc 2441 drivers/pinctrl/tegra/pinctrl-tegra30.c DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2), ddc 1331 include/drm/drm_connector.h struct i2c_adapter *ddc; ddc 1425 include/drm/drm_connector.h struct i2c_adapter *ddc); ddc 1292 include/drm/drm_dp_helper.h struct i2c_adapter ddc;