dd_emit           802 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);	/* 00000001 UNK0F90 */
dd_emit           803 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);	/* 00000001 UNK135C */
dd_emit           806 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);	/* 00000007 SRC_TILE_MODE_Z */
dd_emit           807 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 2);	/* 00000007 SRC_TILE_MODE_Y */
dd_emit           808 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);	/* 00000001 SRC_LINEAR #1 */
dd_emit           809 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);	/* 000000ff SRC_ADDRESS_HIGH */
dd_emit           810 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);	/* 00000001 SRC_SRGB */
dd_emit           812 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 00000003 eng2d UNK0258 */
dd_emit           813 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);	/* 00000fff SRC_DEPTH */
dd_emit           814 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x100);	/* 0000ffff SRC_HEIGHT */
dd_emit           817 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 0000000f TEXTURES_LOG2 */
dd_emit           818 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 0000000f SAMPLERS_LOG2 */
dd_emit           819 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 000000ff CB_DEF_ADDRESS_HIGH */
dd_emit           820 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* ffffffff CB_DEF_ADDRESS_LOW */
dd_emit           821 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* ffffffff SHARED_SIZE */
dd_emit           822 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 2);		/* ffffffff REG_MODE */
dd_emit           823 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 0000ffff BLOCK_ALLOC_THREADS */
dd_emit           824 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000001 LANES32 */
dd_emit           825 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 000000ff UNK370 */
dd_emit           826 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 000000ff USER_PARAM_UNK */
dd_emit           827 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 000000ff USER_PARAM_COUNT */
dd_emit           828 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 000000ff UNK384 bits 8-15 */
dd_emit           829 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x3fffff);	/* 003fffff TIC_LIMIT */
dd_emit           830 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x1fff);	/* 000fffff TSC_LIMIT */
dd_emit           831 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 0000ffff CB_ADDR_INDEX */
dd_emit           832 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 000007ff BLOCKDIM_X */
dd_emit           833 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 000007ff BLOCKDIM_XMY */
dd_emit           834 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 BLOCKDIM_XMY_OVERFLOW */
dd_emit           835 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 0003ffff BLOCKDIM_XMYMZ */
dd_emit           836 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 000007ff BLOCKDIM_Y */
dd_emit           837 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 0000007f BLOCKDIM_Z */
dd_emit           838 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 4);		/* 000000ff CP_REG_ALLOC_TEMP */
dd_emit           839 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000001 BLOCKDIM_DIRTY */
dd_emit           841 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 00000003 UNK03E8 */
dd_emit           842 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 0000007f BLOCK_ALLOC_HALFWARPS */
dd_emit           843 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000007 LOCAL_WARPS_NO_CLAMP */
dd_emit           844 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 7);		/* 00000007 LOCAL_WARPS_LOG_ALLOC */
dd_emit           845 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000007 STACK_WARPS_NO_CLAMP */
dd_emit           846 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 7);		/* 00000007 STACK_WARPS_LOG_ALLOC */
dd_emit           847 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00001fff BLOCK_ALLOC_REGSLOTS_PACKED */
dd_emit           848 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00001fff BLOCK_ALLOC_REGSLOTS_STRIDED */
dd_emit           849 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 000007ff BLOCK_ALLOC_THREADS */
dd_emit           853 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 4, 0);		/* 0000ffff clip X, Y, W, H */
dd_emit           855 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);		/* ffffffff chroma COLOR_FORMAT */
dd_emit           857 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);		/* ffffffff pattern COLOR_FORMAT */
dd_emit           858 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff pattern SHAPE */
dd_emit           859 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);		/* ffffffff pattern PATTERN_SELECT */
dd_emit           861 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0xa);		/* ffffffff surf2d SRC_FORMAT */
dd_emit           862 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff surf2d DMA_SRC */
dd_emit           863 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 000000ff surf2d SRC_ADDRESS_HIGH */
dd_emit           864 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff surf2d SRC_ADDRESS_LOW */
dd_emit           865 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x40);		/* 0000ffff surf2d SRC_PITCH */
dd_emit           866 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000000f surf2d SRC_TILE_MODE_Z */
dd_emit           867 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 2);		/* 0000000f surf2d SRC_TILE_MODE_Y */
dd_emit           868 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x100);		/* ffffffff surf2d SRC_HEIGHT */
dd_emit           869 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);		/* 00000001 surf2d SRC_LINEAR */
dd_emit           870 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x100);		/* ffffffff surf2d SRC_WIDTH */
dd_emit           872 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_B_X */
dd_emit           873 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_B_Y */
dd_emit           874 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_C_X */
dd_emit           875 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_C_Y */
dd_emit           876 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_D_X */
dd_emit           877 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_D_Y */
dd_emit           878 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);		/* ffffffff gdirect COLOR_FORMAT */
dd_emit           879 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff gdirect OPERATION */
dd_emit           880 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect POINT_X */
dd_emit           881 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect POINT_Y */
dd_emit           883 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000ffff blit SRC_Y */
dd_emit           884 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff blit OPERATION */
dd_emit           886 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff ifc OPERATION */
dd_emit           888 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff iifc INDEX_FORMAT */
dd_emit           889 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff iifc LUT_OFFSET */
dd_emit           890 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 4);		/* ffffffff iifc COLOR_FORMAT */
dd_emit           891 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff iifc OPERATION */
dd_emit           895 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* ffffffff m2mf LINE_COUNT */
dd_emit           896 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* ffffffff m2mf LINE_LENGTH_IN */
dd_emit           897 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 2, 0);		/* ffffffff m2mf OFFSET_IN, OFFSET_OUT */
dd_emit           898 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* ffffffff m2mf TILING_DEPTH_OUT */
dd_emit           899 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x100);		/* ffffffff m2mf TILING_HEIGHT_OUT */
dd_emit           900 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* ffffffff m2mf TILING_POSITION_OUT_Z */
dd_emit           901 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000001 m2mf LINEAR_OUT */
dd_emit           902 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 2, 0);		/* 0000ffff m2mf TILING_POSITION_OUT_X, Y */
dd_emit           903 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x100);		/* ffffffff m2mf TILING_PITCH_OUT */
dd_emit           904 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* ffffffff m2mf TILING_DEPTH_IN */
dd_emit           905 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x100);		/* ffffffff m2mf TILING_HEIGHT_IN */
dd_emit           906 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* ffffffff m2mf TILING_POSITION_IN_Z */
dd_emit           907 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000001 m2mf LINEAR_IN */
dd_emit           908 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 2, 0);		/* 0000ffff m2mf TILING_POSITION_IN_X, Y */
dd_emit           909 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x100);		/* ffffffff m2mf TILING_PITCH_IN */
dd_emit           913 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);		/* ffffffff line COLOR_FORMAT */
dd_emit           914 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff line OPERATION */
dd_emit           916 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);		/* ffffffff triangle COLOR_FORMAT */
dd_emit           917 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff triangle OPERATION */
dd_emit           919 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000000f sifm TILE_MODE_Z */
dd_emit           920 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 2);		/* 0000000f sifm TILE_MODE_Y */
dd_emit           921 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 000000ff sifm FORMAT_FILTER */
dd_emit           922 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);		/* 000000ff sifm FORMAT_ORIGIN */
dd_emit           923 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000ffff sifm SRC_PITCH */
dd_emit           924 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);		/* 00000001 sifm SRC_LINEAR */
dd_emit           925 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 000000ff sifm SRC_OFFSET_HIGH */
dd_emit           926 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff sifm SRC_OFFSET */
dd_emit           927 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000ffff sifm SRC_HEIGHT */
dd_emit           928 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* 0000ffff sifm SRC_WIDTH */
dd_emit           929 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 3);		/* ffffffff sifm COLOR_FORMAT */
dd_emit           930 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff sifm OPERATION */
dd_emit           932 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);		/* ffffffff sifc OPERATION */
dd_emit           936 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 0000000f GP_TEXTURES_LOG2 */
dd_emit           937 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 0000000f GP_SAMPLERS_LOG2 */
dd_emit           938 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 000000ff */
dd_emit           939 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* ffffffff */
dd_emit           940 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 4);		/* 000000ff UNK12B0_0 */
dd_emit           941 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x70);		/* 000000ff UNK12B0_1 */
dd_emit           942 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x80);		/* 000000ff UNK12B0_3 */
dd_emit           943 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 000000ff UNK12B0_2 */
dd_emit           944 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 0000000f FP_TEXTURES_LOG2 */
dd_emit           945 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 0000000f FP_SAMPLERS_LOG2 */
dd_emit           947 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* ffffffff */
dd_emit           948 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 0000007f MULTISAMPLE_SAMPLES_LOG2 */
dd_emit           950 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 0000000f MULTISAMPLE_SAMPLES_LOG2 */
dd_emit           952 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0xc);		/* 000000ff SEMANTIC_COLOR.BFC0_ID */
dd_emit           954 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 00000001 SEMANTIC_COLOR.CLMP_EN */
dd_emit           955 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 8);		/* 000000ff SEMANTIC_COLOR.COLR_NR */
dd_emit           956 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x14);		/* 000000ff SEMANTIC_COLOR.FFC0_ID */
dd_emit           958 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 000000ff SEMANTIC_LAYER */
dd_emit           959 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 00000001 */
dd_emit           961 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 00000001 SEMANTIC_PTSZ.ENABLE */
dd_emit           962 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x29);	/* 000000ff SEMANTIC_PTSZ.PTSZ_ID */
dd_emit           963 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x27);	/* 000000ff SEMANTIC_PRIM */
dd_emit           964 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x26);	/* 000000ff SEMANTIC_LAYER */
dd_emit           965 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 8);	/* 0000000f SMENATIC_CLIP.CLIP_HIGH */
dd_emit           966 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 4);	/* 000000ff SEMANTIC_CLIP.CLIP_LO */
dd_emit           967 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x27);	/* 000000ff UNK0FD4 */
dd_emit           968 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 00000001 UNK1900 */
dd_emit           970 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000007 RT_CONTROL_MAP0 */
dd_emit           971 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000007 RT_CONTROL_MAP1 */
dd_emit           972 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 2);		/* 00000007 RT_CONTROL_MAP2 */
dd_emit           973 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 3);		/* 00000007 RT_CONTROL_MAP3 */
dd_emit           974 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 4);		/* 00000007 RT_CONTROL_MAP4 */
dd_emit           975 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 5);		/* 00000007 RT_CONTROL_MAP5 */
dd_emit           976 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 6);		/* 00000007 RT_CONTROL_MAP6 */
dd_emit           977 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 7);		/* 00000007 RT_CONTROL_MAP7 */
dd_emit           978 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 0000000f RT_CONTROL_COUNT */
dd_emit           979 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 8, 0);		/* 00000001 RT_HORIZ_UNK */
dd_emit           980 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 8, 0);		/* ffffffff RT_ADDRESS_LOW */
dd_emit           981 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0xcf);		/* 000000ff RT_FORMAT */
dd_emit           982 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 7, 0);		/* 000000ff RT_FORMAT */
dd_emit           984 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 3, 0);	/* 1, 1, 1 */
dd_emit           986 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 2, 0);	/* 1, 1 */
dd_emit           987 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* ffffffff GP_ENABLE */
dd_emit           988 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x80);		/* 0000ffff GP_VERTEX_OUTPUT_COUNT*/
dd_emit           989 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 4);		/* 000000ff GP_REG_ALLOC_RESULT */
dd_emit           990 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 4);		/* 000000ff GP_RESULT_MAP_SIZE */
dd_emit           992 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 3);	/* 00000003 */
dd_emit           993 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 00000001 UNK1418. Alone. */
dd_emit           996 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 3);	/* 00000003 UNK15AC */
dd_emit           997 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* ffffffff RASTERIZE_ENABLE */
dd_emit           998 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 FP_CONTROL.EXPORTS_Z */
dd_emit          1000 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 00000001 FP_CONTROL.MULTIPLE_RESULTS */
dd_emit          1001 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x12);		/* 000000ff FP_INTERPOLANT_CTRL.COUNT */
dd_emit          1002 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x10);		/* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */
dd_emit          1003 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0xc);		/* 000000ff FP_INTERPOLANT_CTRL.OFFSET */
dd_emit          1004 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000001 FP_INTERPOLANT_CTRL.UMASK.W */
dd_emit          1005 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 FP_INTERPOLANT_CTRL.UMASK.X */
dd_emit          1006 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 FP_INTERPOLANT_CTRL.UMASK.Y */
dd_emit          1007 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 FP_INTERPOLANT_CTRL.UMASK.Z */
dd_emit          1008 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 4);		/* 000000ff FP_RESULT_COUNT */
dd_emit          1009 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 2);		/* ffffffff REG_MODE */
dd_emit          1010 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 4);		/* 000000ff FP_REG_ALLOC_TEMP */
dd_emit          1012 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* ffffffff */
dd_emit          1013 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */
dd_emit          1014 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* ffffffff STRMOUT_ENABLE */
dd_emit          1015 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x3fffff);	/* 003fffff TIC_LIMIT */
dd_emit          1016 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x1fff);	/* 000fffff TSC_LIMIT */
dd_emit          1017 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 VERTEX_TWO_SIDE_ENABLE*/
dd_emit          1019 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 8, 0);	/* 00000001 */
dd_emit          1021 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);	/* 00000007 VTX_ATTR_DEFINE.COMP */
dd_emit          1022 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);	/* 00000007 VTX_ATTR_DEFINE.SIZE */
dd_emit          1023 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 2);	/* 00000007 VTX_ATTR_DEFINE.TYPE */
dd_emit          1024 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 000000ff VTX_ATTR_DEFINE.ATTR */
dd_emit          1026 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 4);		/* 0000007f VP_RESULT_MAP_SIZE */
dd_emit          1027 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x14);		/* 0000001f ZETA_FORMAT */
dd_emit          1028 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000001 ZETA_ENABLE */
dd_emit          1029 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 0000000f VP_TEXTURES_LOG2 */
dd_emit          1030 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 0000000f VP_SAMPLERS_LOG2 */
dd_emit          1032 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 00000001 */
dd_emit          1033 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 2);		/* 00000003 POLYGON_MODE_BACK */
dd_emit          1035 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */
dd_emit          1036 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 0000ffff CB_ADDR_INDEX */
dd_emit          1038 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 00000003 */
dd_emit          1039 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 CULL_FACE_ENABLE */
dd_emit          1040 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000003 CULL_FACE */
dd_emit          1041 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 FRONT_FACE */
dd_emit          1042 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 2);		/* 00000003 POLYGON_MODE_FRONT */
dd_emit          1043 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x1000);	/* 00007fff UNK141C */
dd_emit          1045 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0xe00);		/* 7fff */
dd_emit          1046 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x1000);	/* 7fff */
dd_emit          1047 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x1e00);	/* 7fff */
dd_emit          1049 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 BEGIN_END_ACTIVE */
dd_emit          1050 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000001 POLYGON_MODE_??? */
dd_emit          1051 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 000000ff GP_REG_ALLOC_TEMP / 4 rounded up */
dd_emit          1052 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 000000ff FP_REG_ALLOC_TEMP... without /4? */
dd_emit          1053 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 000000ff VP_REG_ALLOC_TEMP / 4 rounded up */
dd_emit          1054 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000001 */
dd_emit          1055 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 */
dd_emit          1056 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 VTX_ATTR_MASK_UNK0 nonempty */
dd_emit          1057 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 VTX_ATTR_MASK_UNK1 nonempty */
dd_emit          1058 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0x200);		/* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */
dd_emit          1060 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x200);
dd_emit          1061 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 */
dd_emit          1063 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);	/* 00000001 */
dd_emit          1064 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x70);	/* 000000ff */
dd_emit          1065 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x80);	/* 000000ff */
dd_emit          1066 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 000000ff */
dd_emit          1067 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 00000001 */
dd_emit          1068 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);	/* 00000001 */
dd_emit          1069 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x70);	/* 000000ff */
dd_emit          1070 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0x80);	/* 000000ff */
dd_emit          1071 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 000000ff */
dd_emit          1073 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);	/* 00000001 */
dd_emit          1074 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0xf0);	/* 000000ff */
dd_emit          1075 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0xff);	/* 000000ff */
dd_emit          1076 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 000000ff */
dd_emit          1077 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 00000001 */
dd_emit          1078 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 1);	/* 00000001 */
dd_emit          1079 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0xf0);	/* 000000ff */
dd_emit          1080 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0xff);	/* 000000ff */
dd_emit          1081 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 0);	/* 000000ff */
dd_emit          1082 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 		dd_emit(ctx, 1, 9);	/* 0000003f UNK114C.COMP,SIZE */
dd_emit          1086 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 eng2d COLOR_KEY_ENABLE */
dd_emit          1087 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000007 eng2d COLOR_KEY_FORMAT */
dd_emit          1088 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* ffffffff eng2d DST_DEPTH */
dd_emit          1089 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0xcf);		/* 000000ff eng2d DST_FORMAT */
dd_emit          1090 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* ffffffff eng2d DST_LAYER */
dd_emit          1091 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000001 eng2d DST_LINEAR */
dd_emit          1092 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000007 eng2d PATTERN_COLOR_FORMAT */
dd_emit          1093 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000007 eng2d OPERATION */
dd_emit          1094 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000003 eng2d PATTERN_SELECT */
dd_emit          1095 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0xcf);		/* 000000ff eng2d SIFC_FORMAT */
dd_emit          1096 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 eng2d SIFC_BITMAP_ENABLE */
dd_emit          1097 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 2);		/* 00000003 eng2d SIFC_BITMAP_UNK808 */
dd_emit          1098 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* ffffffff eng2d BLIT_DU_DX_FRACT */
dd_emit          1099 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* ffffffff eng2d BLIT_DU_DX_INT */
dd_emit          1100 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* ffffffff eng2d BLIT_DV_DY_FRACT */
dd_emit          1101 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* ffffffff eng2d BLIT_DV_DY_INT */
dd_emit          1102 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0);		/* 00000001 eng2d BLIT_CONTROL_FILTER */
dd_emit          1103 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0xcf);		/* 000000ff eng2d DRAW_COLOR_FORMAT */
dd_emit          1104 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 0xcf);		/* 000000ff eng2d SRC_FORMAT */
dd_emit          1105 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	dd_emit(ctx, 1, 1);		/* 00000001 eng2d SRC_LINEAR #2 */