dcr_write          70 arch/powerpc/platforms/4xx/cpm.c 	dcr_write(cpm.dcr_host, cpm.dcr_offset[cpm_reg], value | mask);
dcr_write         103 arch/powerpc/platforms/4xx/cpm.c 	dcr_write(cpm.dcr_host, cpm.dcr_offset[CPM_ER], er_save);
dcr_write         898 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
dcr_write        1025 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
dcr_write        1327 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000);  /* guarded on */
dcr_write        1336 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
dcr_write        1466 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
dcr_write        1468 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
dcr_write        1472 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
dcr_write        1475 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
dcr_write        1477 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
dcr_write        1481 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
dcr_write        1484 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
dcr_write        1485 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
dcr_write        1486 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
dcr_write        1487 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
dcr_write        1625 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
dcr_write        1655 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
dcr_write        1680 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
dcr_write        1699 arch/powerpc/platforms/4xx/pci.c 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
dcr_write        1741 arch/powerpc/platforms/4xx/pci.c 		dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
dcr_write        1742 arch/powerpc/platforms/4xx/pci.c 		dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
dcr_write        1743 arch/powerpc/platforms/4xx/pci.c 		dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
dcr_write        1746 arch/powerpc/platforms/4xx/pci.c 			dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
dcr_write        1753 arch/powerpc/platforms/4xx/pci.c 			dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
dcr_write        1757 arch/powerpc/platforms/4xx/pci.c 			dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
dcr_write        1764 arch/powerpc/platforms/4xx/pci.c 		dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
dcr_write        1765 arch/powerpc/platforms/4xx/pci.c 		dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
dcr_write        1766 arch/powerpc/platforms/4xx/pci.c 		dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
dcr_write        1767 arch/powerpc/platforms/4xx/pci.c 		dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL,
dcr_write        1773 arch/powerpc/platforms/4xx/pci.c 		dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
dcr_write        1774 arch/powerpc/platforms/4xx/pci.c 		dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
dcr_write        1775 arch/powerpc/platforms/4xx/pci.c 		dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
dcr_write        1777 arch/powerpc/platforms/4xx/pci.c 		dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL,
dcr_write          89 arch/powerpc/platforms/cell/axon_msi.c 	dcr_write(msic->dcr_host, dcr_n, val);
dcr_write         197 arch/powerpc/sysdev/mpic.c 		dcr_write(rb->dhost, reg, value);
dcr_write         673 drivers/dma/ppc4xx/adma.c 	dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_CF2H, byte_count);
dcr_write        4334 drivers/dma/ppc4xx/adma.c 	dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_XORBA, val);
dcr_write        4393 drivers/dma/ppc4xx/adma.c 	dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_CFBHL, reg);
dcr_write        4473 drivers/dma/ppc4xx/adma.c 	dcr_write(i2o_dcr_host, DCRN_I2O0_IBAH, (u32)(i2o_res.start >> 32));
dcr_write        4474 drivers/dma/ppc4xx/adma.c 	dcr_write(i2o_dcr_host, DCRN_I2O0_IBAL, (u32)(i2o_res.start) |
dcr_write        4520 drivers/dma/ppc4xx/adma.c 	dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_BAUH, DMA_CUED_XOR_HB);
dcr_write        4527 drivers/dma/ppc4xx/adma.c 	dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_CFBHL,
dcr_write         220 drivers/net/ethernet/ibm/emac/mal.h 	dcr_write(mal->dcr_host, reg, val);
dcr_write         253 drivers/net/ethernet/xilinx/ll_temac_main.c 	dcr_write(lp->sdma_dcrs, reg, value);
dcr_write         178 drivers/video/fbdev/xilinxfb.c 		dcr_write(drvdata->dcr_host, offset, val);