dcn_bw_no 133 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->scale_ratio_support = dcn_bw_no; dcn_bw_no 141 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->source_format_pixel_and_scan_support = dcn_bw_no; dcn_bw_no 205 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dcc_enabled_in_any_plane = dcn_bw_no; dcn_bw_no 235 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->bandwidth_support[i] = dcn_bw_no; dcn_bw_no 243 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->writeback_latency_support = dcn_bw_no; dcn_bw_no 246 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->writeback_latency_support = dcn_bw_no; dcn_bw_no 257 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->rob_support[i] = dcn_bw_no; dcn_bw_no 302 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dio_support[i] = dcn_bw_no; dcn_bw_no 318 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->total_available_writeback_support = dcn_bw_no; dcn_bw_no 462 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dispclk_dppclk_support[i][j] = dcn_bw_no; dcn_bw_no 481 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dispclk_dppclk_support[i][j] = dcn_bw_no; dcn_bw_no 488 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dispclk_dppclk_support[i][j] = dcn_bw_no; dcn_bw_no 501 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->viewport_size_support = dcn_bw_no; dcn_bw_no 512 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->total_available_pipes_support[i][j] = dcn_bw_no; dcn_bw_no 572 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->urgent_latency_support[i][j] = dcn_bw_no; dcn_bw_no 930 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no; dcn_bw_no 934 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no; dcn_bw_no 939 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no; dcn_bw_no 943 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no; dcn_bw_no 953 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no; dcn_bw_no 959 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no; dcn_bw_no 973 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->mode_support_with_immediate_flip[i][j] = dcn_bw_no; dcn_bw_no 979 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->mode_support_without_immediate_flip[i][j] = dcn_bw_no; dcn_bw_no 983 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->mode_support_with_immediate_flip[i][j] = dcn_bw_no; dcn_bw_no 984 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->mode_support_without_immediate_flip[i][j] = dcn_bw_no; dcn_bw_no 999 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->immediate_flip_supported = dcn_bw_no; dcn_bw_no 1029 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->dispclk_dppclk_support_per_ratio[0] == dcn_bw_yes && v->dispclk_dppclk_support_per_ratio[1] == dcn_bw_no) || (v->dispclk_dppclk_support_per_ratio[0] == v->dispclk_dppclk_support_per_ratio[1] && (v->total_number_of_active_dpp_per_ratio[0] < v->total_number_of_active_dpp_per_ratio[1] || (((v->total_number_of_active_dpp_per_ratio[0] == v->total_number_of_active_dpp_per_ratio[1]) && v->required_dispclk_per_ratio[0] <= 0.5 * v->required_dispclk_per_ratio[1]))))) { dcn_bw_no 1227 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dcc_enabled_any_plane = dcn_bw_no; dcn_bw_no 1637 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 = dcn_bw_no; dcn_bw_no 1638 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 = dcn_bw_no; dcn_bw_no 1639 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_prefetch_more_than4 = dcn_bw_no; dcn_bw_no 1640 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->destination_line_times_for_prefetch_less_than2 = dcn_bw_no; dcn_bw_no 1761 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw = dcn_bw_no; dcn_bw_no 1771 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->max_rd_bandwidth <= v->return_bw && v->v_ratio_prefetch_more_than4 == dcn_bw_no && v->destination_line_times_for_prefetch_less_than2 == dcn_bw_no) { dcn_bw_no 1775 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefetch_mode_supported = dcn_bw_no; dcn_bw_no 1778 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c } while (!(v->prefetch_mode_supported == dcn_bw_yes || (v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw == dcn_bw_yes && v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 == dcn_bw_no && v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 == dcn_bw_no))); dcn_bw_no 1809 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no; dcn_bw_no 1814 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no; dcn_bw_no 1815 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_no; dcn_bw_no 138 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c .odm_capability = dcn_bw_no, dcn_bw_no 139 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c .dsc_capability = dcn_bw_no, dcn_bw_no 142 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c .is_line_buffer_bpp_fixed = dcn_bw_no, dcn_bw_no 160 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no, dcn_bw_no 161 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c .bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no, dcn_bw_no 861 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->synchronized_vblank = dcn_bw_no; dcn_bw_no 965 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; dcn_bw_no 976 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;