dcn_bw_max3       331 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], 1.0);
dcn_bw_max3       807 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 						v->time_for_meta_pte_without_immediate_flip = dcn_bw_max3(
dcn_bw_max3       816 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 						v->time_for_meta_and_dpte_row_without_immediate_flip = dcn_bw_max3((
dcn_bw_max3      1190 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		v->dppclk_using_single_dpp_luma = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_throughput[k], 1.0);
dcn_bw_max3      1202 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->dppclk_using_single_dpp_chroma = v->pixel_clock[k] *dcn_bw_max3(v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_throughput_chroma[k], 1.0);
dcn_bw_max3      1660 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 					v->t_wait =dcn_bw_max3(v->dram_clock_change_latency + v->urgent_latency, v->sr_enter_plus_exit_time, v->urgent_latency);
dcn_bw_max3      1693 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 						v->time_for_fetching_meta_pte =dcn_bw_max3(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
dcn_bw_max3      1705 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 						v->time_for_fetching_row_in_vblank =dcn_bw_max3((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte);
dcn_bw_max3      1806 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max3(v->dram_clock_change_watermark, v->stutter_enter_plus_exit_watermark, v->urgent_watermark);
dcn_bw_max3       103 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c 	return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v5);
dcn_bw_max3        37 drivers/gpu/drm/amd/display/dc/inc/dcn_calc_math.h float dcn_bw_max3(float v1, float v2, float v3);