dce_i2c_hw 33 drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c struct dce_i2c_hw *dce_i2c_hw; dce_i2c_hw 50 drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c dce_i2c_hw = acquire_i2c_hw_engine(pool, ddc); dce_i2c_hw 52 drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c if (!dce_i2c_hw) dce_i2c_hw 55 drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c return dce_i2c_submit_command_hw(pool, ddc, cmd, dce_i2c_hw); dce_i2c_hw 35 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->ctx dce_i2c_hw 37 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->regs->reg dce_i2c_hw 41 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name dce_i2c_hw 44 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw) dce_i2c_hw 59 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c DC_I2C_TRANSACTION_COUNT, dce_i2c_hw->transaction_count - 1); dce_i2c_hw 67 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->transaction_count = 0; dce_i2c_hw 68 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->buffer_used_bytes = 0; dce_i2c_hw 72 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 80 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK) dce_i2c_hw 82 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT) dce_i2c_hw 84 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED) dce_i2c_hw 86 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE) dce_i2c_hw 97 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c const struct dce_i2c_hw *dce_i2c_hw) dce_i2c_hw 99 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c return dce_i2c_hw->buffer_size - dce_i2c_hw 100 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->buffer_used_bytes; dce_i2c_hw 104 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c const struct dce_i2c_hw *dce_i2c_hw) dce_i2c_hw 113 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->reference_frequency / pre_scale : dce_i2c_hw 114 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->default_speed; dce_i2c_hw 118 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 125 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c DC_I2C_INDEX, dce_i2c_hw->buffer_used_write, dce_i2c_hw 145 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c static bool is_engine_available(struct dce_i2c_hw *dce_i2c_hw) dce_i2c_hw 161 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c static bool is_hw_busy(struct dce_i2c_hw *dce_i2c_hw) dce_i2c_hw 169 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (is_engine_available(dce_i2c_hw)) dce_i2c_hw 176 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 185 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (is_hw_busy(dce_i2c_hw)) { dce_i2c_hw 190 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c last_transaction = ((dce_i2c_hw->transaction_count == 3) || dce_i2c_hw 195 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c switch (dce_i2c_hw->transaction_count) { dce_i2c_hw 240 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (dce_i2c_hw->transaction_count == 0) { dce_i2c_hw 246 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->buffer_used_write = 0; dce_i2c_hw 252 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->buffer_used_write++; dce_i2c_hw 259 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->buffer_used_write++; dce_i2c_hw 264 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c ++dce_i2c_hw->transaction_count; dce_i2c_hw 265 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->buffer_used_bytes += length + 1; dce_i2c_hw 270 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c static inline void reset_hw_engine(struct dce_i2c_hw *dce_i2c_hw) dce_i2c_hw 278 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 283 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL) dce_i2c_hw 285 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), dce_i2c_hw->reference_frequency / speed, dce_i2c_hw 290 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), dce_i2c_hw->reference_frequency / speed, dce_i2c_hw 296 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw) dce_i2c_hw 308 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (dce_i2c_hw->setup_limit != 0) dce_i2c_hw 309 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c i2c_setup_limit = dce_i2c_hw->setup_limit; dce_i2c_hw 317 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c DC_I2C_DDC_SELECT, dce_i2c_hw->engine_id); dce_i2c_hw 320 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (dce_i2c_hw->send_reset_length == 0) { dce_i2c_hw 327 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c reset_length = dce_i2c_hw->send_reset_length; dce_i2c_hw 346 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw) dce_i2c_hw 352 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c set_speed(dce_i2c_hw, dce_i2c_hw->original_speed); dce_i2c_hw 371 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (!dce_i2c_hw->engine_keep_power_up_count) dce_i2c_hw 379 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *acquire_i2c_hw_engine( dce_i2c_hw 386 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw = NULL; dce_i2c_hw 395 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw = pool->hw_i2cs[line]; dce_i2c_hw 398 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (!dce_i2c_hw) dce_i2c_hw 401 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (pool->i2c_hw_buffer_in_use || !is_engine_available(dce_i2c_hw)) dce_i2c_hw 421 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->ddc = ddc; dce_i2c_hw 423 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c current_speed = get_speed(dce_i2c_hw); dce_i2c_hw 426 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->original_speed = current_speed; dce_i2c_hw 428 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (!setup_engine(dce_i2c_hw)) { dce_i2c_hw 429 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c release_engine(dce_i2c_hw); dce_i2c_hw 434 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c return dce_i2c_hw; dce_i2c_hw 438 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 451 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw, NULL); dce_i2c_hw 464 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 469 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (!process_transaction(dce_i2c_hw, request)) dce_i2c_hw 472 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c if (is_hw_busy(dce_i2c_hw)) { dce_i2c_hw 476 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c reset_hw_engine(dce_i2c_hw); dce_i2c_hw 478 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c execute_transaction(dce_i2c_hw); dce_i2c_hw 484 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c const struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 488 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c uint32_t speed = get_speed(dce_i2c_hw); dce_i2c_hw 502 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c (dce_i2c_hw->buffer_used_bytes << 3) + dce_i2c_hw 503 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c (dce_i2c_hw->transaction_count << 1); dce_i2c_hw 509 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 528 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c get_hw_buffer_available_size(dce_i2c_hw)) { dce_i2c_hw 549 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw, payload->length + 1); dce_i2c_hw 552 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw, &request); dce_i2c_hw 561 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw, dce_i2c_hw 571 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c process_channel_reply(dce_i2c_hw, payload); dce_i2c_hw 580 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw) dce_i2c_hw 585 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c set_speed(dce_i2c_hw, cmd->speed); dce_i2c_hw 595 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw, payload, mot)) { dce_i2c_hw 607 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c release_engine(dce_i2c_hw); dce_i2c_hw 608 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dal_ddc_close(dce_i2c_hw->ddc); dce_i2c_hw 610 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->ddc = NULL; dce_i2c_hw 616 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 623 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->ctx = ctx; dce_i2c_hw 624 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->engine_id = engine_id; dce_i2c_hw 625 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->reference_frequency = (ctx->dc_bios->fw_info.pll_info.crystal_frequency) >> 1; dce_i2c_hw 626 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->regs = regs; dce_i2c_hw 627 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->shifts = shifts; dce_i2c_hw 628 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->masks = masks; dce_i2c_hw 629 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->buffer_used_bytes = 0; dce_i2c_hw 630 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->transaction_count = 0; dce_i2c_hw 631 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->engine_keep_power_up_count = 1; dce_i2c_hw 632 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->original_speed = DEFAULT_I2C_HW_SPEED; dce_i2c_hw 633 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->default_speed = DEFAULT_I2C_HW_SPEED; dce_i2c_hw 634 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->send_reset_length = 0; dce_i2c_hw 635 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCE; dce_i2c_hw 636 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->buffer_size = I2C_HW_BUFFER_SIZE_DCE; dce_i2c_hw 640 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 650 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw_construct(dce_i2c_hw, dce_i2c_hw 656 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->buffer_size = I2C_HW_BUFFER_SIZE_DCE100; dce_i2c_hw 670 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->reference_frequency = dce_i2c_hw 671 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c (dce_i2c_hw->reference_frequency * 2) / xtal_ref_div; dce_i2c_hw 675 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 682 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce100_i2c_hw_construct(dce_i2c_hw, dce_i2c_hw 688 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->default_speed = DEFAULT_I2C_HW_SPEED_100KHZ; dce_i2c_hw 692 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 699 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce112_i2c_hw_construct(dce_i2c_hw, dce_i2c_hw 705 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCN; dce_i2c_hw 710 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 717 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dcn1_i2c_hw_construct(dce_i2c_hw, dce_i2c_hw 723 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_9; dce_i2c_hw 725 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_10; dce_i2c_hw 284 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 292 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 300 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 308 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 317 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h struct dce_i2c_hw *dce_i2c_hw, dce_i2c_hw 329 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h struct dce_i2c_hw *dce_i2c_hw); dce_i2c_hw 331 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h struct dce_i2c_hw *acquire_i2c_hw_engine( dce_i2c_hw 637 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c struct dce_i2c_hw *dce100_i2c_hw_create( dce_i2c_hw 641 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c struct dce_i2c_hw *dce_i2c_hw = dce_i2c_hw 642 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); dce_i2c_hw 644 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (!dce_i2c_hw) dce_i2c_hw 647 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, dce_i2c_hw 650 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return dce_i2c_hw; dce_i2c_hw 683 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c struct dce_i2c_hw *dce110_i2c_hw_create( dce_i2c_hw 687 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c struct dce_i2c_hw *dce_i2c_hw = dce_i2c_hw 688 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); dce_i2c_hw 690 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (!dce_i2c_hw) dce_i2c_hw 693 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, dce_i2c_hw 696 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return dce_i2c_hw; dce_i2c_hw 656 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c struct dce_i2c_hw *dce112_i2c_hw_create( dce_i2c_hw 660 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c struct dce_i2c_hw *dce_i2c_hw = dce_i2c_hw 661 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); dce_i2c_hw 663 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (!dce_i2c_hw) dce_i2c_hw 666 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, dce_i2c_hw 669 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return dce_i2c_hw; dce_i2c_hw 430 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c struct dce_i2c_hw *dce120_i2c_hw_create( dce_i2c_hw 434 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c struct dce_i2c_hw *dce_i2c_hw = dce_i2c_hw 435 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); dce_i2c_hw 437 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (!dce_i2c_hw) dce_i2c_hw 440 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, dce_i2c_hw 443 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return dce_i2c_hw; dce_i2c_hw 517 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c struct dce_i2c_hw *dce80_i2c_hw_create( dce_i2c_hw 521 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c struct dce_i2c_hw *dce_i2c_hw = dce_i2c_hw 522 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); dce_i2c_hw 524 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (!dce_i2c_hw) dce_i2c_hw 527 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce_i2c_hw_construct(dce_i2c_hw, ctx, inst, dce_i2c_hw 530 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return dce_i2c_hw; dce_i2c_hw 668 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c struct dce_i2c_hw *dcn10_i2c_hw_create( dce_i2c_hw 672 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c struct dce_i2c_hw *dce_i2c_hw = dce_i2c_hw 673 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); dce_i2c_hw 675 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (!dce_i2c_hw) dce_i2c_hw 678 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, dce_i2c_hw 681 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return dce_i2c_hw; dce_i2c_hw 1059 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dce_i2c_hw *dcn20_i2c_hw_create( dce_i2c_hw 1063 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dce_i2c_hw *dce_i2c_hw = dce_i2c_hw 1064 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); dce_i2c_hw 1066 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!dce_i2c_hw) dce_i2c_hw 1069 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, dce_i2c_hw 1072 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return dce_i2c_hw; dce_i2c_hw 88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h struct dce_i2c_hw *dcn20_i2c_hw_create( dce_i2c_hw 710 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct dce_i2c_hw *dcn21_i2c_hw_create( dce_i2c_hw 714 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct dce_i2c_hw *dce_i2c_hw = dce_i2c_hw 715 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); dce_i2c_hw 717 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (!dce_i2c_hw) dce_i2c_hw 720 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, dce_i2c_hw 723 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return dce_i2c_hw; dce_i2c_hw 177 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct dce_i2c_hw *hw_i2cs[MAX_PIPES];