dce_environment   684 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
dce_environment   113 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
dce_environment   155 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
dce_environment   103 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
dce_environment   449 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
dce_environment    95 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
dce_environment   541 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
dce_environment    98 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
dce_environment   645 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc_ctx->dce_environment = init_params->dce_environment;
dce_environment   682 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc_ctx->dce_environment,
dce_environment  2037 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
dce_environment  2719 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
dce_environment  3464 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 			IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment))
dce_environment  3500 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 			IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment))
dce_environment   372 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
dce_environment   421 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
dce_environment   446 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
dce_environment   508 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
dce_environment   517 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
dce_environment   542 drivers/gpu/drm/amd/display/dc/dc.h 	enum dce_environment dce_environment;
dce_environment   319 drivers/gpu/drm/amd/display/dc/dc_helper.c 					!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
dce_environment   331 drivers/gpu/drm/amd/display/dc/dc_helper.c 	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
dce_environment    58 drivers/gpu/drm/amd/display/dc/dc_types.h #define IS_FPGA_MAXIMUS_DC(dce_environment) \
dce_environment    59 drivers/gpu/drm/amd/display/dc/dc_types.h 	(dce_environment == DCE_ENV_FPGA_MAXIMUS)
dce_environment    61 drivers/gpu/drm/amd/display/dc/dc_types.h #define IS_DIAG_DC(dce_environment) \
dce_environment    62 drivers/gpu/drm/amd/display/dc/dc_types.h 	(IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
dce_environment    90 drivers/gpu/drm/amd/display/dc/dc_types.h 	enum dce_environment dce_environment;
dce_environment   329 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
dce_environment   909 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
dce_environment   203 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
dce_environment   123 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c 	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
dce_environment   162 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
dce_environment   828 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dce_environment  1191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dce_environment  1220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dce_environment  2694 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dce_environment  2726 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dce_environment   602 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) {
dce_environment  1314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dce_environment  1540 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
dce_environment   699 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	if (IS_FPGA_MAXIMUS_DC(dsc20->base.ctx->dce_environment)) {
dce_environment  1636 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dce_environment  2154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dce_environment   330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
dce_environment  3473 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
dce_environment  3475 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	} else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
dce_environment  3720 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
dce_environment  1450 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
dce_environment  1473 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dce_environment  1475 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
dce_environment  1650 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
dce_environment    67 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c 	enum dce_environment dce_environment)
dce_environment    69 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c 	if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
dce_environment    75 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h 	enum dce_environment dce_environment);
dce_environment    65 drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c 	enum dce_environment dce_environment)
dce_environment    67 drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c 	if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
dce_environment    48 drivers/gpu/drm/amd/display/dc/gpio/hw_translate.h 	enum dce_environment dce_environment);