dccg 69 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) dccg 116 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); dccg 134 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); dccg 48 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg); dccg 115 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dccg->funcs->update_dpp_dto( dccg 116 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dccg, dpp_inst, dppclk_khz, false); dccg 175 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dccg->ref_dppclk = khz; dccg 290 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, true); dccg 307 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, false); dccg 372 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; dccg 431 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct dccg *dccg) dccg 440 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dccg = dccg; dccg 29 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h void dcn2_update_clocks(struct clk_mgr *dccg, dccg 44 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h struct dccg *dccg); dccg 520 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c struct dccg *dccg) dccg 531 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->dccg = dccg; dccg 37 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h struct dccg *dccg); dccg 694 drivers/gpu/drm/amd/display/dc/core/dc.c dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); dccg 2439 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct clk_mgr *dccg = dc->clk_mgr; dccg 2443 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dccg->funcs->update_clocks( dccg 2444 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dccg, dccg 2453 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct clk_mgr *dccg = dc->clk_mgr; dccg 2457 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dccg->funcs->update_clocks( dccg 2458 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dccg, dccg 1188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init) dccg 1189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg); dccg 1221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (res_pool->dccg && res_pool->hubbub) { dccg 1223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, dccg 2303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (dc->res_pool->dccg) dccg 2304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->dccg->funcs->update_dpp_dto( dccg 2305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->dccg, dccg 32 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c #define TO_DCN_DCCG(dccg)\ dccg 33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c container_of(dccg, struct dcn_dccg, base) dccg 45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c dccg->ctx->logger dccg 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c void dccg2_update_dpp_dto(struct dccg *dccg, dccg 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); dccg 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c if (dccg->ref_dppclk && req_dppclk) { dccg 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c int ref_dppclk = dccg->ref_dppclk; dccg 98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c void dccg2_get_dccg_ref_freq(struct dccg *dccg, dccg 102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); dccg 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c void dccg2_init(struct dccg *dccg) dccg 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); dccg 156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c struct dccg *dccg2_create( dccg 163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c struct dccg *base; dccg 181 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c void dcn_dccg_destroy(struct dccg **dccg) dccg 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(*dccg); dccg 186 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c *dccg = NULL; dccg 94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h struct dccg base; dccg 100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk, bool raise_divider_only); dccg 102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h void dccg2_get_dccg_ref_freq(struct dccg *dccg, dccg 106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h void dccg2_init(struct dccg *dccg); dccg 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h struct dccg *dccg2_create( dccg 114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h void dcn_dccg_destroy(struct dccg **dccg); dccg 2004 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (res_pool->dccg->funcs->dccg_init) dccg 2005 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c res_pool->dccg->funcs->dccg_init(res_pool->dccg); dccg 1407 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.dccg != NULL) dccg 1408 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn_dccg_destroy(&pool->base.dccg); dccg 3532 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); dccg 3533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.dccg == NULL) { dccg 940 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.dccg != NULL) dccg 941 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn_dccg_destroy(&pool->base.dccg); dccg 1518 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); dccg 1519 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.dccg == NULL) { dccg 222 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct dccg *dccg; dccg 196 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h struct dccg; dccg 198 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); dccg 198 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h struct dccg *dccg; dccg 39 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h void (*update_dpp_dto)(struct dccg *dccg, dccg 43 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h void (*get_dccg_ref_freq)(struct dccg *dccg, dccg 46 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h void (*dccg_init)(struct dccg *dccg);