dc_status 540 drivers/acpi/acpi_tad.c static DEVICE_ATTR(dc_status, S_IRUSR | S_IWUSR, dc_status_show, dc_status_store); dc_status 4106 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c enum dc_status dc_result = DC_OK; dc_status 1055 drivers/gpu/drm/amd/display/dc/core/dc.c static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context) dc_status 1058 drivers/gpu/drm/amd/display/dc/core/dc.c enum dc_status result = DC_ERROR_UNEXPECTED; dc_status 1165 drivers/gpu/drm/amd/display/dc/core/dc.c enum dc_status result = DC_ERROR_UNEXPECTED; dc_status 2527 drivers/gpu/drm/amd/display/dc/core/dc.c enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping) dc_status 529 drivers/gpu/drm/amd/display/dc/core/dc_link.c enum dc_status status = DC_ERROR_UNEXPECTED; dc_status 1450 drivers/gpu/drm/amd/display/dc/core/dc_link.c static enum dc_status enable_link_dp( dc_status 1455 drivers/gpu/drm/amd/display/dc/core/dc_link.c enum dc_status status; dc_status 1544 drivers/gpu/drm/amd/display/dc/core/dc_link.c static enum dc_status enable_link_edp( dc_status 1548 drivers/gpu/drm/amd/display/dc/core/dc_link.c enum dc_status status; dc_status 1555 drivers/gpu/drm/amd/display/dc/core/dc_link.c static enum dc_status enable_link_dp_mst( dc_status 2106 drivers/gpu/drm/amd/display/dc/core/dc_link.c static enum dc_status enable_link( dc_status 2110 drivers/gpu/drm/amd/display/dc/core/dc_link.c enum dc_status status = DC_ERROR_UNEXPECTED; dc_status 2269 drivers/gpu/drm/amd/display/dc/core/dc_link.c enum dc_status dc_link_validate_mode_timing( dc_status 2514 drivers/gpu/drm/amd/display/dc/core/dc_link.c static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) dc_status 2594 drivers/gpu/drm/amd/display/dc/core/dc_link.c static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) dc_status 2678 drivers/gpu/drm/amd/display/dc/core/dc_link.c enum dc_status status; dc_status 1426 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c static enum dc_status read_hpd_rx_irq_data( dc_status 1430 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c static enum dc_status retval; dc_status 1477 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c enum dc_status dpcd_result = DC_ERROR_UNEXPECTED; dc_status 2364 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c enum dc_status result; dc_status 2471 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c enum dc_status st = DC_OK; dc_status 2721 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c enum dc_status status = DC_ERROR_UNEXPECTED; dc_status 22 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c enum dc_status core_link_read_dpcd( dc_status 37 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c enum dc_status core_link_write_dpcd( dc_status 128 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c enum dc_status result = DC_OK; dc_status 153 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c enum dc_status result = DC_OK; dc_status 1052 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status resource_build_scaling_params_for_context( dc_status 1684 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status dc_add_stream_to_ctx( dc_status 1689 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status res; dc_status 1711 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status dc_remove_stream_from_ctx( dc_status 1905 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status resource_map_pool_resources( dc_status 2034 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status dc_validate_global_state( dc_status 2039 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status result = DC_ERROR_UNEXPECTED; dc_status 2531 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status resource_map_clock_resources( dc_status 2745 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) dc_status 2750 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status res = DC_OK; dc_status 2773 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) dc_status 2775 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status res = DC_OK; dc_status 873 drivers/gpu/drm/amd/display/dc/dc.h enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); dc_status 884 drivers/gpu/drm/amd/display/dc/dc.h enum dc_status dc_validate_global_state( dc_status 1066 drivers/gpu/drm/amd/display/dc/dc.h enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); dc_status 301 drivers/gpu/drm/amd/display/dc/dc_stream.h enum dc_status dc_add_stream_to_ctx( dc_status 306 drivers/gpu/drm/amd/display/dc/dc_stream.h enum dc_status dc_remove_stream_from_ctx( dc_status 349 drivers/gpu/drm/amd/display/dc/dc_stream.h enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); dc_status 748 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c static enum dc_status build_mapped_resource( dc_status 810 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c enum dc_status dce100_validate_global( dc_status 820 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c enum dc_status dce100_add_stream_to_ctx( dc_status 825 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c enum dc_status result = DC_ERROR_UNEXPECTED; dc_status 847 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) dc_status 42 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps); dc_status 44 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h enum dc_status dce100_add_stream_to_ctx( dc_status 1269 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static enum dc_status dce110_enable_stream_timing( dc_status 1324 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static enum dc_status apply_single_controller_ctx_to_hw( dc_status 2029 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c enum dc_status dce110_apply_ctx_to_hw( dc_status 2034 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c enum dc_status status; dc_status 38 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h enum dc_status dce110_apply_ctx_to_hw( dc_status 867 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c static enum dc_status build_mapped_resource( dc_status 964 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, dc_status 1019 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c enum dc_status dce110_validate_global( dc_status 1029 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c static enum dc_status dce110_add_stream_to_ctx( dc_status 1034 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c enum dc_status result = DC_ERROR_UNEXPECTED; dc_status 795 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c static enum dc_status build_mapped_resource( dc_status 884 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c enum dc_status resource_map_phy_clock_resources( dc_status 937 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c enum dc_status dce112_add_stream_to_ctx( dc_status 942 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c enum dc_status result = DC_ERROR_UNEXPECTED; dc_status 956 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c enum dc_status dce112_validate_global( dc_status 38 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h enum dc_status dce112_validate_with_context( dc_status 50 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h enum dc_status dce112_add_stream_to_ctx( dc_status 844 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c enum dc_status dce80_validate_global( dc_status 731 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static enum dc_status dcn10_enable_stream_timing( dc_status 3258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static enum dc_status dcn10_set_clock(struct dc *dc, dc_status 1037 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static enum dc_status build_mapped_resource( dc_status 1069 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c enum dc_status dcn10_add_stream_to_ctx( dc_status 1074 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c enum dc_status result = DC_ERROR_UNEXPECTED; dc_status 1137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) dc_status 1147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) dc_status 1197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state) dc_status 1199 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c enum dc_status result = DC_OK; dc_status 523 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c enum dc_status dcn20_enable_stream_timing( dc_status 33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h enum dc_status dcn20_enable_stream_timing( dc_status 1478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) dc_status 1497 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) dc_status 1499 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c enum dc_status status = DC_OK; dc_status 1574 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static enum dc_status add_dsc_to_stream_resource(struct dc *dc, dc_status 1578 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c enum dc_status result = DC_OK; dc_status 1604 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, dc_status 1628 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) dc_status 1630 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c enum dc_status result = DC_ERROR_UNEXPECTED; dc_status 1650 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) dc_status 1652 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c enum dc_status result = DC_OK; dc_status 2986 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state) dc_status 2988 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c enum dc_status result = DC_OK; dc_status 132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream); dc_status 133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream); dc_status 134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream); dc_status 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state); dc_status 69 drivers/gpu/drm/amd/display/dc/inc/core_types.h enum dc_status dc_link_validate_mode_timing( dc_status 109 drivers/gpu/drm/amd/display/dc/inc/core_types.h enum dc_status (*validate_global)( dc_status 118 drivers/gpu/drm/amd/display/dc/inc/core_types.h enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); dc_status 120 drivers/gpu/drm/amd/display/dc/inc/core_types.h enum dc_status (*add_stream_to_ctx)( dc_status 125 drivers/gpu/drm/amd/display/dc/inc/core_types.h enum dc_status (*remove_stream_from_ctx)( dc_status 129 drivers/gpu/drm/amd/display/dc/inc/core_types.h enum dc_status (*get_default_swizzle_mode)( dc_status 95 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h enum dc_status (*apply_ctx_to_hw)( dc_status 250 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h enum dc_status (*enable_stream_timing)( dc_status 333 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h enum dc_status (*set_clock)(struct dc *dc, dc_status 31 drivers/gpu/drm/amd/display/dc/inc/link_hwss.h enum dc_status core_link_read_dpcd( dc_status 37 drivers/gpu/drm/amd/display/dc/inc/link_hwss.h enum dc_status core_link_write_dpcd( dc_status 89 drivers/gpu/drm/amd/display/dc/inc/resource.h enum dc_status resource_map_pool_resources( dc_status 96 drivers/gpu/drm/amd/display/dc/inc/resource.h enum dc_status resource_build_scaling_params_for_context( dc_status 159 drivers/gpu/drm/amd/display/dc/inc/resource.h enum dc_status resource_map_clock_resources( dc_status 164 drivers/gpu/drm/amd/display/dc/inc/resource.h enum dc_status resource_map_phy_clock_resources( dc_status 1166 drivers/gpu/drm/arm/malidp_hw.c u32 status, mask, dc_status; dc_status 1182 drivers/gpu/drm/arm/malidp_hw.c dc_status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS); dc_status 1183 drivers/gpu/drm/arm/malidp_hw.c if (dc_status & hw->map.dc_irq_map.vsync_irq) { dc_status 1184 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);