dc                246 arch/arc/include/asm/arcregs.h 	unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;
dc                248 arch/arc/include/asm/arcregs.h 	unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;
dc                385 arch/arc/kernel/setup.c 				IS_AVAIL3(erp.dc,  !ctl.dpd, "DC "),
dc               1241 arch/arc/mm/cache.c 		struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
dc               1243 arch/arc/mm/cache.c 		if (!dc->line_len)
dc               1246 arch/arc/mm/cache.c 		if (dc->line_len != L1_CACHE_BYTES)
dc               1248 arch/arc/mm/cache.c 			      dc->line_len, L1_CACHE_BYTES);
dc               1253 arch/arc/mm/cache.c 			int num_colors = dc->sz_k/dc->assoc/TO_KB(PAGE_SIZE);
dc               1255 arch/arc/mm/cache.c 			if (dc->alias) {
dc               1260 arch/arc/mm/cache.c 			} else if (!dc->alias && handled) {
dc                378 arch/arm64/include/asm/assembler.h 	dc	\op, \kaddr
dc                380 arch/arm64/include/asm/assembler.h 	dc	civac, \kaddr
dc                402 arch/arm64/include/asm/assembler.h 	dc	\op, \kaddr
dc                501 arch/ia64/include/asm/pal.h 			dc		: 1,	/* Failure in dcache */
dc                719 arch/ia64/include/asm/pal.h #define pmci_cache_data_cache_fail		pme_cache.dc
dc                619 arch/mips/include/asm/octeon/cvmx-pci-defs.h 		uint32_t dc:1;
dc                635 arch/mips/include/asm/octeon/cvmx-pci-defs.h 		uint32_t dc:1;
dc                652 arch/mips/kvm/emulate.c 	int dc;
dc                664 arch/mips/kvm/emulate.c 	dc = kvm_mips_count_disabled(vcpu);
dc                665 arch/mips/kvm/emulate.c 	if (dc) {
dc                681 arch/mips/kvm/emulate.c 	if (!dc)
dc                699 arch/mips/kvm/emulate.c 	int dc;
dc                731 arch/mips/kvm/emulate.c 	dc = kvm_mips_count_disabled(vcpu);
dc                732 arch/mips/kvm/emulate.c 	if (!dc)
dc                757 arch/mips/kvm/emulate.c 	if (!dc)
dc                146 arch/powerpc/platforms/powermac/setup.c 		const unsigned int *dc =
dc                150 arch/powerpc/platforms/powermac/setup.c 		if (of_get_property(np, "cache-unified", NULL) && dc) {
dc                151 arch/powerpc/platforms/powermac/setup.c 			seq_printf(m, " %dK unified", *dc / 1024);
dc                155 arch/powerpc/platforms/powermac/setup.c 			if (dc)
dc                157 arch/powerpc/platforms/powermac/setup.c 					   (ic? " +": ""), *dc / 1024);
dc                 54 arch/s390/include/uapi/asm/runtime_instr.h 	__u32 dc		: 4;
dc                467 arch/x86/kernel/cpu/resctrl/core.c void setup_default_ctrlval(struct rdt_resource *r, u32 *dc, u32 *dm)
dc                477 arch/x86/kernel/cpu/resctrl/core.c 	for (i = 0; i < r->num_closid; i++, dc++, dm++) {
dc                478 arch/x86/kernel/cpu/resctrl/core.c 		*dc = r->default_ctrl;
dc                486 arch/x86/kernel/cpu/resctrl/core.c 	u32 *dc, *dm;
dc                488 arch/x86/kernel/cpu/resctrl/core.c 	dc = kmalloc_array(r->num_closid, sizeof(*d->ctrl_val), GFP_KERNEL);
dc                489 arch/x86/kernel/cpu/resctrl/core.c 	if (!dc)
dc                494 arch/x86/kernel/cpu/resctrl/core.c 		kfree(dc);
dc                498 arch/x86/kernel/cpu/resctrl/core.c 	d->ctrl_val = dc;
dc                500 arch/x86/kernel/cpu/resctrl/core.c 	setup_default_ctrlval(r, dc, dm);
dc                311 arch/x86/kernel/cpu/resctrl/ctrlmondata.c 	u32 *dc;
dc                323 arch/x86/kernel/cpu/resctrl/ctrlmondata.c 		dc = !mba_sc ? d->ctrl_val : d->mbps_val;
dc                324 arch/x86/kernel/cpu/resctrl/ctrlmondata.c 		if (d->have_new_ctrl && d->new_ctrl != dc[closid]) {
dc                326 arch/x86/kernel/cpu/resctrl/ctrlmondata.c 			dc[closid] = d->new_ctrl;
dc                596 arch/x86/kernel/cpu/resctrl/internal.h void setup_default_ctrlval(struct rdt_resource *r, u32 *dc, u32 *dm);
dc                726 drivers/block/drbd/drbd_main.c 	struct disk_conf *dc;
dc                748 drivers/block/drbd/drbd_main.c 		dc = rcu_dereference(peer_device->device->ldev->disk_conf);
dc                749 drivers/block/drbd/drbd_main.c 		p->resync_rate = cpu_to_be32(dc->resync_rate);
dc                750 drivers/block/drbd/drbd_main.c 		p->c_plan_ahead = cpu_to_be32(dc->c_plan_ahead);
dc                751 drivers/block/drbd/drbd_main.c 		p->c_delay_target = cpu_to_be32(dc->c_delay_target);
dc                752 drivers/block/drbd/drbd_main.c 		p->c_fill_target = cpu_to_be32(dc->c_fill_target);
dc                753 drivers/block/drbd/drbd_main.c 		p->c_max_rate = cpu_to_be32(dc->c_max_rate);
dc               1146 drivers/block/drbd/drbd_nl.c static int drbd_check_al_size(struct drbd_device *device, struct disk_conf *dc)
dc               1154 drivers/block/drbd/drbd_nl.c 	    device->act_log->nr_elements == dc->al_extents)
dc               1160 drivers/block/drbd/drbd_nl.c 		dc->al_extents, sizeof(struct lc_element), 0);
dc               1339 drivers/block/drbd/drbd_nl.c 	struct disk_conf *dc;
dc               1348 drivers/block/drbd/drbd_nl.c 		dc = rcu_dereference(device->ldev->disk_conf);
dc               1349 drivers/block/drbd/drbd_nl.c 		max_segments = dc->max_bio_bvecs;
dc               1350 drivers/block/drbd/drbd_nl.c 		discard_zeroes_if_aligned = dc->discard_zeroes_if_aligned;
dc               1351 drivers/block/drbd/drbd_nl.c 		disable_write_same = dc->disable_write_same;
dc               1548 drivers/block/drbd/drbd_nl.c static int disk_opts_check_al_size(struct drbd_device *device, struct disk_conf *dc)
dc               1553 drivers/block/drbd/drbd_nl.c 	    device->act_log->nr_elements == dc->al_extents)
dc               1564 drivers/block/drbd/drbd_nl.c 	err = drbd_check_al_size(device, dc);
dc               1429 drivers/block/drbd/drbd_receiver.c 	struct disk_conf *dc;
dc               1431 drivers/block/drbd/drbd_receiver.c 	dc = rcu_dereference(bdev->disk_conf);
dc               1433 drivers/block/drbd/drbd_receiver.c 	if (wo == WO_BDEV_FLUSH && !dc->disk_flushes)
dc               1435 drivers/block/drbd/drbd_receiver.c 	if (wo == WO_DRAIN_IO && !dc->disk_drain)
dc               1579 drivers/block/drbd/drbd_receiver.c 	struct disk_conf *dc;
dc               1586 drivers/block/drbd/drbd_receiver.c 	dc = rcu_dereference(device->ldev->disk_conf);
dc               1587 drivers/block/drbd/drbd_receiver.c 	can_do = dc->discard_zeroes_if_aligned;
dc               3293 drivers/block/drbd/drbd_receiver.c 		int rct, dc; /* roles at crash time */
dc               3384 drivers/block/drbd/drbd_receiver.c 			dc = test_bit(RESOLVE_CONFLICTS, &connection->flags);
dc               3385 drivers/block/drbd/drbd_receiver.c 			return dc ? -1 : 1;
dc                502 drivers/block/drbd/drbd_worker.c 	struct disk_conf *dc;
dc                512 drivers/block/drbd/drbd_worker.c 	dc = rcu_dereference(device->ldev->disk_conf);
dc                518 drivers/block/drbd/drbd_worker.c 		want = ((dc->resync_rate * 2 * SLEEP_TIME) / HZ) * steps;
dc                520 drivers/block/drbd/drbd_worker.c 		want = dc->c_fill_target ? dc->c_fill_target :
dc                521 drivers/block/drbd/drbd_worker.c 			sect_in * dc->c_delay_target * HZ / (SLEEP_TIME * 10);
dc                539 drivers/block/drbd/drbd_worker.c 	max_sect = (dc->c_max_rate * 2 * SLEEP_TIME) / HZ;
dc                307 drivers/clk/clk-asm9260.c 		const struct asm9260_div_clk *dc = &asm9260_div_clks[n];
dc                309 drivers/clk/clk-asm9260.c 		hws[dc->idx] = clk_hw_register_divider(NULL, dc->name,
dc                310 drivers/clk/clk-asm9260.c 				dc->parent_name, CLK_SET_RATE_PARENT,
dc                311 drivers/clk/clk-asm9260.c 				base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED,
dc                 51 drivers/clk/mvebu/dove-divider.c static unsigned int dove_get_divider(struct dove_clk *dc)
dc                 56 drivers/clk/mvebu/dove-divider.c 	val = readl_relaxed(dc->base + DIV_CTRL0);
dc                 57 drivers/clk/mvebu/dove-divider.c 	val >>= dc->div_bit_start;
dc                 59 drivers/clk/mvebu/dove-divider.c 	divider = val & ~(~0 << dc->div_bit_size);
dc                 61 drivers/clk/mvebu/dove-divider.c 	if (dc->divider_table)
dc                 62 drivers/clk/mvebu/dove-divider.c 		divider = dc->divider_table[divider];
dc                 67 drivers/clk/mvebu/dove-divider.c static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate,
dc                 74 drivers/clk/mvebu/dove-divider.c 	if (dc->divider_table) {
dc                 77 drivers/clk/mvebu/dove-divider.c 		for (i = 0; dc->divider_table[i]; i++)
dc                 78 drivers/clk/mvebu/dove-divider.c 			if (divider == dc->divider_table[i]) {
dc                 83 drivers/clk/mvebu/dove-divider.c 		if (!dc->divider_table[i])
dc                 86 drivers/clk/mvebu/dove-divider.c 		max = 1 << dc->div_bit_size;
dc                101 drivers/clk/mvebu/dove-divider.c 	struct dove_clk *dc = to_dove_clk(hw);
dc                102 drivers/clk/mvebu/dove-divider.c 	unsigned int divider = dove_get_divider(dc);
dc                106 drivers/clk/mvebu/dove-divider.c 		 __func__, dc->name, divider, parent, rate);
dc                114 drivers/clk/mvebu/dove-divider.c 	struct dove_clk *dc = to_dove_clk(hw);
dc                118 drivers/clk/mvebu/dove-divider.c 	divider = dove_calc_divider(dc, rate, parent_rate, false);
dc                125 drivers/clk/mvebu/dove-divider.c 		 __func__, dc->name, divider, parent_rate, rate);
dc                133 drivers/clk/mvebu/dove-divider.c 	struct dove_clk *dc = to_dove_clk(hw);
dc                137 drivers/clk/mvebu/dove-divider.c 	divider = dove_calc_divider(dc, rate, parent_rate, true);
dc                142 drivers/clk/mvebu/dove-divider.c 		 __func__, dc->name, divider, parent_rate, rate);
dc                144 drivers/clk/mvebu/dove-divider.c 	div = (u32)divider << dc->div_bit_start;
dc                145 drivers/clk/mvebu/dove-divider.c 	mask = ~(~0 << dc->div_bit_size) << dc->div_bit_start;
dc                146 drivers/clk/mvebu/dove-divider.c 	load = BIT(dc->div_bit_load);
dc                148 drivers/clk/mvebu/dove-divider.c 	spin_lock(dc->lock);
dc                149 drivers/clk/mvebu/dove-divider.c 	dove_load_divider(dc->base, div, mask, load);
dc                150 drivers/clk/mvebu/dove-divider.c 	spin_unlock(dc->lock);
dc                162 drivers/clk/mvebu/dove-divider.c 	struct dove_clk *dc, const char **parent_names, size_t num_parents,
dc                173 drivers/clk/mvebu/dove-divider.c 	strlcpy(name, dc->name, sizeof(name));
dc                175 drivers/clk/mvebu/dove-divider.c 	dc->hw.init = &init;
dc                176 drivers/clk/mvebu/dove-divider.c 	dc->base = base;
dc                177 drivers/clk/mvebu/dove-divider.c 	dc->div_bit_size = dc->div_bit_end - dc->div_bit_start + 1;
dc                179 drivers/clk/mvebu/dove-divider.c 	return clk_register(dev, &dc->hw);
dc                253 drivers/dma/tegra20-apb-dma.c static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
dc                255 drivers/dma/tegra20-apb-dma.c 	return container_of(dc, struct tegra_dma_channel, dma_chan);
dc                338 drivers/dma/tegra20-apb-dma.c static int tegra_dma_slave_config(struct dma_chan *dc,
dc                341 drivers/dma/tegra20-apb-dma.c 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
dc                721 drivers/dma/tegra20-apb-dma.c static void tegra_dma_issue_pending(struct dma_chan *dc)
dc                723 drivers/dma/tegra20-apb-dma.c 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
dc                748 drivers/dma/tegra20-apb-dma.c static int tegra_dma_terminate_all(struct dma_chan *dc)
dc                750 drivers/dma/tegra20-apb-dma.c 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
dc                860 drivers/dma/tegra20-apb-dma.c static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
dc                863 drivers/dma/tegra20-apb-dma.c 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
dc                871 drivers/dma/tegra20-apb-dma.c 	ret = dma_cookie_status(dc, cookie, txstate);
dc               1001 drivers/dma/tegra20-apb-dma.c 	struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
dc               1005 drivers/dma/tegra20-apb-dma.c 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
dc               1124 drivers/dma/tegra20-apb-dma.c 	struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
dc               1128 drivers/dma/tegra20-apb-dma.c 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
dc               1259 drivers/dma/tegra20-apb-dma.c static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
dc               1261 drivers/dma/tegra20-apb-dma.c 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
dc               1275 drivers/dma/tegra20-apb-dma.c static void tegra_dma_free_chan_resources(struct dma_chan *dc)
dc               1277 drivers/dma/tegra20-apb-dma.c 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
dc               1291 drivers/dma/tegra20-apb-dma.c 		tegra_dma_terminate_all(dc);
dc                190 drivers/dma/tegra210-adma.c static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc)
dc                192 drivers/dma/tegra210-adma.c 	return container_of(dc, struct tegra_adma_chan, vc.chan);
dc                211 drivers/dma/tegra210-adma.c static int tegra_adma_slave_config(struct dma_chan *dc,
dc                214 drivers/dma/tegra210-adma.c 	struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
dc                428 drivers/dma/tegra210-adma.c static void tegra_adma_issue_pending(struct dma_chan *dc)
dc                430 drivers/dma/tegra210-adma.c 	struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
dc                453 drivers/dma/tegra210-adma.c static int tegra_adma_pause(struct dma_chan *dc)
dc                455 drivers/dma/tegra210-adma.c 	struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
dc                475 drivers/dma/tegra210-adma.c static int tegra_adma_resume(struct dma_chan *dc)
dc                477 drivers/dma/tegra210-adma.c 	struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
dc                488 drivers/dma/tegra210-adma.c static int tegra_adma_terminate_all(struct dma_chan *dc)
dc                490 drivers/dma/tegra210-adma.c 	struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
dc                507 drivers/dma/tegra210-adma.c static enum dma_status tegra_adma_tx_status(struct dma_chan *dc,
dc                511 drivers/dma/tegra210-adma.c 	struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
dc                518 drivers/dma/tegra210-adma.c 	ret = dma_cookie_status(dc, cookie, txstate);
dc                609 drivers/dma/tegra210-adma.c 	struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
dc                613 drivers/dma/tegra210-adma.c 	struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
dc                647 drivers/dma/tegra210-adma.c static int tegra_adma_alloc_chan_resources(struct dma_chan *dc)
dc                649 drivers/dma/tegra210-adma.c 	struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
dc                652 drivers/dma/tegra210-adma.c 	ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc);
dc                655 drivers/dma/tegra210-adma.c 			dma_chan_name(dc));
dc                670 drivers/dma/tegra210-adma.c static void tegra_adma_free_chan_resources(struct dma_chan *dc)
dc                672 drivers/dma/tegra210-adma.c 	struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
dc                674 drivers/dma/tegra210-adma.c 	tegra_adma_terminate_all(dc);
dc                 24 drivers/dma/txx9dmac.c static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)
dc                 26 drivers/dma/txx9dmac.c 	return dc->ch_regs;
dc                 30 drivers/dma/txx9dmac.c 	const struct txx9dmac_chan *dc)
dc                 32 drivers/dma/txx9dmac.c 	return dc->ch_regs;
dc                 35 drivers/dma/txx9dmac.c #define channel64_readq(dc, name) \
dc                 36 drivers/dma/txx9dmac.c 	__raw_readq(&(__dma_regs(dc)->name))
dc                 37 drivers/dma/txx9dmac.c #define channel64_writeq(dc, name, val) \
dc                 38 drivers/dma/txx9dmac.c 	__raw_writeq((val), &(__dma_regs(dc)->name))
dc                 39 drivers/dma/txx9dmac.c #define channel64_readl(dc, name) \
dc                 40 drivers/dma/txx9dmac.c 	__raw_readl(&(__dma_regs(dc)->name))
dc                 41 drivers/dma/txx9dmac.c #define channel64_writel(dc, name, val) \
dc                 42 drivers/dma/txx9dmac.c 	__raw_writel((val), &(__dma_regs(dc)->name))
dc                 44 drivers/dma/txx9dmac.c #define channel32_readl(dc, name) \
dc                 45 drivers/dma/txx9dmac.c 	__raw_readl(&(__dma_regs32(dc)->name))
dc                 46 drivers/dma/txx9dmac.c #define channel32_writel(dc, name, val) \
dc                 47 drivers/dma/txx9dmac.c 	__raw_writel((val), &(__dma_regs32(dc)->name))
dc                 49 drivers/dma/txx9dmac.c #define channel_readq(dc, name) channel64_readq(dc, name)
dc                 50 drivers/dma/txx9dmac.c #define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)
dc                 51 drivers/dma/txx9dmac.c #define channel_readl(dc, name) \
dc                 52 drivers/dma/txx9dmac.c 	(is_dmac64(dc) ? \
dc                 53 drivers/dma/txx9dmac.c 	 channel64_readl(dc, name) : channel32_readl(dc, name))
dc                 54 drivers/dma/txx9dmac.c #define channel_writel(dc, name, val) \
dc                 55 drivers/dma/txx9dmac.c 	(is_dmac64(dc) ? \
dc                 56 drivers/dma/txx9dmac.c 	 channel64_writel(dc, name, val) : channel32_writel(dc, name, val))
dc                 58 drivers/dma/txx9dmac.c static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)
dc                 60 drivers/dma/txx9dmac.c 	if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
dc                 61 drivers/dma/txx9dmac.c 		return channel64_readq(dc, CHAR);
dc                 63 drivers/dma/txx9dmac.c 		return channel64_readl(dc, CHAR);
dc                 66 drivers/dma/txx9dmac.c static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
dc                 68 drivers/dma/txx9dmac.c 	if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
dc                 69 drivers/dma/txx9dmac.c 		channel64_writeq(dc, CHAR, val);
dc                 71 drivers/dma/txx9dmac.c 		channel64_writel(dc, CHAR, val);
dc                 74 drivers/dma/txx9dmac.c static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
dc                 77 drivers/dma/txx9dmac.c 	channel64_writel(dc, CHAR, 0);
dc                 78 drivers/dma/txx9dmac.c 	channel64_writel(dc, __pad_CHAR, 0);
dc                 80 drivers/dma/txx9dmac.c 	channel64_writeq(dc, CHAR, 0);
dc                 84 drivers/dma/txx9dmac.c static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
dc                 86 drivers/dma/txx9dmac.c 	if (is_dmac64(dc))
dc                 87 drivers/dma/txx9dmac.c 		return channel64_read_CHAR(dc);
dc                 89 drivers/dma/txx9dmac.c 		return channel32_readl(dc, CHAR);
dc                 92 drivers/dma/txx9dmac.c static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
dc                 94 drivers/dma/txx9dmac.c 	if (is_dmac64(dc))
dc                 95 drivers/dma/txx9dmac.c 		channel64_write_CHAR(dc, val);
dc                 97 drivers/dma/txx9dmac.c 		channel32_writel(dc, CHAR, val);
dc                144 drivers/dma/txx9dmac.c static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,
dc                147 drivers/dma/txx9dmac.c 	return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;
dc                150 drivers/dma/txx9dmac.c static void desc_write_CHAR(const struct txx9dmac_chan *dc,
dc                153 drivers/dma/txx9dmac.c 	if (is_dmac64(dc))
dc                163 drivers/dma/txx9dmac.c static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)
dc                165 drivers/dma/txx9dmac.c 	return list_entry(dc->active_list.next,
dc                169 drivers/dma/txx9dmac.c static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)
dc                171 drivers/dma/txx9dmac.c 	return list_entry(dc->active_list.prev,
dc                175 drivers/dma/txx9dmac.c static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)
dc                177 drivers/dma/txx9dmac.c 	return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);
dc                189 drivers/dma/txx9dmac.c static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,
dc                192 drivers/dma/txx9dmac.c 	struct txx9dmac_dev *ddev = dc->ddev;
dc                199 drivers/dma/txx9dmac.c 	dma_async_tx_descriptor_init(&desc->txd, &dc->chan);
dc                203 drivers/dma/txx9dmac.c 	desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,
dc                208 drivers/dma/txx9dmac.c static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)
dc                214 drivers/dma/txx9dmac.c 	spin_lock_bh(&dc->lock);
dc                215 drivers/dma/txx9dmac.c 	list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {
dc                221 drivers/dma/txx9dmac.c 		dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);
dc                224 drivers/dma/txx9dmac.c 	spin_unlock_bh(&dc->lock);
dc                226 drivers/dma/txx9dmac.c 	dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",
dc                229 drivers/dma/txx9dmac.c 		ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);
dc                231 drivers/dma/txx9dmac.c 			spin_lock_bh(&dc->lock);
dc                232 drivers/dma/txx9dmac.c 			dc->descs_allocated++;
dc                233 drivers/dma/txx9dmac.c 			spin_unlock_bh(&dc->lock);
dc                235 drivers/dma/txx9dmac.c 			dev_err(chan2dev(&dc->chan),
dc                241 drivers/dma/txx9dmac.c static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,
dc                244 drivers/dma/txx9dmac.c 	struct txx9dmac_dev *ddev = dc->ddev;
dc                248 drivers/dma/txx9dmac.c 		dma_sync_single_for_cpu(chan2parent(&dc->chan),
dc                251 drivers/dma/txx9dmac.c 	dma_sync_single_for_cpu(chan2parent(&dc->chan),
dc                260 drivers/dma/txx9dmac.c static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
dc                266 drivers/dma/txx9dmac.c 		txx9dmac_sync_desc_for_cpu(dc, desc);
dc                268 drivers/dma/txx9dmac.c 		spin_lock_bh(&dc->lock);
dc                270 drivers/dma/txx9dmac.c 			dev_vdbg(chan2dev(&dc->chan),
dc                273 drivers/dma/txx9dmac.c 		list_splice_init(&desc->tx_list, &dc->free_list);
dc                274 drivers/dma/txx9dmac.c 		dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",
dc                276 drivers/dma/txx9dmac.c 		list_add(&desc->desc_node, &dc->free_list);
dc                277 drivers/dma/txx9dmac.c 		spin_unlock_bh(&dc->lock);
dc                283 drivers/dma/txx9dmac.c static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
dc                285 drivers/dma/txx9dmac.c 	if (is_dmac64(dc))
dc                286 drivers/dma/txx9dmac.c 		dev_err(chan2dev(&dc->chan),
dc                289 drivers/dma/txx9dmac.c 			(u64)channel64_read_CHAR(dc),
dc                290 drivers/dma/txx9dmac.c 			channel64_readq(dc, SAR),
dc                291 drivers/dma/txx9dmac.c 			channel64_readq(dc, DAR),
dc                292 drivers/dma/txx9dmac.c 			channel64_readl(dc, CNTR),
dc                293 drivers/dma/txx9dmac.c 			channel64_readl(dc, SAIR),
dc                294 drivers/dma/txx9dmac.c 			channel64_readl(dc, DAIR),
dc                295 drivers/dma/txx9dmac.c 			channel64_readl(dc, CCR),
dc                296 drivers/dma/txx9dmac.c 			channel64_readl(dc, CSR));
dc                298 drivers/dma/txx9dmac.c 		dev_err(chan2dev(&dc->chan),
dc                301 drivers/dma/txx9dmac.c 			channel32_readl(dc, CHAR),
dc                302 drivers/dma/txx9dmac.c 			channel32_readl(dc, SAR),
dc                303 drivers/dma/txx9dmac.c 			channel32_readl(dc, DAR),
dc                304 drivers/dma/txx9dmac.c 			channel32_readl(dc, CNTR),
dc                305 drivers/dma/txx9dmac.c 			channel32_readl(dc, SAIR),
dc                306 drivers/dma/txx9dmac.c 			channel32_readl(dc, DAIR),
dc                307 drivers/dma/txx9dmac.c 			channel32_readl(dc, CCR),
dc                308 drivers/dma/txx9dmac.c 			channel32_readl(dc, CSR));
dc                311 drivers/dma/txx9dmac.c static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
dc                313 drivers/dma/txx9dmac.c 	channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
dc                314 drivers/dma/txx9dmac.c 	if (is_dmac64(dc)) {
dc                315 drivers/dma/txx9dmac.c 		channel64_clear_CHAR(dc);
dc                316 drivers/dma/txx9dmac.c 		channel_writeq(dc, SAR, 0);
dc                317 drivers/dma/txx9dmac.c 		channel_writeq(dc, DAR, 0);
dc                319 drivers/dma/txx9dmac.c 		channel_writel(dc, CHAR, 0);
dc                320 drivers/dma/txx9dmac.c 		channel_writel(dc, SAR, 0);
dc                321 drivers/dma/txx9dmac.c 		channel_writel(dc, DAR, 0);
dc                323 drivers/dma/txx9dmac.c 	channel_writel(dc, CNTR, 0);
dc                324 drivers/dma/txx9dmac.c 	channel_writel(dc, SAIR, 0);
dc                325 drivers/dma/txx9dmac.c 	channel_writel(dc, DAIR, 0);
dc                326 drivers/dma/txx9dmac.c 	channel_writel(dc, CCR, 0);
dc                330 drivers/dma/txx9dmac.c static void txx9dmac_dostart(struct txx9dmac_chan *dc,
dc                333 drivers/dma/txx9dmac.c 	struct txx9dmac_slave *ds = dc->chan.private;
dc                336 drivers/dma/txx9dmac.c 	dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",
dc                339 drivers/dma/txx9dmac.c 	if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
dc                340 drivers/dma/txx9dmac.c 		dev_err(chan2dev(&dc->chan),
dc                342 drivers/dma/txx9dmac.c 		txx9dmac_dump_regs(dc);
dc                347 drivers/dma/txx9dmac.c 	if (is_dmac64(dc)) {
dc                348 drivers/dma/txx9dmac.c 		channel64_writel(dc, CNTR, 0);
dc                349 drivers/dma/txx9dmac.c 		channel64_writel(dc, CSR, 0xffffffff);
dc                362 drivers/dma/txx9dmac.c 		channel64_writel(dc, SAIR, sai);
dc                363 drivers/dma/txx9dmac.c 		channel64_writel(dc, DAIR, dai);
dc                365 drivers/dma/txx9dmac.c 		channel64_writel(dc, CCR, dc->ccr);
dc                367 drivers/dma/txx9dmac.c 		channel64_write_CHAR(dc, first->txd.phys);
dc                369 drivers/dma/txx9dmac.c 		channel32_writel(dc, CNTR, 0);
dc                370 drivers/dma/txx9dmac.c 		channel32_writel(dc, CSR, 0xffffffff);
dc                383 drivers/dma/txx9dmac.c 		channel32_writel(dc, SAIR, sai);
dc                384 drivers/dma/txx9dmac.c 		channel32_writel(dc, DAIR, dai);
dc                386 drivers/dma/txx9dmac.c 			channel32_writel(dc, CCR, dc->ccr);
dc                388 drivers/dma/txx9dmac.c 			channel32_writel(dc, CHAR, first->txd.phys);
dc                390 drivers/dma/txx9dmac.c 			channel32_writel(dc, CHAR, first->txd.phys);
dc                391 drivers/dma/txx9dmac.c 			channel32_writel(dc, CCR, dc->ccr);
dc                399 drivers/dma/txx9dmac.c txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
dc                405 drivers/dma/txx9dmac.c 	dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
dc                411 drivers/dma/txx9dmac.c 	txx9dmac_sync_desc_for_cpu(dc, desc);
dc                412 drivers/dma/txx9dmac.c 	list_splice_init(&desc->tx_list, &dc->free_list);
dc                413 drivers/dma/txx9dmac.c 	list_move(&desc->desc_node, &dc->free_list);
dc                424 drivers/dma/txx9dmac.c static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)
dc                426 drivers/dma/txx9dmac.c 	struct txx9dmac_dev *ddev = dc->ddev;
dc                432 drivers/dma/txx9dmac.c 		desc = txx9dmac_first_queued(dc);
dc                434 drivers/dma/txx9dmac.c 			desc_write_CHAR(dc, prev, desc->txd.phys);
dc                435 drivers/dma/txx9dmac.c 			dma_sync_single_for_device(chan2parent(&dc->chan),
dc                443 drivers/dma/txx9dmac.c 		    !txx9dmac_chan_INTENT(dc))
dc                445 drivers/dma/txx9dmac.c 	} while (!list_empty(&dc->queue));
dc                448 drivers/dma/txx9dmac.c static void txx9dmac_complete_all(struct txx9dmac_chan *dc)
dc                457 drivers/dma/txx9dmac.c 	list_splice_init(&dc->active_list, &list);
dc                458 drivers/dma/txx9dmac.c 	if (!list_empty(&dc->queue)) {
dc                459 drivers/dma/txx9dmac.c 		txx9dmac_dequeue(dc, &dc->active_list);
dc                460 drivers/dma/txx9dmac.c 		txx9dmac_dostart(dc, txx9dmac_first_active(dc));
dc                464 drivers/dma/txx9dmac.c 		txx9dmac_descriptor_complete(dc, desc);
dc                467 drivers/dma/txx9dmac.c static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,
dc                470 drivers/dma/txx9dmac.c 	if (is_dmac64(dc)) {
dc                472 drivers/dma/txx9dmac.c 		dev_crit(chan2dev(&dc->chan),
dc                476 drivers/dma/txx9dmac.c 		dev_crit(chan2dev(&dc->chan),
dc                485 drivers/dma/txx9dmac.c 		dev_crit(chan2dev(&dc->chan),
dc                489 drivers/dma/txx9dmac.c 		dev_crit(chan2dev(&dc->chan),
dc                498 drivers/dma/txx9dmac.c static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)
dc                509 drivers/dma/txx9dmac.c 	dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");
dc                510 drivers/dma/txx9dmac.c 	txx9dmac_dump_regs(dc);
dc                512 drivers/dma/txx9dmac.c 	bad_desc = txx9dmac_first_active(dc);
dc                519 drivers/dma/txx9dmac.c 	channel_writel(dc, CSR, errors);
dc                521 drivers/dma/txx9dmac.c 	if (list_empty(&dc->active_list) && !list_empty(&dc->queue))
dc                522 drivers/dma/txx9dmac.c 		txx9dmac_dequeue(dc, &dc->active_list);
dc                523 drivers/dma/txx9dmac.c 	if (!list_empty(&dc->active_list))
dc                524 drivers/dma/txx9dmac.c 		txx9dmac_dostart(dc, txx9dmac_first_active(dc));
dc                526 drivers/dma/txx9dmac.c 	dev_crit(chan2dev(&dc->chan),
dc                529 drivers/dma/txx9dmac.c 	txx9dmac_dump_desc(dc, &bad_desc->hwdesc);
dc                531 drivers/dma/txx9dmac.c 		txx9dmac_dump_desc(dc, &child->hwdesc);
dc                533 drivers/dma/txx9dmac.c 	txx9dmac_descriptor_complete(dc, bad_desc);
dc                536 drivers/dma/txx9dmac.c static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)
dc                543 drivers/dma/txx9dmac.c 	if (is_dmac64(dc)) {
dc                544 drivers/dma/txx9dmac.c 		chain = channel64_read_CHAR(dc);
dc                545 drivers/dma/txx9dmac.c 		csr = channel64_readl(dc, CSR);
dc                546 drivers/dma/txx9dmac.c 		channel64_writel(dc, CSR, csr);
dc                548 drivers/dma/txx9dmac.c 		chain = channel32_readl(dc, CHAR);
dc                549 drivers/dma/txx9dmac.c 		csr = channel32_readl(dc, CSR);
dc                550 drivers/dma/txx9dmac.c 		channel32_writel(dc, CSR, csr);
dc                555 drivers/dma/txx9dmac.c 		txx9dmac_complete_all(dc);
dc                561 drivers/dma/txx9dmac.c 	dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",
dc                564 drivers/dma/txx9dmac.c 	list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {
dc                565 drivers/dma/txx9dmac.c 		if (desc_read_CHAR(dc, desc) == chain) {
dc                573 drivers/dma/txx9dmac.c 			if (desc_read_CHAR(dc, child) == chain) {
dc                584 drivers/dma/txx9dmac.c 		txx9dmac_descriptor_complete(dc, desc);
dc                588 drivers/dma/txx9dmac.c 		txx9dmac_handle_error(dc, csr);
dc                592 drivers/dma/txx9dmac.c 	dev_err(chan2dev(&dc->chan),
dc                596 drivers/dma/txx9dmac.c 	txx9dmac_reset_chan(dc);
dc                598 drivers/dma/txx9dmac.c 	if (!list_empty(&dc->queue)) {
dc                599 drivers/dma/txx9dmac.c 		txx9dmac_dequeue(dc, &dc->active_list);
dc                600 drivers/dma/txx9dmac.c 		txx9dmac_dostart(dc, txx9dmac_first_active(dc));
dc                608 drivers/dma/txx9dmac.c 	struct txx9dmac_chan *dc;
dc                610 drivers/dma/txx9dmac.c 	dc = (struct txx9dmac_chan *)data;
dc                611 drivers/dma/txx9dmac.c 	csr = channel_readl(dc, CSR);
dc                612 drivers/dma/txx9dmac.c 	dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);
dc                614 drivers/dma/txx9dmac.c 	spin_lock(&dc->lock);
dc                617 drivers/dma/txx9dmac.c 		txx9dmac_scan_descriptors(dc);
dc                618 drivers/dma/txx9dmac.c 	spin_unlock(&dc->lock);
dc                619 drivers/dma/txx9dmac.c 	irq = dc->irq;
dc                626 drivers/dma/txx9dmac.c 	struct txx9dmac_chan *dc = dev_id;
dc                628 drivers/dma/txx9dmac.c 	dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",
dc                629 drivers/dma/txx9dmac.c 			channel_readl(dc, CSR));
dc                631 drivers/dma/txx9dmac.c 	tasklet_schedule(&dc->tasklet);
dc                645 drivers/dma/txx9dmac.c 	struct txx9dmac_chan *dc;
dc                655 drivers/dma/txx9dmac.c 			dc = ddev->chan[i];
dc                656 drivers/dma/txx9dmac.c 			csr = channel_readl(dc, CSR);
dc                657 drivers/dma/txx9dmac.c 			dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",
dc                659 drivers/dma/txx9dmac.c 			spin_lock(&dc->lock);
dc                662 drivers/dma/txx9dmac.c 				txx9dmac_scan_descriptors(dc);
dc                663 drivers/dma/txx9dmac.c 			spin_unlock(&dc->lock);
dc                693 drivers/dma/txx9dmac.c 	struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);
dc                696 drivers/dma/txx9dmac.c 	spin_lock_bh(&dc->lock);
dc                702 drivers/dma/txx9dmac.c 	list_add_tail(&desc->desc_node, &dc->queue);
dc                703 drivers/dma/txx9dmac.c 	spin_unlock_bh(&dc->lock);
dc                712 drivers/dma/txx9dmac.c 	struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
dc                713 drivers/dma/txx9dmac.c 	struct txx9dmac_dev *ddev = dc->ddev;
dc                748 drivers/dma/txx9dmac.c 		desc = txx9dmac_desc_get(dc);
dc                750 drivers/dma/txx9dmac.c 			txx9dmac_desc_put(dc, first);
dc                759 drivers/dma/txx9dmac.c 					dc->ccr | TXX9_DMA_CCR_XFACT);
dc                765 drivers/dma/txx9dmac.c 					dc->ccr | TXX9_DMA_CCR_XFACT);
dc                778 drivers/dma/txx9dmac.c 			desc_write_CHAR(dc, prev, desc->txd.phys);
dc                779 drivers/dma/txx9dmac.c 			dma_sync_single_for_device(chan2parent(&dc->chan),
dc                791 drivers/dma/txx9dmac.c 	desc_write_CHAR(dc, prev, 0);
dc                792 drivers/dma/txx9dmac.c 	dma_sync_single_for_device(chan2parent(&dc->chan),
dc                807 drivers/dma/txx9dmac.c 	struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
dc                808 drivers/dma/txx9dmac.c 	struct txx9dmac_dev *ddev = dc->ddev;
dc                832 drivers/dma/txx9dmac.c 		desc = txx9dmac_desc_get(dc);
dc                834 drivers/dma/txx9dmac.c 			txx9dmac_desc_put(dc, first);
dc                867 drivers/dma/txx9dmac.c 					dc->ccr | TXX9_DMA_CCR_XFACT);
dc                872 drivers/dma/txx9dmac.c 			desc_write_CHAR(dc, prev, desc->txd.phys);
dc                873 drivers/dma/txx9dmac.c 			dma_sync_single_for_device(chan2parent(&dc->chan),
dc                886 drivers/dma/txx9dmac.c 	desc_write_CHAR(dc, prev, 0);
dc                887 drivers/dma/txx9dmac.c 	dma_sync_single_for_device(chan2parent(&dc->chan),
dc                899 drivers/dma/txx9dmac.c 	struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
dc                904 drivers/dma/txx9dmac.c 	spin_lock_bh(&dc->lock);
dc                906 drivers/dma/txx9dmac.c 	txx9dmac_reset_chan(dc);
dc                909 drivers/dma/txx9dmac.c 	list_splice_init(&dc->queue, &list);
dc                910 drivers/dma/txx9dmac.c 	list_splice_init(&dc->active_list, &list);
dc                912 drivers/dma/txx9dmac.c 	spin_unlock_bh(&dc->lock);
dc                916 drivers/dma/txx9dmac.c 		txx9dmac_descriptor_complete(dc, desc);
dc                925 drivers/dma/txx9dmac.c 	struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
dc                932 drivers/dma/txx9dmac.c 	spin_lock_bh(&dc->lock);
dc                933 drivers/dma/txx9dmac.c 	txx9dmac_scan_descriptors(dc);
dc                934 drivers/dma/txx9dmac.c 	spin_unlock_bh(&dc->lock);
dc                939 drivers/dma/txx9dmac.c static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,
dc                942 drivers/dma/txx9dmac.c 	struct txx9dmac_dev *ddev = dc->ddev;
dc                947 drivers/dma/txx9dmac.c 	txx9dmac_dequeue(dc, &list);
dc                949 drivers/dma/txx9dmac.c 	desc_write_CHAR(dc, prev, desc->txd.phys);
dc                950 drivers/dma/txx9dmac.c 	dma_sync_single_for_device(chan2parent(&dc->chan),
dc                953 drivers/dma/txx9dmac.c 	if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
dc                954 drivers/dma/txx9dmac.c 	    channel_read_CHAR(dc) == prev->txd.phys)
dc                956 drivers/dma/txx9dmac.c 		channel_write_CHAR(dc, desc->txd.phys);
dc                957 drivers/dma/txx9dmac.c 	list_splice_tail(&list, &dc->active_list);
dc                962 drivers/dma/txx9dmac.c 	struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
dc                964 drivers/dma/txx9dmac.c 	spin_lock_bh(&dc->lock);
dc                966 drivers/dma/txx9dmac.c 	if (!list_empty(&dc->active_list))
dc                967 drivers/dma/txx9dmac.c 		txx9dmac_scan_descriptors(dc);
dc                968 drivers/dma/txx9dmac.c 	if (!list_empty(&dc->queue)) {
dc                969 drivers/dma/txx9dmac.c 		if (list_empty(&dc->active_list)) {
dc                970 drivers/dma/txx9dmac.c 			txx9dmac_dequeue(dc, &dc->active_list);
dc                971 drivers/dma/txx9dmac.c 			txx9dmac_dostart(dc, txx9dmac_first_active(dc));
dc                973 drivers/dma/txx9dmac.c 			struct txx9dmac_desc *prev = txx9dmac_last_active(dc);
dc                976 drivers/dma/txx9dmac.c 			    txx9dmac_chan_INTENT(dc))
dc                977 drivers/dma/txx9dmac.c 				txx9dmac_chain_dynamic(dc, prev);
dc                981 drivers/dma/txx9dmac.c 	spin_unlock_bh(&dc->lock);
dc                986 drivers/dma/txx9dmac.c 	struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
dc                994 drivers/dma/txx9dmac.c 	if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
dc               1001 drivers/dma/txx9dmac.c 	dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
dc               1002 drivers/dma/txx9dmac.c 	txx9dmac_chan_set_SMPCHN(dc);
dc               1003 drivers/dma/txx9dmac.c 	if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN))
dc               1004 drivers/dma/txx9dmac.c 		dc->ccr |= TXX9_DMA_CCR_INTENC;
dc               1008 drivers/dma/txx9dmac.c 		dc->ccr |= TXX9_DMA_CCR_XFSZ_X8;
dc               1013 drivers/dma/txx9dmac.c 		dc->ccr |= TXX9_DMA_CCR_EXTRQ |
dc               1015 drivers/dma/txx9dmac.c 		txx9dmac_chan_set_INTENT(dc);
dc               1018 drivers/dma/txx9dmac.c 	spin_lock_bh(&dc->lock);
dc               1019 drivers/dma/txx9dmac.c 	i = dc->descs_allocated;
dc               1020 drivers/dma/txx9dmac.c 	while (dc->descs_allocated < TXX9_DMA_INITIAL_DESC_COUNT) {
dc               1021 drivers/dma/txx9dmac.c 		spin_unlock_bh(&dc->lock);
dc               1023 drivers/dma/txx9dmac.c 		desc = txx9dmac_desc_alloc(dc, GFP_KERNEL);
dc               1027 drivers/dma/txx9dmac.c 			spin_lock_bh(&dc->lock);
dc               1030 drivers/dma/txx9dmac.c 		txx9dmac_desc_put(dc, desc);
dc               1032 drivers/dma/txx9dmac.c 		spin_lock_bh(&dc->lock);
dc               1033 drivers/dma/txx9dmac.c 		i = ++dc->descs_allocated;
dc               1035 drivers/dma/txx9dmac.c 	spin_unlock_bh(&dc->lock);
dc               1045 drivers/dma/txx9dmac.c 	struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
dc               1046 drivers/dma/txx9dmac.c 	struct txx9dmac_dev *ddev = dc->ddev;
dc               1051 drivers/dma/txx9dmac.c 			dc->descs_allocated);
dc               1054 drivers/dma/txx9dmac.c 	BUG_ON(!list_empty(&dc->active_list));
dc               1055 drivers/dma/txx9dmac.c 	BUG_ON(!list_empty(&dc->queue));
dc               1056 drivers/dma/txx9dmac.c 	BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
dc               1058 drivers/dma/txx9dmac.c 	spin_lock_bh(&dc->lock);
dc               1059 drivers/dma/txx9dmac.c 	list_splice_init(&dc->free_list, &list);
dc               1060 drivers/dma/txx9dmac.c 	dc->descs_allocated = 0;
dc               1061 drivers/dma/txx9dmac.c 	spin_unlock_bh(&dc->lock);
dc               1086 drivers/dma/txx9dmac.c 	struct txx9dmac_chan *dc;
dc               1091 drivers/dma/txx9dmac.c 	dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
dc               1092 drivers/dma/txx9dmac.c 	if (!dc)
dc               1095 drivers/dma/txx9dmac.c 	dc->dma.dev = &pdev->dev;
dc               1096 drivers/dma/txx9dmac.c 	dc->dma.device_alloc_chan_resources = txx9dmac_alloc_chan_resources;
dc               1097 drivers/dma/txx9dmac.c 	dc->dma.device_free_chan_resources = txx9dmac_free_chan_resources;
dc               1098 drivers/dma/txx9dmac.c 	dc->dma.device_terminate_all = txx9dmac_terminate_all;
dc               1099 drivers/dma/txx9dmac.c 	dc->dma.device_tx_status = txx9dmac_tx_status;
dc               1100 drivers/dma/txx9dmac.c 	dc->dma.device_issue_pending = txx9dmac_issue_pending;
dc               1102 drivers/dma/txx9dmac.c 		dc->dma.device_prep_dma_memcpy = txx9dmac_prep_dma_memcpy;
dc               1103 drivers/dma/txx9dmac.c 		dma_cap_set(DMA_MEMCPY, dc->dma.cap_mask);
dc               1105 drivers/dma/txx9dmac.c 		dc->dma.device_prep_slave_sg = txx9dmac_prep_slave_sg;
dc               1106 drivers/dma/txx9dmac.c 		dma_cap_set(DMA_SLAVE, dc->dma.cap_mask);
dc               1107 drivers/dma/txx9dmac.c 		dma_cap_set(DMA_PRIVATE, dc->dma.cap_mask);
dc               1110 drivers/dma/txx9dmac.c 	INIT_LIST_HEAD(&dc->dma.channels);
dc               1111 drivers/dma/txx9dmac.c 	dc->ddev = platform_get_drvdata(dmac_dev);
dc               1112 drivers/dma/txx9dmac.c 	if (dc->ddev->irq < 0) {
dc               1116 drivers/dma/txx9dmac.c 		tasklet_init(&dc->tasklet, txx9dmac_chan_tasklet,
dc               1117 drivers/dma/txx9dmac.c 				(unsigned long)dc);
dc               1118 drivers/dma/txx9dmac.c 		dc->irq = irq;
dc               1119 drivers/dma/txx9dmac.c 		err = devm_request_irq(&pdev->dev, dc->irq,
dc               1120 drivers/dma/txx9dmac.c 			txx9dmac_chan_interrupt, 0, dev_name(&pdev->dev), dc);
dc               1124 drivers/dma/txx9dmac.c 		dc->irq = -1;
dc               1125 drivers/dma/txx9dmac.c 	dc->ddev->chan[ch] = dc;
dc               1126 drivers/dma/txx9dmac.c 	dc->chan.device = &dc->dma;
dc               1127 drivers/dma/txx9dmac.c 	list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
dc               1128 drivers/dma/txx9dmac.c 	dma_cookie_init(&dc->chan);
dc               1130 drivers/dma/txx9dmac.c 	if (is_dmac64(dc))
dc               1131 drivers/dma/txx9dmac.c 		dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
dc               1133 drivers/dma/txx9dmac.c 		dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];
dc               1134 drivers/dma/txx9dmac.c 	spin_lock_init(&dc->lock);
dc               1136 drivers/dma/txx9dmac.c 	INIT_LIST_HEAD(&dc->active_list);
dc               1137 drivers/dma/txx9dmac.c 	INIT_LIST_HEAD(&dc->queue);
dc               1138 drivers/dma/txx9dmac.c 	INIT_LIST_HEAD(&dc->free_list);
dc               1140 drivers/dma/txx9dmac.c 	txx9dmac_reset_chan(dc);
dc               1142 drivers/dma/txx9dmac.c 	platform_set_drvdata(pdev, dc);
dc               1144 drivers/dma/txx9dmac.c 	err = dma_async_device_register(&dc->dma);
dc               1148 drivers/dma/txx9dmac.c 		dc->dma.dev_id,
dc               1149 drivers/dma/txx9dmac.c 		dma_has_cap(DMA_MEMCPY, dc->dma.cap_mask) ? " memcpy" : "",
dc               1150 drivers/dma/txx9dmac.c 		dma_has_cap(DMA_SLAVE, dc->dma.cap_mask) ? " slave" : "");
dc               1157 drivers/dma/txx9dmac.c 	struct txx9dmac_chan *dc = platform_get_drvdata(pdev);
dc               1160 drivers/dma/txx9dmac.c 	dma_async_device_unregister(&dc->dma);
dc               1161 drivers/dma/txx9dmac.c 	if (dc->irq >= 0) {
dc               1162 drivers/dma/txx9dmac.c 		devm_free_irq(&pdev->dev, dc->irq, dc);
dc               1163 drivers/dma/txx9dmac.c 		tasklet_kill(&dc->tasklet);
dc               1165 drivers/dma/txx9dmac.c 	dc->ddev->chan[pdev->id % TXX9_DMA_MAX_NR_CHANNELS] = NULL;
dc                193 drivers/dma/txx9dmac.h static inline bool is_dmac64(const struct txx9dmac_chan *dc)
dc                195 drivers/dma/txx9dmac.h 	return __is_dmac64(dc->ddev);
dc                237 drivers/dma/txx9dmac.h static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc)
dc                239 drivers/dma/txx9dmac.h 	return (dc->ccr & TXX9_DMA_CCR_INTENT) != 0;
dc                242 drivers/dma/txx9dmac.h static inline void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc)
dc                244 drivers/dma/txx9dmac.h 	dc->ccr |= TXX9_DMA_CCR_INTENT;
dc                252 drivers/dma/txx9dmac.h static inline void txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc)
dc                254 drivers/dma/txx9dmac.h 	dc->ccr |= TXX9_DMA_CCR_SMPCHN;
dc                265 drivers/dma/txx9dmac.h static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc)
dc                270 drivers/dma/txx9dmac.h static void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc)
dc                283 drivers/dma/txx9dmac.h static inline void txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc)
dc                369 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
dc                370 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c module_param_named(dc, amdgpu_dc, int, 0444);
dc                401 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 				    adev->dm.dc,
dc                449 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 				adev->dm.dc,
dc                482 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (adev->dm.dc->fbc_compressor == NULL)
dc                505 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
dc                593 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
dc                603 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			adev->dm.dc->res_pool->audios[i]->inst;
dc                707 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	adev->dm.dc = dc_create(&init_data);
dc                709 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (adev->dm.dc) {
dc                716 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
dc                738 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
dc                739 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
dc                768 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (adev->dm.dc)
dc                769 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		dc_destroy(&adev->dm.dc);
dc                931 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
dc               1058 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
dc               1183 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	dm_state->context = dc_create_state(dm->dc);
dc               1185 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	dc_resource_state_construct(dm->dc, dm_state->context);
dc               1188 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
dc               1191 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	dc_resume(dm->dc);
dc               1686 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct dc *dc = adev->dm.dc;
dc               1720 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			dc_interrupt_to_irq_source(dc, i, 0);
dc               1741 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			dc_interrupt_to_irq_source(dc, i, 0);
dc               1763 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			dc_interrupt_to_irq_source(dc, i, 0);
dc               1792 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct dc *dc = adev->dm.dc;
dc               1826 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			dc_interrupt_to_irq_source(dc, i, 0);
dc               1854 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			dc_interrupt_to_irq_source(dc, i, 0);
dc               1877 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			dc_interrupt_to_irq_source(dc, i, 0);
dc               2029 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	state->context = dc_create_state(adev->dm.dc);
dc               2035 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
dc               2183 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (plane_id >= dm->dc->caps.max_streams)
dc               2243 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	link_cnt = dm->dc->caps.max_links;
dc               2250 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	primary_planes = dm->dc->caps.max_streams;
dc               2258 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		plane = &dm->dc->caps.planes[i];
dc               2276 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	for (i = 0; i < dm->dc->caps.max_planes; ++i) {
dc               2277 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
dc               2298 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	for (i = 0; i < dm->dc->caps.max_streams; i++)
dc               2304 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	dm->display_indexes_num = dm->dc->caps.max_streams;
dc               2335 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		link = dc_get_link_at_index(dm->dc, i);
dc               2397 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
dc               2709 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct dc *dc = adev->dm.dc;
dc               2728 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (!dc->cap_funcs.get_dcc_compression_cap)
dc               2741 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
dc               3646 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc,
dc               3754 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
dc               3782 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
dc               4133 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	dc_result = dc_validate_stream(adev->dm.dc, stream);
dc               4365 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct dc *dc = adev->dm.dc;
dc               4396 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
dc               4596 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct dc *dc = adev->dm.dc;
dc               4610 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
dc               4817 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
dc               4818 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
dc               5096 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	    dc_is_dmcu_initialized(adev->dm.dc)) {
dc               5139 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			ddc_service->ctx->dc,
dc               5193 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct dc *dc = dm->dc;
dc               5194 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct dc_link *link = dc_get_link_at_index(dc, link_index);
dc               5537 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			dc_stream_adjust_vmin_vmax(dm->dc,
dc               5928 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 				dm->dc, acrtc_state->stream,
dc               5934 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		dc_commit_updates_for_stream(dm->dc,
dc               6178 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		dc_state_temp = dc_create_state(dm->dc);
dc               6181 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		dc_resource_state_copy_construct_current(dm->dc, dc_state);
dc               6258 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		WARN_ON(!dc_commit_state(dm->dc, dc_state));
dc               6353 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		dc_commit_updates_for_stream(dm->dc,
dc               6741 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 				dm->dc,
dc               6784 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 					dm->dc,
dc               6915 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c static int dm_update_plane_state(struct dc *dc,
dc               6983 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 				dc,
dc               7018 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		dc_new_plane_state = dc_create_plane_state(dc);
dc               7049 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 				dc,
dc               7077 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct dc *dc = dm->dc;
dc               7213 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
dc               7260 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct dc *dc = adev->dm.dc;
dc               7338 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		ret = dm_update_plane_state(dc, state, plane,
dc               7371 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		ret = dm_update_plane_state(dc, state, plane,
dc               7453 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
dc               7505 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c static bool is_dp_capable_without_timing_msa(struct dc *dc,
dc               7570 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 						adev->dm.dc,
dc                 59 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h struct dc;
dc                116 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 	struct dc *dc;
dc                117 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c 		if (!dc_stream_configure_crc(stream_state->ctx->dc,
dc                308 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c 		if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
dc                148 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	struct dc *dc = (struct dc *)link->dc;
dc                233 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	dc_link_set_preferred_link_settings(dc, &prefer_link_settings, link);
dc                325 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	struct dc *dc = (struct dc *)link->dc;
dc                416 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	dc_link_set_drive_settings(dc, &link_lane_settings, link);
dc                971 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	struct dc *dc = adev->dm.dc;
dc                978 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	if (!dc->hwss.log_hw_state)
dc                981 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	dc->hwss.log_hw_state(dc, &log_ctx);
dc               1010 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	struct dc *dc = adev->dm.dc;
dc               1016 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	if (dc->hwss.log_hw_state)
dc               1017 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 		dc->hwss.log_hw_state(dc, NULL);
dc               1032 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	struct dc *dc = adev->dm.dc;
dc               1033 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	unsigned int backlight = dc_get_current_backlight_pwm(dc);
dc               1049 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	struct dc *dc = adev->dm.dc;
dc               1050 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	unsigned int backlight = dc_get_target_backlight_pwm(dc);
dc               1093 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
dc               1106 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 	*val = adev->dm.dc->debug.visual_confirm;
dc                438 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 			dc_interrupt_set(adev->dm.dc, src, false);
dc                465 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 			dc_interrupt_set(adev->dm.dc, src, true);
dc                491 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 			dc_interrupt_set(adev->dm.dc, src, true);
dc                568 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 			adev->dm.dc,
dc                572 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 	dc_interrupt_ack(adev->dm.dc, src);
dc                610 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 	dc_interrupt_set(adev->dm.dc, src, st);
dc                641 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 	dc_interrupt_set(adev->dm.dc, irq_source, st);
dc                743 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 			dc_interrupt_set(adev->dm.dc,
dc                749 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 			dc_interrupt_set(adev->dm.dc,
dc                774 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 		dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, false);
dc                777 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 			dc_interrupt_set(adev->dm.dc,
dc               3028 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	if (ctx->dc->config.multi_mon_pp_mclk_switch)
dc               3047 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (ctx->dc->debug.bandwidth_calcs_trace) {
dc               3098 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (ctx->dc->caps.max_slave_planes) {
dc               3128 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (ctx->dc->caps.max_slave_planes) {
dc               3156 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (ctx->dc->caps.max_slave_planes) {
dc               3184 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (ctx->dc->caps.max_slave_planes) {
dc               3219 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (ctx->dc->caps.max_slave_planes) {
dc               3249 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (ctx->dc->caps.max_slave_planes) {
dc               3277 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (ctx->dc->caps.max_slave_planes) {
dc               3305 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (ctx->dc->caps.max_slave_planes) {
dc               3339 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (ctx->dc->caps.max_slave_planes) {
dc               3368 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (ctx->dc->caps.max_slave_planes) {
dc               3396 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (ctx->dc->caps.max_slave_planes) {
dc               3424 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (ctx->dc->caps.max_slave_planes) {
dc               3472 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (ctx->dc->caps.max_slave_planes) {
dc               3500 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (ctx->dc->caps.max_slave_planes) {
dc               3528 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (ctx->dc->caps.max_slave_planes) {
dc               3556 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (ctx->dc->caps.max_slave_planes) {
dc                 39 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->ctx->logger
dc                313 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {
dc                328 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
dc                442 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		const struct dc *dc,
dc                447 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);
dc                483 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
dc                492 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
dc                625 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c static bool dcn_bw_apply_registry_override(struct dc *dc)
dc                630 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
dc                631 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			&& dc->debug.sr_exit_time_ns) {
dc                633 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;
dc                636 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)
dc                637 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				!= dc->debug.sr_enter_plus_exit_time_ns
dc                638 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			&& dc->debug.sr_enter_plus_exit_time_ns) {
dc                640 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_soc->sr_enter_plus_exit_time =
dc                641 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				dc->debug.sr_enter_plus_exit_time_ns / 1000.0;
dc                644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns
dc                645 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			&& dc->debug.urgent_latency_ns) {
dc                647 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;
dc                650 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)
dc                651 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				!= dc->debug.percent_of_ideal_drambw
dc                652 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			&& dc->debug.percent_of_ideal_drambw) {
dc                654 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =
dc                655 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				dc->debug.percent_of_ideal_drambw;
dc                658 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)
dc                659 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				!= dc->debug.dram_clock_change_latency_ns
dc                660 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			&& dc->debug.dram_clock_change_latency_ns) {
dc                662 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_soc->dram_clock_change_latency =
dc                663 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				dc->debug.dram_clock_change_latency_ns / 1000.0;
dc                720 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		struct dc *dc,
dc                730 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	const struct resource_pool *pool = dc->res_pool;
dc                741 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if (dcn_bw_apply_registry_override(dc))
dc                742 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dcn_bw_sync_calcs_and_dml(dc);
dc                747 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->sr_exit_time = dc->dcn_soc->sr_exit_time;
dc                748 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
dc                749 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->urgent_latency = dc->dcn_soc->urgent_latency;
dc                750 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->write_back_latency = dc->dcn_soc->write_back_latency;
dc                752 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
dc                754 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;
dc                755 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;
dc                756 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;
dc                757 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;
dc                759 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;
dc                760 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;
dc                761 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;
dc                762 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;
dc                764 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;
dc                765 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;
dc                766 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;
dc                767 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;
dc                769 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->socclk = dc->dcn_soc->socclk;
dc                771 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
dc                772 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
dc                773 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
dc                774 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
dc                776 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;
dc                777 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;
dc                778 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;
dc                779 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;
dc                781 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->downspreading = dc->dcn_soc->downspreading;
dc                782 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles;
dc                783 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel;
dc                784 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->number_of_channels = dc->dcn_soc->number_of_channels;
dc                785 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->vmm_page_size = dc->dcn_soc->vmm_page_size;
dc                786 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;
dc                787 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->return_bus_width = dc->dcn_soc->return_bus_width;
dc                789 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;
dc                790 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;
dc                791 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
dc                792 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
dc                793 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;
dc                794 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->pte_enable = dc->dcn_ip->pte_enable;
dc                795 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->pte_chunk_size = dc->dcn_ip->pte_chunk_size;
dc                796 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;
dc                797 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size;
dc                798 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->odm_capability = dc->dcn_ip->odm_capability;
dc                799 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dsc_capability = dc->dcn_ip->dsc_capability;
dc                800 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->line_buffer_size = dc->dcn_ip->line_buffer_size;
dc                801 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;
dc                802 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp;
dc                803 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
dc                804 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size;
dc                805 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size;
dc                806 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_num_dpp = dc->dcn_ip->max_num_dpp;
dc                807 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_num_writeback = dc->dcn_ip->max_num_writeback;
dc                808 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput;
dc                809 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput;
dc                810 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput;
dc                811 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput;
dc                812 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
dc                813 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
dc                814 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_hscl_taps = dc->dcn_ip->max_hscl_taps;
dc                815 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_vscl_taps = dc->dcn_ip->max_vscl_taps;
dc                816 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->under_scan_factor = dc->dcn_ip->under_scan_factor;
dc                817 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests;
dc                818 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin;
dc                819 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
dc                821 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
dc                823 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed;
dc                960 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			if (dc->debug.optimized_watermark) {
dc                975 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(
dc               1029 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	hack_bounding_box(v, &dc->debug, context);
dc               1036 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			&& dc->debug.force_single_disp_pipe_split) {
dc               1042 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			(dc->debug.sr_exit_time_dpm0_ns
dc               1043 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				|| dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {
dc               1045 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)
dc               1047 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
dc               1048 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		if (dc->debug.sr_exit_time_dpm0_ns)
dc               1049 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			v->sr_exit_time =  dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
dc               1107 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			if (dc->debug.voltage_align_fclk)
dc               1138 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		if (dc->debug.max_disp_clk == true)
dc               1139 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
dc               1142 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				dc->debug.min_disp_clk_khz) {
dc               1144 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					dc->debug.min_disp_clk_khz;
dc               1153 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					(int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000);
dc               1157 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					(int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000);
dc               1161 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					(int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000);
dc               1165 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					(int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000);
dc               1238 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);
dc               1254 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);
dc               1267 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				dc->dcn_soc->sr_enter_plus_exit_time;
dc               1268 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
dc               1275 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
dc               1283 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->ctx->asic_id.hw_internal_rev))
dc               1290 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	const struct dc *dc,
dc               1301 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
dc               1304 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		} else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
dc               1306 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		} else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {
dc               1308 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		} else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {
dc               1314 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
dc               1317 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		} else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
dc               1319 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		} else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {
dc               1321 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		} else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) {
dc               1328 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {
dc               1331 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		} else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {
dc               1333 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		} else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {
dc               1335 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		} else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) {
dc               1343 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
dc               1345 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
dc               1348 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
dc               1350 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
dc               1352 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {
dc               1360 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {
dc               1363 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		} else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {
dc               1365 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		} else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {
dc               1367 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		} else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) {
dc               1380 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	const struct dc *dc,
dc               1388 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz);
dc               1390 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);
dc               1394 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
dc               1398 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz);
dc               1401 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz);
dc               1407 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
dc               1409 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dcf_clk =  dc->dcn_soc->dcfclkv_max0p9*1000;
dc               1411 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dcf_clk =  dc->dcn_soc->dcfclkv_nom0p8*1000;
dc               1413 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dcf_clk =  dc->dcn_soc->dcfclkv_mid0p72*1000;
dc               1415 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dcf_clk =  dc->dcn_soc->dcfclkv_min0p65*1000;
dc               1436 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c void dcn_bw_update_from_pplib(struct dc *dc)
dc               1438 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	struct dc_context *ctx = dc->ctx;
dc               1461 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 =
dc               1463 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 =
dc               1464 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->number_of_channels *
dc               1467 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 =
dc               1468 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->number_of_channels *
dc               1471 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 =
dc               1472 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->number_of_channels *
dc               1489 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0;
dc               1490 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0;
dc               1491 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0;
dc               1492 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0;
dc               1499 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
dc               1506 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if (dc->res_pool->pp_smu)
dc               1507 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		pp = &dc->res_pool->pp_smu->rv_funcs;
dc               1512 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
dc               1513 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
dc               1514 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	socclk_khz = dc->dcn_soc->socclk * 1000;
dc               1538 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
dc               1564 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c void dcn_bw_sync_calcs_and_dml(struct dc *dc)
dc               1601 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->sr_exit_time * 1000,
dc               1602 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->sr_enter_plus_exit_time * 1000,
dc               1603 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->urgent_latency * 1000,
dc               1604 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->write_back_latency * 1000,
dc               1605 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency,
dc               1606 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->max_request_size,
dc               1607 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->dcfclkv_max0p9 * 1000,
dc               1608 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->dcfclkv_nom0p8 * 1000,
dc               1609 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->dcfclkv_mid0p72 * 1000,
dc               1610 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->dcfclkv_min0p65 * 1000,
dc               1611 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->max_dispclk_vmax0p9 * 1000,
dc               1612 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->max_dispclk_vnom0p8 * 1000,
dc               1613 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->max_dispclk_vmid0p72 * 1000,
dc               1614 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->max_dispclk_vmin0p65 * 1000,
dc               1615 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->max_dppclk_vmax0p9 * 1000,
dc               1616 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->max_dppclk_vnom0p8 * 1000,
dc               1617 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->max_dppclk_vmid0p72 * 1000,
dc               1618 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->max_dppclk_vmin0p65 * 1000,
dc               1619 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->socclk * 1000,
dc               1620 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000,
dc               1621 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000,
dc               1622 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000,
dc               1623 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000,
dc               1624 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->phyclkv_max0p9 * 1000,
dc               1625 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->phyclkv_nom0p8 * 1000,
dc               1626 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->phyclkv_mid0p72 * 1000,
dc               1627 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->phyclkv_min0p65 * 1000,
dc               1628 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->downspreading * 100,
dc               1629 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->round_trip_ping_latency_cycles,
dc               1630 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->urgent_out_of_order_return_per_channel,
dc               1631 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->number_of_channels,
dc               1632 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->vmm_page_size,
dc               1633 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->dram_clock_change_latency * 1000,
dc               1634 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->return_bus_width);
dc               1669 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->rob_buffer_size_in_kbyte,
dc               1670 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->det_buffer_size_in_kbyte,
dc               1671 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->dpp_output_buffer_pixels,
dc               1672 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->opp_output_buffer_lines,
dc               1673 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->pixel_chunk_size_in_kbyte,
dc               1674 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->pte_enable,
dc               1675 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->pte_chunk_size,
dc               1676 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->meta_chunk_size,
dc               1677 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->writeback_chunk_size,
dc               1678 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->odm_capability,
dc               1679 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->dsc_capability,
dc               1680 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->line_buffer_size,
dc               1681 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->max_line_buffer_lines,
dc               1682 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->is_line_buffer_bpp_fixed,
dc               1683 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->line_buffer_fixed_bpp,
dc               1684 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->writeback_luma_buffer_size,
dc               1685 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->writeback_chroma_buffer_size,
dc               1686 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->max_num_dpp,
dc               1687 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->max_num_writeback,
dc               1688 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->max_dchub_topscl_throughput,
dc               1689 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->max_pscl_tolb_throughput,
dc               1690 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->max_lb_tovscl_throughput,
dc               1691 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->max_vscl_tohscl_throughput,
dc               1692 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->max_hscl_ratio,
dc               1693 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->max_vscl_ratio,
dc               1694 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->max_hscl_taps,
dc               1695 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->max_vscl_taps,
dc               1696 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->pte_buffer_size_in_requests,
dc               1697 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->dispclk_ramping_margin,
dc               1698 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->under_scan_factor * 100,
dc               1699 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->max_inter_dcn_tile_repeaters,
dc               1700 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
dc               1701 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,
dc               1702 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_ip->dcfclk_cstate_latency);
dc               1704 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
dc               1705 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;
dc               1706 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency;
dc               1707 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency;
dc               1708 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.soc.ideal_dram_bw_after_urgent_percent =
dc               1709 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
dc               1710 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size;
dc               1711 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading;
dc               1712 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =
dc               1713 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->round_trip_ping_latency_cycles;
dc               1714 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =
dc               1715 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dc->dcn_soc->urgent_out_of_order_return_per_channel;
dc               1716 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels;
dc               1717 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size;
dc               1718 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;
dc               1719 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width;
dc               1721 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte;
dc               1722 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte;
dc               1723 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
dc               1724 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
dc               1725 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte;
dc               1726 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;
dc               1727 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size;
dc               1728 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size;
dc               1729 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size;
dc               1730 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size;
dc               1731 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
dc               1732 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;
dc               1733 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp;
dc               1734 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size;
dc               1735 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size;
dc               1736 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp;
dc               1737 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback;
dc               1738 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput;
dc               1739 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput;
dc               1740 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput;
dc               1741 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput;
dc               1742 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
dc               1743 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
dc               1744 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps;
dc               1745 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps;
dc               1747 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin;
dc               1748 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor;
dc               1749 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
dc               1750 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
dc               1751 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;
dc               1752 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
dc               1753 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
dc               1754 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
dc                 46 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c 		struct dc *dc,
dc                237 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
dc                274 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
dc                382 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct dc *dc,
dc                391 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
dc                392 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
dc                419 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	dce_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
dc                 67 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 		const struct dc *dc,
dc                 76 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	if (dc->sclk_lvls.num_levels == 0)
dc                 79 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
dc                 80 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 		if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
dc                 81 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 			return dc->sclk_lvls.clocks_in_khz[i];
dc                 89 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
dc                173 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	struct dc *dc,
dc                179 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
dc                198 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {
dc                201 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 								   div64_s64(dc->bw_vbios->high_yclk.value,
dc                209 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 			dc,
dc                230 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
dc                244 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
dc                245 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
dc                272 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
dc                 39 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h 	struct dc *dc,
dc                 75 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct dc *core_dc = clk_mgr_base->ctx->dc;
dc                129 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct dc *core_dc = clk_mgr->base.ctx->dc;
dc                217 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
dc                119 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c 	dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
dc                149 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c 	if (dce121_xgmi_enabled(ctx->dc->hwseq))
dc                 88 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c static void ramp_up_dispclk_with_dpp(struct clk_mgr_internal *clk_mgr, struct dc *dc, struct dc_clocks *new_clocks)
dc                101 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc                102 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 		struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
dc                130 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	struct dc *dc = clk_mgr_base->ctx->dc;
dc                131 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	struct dc_debug_options *debug = &dc->debug;
dc                144 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
dc                209 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 		ramp_up_dispclk_with_dpp(clk_mgr, dc, new_clocks);
dc                253 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	struct dc_debug_options *debug = &ctx->dc->debug;
dc                 91 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 	struct dc *core_dc = clk_mgr->base.ctx->dc;
dc                107 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
dc                146 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct dc *dc = clk_mgr_base->ctx->dc;
dc                150 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (dc->res_pool->pp_smu)
dc                151 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
dc                167 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct dc *dc = clk_mgr_base->ctx->dc;
dc                171 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (dc->res_pool->pp_smu)
dc                172 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
dc                192 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct dc *dc = clk_mgr_base->ctx->dc;
dc                197 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
dc                201 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (dc->work_arounds.skip_clock_update)
dc                205 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		dc->debug.force_clock_mode & 0x1) {
dc                210 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
dc                211 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (dc->res_pool->pp_smu)
dc                212 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
dc                229 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (dc->debug.force_min_dcfclk_mhz > 0)
dc                230 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
dc                231 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
dc                267 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (dc->config.forced_clocks == false) {
dc                281 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
dc                298 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
dc                 61 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	struct dc *dc = clk_mgr_base->ctx->dc;
dc                 67 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
dc                 69 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
dc                 95 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
dc                522 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	struct dc_debug_options *debug = &ctx->dc->debug;
dc                 85 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 	struct dc *core_dc = clk_mgr->base.ctx->dc;
dc                 73 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->ctx->logger
dc                136 drivers/gpu/drm/amd/display/dc/core/dc.c static void destroy_links(struct dc *dc)
dc                140 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < dc->link_count; i++) {
dc                141 drivers/gpu/drm/amd/display/dc/core/dc.c 		if (NULL != dc->links[i])
dc                142 drivers/gpu/drm/amd/display/dc/core/dc.c 			link_destroy(&dc->links[i]);
dc                147 drivers/gpu/drm/amd/display/dc/core/dc.c 		struct dc *dc,
dc                152 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct dc_bios *bios = dc->ctx->dc_bios;
dc                154 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->link_count = 0;
dc                176 drivers/gpu/drm/amd/display/dc/core/dc.c 		link_init_params.ctx = dc->ctx;
dc                179 drivers/gpu/drm/amd/display/dc/core/dc.c 		link_init_params.link_index = dc->link_count;
dc                180 drivers/gpu/drm/amd/display/dc/core/dc.c 		link_init_params.dc = dc;
dc                187 drivers/gpu/drm/amd/display/dc/core/dc.c 				if (dc->config.edp_not_connected)
dc                189 drivers/gpu/drm/amd/display/dc/core/dc.c 				else if (dc->debug.remove_disconnect_edp) {
dc                198 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc->links[dc->link_count] = link;
dc                199 drivers/gpu/drm/amd/display/dc/core/dc.c 				link->dc = dc;
dc                200 drivers/gpu/drm/amd/display/dc/core/dc.c 				++dc->link_count;
dc                216 drivers/gpu/drm/amd/display/dc/core/dc.c 		link->link_index = dc->link_count;
dc                217 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->links[dc->link_count] = link;
dc                218 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->link_count++;
dc                220 drivers/gpu/drm/amd/display/dc/core/dc.c 		link->ctx = dc->ctx;
dc                221 drivers/gpu/drm/amd/display/dc/core/dc.c 		link->dc = dc;
dc                235 drivers/gpu/drm/amd/display/dc/core/dc.c 		enc_init.ctx = dc->ctx;
dc                279 drivers/gpu/drm/amd/display/dc/core/dc.c bool dc_stream_adjust_vmin_vmax(struct dc *dc,
dc                289 drivers/gpu/drm/amd/display/dc/core/dc.c 		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
dc                293 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->hwss.set_drr(&pipe,
dc                306 drivers/gpu/drm/amd/display/dc/core/dc.c bool dc_stream_get_crtc_position(struct dc *dc,
dc                318 drivers/gpu/drm/amd/display/dc/core/dc.c 				&dc->current_state->res_ctx.pipe_ctx[i];
dc                321 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->hwss.get_position(&pipe, 1, &position);
dc                342 drivers/gpu/drm/amd/display/dc/core/dc.c bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
dc                351 drivers/gpu/drm/amd/display/dc/core/dc.c 		pipe = &dc->current_state->res_ctx.pipe_ctx[i];
dc                392 drivers/gpu/drm/amd/display/dc/core/dc.c bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
dc                400 drivers/gpu/drm/amd/display/dc/core/dc.c 		pipe = &dc->current_state->res_ctx.pipe_ctx[i];
dc                425 drivers/gpu/drm/amd/display/dc/core/dc.c 		if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
dc                427 drivers/gpu/drm/amd/display/dc/core/dc.c 			pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
dc                455 drivers/gpu/drm/amd/display/dc/core/dc.c bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
dc                462 drivers/gpu/drm/amd/display/dc/core/dc.c 		if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
dc                463 drivers/gpu/drm/amd/display/dc/core/dc.c 			pipes = &dc->current_state->res_ctx.pipe_ctx[i];
dc                464 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->hwss.program_gamut_remap(pipes);
dc                472 drivers/gpu/drm/amd/display/dc/core/dc.c bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
dc                479 drivers/gpu/drm/amd/display/dc/core/dc.c 		if (dc->current_state->res_ctx.pipe_ctx[i].stream
dc                482 drivers/gpu/drm/amd/display/dc/core/dc.c 			pipes = &dc->current_state->res_ctx.pipe_ctx[i];
dc                483 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->hwss.program_output_csc(dc,
dc                495 drivers/gpu/drm/amd/display/dc/core/dc.c void dc_stream_set_static_screen_events(struct dc *dc,
dc                509 drivers/gpu/drm/amd/display/dc/core/dc.c 			if (dc->current_state->res_ctx.pipe_ctx[j].stream
dc                512 drivers/gpu/drm/amd/display/dc/core/dc.c 						&dc->current_state->res_ctx.pipe_ctx[j];
dc                517 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
dc                520 drivers/gpu/drm/amd/display/dc/core/dc.c static void destruct(struct dc *dc)
dc                522 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->current_state) {
dc                523 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc_release_state(dc->current_state);
dc                524 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->current_state = NULL;
dc                527 drivers/gpu/drm/amd/display/dc/core/dc.c 	destroy_links(dc);
dc                529 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->clk_mgr) {
dc                530 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc_destroy_clk_mgr(dc->clk_mgr);
dc                531 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->clk_mgr = NULL;
dc                534 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc_destroy_resource_pool(dc);
dc                536 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->ctx->gpio_service)
dc                537 drivers/gpu/drm/amd/display/dc/core/dc.c 		dal_gpio_service_destroy(&dc->ctx->gpio_service);
dc                539 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->ctx->created_bios)
dc                540 drivers/gpu/drm/amd/display/dc/core/dc.c 		dal_bios_parser_destroy(&dc->ctx->dc_bios);
dc                542 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc_perf_trace_destroy(&dc->ctx->perf_trace);
dc                544 drivers/gpu/drm/amd/display/dc/core/dc.c 	kfree(dc->ctx);
dc                545 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->ctx = NULL;
dc                547 drivers/gpu/drm/amd/display/dc/core/dc.c 	kfree(dc->bw_vbios);
dc                548 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->bw_vbios = NULL;
dc                550 drivers/gpu/drm/amd/display/dc/core/dc.c 	kfree(dc->bw_dceip);
dc                551 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->bw_dceip = NULL;
dc                554 drivers/gpu/drm/amd/display/dc/core/dc.c 	kfree(dc->dcn_soc);
dc                555 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->dcn_soc = NULL;
dc                557 drivers/gpu/drm/amd/display/dc/core/dc.c 	kfree(dc->dcn_ip);
dc                558 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->dcn_ip = NULL;
dc                562 drivers/gpu/drm/amd/display/dc/core/dc.c 	kfree(dc->vm_helper);
dc                563 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->vm_helper = NULL;
dc                568 drivers/gpu/drm/amd/display/dc/core/dc.c static bool construct(struct dc *dc,
dc                580 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->config = init_params->flags;
dc                584 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
dc                585 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (!dc->vm_helper) {
dc                591 drivers/gpu/drm/amd/display/dc/core/dc.c 	memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
dc                599 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->bw_dceip = dc_dceip;
dc                607 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->bw_vbios = dc_vbios;
dc                615 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->dcn_soc = dcn_soc;
dc                623 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->dcn_ip = dcn_ip;
dc                625 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->soc_bounding_box = init_params->soc_bounding_box;
dc                637 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc_ctx->dc = dc;
dc                641 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->ctx = dc_ctx;
dc                690 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->res_pool = dc_create_resource_pool(dc, init_params, dc_version);
dc                691 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (!dc->res_pool)
dc                694 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
dc                695 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (!dc->clk_mgr)
dc                699 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->res_pool->funcs->update_bw_bounding_box)
dc                700 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
dc                708 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->current_state = dc_create_state(dc);
dc                710 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (!dc->current_state) {
dc                715 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc_resource_state_construct(dc, dc->current_state);
dc                717 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (!create_links(dc, init_params->num_virtual_links))
dc                724 drivers/gpu/drm/amd/display/dc/core/dc.c 	destruct(dc);
dc                730 drivers/gpu/drm/amd/display/dc/core/dc.c 		const struct dc *dc,
dc                743 drivers/gpu/drm/amd/display/dc/core/dc.c static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
dc                746 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct dc_state *dangling_context = dc_create_state(dc);
dc                752 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc_resource_state_copy_construct(dc->current_state, dangling_context);
dc                754 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc                756 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc->current_state->res_ctx.pipe_ctx[i].stream;
dc                766 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
dc                768 drivers/gpu/drm/amd/display/dc/core/dc.c 			disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
dc                770 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
dc                774 drivers/gpu/drm/amd/display/dc/core/dc.c 	current_ctx = dc->current_state;
dc                775 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->current_state = dangling_context;
dc                783 drivers/gpu/drm/amd/display/dc/core/dc.c struct dc *dc_create(const struct dc_init_data *init_params)
dc                785 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
dc                788 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (NULL == dc)
dc                791 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (false == construct(dc, init_params))
dc                795 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->hwss.init_hw(dc);
dc                797 drivers/gpu/drm/amd/display/dc/core/dc.c 	full_pipe_count = dc->res_pool->pipe_count;
dc                798 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
dc                800 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->caps.max_streams = min(
dc                802 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->res_pool->stream_enc_count);
dc                804 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->caps.max_links = dc->link_count;
dc                805 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->caps.max_audios = dc->res_pool->audio_count;
dc                806 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->caps.linear_pitch_alignment = 64;
dc                809 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->versions.dc_ver = DC_VER;
dc                811 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->res_pool->dmcu != NULL)
dc                812 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
dc                814 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->build_id = DC_BUILD_ID;
dc                820 drivers/gpu/drm/amd/display/dc/core/dc.c 	return dc;
dc                823 drivers/gpu/drm/amd/display/dc/core/dc.c 	kfree(dc);
dc                829 drivers/gpu/drm/amd/display/dc/core/dc.c void dc_init_callbacks(struct dc *dc,
dc                834 drivers/gpu/drm/amd/display/dc/core/dc.c void dc_destroy(struct dc **dc)
dc                836 drivers/gpu/drm/amd/display/dc/core/dc.c 	destruct(*dc);
dc                837 drivers/gpu/drm/amd/display/dc/core/dc.c 	kfree(*dc);
dc                838 drivers/gpu/drm/amd/display/dc/core/dc.c 	*dc = NULL;
dc                842 drivers/gpu/drm/amd/display/dc/core/dc.c 		struct dc *dc,
dc                846 drivers/gpu/drm/amd/display/dc/core/dc.c 	int pipe_count = dc->res_pool->pipe_count;
dc                860 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.enable_per_frame_crtc_position_reset(
dc                861 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc, multisync_count, multisync_pipes);
dc                866 drivers/gpu/drm/amd/display/dc/core/dc.c 		struct dc *dc,
dc                872 drivers/gpu/drm/amd/display/dc/core/dc.c 	int pipe_count = dc->res_pool->pipe_count;
dc                945 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->hwss.enable_timing_synchronization(
dc                946 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc, group_index, group_size, pipe_set);
dc                954 drivers/gpu/drm/amd/display/dc/core/dc.c 		struct dc *dc,
dc                959 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (context->stream_count != dc->current_state->stream_count)
dc                962 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < dc->current_state->stream_count; i++) {
dc                963 drivers/gpu/drm/amd/display/dc/core/dc.c 		if (dc->current_state->streams[i] != context->streams[i])
dc                970 drivers/gpu/drm/amd/display/dc/core/dc.c bool dc_validate_seamless_boot_timing(const struct dc *dc,
dc                991 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (enc_inst >= dc->res_pool->pipe_count)
dc                994 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (enc_inst >= dc->res_pool->stream_enc_count)
dc                997 drivers/gpu/drm/amd/display/dc/core/dc.c 	tg_inst = dc->res_pool->stream_enc[enc_inst]->funcs->dig_source_otg(
dc                998 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->res_pool->stream_enc[enc_inst]);
dc               1000 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (tg_inst >= dc->res_pool->timing_generator_count)
dc               1003 drivers/gpu/drm/amd/display/dc/core/dc.c 	tg = dc->res_pool->timing_generators[tg_inst];
dc               1014 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
dc               1015 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->res_pool->dp_clock_source,
dc               1027 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct dc *dc,
dc               1040 drivers/gpu/drm/amd/display/dc/core/dc.c 			pipe = &dc->current_state->res_ctx.pipe_ctx[i];
dc               1043 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc->hwss.setup_stereo)
dc               1044 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc->hwss.setup_stereo(pipe, dc);
dc               1055 drivers/gpu/drm/amd/display/dc/core/dc.c static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
dc               1057 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct dc_bios *dcb = dc->ctx->dc_bios;
dc               1063 drivers/gpu/drm/amd/display/dc/core/dc.c 	disable_dangling_plane(dc, context);
dc               1069 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.enable_accelerated_mode(dc, context);
dc               1073 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->optimize_seamless_boot = true;
dc               1076 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (!dc->optimize_seamless_boot)
dc               1077 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.prepare_bandwidth(dc, context);
dc               1086 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.apply_ctx_for_surface(
dc               1087 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc, context->streams[i],
dc               1093 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               1095 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
dc               1098 drivers/gpu/drm/amd/display/dc/core/dc.c 	result = dc->hwss.apply_ctx_to_hw(dc, context);
dc               1103 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
dc               1104 drivers/gpu/drm/amd/display/dc/core/dc.c 		enable_timing_multisync(dc, context);
dc               1105 drivers/gpu/drm/amd/display/dc/core/dc.c 		program_timing_sync(dc, context);
dc               1115 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.apply_ctx_for_surface(
dc               1116 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc, context->streams[i],
dc               1130 drivers/gpu/drm/amd/display/dc/core/dc.c 					dc->hwss.setup_stereo)
dc               1131 drivers/gpu/drm/amd/display/dc/core/dc.c 					dc->hwss.setup_stereo(pipe, dc);
dc               1143 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc_enable_stereo(dc, context, dc_streams, context->stream_count);
dc               1145 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (!dc->optimize_seamless_boot)
dc               1147 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.optimize_bandwidth(dc, context);
dc               1154 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc_release_state(dc->current_state);
dc               1156 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->current_state = context;
dc               1158 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc_retain_state(dc->current_state);
dc               1163 drivers/gpu/drm/amd/display/dc/core/dc.c bool dc_commit_state(struct dc *dc, struct dc_state *context)
dc               1168 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (false == context_changed(dc, context))
dc               1177 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc_stream_log(dc, stream);
dc               1180 drivers/gpu/drm/amd/display/dc/core/dc.c 	result = dc_commit_state_no_check(dc, context);
dc               1185 drivers/gpu/drm/amd/display/dc/core/dc.c static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
dc               1198 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.update_pending_status(pipe);
dc               1205 drivers/gpu/drm/amd/display/dc/core/dc.c bool dc_post_update_surfaces_to_stream(struct dc *dc)
dc               1208 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct dc_state *context = dc->current_state;
dc               1210 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (!dc->optimized_required || dc->optimize_seamless_boot)
dc               1213 drivers/gpu/drm/amd/display/dc/core/dc.c 	post_surface_trace(dc);
dc               1215 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (is_flip_pending_in_pipes(dc, context))
dc               1218 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
dc               1222 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
dc               1225 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->optimized_required = false;
dc               1227 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->hwss.optimize_bandwidth(dc, context);
dc               1231 drivers/gpu/drm/amd/display/dc/core/dc.c struct dc_state *dc_create_state(struct dc *dc)
dc               1243 drivers/gpu/drm/amd/display/dc/core/dc.c 	memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
dc               1516 drivers/gpu/drm/amd/display/dc/core/dc.c static enum surface_update_type det_surface_update(const struct dc *dc,
dc               1519 drivers/gpu/drm/amd/display/dc/core/dc.c 	const struct dc_state *context = dc->current_state;
dc               1585 drivers/gpu/drm/amd/display/dc/core/dc.c 		struct dc *dc,
dc               1624 drivers/gpu/drm/amd/display/dc/core/dc.c 				det_surface_update(dc, &updates[i]);
dc               1641 drivers/gpu/drm/amd/display/dc/core/dc.c 		struct dc *dc,
dc               1653 drivers/gpu/drm/amd/display/dc/core/dc.c 	type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
dc               1658 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (type == UPDATE_TYPE_FAST && memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0)
dc               1659 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->optimized_required = true;
dc               1798 drivers/gpu/drm/amd/display/dc/core/dc.c static void copy_stream_update_to_stream(struct dc *dc,
dc               1884 drivers/gpu/drm/amd/display/dc/core/dc.c 		if (!dc->res_pool->funcs->validate_bandwidth(dc, context,
dc               1893 drivers/gpu/drm/amd/display/dc/core/dc.c static void commit_planes_do_stream_update(struct dc *dc,
dc               1902 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
dc               1908 drivers/gpu/drm/amd/display/dc/core/dc.c 					dc->hwss.setup_periodic_interrupt)
dc               1909 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE0);
dc               1912 drivers/gpu/drm/amd/display/dc/core/dc.c 					dc->hwss.setup_periodic_interrupt)
dc               1913 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE1);
dc               1920 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc->hwss.update_info_frame(pipe_ctx);
dc               1924 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc_stream_set_gamut_remap(dc, stream);
dc               1927 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc_stream_program_csc_matrix(dc, stream);
dc               1949 drivers/gpu/drm/amd/display/dc/core/dc.c 			if (stream_update->dsc_config && dc->hwss.pipe_control_lock_global) {
dc               1950 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc->hwss.pipe_control_lock_global(dc, pipe_ctx, true);
dc               1952 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc->hwss.pipe_control_lock_global(dc, pipe_ctx, false);
dc               1960 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
dc               1965 drivers/gpu/drm/amd/display/dc/core/dc.c 					if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
dc               1968 drivers/gpu/drm/amd/display/dc/core/dc.c 					dc->hwss.optimize_bandwidth(dc, dc->current_state);
dc               1970 drivers/gpu/drm/amd/display/dc/core/dc.c 					if (!dc->optimize_seamless_boot)
dc               1971 drivers/gpu/drm/amd/display/dc/core/dc.c 						dc->hwss.prepare_bandwidth(dc, dc->current_state);
dc               1973 drivers/gpu/drm/amd/display/dc/core/dc.c 					core_link_enable_stream(dc->current_state, pipe_ctx);
dc               1976 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
dc               1993 drivers/gpu/drm/amd/display/dc/core/dc.c static void commit_planes_for_stream(struct dc *dc,
dc               2004 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->optimize_seamless_boot && surface_count > 0) {
dc               2013 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->optimize_seamless_boot = false;
dc               2014 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->optimized_required = true;
dc               2018 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (update_type == UPDATE_TYPE_FULL && !dc->optimize_seamless_boot) {
dc               2019 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.prepare_bandwidth(dc, context);
dc               2020 drivers/gpu/drm/amd/display/dc/core/dc.c 		context_clock_trace(dc, context);
dc               2025 drivers/gpu/drm/amd/display/dc/core/dc.c 		commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
dc               2032 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
dc               2037 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
dc               2041 drivers/gpu/drm/amd/display/dc/core/dc.c 			for (j = 0; j < dc->res_pool->pipe_count; j++) {
dc               2049 drivers/gpu/drm/amd/display/dc/core/dc.c 					dc->hwss.program_triplebuffer != NULL &&
dc               2051 drivers/gpu/drm/amd/display/dc/core/dc.c 					!dc->debug.disable_tri_buf) {
dc               2061 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
dc               2082 drivers/gpu/drm/amd/display/dc/core/dc.c 			if (dc->hwss.program_triplebuffer != NULL &&
dc               2083 drivers/gpu/drm/amd/display/dc/core/dc.c 				!dc->debug.disable_tri_buf) {
dc               2085 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc->hwss.program_triplebuffer(
dc               2086 drivers/gpu/drm/amd/display/dc/core/dc.c 					dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
dc               2092 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->hwss.apply_ctx_for_surface(
dc               2093 drivers/gpu/drm/amd/display/dc/core/dc.c 					dc, pipe_ctx->stream, stream_status->plane_count, context);
dc               2103 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
dc               2106 drivers/gpu/drm/amd/display/dc/core/dc.c 		if (dc->hwss.set_flip_control_gsl)
dc               2110 drivers/gpu/drm/amd/display/dc/core/dc.c 				for (j = 0; j < dc->res_pool->pipe_count; j++) {
dc               2120 drivers/gpu/drm/amd/display/dc/core/dc.c 					dc->hwss.set_flip_control_gsl(pipe_ctx,
dc               2129 drivers/gpu/drm/amd/display/dc/core/dc.c 			for (j = 0; j < dc->res_pool->pipe_count; j++) {
dc               2139 drivers/gpu/drm/amd/display/dc/core/dc.c 				if (dc->hwss.program_triplebuffer != NULL &&
dc               2140 drivers/gpu/drm/amd/display/dc/core/dc.c 					!dc->debug.disable_tri_buf) {
dc               2142 drivers/gpu/drm/amd/display/dc/core/dc.c 					dc->hwss.program_triplebuffer(
dc               2143 drivers/gpu/drm/amd/display/dc/core/dc.c 						dc, pipe_ctx, plane_state->triplebuffer_flips);
dc               2147 drivers/gpu/drm/amd/display/dc/core/dc.c 					dc->hwss.update_plane_addr(dc, pipe_ctx);
dc               2151 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
dc               2155 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
dc               2169 drivers/gpu/drm/amd/display/dc/core/dc.c void dc_commit_updates_for_stream(struct dc *dc,
dc               2179 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct dc_context *dc_ctx = dc->ctx;
dc               2183 drivers/gpu/drm/amd/display/dc/core/dc.c 	context = dc->current_state;
dc               2186 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc, srf_updates, surface_count, stream_update, stream_status);
dc               2189 drivers/gpu/drm/amd/display/dc/core/dc.c 		update_surface_trace(dc, srf_updates, surface_count);
dc               2195 drivers/gpu/drm/amd/display/dc/core/dc.c 		context = dc_create_state(dc);
dc               2203 drivers/gpu/drm/amd/display/dc/core/dc.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2205 drivers/gpu/drm/amd/display/dc/core/dc.c 			struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
dc               2219 drivers/gpu/drm/amd/display/dc/core/dc.c 			for (j = 0; j < dc->res_pool->pipe_count; j++) {
dc               2231 drivers/gpu/drm/amd/display/dc/core/dc.c 	copy_stream_update_to_stream(dc, context, stream, stream_update);
dc               2234 drivers/gpu/drm/amd/display/dc/core/dc.c 				dc,
dc               2242 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->current_state != context) {
dc               2244 drivers/gpu/drm/amd/display/dc/core/dc.c 		struct dc_state *old = dc->current_state;
dc               2246 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->current_state = context;
dc               2249 drivers/gpu/drm/amd/display/dc/core/dc.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2258 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc_post_update_surfaces_to_stream(dc);
dc               2264 drivers/gpu/drm/amd/display/dc/core/dc.c uint8_t dc_get_current_stream_count(struct dc *dc)
dc               2266 drivers/gpu/drm/amd/display/dc/core/dc.c 	return dc->current_state->stream_count;
dc               2269 drivers/gpu/drm/amd/display/dc/core/dc.c struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
dc               2271 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (i < dc->current_state->stream_count)
dc               2272 drivers/gpu/drm/amd/display/dc/core/dc.c 		return dc->current_state->streams[i];
dc               2277 drivers/gpu/drm/amd/display/dc/core/dc.c 		struct dc *dc,
dc               2281 drivers/gpu/drm/amd/display/dc/core/dc.c 	return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
dc               2287 drivers/gpu/drm/amd/display/dc/core/dc.c bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
dc               2290 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc == NULL)
dc               2293 drivers/gpu/drm/amd/display/dc/core/dc.c 	return dal_irq_service_set(dc->res_pool->irqs, src, enable);
dc               2296 drivers/gpu/drm/amd/display/dc/core/dc.c void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
dc               2298 drivers/gpu/drm/amd/display/dc/core/dc.c 	dal_irq_service_ack(dc->res_pool->irqs, src);
dc               2302 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct dc *dc,
dc               2310 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc_resource_state_construct(dc, dc->current_state);
dc               2312 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.init_hw(dc);
dc               2315 drivers/gpu/drm/amd/display/dc/core/dc.c 		if (dc->hwss.init_sys_ctx != NULL &&
dc               2316 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->vm_pa_config.valid) {
dc               2317 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
dc               2323 drivers/gpu/drm/amd/display/dc/core/dc.c 		ASSERT(dc->current_state->stream_count == 0);
dc               2336 drivers/gpu/drm/amd/display/dc/core/dc.c 		refcount = dc->current_state->refcount;
dc               2338 drivers/gpu/drm/amd/display/dc/core/dc.c 		memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
dc               2340 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc_resource_state_destruct(dc->current_state);
dc               2341 drivers/gpu/drm/amd/display/dc/core/dc.c 		memset(dc->current_state, 0,
dc               2342 drivers/gpu/drm/amd/display/dc/core/dc.c 				sizeof(*dc->current_state));
dc               2344 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->current_state->refcount = refcount;
dc               2345 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->current_state->bw_ctx.dml = *dml;
dc               2353 drivers/gpu/drm/amd/display/dc/core/dc.c void dc_resume(struct dc *dc)
dc               2358 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < dc->link_count; i++)
dc               2359 drivers/gpu/drm/amd/display/dc/core/dc.c 		core_link_resume(dc->links[i]);
dc               2362 drivers/gpu/drm/amd/display/dc/core/dc.c unsigned int dc_get_current_backlight_pwm(struct dc *dc)
dc               2364 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct abm *abm = dc->res_pool->abm;
dc               2372 drivers/gpu/drm/amd/display/dc/core/dc.c unsigned int dc_get_target_backlight_pwm(struct dc *dc)
dc               2374 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct abm *abm = dc->res_pool->abm;
dc               2382 drivers/gpu/drm/amd/display/dc/core/dc.c bool dc_is_dmcu_initialized(struct dc *dc)
dc               2384 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct dmcu *dmcu = dc->res_pool->dmcu;
dc               2392 drivers/gpu/drm/amd/display/dc/core/dc.c 		struct dc *dc,
dc               2397 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct dc_link *link = dc->links[link_index];
dc               2400 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->res_pool,
dc               2527 drivers/gpu/drm/amd/display/dc/core/dc.c enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
dc               2529 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->hwss.set_clock)
dc               2530 drivers/gpu/drm/amd/display/dc/core/dc.c 		return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
dc               2533 drivers/gpu/drm/amd/display/dc/core/dc.c void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
dc               2535 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->hwss.get_clock)
dc               2536 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.get_clock(dc, clock_type, clock_cfg);
dc                 44 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 		if (dc->debug.surface_trace) \
dc                 49 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	if (dc->debug.timing_trace) \
dc                 54 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	if (dc->debug.clock_trace) \
dc                 59 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 		struct dc *dc,
dc                 64 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc                179 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 		struct dc *dc,
dc                184 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc                300 drivers/gpu/drm/amd/display/dc/core/dc_debug.c void post_surface_trace(struct dc *dc)
dc                302 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc                309 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 		struct dc *dc,
dc                313 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	struct dc  *core_dc = dc;
dc                317 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc                347 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 		struct dc *dc,
dc                351 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc                226 drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c 	const struct dc *dc,
dc                224 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		link->dc->hwss.edp_power_control(link, true);
dc                225 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
dc                436 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		struct audio_support *aud_support = &link->dc->res_pool->audio_support;
dc                747 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct audio_support *aud_support = &link->dc->res_pool->audio_support;
dc               1217 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dc_bios *bios = init_params->dc->ctx->dc_bios;
dc               1226 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	link->dc = init_params->dc;
dc               1242 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	if (link->dc->res_pool->funcs->link_init)
dc               1243 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		link->dc->res_pool->funcs->link_init(link);
dc               1320 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	link->link_enc = link->dc->res_pool->funcs->link_enc_create(
dc               1488 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		link->dc->hwss.edp_power_control(link, true);
dc               1489 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
dc               1689 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
dc               2309 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct abm *abm = link->ctx->dc->res_pool->abm;
dc               2321 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dc  *core_dc = link->ctx->dc;
dc               2374 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dc  *core_dc = link->ctx->dc;
dc               2387 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dc  *core_dc = link->ctx->dc;
dc               2676 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
dc               2810 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
dc               2856 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
dc               2968 drivers/gpu/drm/amd/display/dc/core/dc_link.c void dc_link_set_drive_settings(struct dc *dc,
dc               2975 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	for (i = 0; i < dc->link_count; i++) {
dc               2976 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		if (dc->links[i] == link)
dc               2980 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	if (i >= dc->link_count)
dc               2983 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
dc               2986 drivers/gpu/drm/amd/display/dc/core/dc_link.c void dc_link_perform_link_training(struct dc *dc,
dc               2992 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	for (i = 0; i < dc->link_count; i++)
dc               2994 drivers/gpu/drm/amd/display/dc/core/dc_link.c 			dc->links[i],
dc               2999 drivers/gpu/drm/amd/display/dc/core/dc_link.c void dc_link_set_preferred_link_settings(struct dc *dc,
dc               3019 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		pipe = &dc->current_state->res_ctx.pipe_ctx[i];
dc               3043 drivers/gpu/drm/amd/display/dc/core/dc_link.c void dc_link_set_preferred_training_settings(struct dc *dc,
dc               3063 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
dc                360 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 		.speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
dc                566 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 			.speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
dc               1230 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		link->ctx->dc->debug_data.ltFailCount++;
dc               1262 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
dc               1557 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	if (link->dc->debug.skip_detection_link_training) {
dc               2205 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
dc               2211 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
dc               2998 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 			(link->dc->config.optimize_edp_link_rate ||
dc               3193 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
dc               3223 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		link->dc->hwss.unblank_stream(
dc               3463 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	if (link->dc->debug.disable_fec ||
dc               3499 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	if (link->dc->debug.disable_fec ||
dc                 72 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dc  *core_dc = link->ctx->dc;
dc                 76 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 			link->dc->current_state->res_ctx.pipe_ctx;
dc                 78 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 			link->dc->res_pool->dp_clock_source;
dc                177 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dc  *core_dc = link->ctx->dc;
dc                185 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		link->dc->hwss.edp_power_control(link, false);
dc                273 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 			&link->dc->current_state->res_ctx.pipe_ctx[0];
dc                293 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 			link->dc->hwss.disable_stream(&pipes[i]);
dc                294 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 			if ((&pipes[i])->stream_res.audio && !link->dc->debug.az_endpoint_mute_only)
dc                320 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 			link->dc->hwss.enable_stream(&pipes[i]);
dc                322 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 			link->dc->hwss.unblank_stream(&pipes[i],
dc                368 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
dc                385 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
dc                489 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
dc                126 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct resource_pool *dc_create_resource_pool(struct dc  *dc,
dc                135 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				init_data->num_virtual_links, dc);
dc                139 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				init_data->num_virtual_links, dc);
dc                143 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				init_data->num_virtual_links, dc);
dc                147 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				init_data->num_virtual_links, dc);
dc                151 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				init_data->num_virtual_links, dc,
dc                157 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				init_data->num_virtual_links, dc);
dc                162 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				init_data->num_virtual_links, dc);
dc                168 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res_pool = dcn10_create_resource_pool(init_data, dc);
dc                175 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res_pool = dcn20_create_resource_pool(init_data, dc);
dc                180 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res_pool = dcn21_create_resource_pool(init_data, dc);
dc                189 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (dc->ctx->dc_bios->fw_info_valid) {
dc                191 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
dc                209 drivers/gpu/drm/amd/display/dc/core/dc_resource.c void dc_destroy_resource_pool(struct dc  *dc)
dc                211 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (dc) {
dc                212 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (dc->res_pool)
dc                213 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			dc->res_pool->funcs->destroy(&dc->res_pool);
dc                215 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		kfree(dc->hwseq);
dc                248 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct dc  *dc,
dc                252 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct dc_context *ctx = dc->ctx;
dc                259 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		create_funcs->read_dce_straps(dc->ctx, &straps);
dc                297 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	dc->caps.dynamic_audio = false;
dc                299 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		dc->caps.dynamic_audio = true;
dc                312 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	dc->hwseq = create_funcs->create_hwseq(ctx);
dc                416 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (stream1->ctx->dc->caps.disable_dp_clk_share)
dc               1053 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	const struct dc  *dc,
dc               1231 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		const struct dc *dc,
dc               1237 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct resource_pool *pool = dc->res_pool;
dc               1309 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		const struct dc *dc,
dc               1316 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct resource_pool *pool = dc->res_pool;
dc               1381 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		const struct dc *dc,
dc               1406 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
dc               1413 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		const struct dc *dc,
dc               1431 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
dc               1438 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		const struct dc *dc,
dc               1453 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	return add_all_planes_for_stream(dc, stream, &set, 1, context);
dc               1685 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		struct dc *dc,
dc               1690 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc               1692 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
dc               1701 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
dc               1712 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			struct dc *dc,
dc               1717 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct dc_context *dc_ctx = dc->ctx;
dc               1732 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				dc->res_pool,
dc               1739 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			dc->res_pool,
dc               1744 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					  dc->res_pool,
dc               1747 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (dc->res_pool->funcs->remove_stream_from_ctx)
dc               1748 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
dc               1906 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		const struct dc  *dc,
dc               1910 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	const struct resource_pool *pool = dc->res_pool;
dc               1912 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct dc_context *dc_ctx = dc->ctx;
dc               1915 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct dc_bios *dcb = dc->ctx->dc_bios;
dc               1931 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (dc->config.allow_seamless_boot_optimization &&
dc               1933 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
dc               1958 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
dc               2011 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		const struct dc *dc,
dc               2014 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	dc_resource_state_copy_construct(dc->current_state, dst_ctx);
dc               2019 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		const struct dc *dc,
dc               2022 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	dst_ctx->clk_mgr = dc->clk_mgr;
dc               2035 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		struct dc *dc,
dc               2045 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (dc->res_pool->funcs->validate_global) {
dc               2046 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		result = dc->res_pool->funcs->validate_global(dc, new_ctx);
dc               2054 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		for (j = 0; j < dc->res_pool->pipe_count; j++) {
dc               2060 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			if (dc->res_pool->funcs->get_default_swizzle_mode &&
dc               2063 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
dc               2077 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 						dc->res_pool,
dc               2080 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
dc               2083 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 						dc->res_pool,
dc               2089 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	result = resource_build_scaling_params_for_context(dc, new_ctx);
dc               2092 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
dc               2532 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		const struct dc  *dc,
dc               2537 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	const struct resource_pool *pool = dc->res_pool;
dc               2550 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (!dc->config.disable_disp_pll_sharing)
dc               2745 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
dc               2747 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct dc  *core_dc = dc;
dc               2773 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
dc               2778 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (dc->res_pool->funcs->validate_plane)
dc               2779 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
dc                 39 drivers/gpu/drm/amd/display/dc/core/dc_stream.c #define DC_LOGGER dc->ctx->logger
dc                 52 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		if (stream->ctx->dc->caps.dual_link_dvi &&
dc                234 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	struct dc *dc = stream->ctx->dc;
dc                235 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	return dc_stream_get_status_from_state(dc->current_state, stream);
dc                238 drivers/gpu/drm/amd/display/dc/core/dc_stream.c static void delay_cursor_until_vupdate(struct pipe_ctx *pipe_ctx, struct dc *dc)
dc                250 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		if (!dc_stream_get_crtc_position(dc, &stream, 1, &vpos, &nvpos))
dc                275 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	struct dc  *core_dc;
dc                293 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	core_dc = stream->ctx->dc;
dc                326 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	struct dc  *core_dc;
dc                340 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	core_dc = stream->ctx->dc;
dc                371 drivers/gpu/drm/amd/display/dc/core/dc_stream.c bool dc_stream_add_writeback(struct dc *dc,
dc                396 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dc                414 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
dc                420 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	if (dc->hwss.enable_writeback) {
dc                422 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dc                426 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			dc->hwss.update_writeback(dc, stream_status, wb_info, dc->current_state);
dc                429 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			dc->hwss.enable_writeback(dc, stream_status, wb_info, dc->current_state);
dc                436 drivers/gpu/drm/amd/display/dc/core/dc_stream.c bool dc_stream_remove_writeback(struct dc *dc,
dc                472 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
dc                478 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	if (dc->hwss.disable_writeback)
dc                479 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		dc->hwss.disable_writeback(dc, dwb_pipe_inst);
dc                488 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	struct dc  *core_dc = stream->ctx->dc;
dc                509 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	struct dc  *dc;
dc                517 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	dc = stream->ctx->dc;
dc                518 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	res_ctx = &dc->current_state->res_ctx;
dc                526 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		if (dc->hwss.send_immediate_sdp_message != NULL)
dc                527 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			dc->hwss.send_immediate_sdp_message(pipe_ctx,
dc                547 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	struct dc  *core_dc = stream->ctx->dc;
dc                571 drivers/gpu/drm/amd/display/dc/core/dc_stream.c bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
dc                577 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	if (!dc->hwss.dmdata_status_done)
dc                581 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		pipe = &dc->current_state->res_ctx.pipe_ctx[i];
dc                589 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	status = dc->hwss.dmdata_status_done(pipe);
dc                593 drivers/gpu/drm/amd/display/dc/core/dc_stream.c bool dc_stream_set_dynamic_metadata(struct dc *dc,
dc                606 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	if (!dc->hwss.program_dmdata_engine)
dc                610 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
dc                624 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	dc->hwss.program_dmdata_engine(pipe_ctx);
dc                635 drivers/gpu/drm/amd/display/dc/core/dc_stream.c void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
dc                113 drivers/gpu/drm/amd/display/dc/core/dc_surface.c struct dc_plane_state *dc_create_plane_state(struct dc *dc)
dc                115 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	struct dc *core_dc = dc;
dc                144 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	struct dc  *core_dc;
dc                149 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		!plane_state->ctx->dc) {
dc                155 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	core_dc = plane_state->ctx->dc;
dc                 37 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config)
dc                 42 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c 	if (dc->hwss.init_sys_ctx) {
dc                 43 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c 		num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config);
dc                 48 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c 		memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config));
dc                 49 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c 		dc->vm_pa_config.valid = true;
dc                 55 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid)
dc                 57 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c 	dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid);
dc                 60 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c int dc_get_vmid_use_vector(struct dc *dc)
dc                 65 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c 	for (i = 0; i < dc->vm_helper->num_vmid; i++)
dc                 66 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c 		in_use |= dc->vm_helper->hubp_vmid_usage[i].vmid_usage[0]
dc                 67 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c 			| dc->vm_helper->hubp_vmid_usage[i].vmid_usage[1];
dc                198 drivers/gpu/drm/amd/display/dc/dc.h struct dc;
dc                204 drivers/gpu/drm/amd/display/dc/dc.h 	bool (*get_dcc_compression_cap)(const struct dc *dc,
dc                293 drivers/gpu/drm/amd/display/dc/dc.h 		unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
dc                294 drivers/gpu/drm/amd/display/dc/dc.h 				dm_get_timestamp(dc->ctx) : 0
dc                297 drivers/gpu/drm/amd/display/dc/dc.h 		if (dc->debug.bw_val_profile.enable) \
dc                298 drivers/gpu/drm/amd/display/dc/dc.h 			dc->debug.bw_val_profile.total_count++
dc                301 drivers/gpu/drm/amd/display/dc/dc.h 		if (dc->debug.bw_val_profile.enable) { \
dc                303 drivers/gpu/drm/amd/display/dc/dc.h 				voltage_level_tick = dm_get_timestamp(dc->ctx); \
dc                304 drivers/gpu/drm/amd/display/dc/dc.h 			dc->debug.bw_val_profile.skip_ ## status ## _count++; \
dc                308 drivers/gpu/drm/amd/display/dc/dc.h 		if (dc->debug.bw_val_profile.enable) \
dc                309 drivers/gpu/drm/amd/display/dc/dc.h 			voltage_level_tick = dm_get_timestamp(dc->ctx)
dc                312 drivers/gpu/drm/amd/display/dc/dc.h 		if (dc->debug.bw_val_profile.enable) \
dc                313 drivers/gpu/drm/amd/display/dc/dc.h 			watermark_tick = dm_get_timestamp(dc->ctx)
dc                316 drivers/gpu/drm/amd/display/dc/dc.h 		if (dc->debug.bw_val_profile.enable) { \
dc                317 drivers/gpu/drm/amd/display/dc/dc.h 			end_tick = dm_get_timestamp(dc->ctx); \
dc                318 drivers/gpu/drm/amd/display/dc/dc.h 			dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
dc                319 drivers/gpu/drm/amd/display/dc/dc.h 			dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
dc                321 drivers/gpu/drm/amd/display/dc/dc.h 				dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
dc                322 drivers/gpu/drm/amd/display/dc/dc.h 				dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
dc                559 drivers/gpu/drm/amd/display/dc/dc.h struct dc *dc_create(const struct dc_init_data *init_params);
dc                560 drivers/gpu/drm/amd/display/dc/dc.h int dc_get_vmid_use_vector(struct dc *dc);
dc                562 drivers/gpu/drm/amd/display/dc/dc.h void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
dc                564 drivers/gpu/drm/amd/display/dc/dc.h int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
dc                566 drivers/gpu/drm/amd/display/dc/dc.h void dc_init_callbacks(struct dc *dc,
dc                568 drivers/gpu/drm/amd/display/dc/dc.h void dc_destroy(struct dc **dc);
dc                823 drivers/gpu/drm/amd/display/dc/dc.h struct dc_plane_state *dc_create_plane_state(struct dc *dc);
dc                856 drivers/gpu/drm/amd/display/dc/dc.h 		struct dc *dc);
dc                869 drivers/gpu/drm/amd/display/dc/dc.h bool dc_validate_seamless_boot_timing(const struct dc *dc,
dc                873 drivers/gpu/drm/amd/display/dc/dc.h enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
dc                885 drivers/gpu/drm/amd/display/dc/dc.h 		struct dc *dc,
dc                891 drivers/gpu/drm/amd/display/dc/dc.h 		const struct dc *dc,
dc                899 drivers/gpu/drm/amd/display/dc/dc.h 		const struct dc *dc,
dc                913 drivers/gpu/drm/amd/display/dc/dc.h bool dc_commit_state(struct dc *dc, struct dc_state *context);
dc                916 drivers/gpu/drm/amd/display/dc/dc.h struct dc_state *dc_create_state(struct dc *dc);
dc               1045 drivers/gpu/drm/amd/display/dc/dc.h 		struct dc *dc,
dc               1048 drivers/gpu/drm/amd/display/dc/dc.h bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
dc               1049 drivers/gpu/drm/amd/display/dc/dc.h void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
dc               1051 drivers/gpu/drm/amd/display/dc/dc.h 		struct dc *dc, uint32_t link_index);
dc               1058 drivers/gpu/drm/amd/display/dc/dc.h 		struct dc *dc,
dc               1060 drivers/gpu/drm/amd/display/dc/dc.h void dc_resume(struct dc *dc);
dc               1061 drivers/gpu/drm/amd/display/dc/dc.h unsigned int dc_get_current_backlight_pwm(struct dc *dc);
dc               1062 drivers/gpu/drm/amd/display/dc/dc.h unsigned int dc_get_target_backlight_pwm(struct dc *dc);
dc               1064 drivers/gpu/drm/amd/display/dc/dc.h bool dc_is_dmcu_initialized(struct dc *dc);
dc               1066 drivers/gpu/drm/amd/display/dc/dc.h enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
dc               1067 drivers/gpu/drm/amd/display/dc/dc.h void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
dc                 48 drivers/gpu/drm/amd/display/dc/dc_dsc.h 		const struct dc *dc,
dc                 56 drivers/gpu/drm/amd/display/dc/dc_dsc.h 		const struct dc *dc,
dc                116 drivers/gpu/drm/amd/display/dc/dc_link.h 	const struct dc *dc;
dc                156 drivers/gpu/drm/amd/display/dc/dc_link.h static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
dc                158 drivers/gpu/drm/amd/display/dc/dc_link.h 	return dc->links[link_index];
dc                261 drivers/gpu/drm/amd/display/dc/dc_link.h void dc_link_set_drive_settings(struct dc *dc,
dc                264 drivers/gpu/drm/amd/display/dc/dc_link.h void dc_link_perform_link_training(struct dc *dc,
dc                267 drivers/gpu/drm/amd/display/dc/dc_link.h void dc_link_set_preferred_link_settings(struct dc *dc,
dc                270 drivers/gpu/drm/amd/display/dc/dc_link.h void dc_link_set_preferred_training_settings(struct dc *dc,
dc                290 drivers/gpu/drm/amd/display/dc/dc_link.h 		struct dc *dc,
dc                265 drivers/gpu/drm/amd/display/dc/dc_stream.h void dc_commit_updates_for_stream(struct dc *dc,
dc                274 drivers/gpu/drm/amd/display/dc/dc_stream.h void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
dc                276 drivers/gpu/drm/amd/display/dc/dc_stream.h uint8_t dc_get_current_stream_count(struct dc *dc);
dc                277 drivers/gpu/drm/amd/display/dc/dc_stream.h struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
dc                302 drivers/gpu/drm/amd/display/dc/dc_stream.h 			struct dc *dc,
dc                307 drivers/gpu/drm/amd/display/dc/dc_stream.h 		struct dc *dc,
dc                313 drivers/gpu/drm/amd/display/dc/dc_stream.h 		const struct dc *dc,
dc                319 drivers/gpu/drm/amd/display/dc/dc_stream.h 		const struct dc *dc,
dc                325 drivers/gpu/drm/amd/display/dc/dc_stream.h 		const struct dc *dc,
dc                330 drivers/gpu/drm/amd/display/dc/dc_stream.h 		const struct dc *dc,
dc                337 drivers/gpu/drm/amd/display/dc/dc_stream.h bool dc_stream_add_writeback(struct dc *dc,
dc                340 drivers/gpu/drm/amd/display/dc/dc_stream.h bool dc_stream_remove_writeback(struct dc *dc,
dc                343 drivers/gpu/drm/amd/display/dc/dc_stream.h bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);
dc                344 drivers/gpu/drm/amd/display/dc/dc_stream.h bool dc_stream_set_dynamic_metadata(struct dc *dc,
dc                349 drivers/gpu/drm/amd/display/dc/dc_stream.h enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
dc                364 drivers/gpu/drm/amd/display/dc/dc_stream.h 	struct dc *dc,
dc                371 drivers/gpu/drm/amd/display/dc/dc_stream.h 		struct dc *dc,
dc                408 drivers/gpu/drm/amd/display/dc/dc_stream.h bool dc_stream_adjust_vmin_vmax(struct dc *dc,
dc                412 drivers/gpu/drm/amd/display/dc/dc_stream.h bool dc_stream_get_crtc_position(struct dc *dc,
dc                418 drivers/gpu/drm/amd/display/dc/dc_stream.h bool dc_stream_configure_crc(struct dc *dc,
dc                423 drivers/gpu/drm/amd/display/dc/dc_stream.h bool dc_stream_get_crc(struct dc *dc,
dc                429 drivers/gpu/drm/amd/display/dc/dc_stream.h void dc_stream_set_static_screen_events(struct dc *dc,
dc                437 drivers/gpu/drm/amd/display/dc/dc_stream.h bool dc_stream_set_gamut_remap(struct dc *dc,
dc                440 drivers/gpu/drm/amd/display/dc/dc_stream.h bool dc_stream_program_csc_matrix(struct dc *dc,
dc                443 drivers/gpu/drm/amd/display/dc/dc_stream.h bool dc_stream_get_crtc_position(struct dc *dc,
dc                 84 drivers/gpu/drm/amd/display/dc/dc_types.h 	struct dc *dc;
dc                466 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
dc                254 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
dc                293 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dc *core_dc = clk_mgr->ctx->dc;
dc                343 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
dc                569 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		const struct dc *dc,
dc                578 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	if (dc->sclk_lvls.num_levels == 0)
dc                581 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
dc                582 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
dc                583 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			return dc->sclk_lvls.clocks_in_khz[i];
dc                591 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
dc                595 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dc *dc,
dc                604 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
dc                605 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
dc                609 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dc *dc,
dc                629 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			dc,
dc                650 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz;
dc                664 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
dc                665 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
dc                692 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	dce_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
dc                719 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
dc                746 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
dc                784 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
dc                373 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	const struct dc_config *config = &dmcu->ctx->dc->config;
dc                 47 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c void dce_pipe_control_lock(struct dc *dc,
dc                 53 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 	struct dce_hwseq *hws = dc->hwseq;
dc                825 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h void dce_pipe_control_lock(struct dc *dc,
dc                724 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 	if (ctx->dc->debug.scl_reset_length10)
dc                266 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	if (ctx->dc->caps.psp_setup_panel_mode)
dc                658 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	if (enc110->base.ctx->dc->debug.hdmi20_disable &&
dc                777 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	if (enc110->base.ctx->dc->debug.hdmi20_disable) {
dc                272 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
dc                297 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
dc                330 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
dc                158 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
dc                 74 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 	struct dc *dc,
dc                 81 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 	struct dc_context *ctx = dc->ctx;
dc                110 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 		struct dc *dc,
dc                113 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 	dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
dc                115 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 	dc->clk_mgr->funcs->update_clocks(
dc                116 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 			dc->clk_mgr,
dc                122 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 		struct dc *dc,
dc                125 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 	dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
dc                127 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 	dc->clk_mgr->funcs->update_clocks(
dc                128 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 			dc->clk_mgr,
dc                135 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c void dce100_hw_sequencer_construct(struct dc *dc)
dc                137 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 	dce110_hw_sequencer_construct(dc);
dc                139 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
dc                140 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 	dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
dc                141 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 	dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
dc                 31 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h struct dc;
dc                 34 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h void dce100_hw_sequencer_construct(struct dc *dc);
dc                 37 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h 		struct dc *dc,
dc                 41 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h 		struct dc *dc,
dc                 44 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
dc                749 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		const struct dc  *dc,
dc                766 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	struct dc  *dc,
dc                773 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc                811 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		struct dc  *dc,
dc                821 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		struct dc *dc,
dc                827 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
dc                830 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		result = resource_map_clock_resources(dc, new_ctx, dc_stream);
dc                833 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		result = build_mapped_resource(dc, new_ctx, dc_stream);
dc                909 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	struct dc  *dc,
dc                913 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	struct dc_context *ctx = dc->ctx;
dc                983 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		init_data.ctx = dc->ctx;
dc                995 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	dc->caps.max_downscale_ratio = 200;
dc                996 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	dc->caps.i2c_speed_in_khz = 40;
dc                997 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	dc->caps.max_cursor_size = 128;
dc                998 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	dc->caps.dual_link_dvi = true;
dc                999 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	dc->caps.disable_dp_clk_share = true;
dc               1063 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
dc               1065 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	for (i = 0; i < dc->caps.max_planes; ++i)
dc               1066 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		dc->caps.planes[i] = plane_cap;
dc               1068 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	if (!resource_construct(num_virtual_links, dc, &pool->base,
dc               1073 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	dce100_hw_sequencer_construct(dc);
dc               1084 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	struct dc  *dc)
dc               1092 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	if (construct(num_virtual_links, dc, pool))
dc                 34 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h struct dc;
dc                 40 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h 	struct dc *dc);
dc                 45 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h 		struct dc *dc,
dc                193 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc *dc,
dc                200 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc_context *ctx = dc->ctx;
dc                201 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
dc                670 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	link->dc->hwss.update_info_frame(pipe_ctx);
dc                807 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dce_hwseq *hwseq = ctx->dc->hwseq;
dc                889 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dce_hwseq *hws = ctx->dc->hwseq;
dc                946 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc *core_dc;
dc                954 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	core_dc = pipe_ctx->stream->ctx->dc;
dc                986 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc *dc;
dc                993 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dc = pipe_ctx->stream->ctx->dc;
dc                994 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	clk_mgr = dc->clk_mgr;
dc               1004 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		if (dc->res_pool->pp_smu)
dc               1005 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pp_smu = dc->res_pool->pp_smu;
dc               1030 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc *dc = pipe_ctx->stream->ctx->dc;
dc               1043 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dc->hwss.disable_audio_stream(pipe_ctx);
dc               1067 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		link->dc->hwss.edp_backlight_control(link, true);
dc               1077 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		link->dc->hwss.edp_backlight_control(link, false);
dc               1228 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void program_scaler(const struct dc *dc,
dc               1239 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
dc               1242 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		color_space_to_black_color(dc,
dc               1272 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc)
dc               1275 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
dc               1282 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		color_space_to_black_color(dc,
dc               1327 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc)
dc               1336 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->hwss.disable_stream_gating) {
dc               1337 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->hwss.disable_stream_gating(dc, pipe_ctx);
dc               1367 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
dc               1369 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->hwss.setup_vupdate_interrupt)
dc               1370 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->hwss.setup_vupdate_interrupt(pipe_ctx);
dc               1428 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void power_down_encoders(struct dc *dc)
dc               1437 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
dc               1438 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->res_pool->stream_enc[i]->funcs->dp_blank(
dc               1439 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 					dc->res_pool->stream_enc[i]);
dc               1442 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->link_count; i++) {
dc               1443 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
dc               1447 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
dc               1448 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dp_receiver_power_ctrl(dc->links[i], false);
dc               1453 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->links[i]->link_enc->funcs->disable_output(
dc               1454 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dc->links[i]->link_enc, signal);
dc               1458 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void power_down_controllers(struct dc *dc)
dc               1462 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
dc               1463 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->res_pool->timing_generators[i]->funcs->disable_crtc(
dc               1464 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dc->res_pool->timing_generators[i]);
dc               1468 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void power_down_clock_sources(struct dc *dc)
dc               1472 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
dc               1473 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->res_pool->dp_clock_source) == false)
dc               1476 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->clk_src_count; i++) {
dc               1477 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
dc               1478 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dc->res_pool->clock_sources[i]) == false)
dc               1483 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void power_down_all_hw_blocks(struct dc *dc)
dc               1485 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	power_down_encoders(dc);
dc               1487 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	power_down_controllers(dc);
dc               1489 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	power_down_clock_sources(dc);
dc               1491 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->fbc_compressor)
dc               1492 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
dc               1496 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc)
dc               1500 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc_context *ctx = dc->ctx;
dc               1502 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
dc               1503 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		tg = dc->res_pool->timing_generators[i];
dc               1508 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               1514 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
dc               1515 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->hwss.disable_plane(dc,
dc               1516 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			&dc->current_state->res_ctx.pipe_ctx[i]);
dc               1532 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static struct dc_link *get_edp_link(struct dc *dc)
dc               1537 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->link_count; i++) {
dc               1538 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
dc               1539 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			return dc->links[i];
dc               1545 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc,
dc               1552 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->link_count; i++) {
dc               1553 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		if (dc->links[i]->local_sink &&
dc               1554 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
dc               1555 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			link = dc->links[i];
dc               1570 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
dc               1573 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc_link *edp_link_with_sink = get_edp_link_with_sink(dc, context);
dc               1574 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc_link *edp_link = get_edp_link(dc);
dc               1580 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->hwss.init_pipes)
dc               1581 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->hwss.init_pipes(dc, context);
dc               1586 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (edp_link && dc->ctx->dce_version != DCE_VERSION_8_0 &&
dc               1587 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		    dc->ctx->dce_version != DCE_VERSION_8_1 &&
dc               1588 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		    dc->ctx->dce_version != DCE_VERSION_8_3) {
dc               1618 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			dc->hwss.edp_backlight_control(edp_link_with_sink, false);
dc               1621 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		power_down_all_hw_blocks(dc);
dc               1622 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		disable_vga_and_power_gate_all_controllers(dc);
dc               1624 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			dc->hwss.edp_power_control(edp_link_with_sink, false);
dc               1626 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
dc               1647 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	const struct dc *dc,
dc               1651 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
dc               1661 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			dc->bw_vbios->blackout_duration, pipe_ctx->stream);
dc               1776 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
dc               1778 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		if (dc->fbc_compressor)
dc               1790 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static bool should_enable_fbc(struct dc *dc,
dc               1797 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
dc               1800 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	ASSERT(dc->fbc_compressor);
dc               1803 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (!dc->ctx->fbc_gpu_addr)
dc               1810 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               1826 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (i == dc->res_pool->pipe_count)
dc               1855 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc,
dc               1860 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (should_enable_fbc(dc, context, &pipe_idx)) {
dc               1863 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct compressor *compr = dc->fbc_compressor;
dc               1869 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
dc               1879 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc,
dc               1888 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			&dc->current_state->res_ctx.pipe_ctx[i];
dc               1917 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 					if (dc->caps.dynamic_audio == true) {
dc               1920 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 						update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
dc               1934 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 					pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
dc               1937 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 										dc->res_pool,
dc               1941 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			dc->hwss.disable_plane(dc, pipe_ctx_old);
dc               1949 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc,
dc               1973 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2000 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (i == dc->res_pool->pipe_count) {
dc               2001 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2030 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc,
dc               2033 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc_bios *dcb = dc->ctx->dc_bios;
dc               2039 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dc->hwss.reset_hw_ctx_wrap(dc, context);
dc               2049 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2051 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 					&dc->current_state->res_ctx.pipe_ctx[i];
dc               2059 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dce_crtc_switch_to_clk_src(dc->hwseq,
dc               2064 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->hwss.enable_display_power_gating(
dc               2065 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dc, i, dc->ctx->dc_bios,
dc               2069 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->fbc_compressor)
dc               2070 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
dc               2072 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dce110_setup_audio_dto(dc, context);
dc               2074 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2076 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 					&dc->current_state->res_ctx.pipe_ctx[i];
dc               2096 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dc);
dc               2102 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->fbc_compressor)
dc               2103 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		enable_fbc(dc, dc->current_state);
dc               2154 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void program_surface_visibility(const struct dc *dc,
dc               2177 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
dc               2200 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void update_plane_addr(const struct dc *dc,
dc               2238 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c void dce110_power_down(struct dc *dc)
dc               2240 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	power_down_all_hw_blocks(dc);
dc               2241 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	disable_vga_and_power_gate_all_controllers(dc);
dc               2283 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc,
dc               2288 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc_context *dc_ctx = dc->ctx;
dc               2329 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc,
dc               2333 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc_context *dc_ctx = dc->ctx;
dc               2361 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void init_pipes(struct dc *dc, struct dc_state *context)
dc               2366 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void init_hw(struct dc *dc)
dc               2374 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	bp = dc->ctx->dc_bios;
dc               2375 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2376 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		xfm = dc->res_pool->transforms[i];
dc               2379 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->hwss.enable_display_power_gating(
dc               2380 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dc, i, bp,
dc               2382 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->hwss.enable_display_power_gating(
dc               2383 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dc, i, bp,
dc               2385 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->hwss.enable_display_pipe_clock_gating(
dc               2386 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			dc->ctx,
dc               2390 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dce_clock_gating_power_up(dc->hwseq, false);
dc               2393 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->link_count; i++) {
dc               2398 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc_link *link = dc->links[i];
dc               2403 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2404 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
dc               2414 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->audio_count; i++) {
dc               2415 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct audio *audio = dc->res_pool->audios[i];
dc               2419 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	abm = dc->res_pool->abm;
dc               2425 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dmcu = dc->res_pool->dmcu;
dc               2429 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->fbc_compressor)
dc               2430 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
dc               2436 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc,
dc               2439 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct clk_mgr *dccg = dc->clk_mgr;
dc               2441 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
dc               2450 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc,
dc               2453 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct clk_mgr *dccg = dc->clk_mgr;
dc               2455 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dce110_set_displaymarks(dc, context);
dc               2464 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc, struct pipe_ctx *pipe_ctx)
dc               2475 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->current_state)
dc               2476 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
dc               2481 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dce_enable_fe_clock(dc->hwseq, mi->inst, true);
dc               2509 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	program_scaler(dc, pipe_ctx);
dc               2522 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->config.gpu_vm_support)
dc               2533 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
dc               2536 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
dc               2577 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc,
dc               2587 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->fbc_compressor)
dc               2588 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
dc               2590 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2592 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
dc               2597 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
dc               2601 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2615 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dce110_program_front_end_for_pipe(dc, pipe_ctx);
dc               2617 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->hwss.update_plane_addr(dc, pipe_ctx);
dc               2619 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		program_surface_visibility(dc, pipe_ctx);
dc               2623 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2625 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
dc               2630 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
dc               2633 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->fbc_compressor)
dc               2634 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		enable_fbc(dc, context);
dc               2637 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
dc               2643 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
dc               2646 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dc->hwss.enable_display_power_gating(
dc               2647 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
dc               2649 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
dc               2650 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dc->res_pool->transforms[fe_idx]);
dc               2654 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct dc *dc,
dc               2661 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static void program_output_csc(struct dc *dc,
dc               2690 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
dc               2776 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c void dce110_hw_sequencer_construct(struct dc *dc)
dc               2778 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dc->hwss = dce110_funcs;
dc                 32 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h struct dc;
dc                 36 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h void dce110_hw_sequencer_construct(struct dc *dc);
dc                 39 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h 		struct dc *dc,
dc                 58 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);
dc                 60 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h void dce110_power_down(struct dc *dc);
dc                 67 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h 		struct dc *dc,
dc                 71 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h 		struct dc *dc,
dc                757 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c 	if (ctx->dc->debug.disable_stutter) {
dc                 58 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		dc->ctx->logger
dc                868 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		const struct dc *dc,
dc                878 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			dc->res_pool->underlay_pipe_index))
dc                891 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	struct dc *dc,
dc                902 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			dc->ctx,
dc                903 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			dc->bw_dceip,
dc                904 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			dc->bw_vbios,
dc                906 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			dc->res_pool->pipe_count,
dc                917 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	if (memcmp(&dc->current_state->bw_ctx.bw.dce,
dc               1020 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		struct dc *dc,
dc               1030 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		struct dc *dc,
dc               1036 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
dc               1039 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		result = resource_map_clock_resources(dc, new_ctx, dc_stream);
dc               1043 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		result = build_mapped_resource(dc, new_ctx, dc_stream);
dc               1053 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	struct dc *dc = stream->ctx->dc;
dc               1070 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {
dc               1072 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		struct dc_bios *dcb = dc->ctx->dc_bios;
dc               1074 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		dc->hwss.enable_display_power_gating(
dc               1075 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 				dc,
dc               1104 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		color_space_to_black_color(dc,
dc               1199 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	ctx->dc->caps.max_slave_planes = 1;
dc               1200 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	ctx->dc->caps.max_slave_planes = 1;
dc               1205 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c static void bw_calcs_data_update_from_pplib(struct dc *dc)
dc               1211 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			dc->ctx,
dc               1215 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
dc               1217 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
dc               1219 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
dc               1221 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
dc               1223 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
dc               1225 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
dc               1227 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
dc               1229 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
dc               1231 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->sclk_lvls = clks;
dc               1235 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			dc->ctx,
dc               1238 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(
dc               1240 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->mid_voltage_max_dispclk  = bw_frc_to_fixed(
dc               1242 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->low_voltage_max_dispclk  = bw_frc_to_fixed(
dc               1247 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			dc->ctx,
dc               1251 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
dc               1253 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
dc               1256 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
dc               1272 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	struct dc *dc,
dc               1277 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	struct dc_context *ctx = dc->ctx;
dc               1292 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->caps.max_downscale_ratio = 150;
dc               1293 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->caps.i2c_speed_in_khz = 100;
dc               1294 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->caps.max_cursor_size = 128;
dc               1295 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->caps.is_apu = true;
dc               1355 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		init_data.ctx = dc->ctx;
dc               1421 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	if (dc->config.fbc_support)
dc               1422 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		dc->fbc_compressor = dce110_compressor_create(ctx);
dc               1427 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	if (!resource_construct(num_virtual_links, dc, &pool->base,
dc               1432 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dce110_hw_sequencer_construct(dc);
dc               1434 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
dc               1437 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		dc->caps.planes[i] = plane_cap;
dc               1439 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap;
dc               1441 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
dc               1443 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	bw_calcs_data_update_from_pplib(dc);
dc               1454 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	struct dc *dc,
dc               1463 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	if (construct(num_virtual_links, dc, pool, asic_id))
dc                 31 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h struct dc;
dc                 45 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h 	struct dc *dc,
dc                240 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c 	if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
dc                114 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c 	struct dc *dc,
dc                121 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c 	struct dc_context *ctx = dc->ctx;
dc                155 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c void dce112_hw_sequencer_construct(struct dc *dc)
dc                160 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c 	dce110_hw_sequencer_construct(dc);
dc                161 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c 	dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
dc                 31 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h struct dc;
dc                 33 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h void dce112_hw_sequencer_construct(struct dc *dc);
dc                 62 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->ctx->logger
dc                796 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		const struct dc *dc,
dc                813 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	struct dc *dc,
dc                824 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 			dc->ctx,
dc                825 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 			dc->bw_dceip,
dc                826 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 			dc->bw_vbios,
dc                828 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 			dc->res_pool->pipe_count,
dc                837 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	if (memcmp(&dc->current_state->bw_ctx.bw.dce,
dc                885 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		const struct dc *dc,
dc                900 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 				dc->res_pool->dp_clock_source;
dc                903 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 			&context->res_ctx, dc->res_pool,
dc                911 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->res_pool,
dc                938 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		struct dc *dc,
dc                944 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
dc                947 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
dc                951 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		result = build_mapped_resource(dc, new_ctx, dc_stream);
dc                957 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		struct dc *dc,
dc                985 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c static void bw_calcs_data_update_from_pplib(struct dc *dc)
dc                993 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
dc               1000 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 			dc->ctx,
dc               1006 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 				dc->ctx,
dc               1010 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->bw_vbios->high_sclk = bw_frc_to_fixed(
dc               1012 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
dc               1014 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
dc               1016 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
dc               1018 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
dc               1020 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
dc               1022 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
dc               1024 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
dc               1029 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 				dc->ctx,
dc               1033 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->bw_vbios->low_yclk = bw_frc_to_fixed(
dc               1035 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
dc               1038 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->bw_vbios->high_yclk = bw_frc_to_fixed(
dc               1046 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
dc               1048 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
dc               1050 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
dc               1052 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
dc               1054 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
dc               1056 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
dc               1058 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
dc               1060 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
dc               1065 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 			dc->ctx,
dc               1074 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
dc               1076 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
dc               1079 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
dc               1130 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
dc               1145 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	struct dc *dc,
dc               1149 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	struct dc_context *ctx = dc->ctx;
dc               1162 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->caps.max_downscale_ratio = 200;
dc               1163 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->caps.i2c_speed_in_khz = 100;
dc               1164 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->caps.max_cursor_size = 128;
dc               1165 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->caps.dual_link_dvi = true;
dc               1239 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		init_data.ctx = dc->ctx;
dc               1310 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	if (!resource_construct(num_virtual_links, dc, &pool->base,
dc               1314 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
dc               1316 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	for (i = 0; i < dc->caps.max_planes; ++i)
dc               1317 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->caps.planes[i] = plane_cap;
dc               1320 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dce112_hw_sequencer_construct(dc);
dc               1322 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
dc               1324 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	bw_calcs_data_update_from_pplib(dc);
dc               1335 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	struct dc *dc)
dc               1343 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	if (construct(num_virtual_links, dc, pool))
dc                 31 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h struct dc;
dc                 36 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h 	struct dc *dc);
dc                 39 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h 		struct dc *dc,
dc                 46 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h 	struct dc *dc,
dc                 51 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h 		struct dc *dc,
dc                151 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 	struct dc *dc,
dc                160 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 	struct dc_context *ctx = dc->ctx;
dc                262 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c void dce120_hw_sequencer_construct(struct dc *dc)
dc                267 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 	dce110_hw_sequencer_construct(dc);
dc                268 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 	dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;
dc                269 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 	dc->hwss.update_dchub = dce120_update_dchub;
dc                 31 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h struct dc;
dc                 34 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h void dce120_hw_sequencer_construct(struct dc *dc);
dc                515 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c static bool dce120_hw_sequencer_create(struct dc *dc)
dc                520 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dce120_hw_sequencer_construct(dc);
dc                843 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c static void bw_calcs_data_update_from_pplib(struct dc *dc)
dc                856 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 				dc->ctx,
dc                870 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
dc                872 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
dc                874 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
dc                876 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
dc                878 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
dc                880 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
dc                882 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
dc                884 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
dc                889 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 			dc->ctx,
dc                911 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	if (dc->bw_vbios->memory_type == bw_def_hbm)
dc                914 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
dc                916 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
dc                919 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
dc                970 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
dc                983 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	struct dc *dc,
dc                988 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	struct dc_context *ctx = dc->ctx;
dc               1004 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->caps.max_downscale_ratio = 200;
dc               1005 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->caps.i2c_speed_in_khz = 100;
dc               1006 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->caps.max_cursor_size = 128;
dc               1007 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->caps.dual_link_dvi = true;
dc               1008 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->caps.psp_setup_panel_mode = true;
dc               1010 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->debug = debug_defaults;
dc               1076 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	irq_init_data.ctx = dc->ctx;
dc               1171 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs))
dc               1175 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	if (!dce120_hw_sequencer_create(dc))
dc               1178 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
dc               1180 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	for (i = 0; i < dc->caps.max_planes; ++i)
dc               1181 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 		dc->caps.planes[i] = plane_cap;
dc               1183 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
dc               1185 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	bw_calcs_data_update_from_pplib(dc);
dc               1201 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	struct dc *dc)
dc               1209 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	if (construct(num_virtual_links, dc, pool))
dc                 31 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h struct dc;
dc                 36 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h 	struct dc *dc);
dc                 73 drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c void dce80_hw_sequencer_construct(struct dc *dc)
dc                 75 drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c 	dce110_hw_sequencer_construct(dc);
dc                 77 drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c 	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
dc                 78 drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c 	dc->hwss.pipe_control_lock = dce_pipe_control_lock;
dc                 79 drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c 	dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
dc                 80 drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c 	dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
dc                 31 drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h struct dc;
dc                 33 drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h void dce80_hw_sequencer_construct(struct dc *dc);
dc                800 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	struct dc *dc,
dc                807 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc                845 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		struct dc *dc,
dc                875 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	struct dc *dc,
dc                879 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	struct dc_context *ctx = dc->ctx;
dc                894 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.max_downscale_ratio = 200;
dc                895 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.i2c_speed_in_khz = 40;
dc                896 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.max_cursor_size = 128;
dc                897 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.dual_link_dvi = true;
dc                964 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		init_data.ctx = dc->ctx;
dc               1032 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
dc               1034 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < dc->caps.max_planes; ++i)
dc               1035 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		dc->caps.planes[i] = plane_cap;
dc               1037 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.disable_dp_clk_share = true;
dc               1039 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	if (!resource_construct(num_virtual_links, dc, &pool->base,
dc               1044 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dce80_hw_sequencer_construct(dc);
dc               1055 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	struct dc *dc)
dc               1063 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	if (dce80_construct(num_virtual_links, dc, pool))
dc               1072 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	struct dc *dc,
dc               1076 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	struct dc_context *ctx = dc->ctx;
dc               1091 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.max_downscale_ratio = 200;
dc               1092 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.i2c_speed_in_khz = 40;
dc               1093 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.max_cursor_size = 128;
dc               1094 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.is_apu = true;
dc               1161 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		init_data.ctx = dc->ctx;
dc               1229 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
dc               1231 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < dc->caps.max_planes; ++i)
dc               1232 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		dc->caps.planes[i] = plane_cap;
dc               1234 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.disable_dp_clk_share = true;
dc               1236 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	if (!resource_construct(num_virtual_links, dc, &pool->base,
dc               1241 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dce80_hw_sequencer_construct(dc);
dc               1252 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	struct dc *dc)
dc               1260 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	if (dce81_construct(num_virtual_links, dc, pool))
dc               1269 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	struct dc *dc,
dc               1273 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	struct dc_context *ctx = dc->ctx;
dc               1288 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.max_downscale_ratio = 200;
dc               1289 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.i2c_speed_in_khz = 40;
dc               1290 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.max_cursor_size = 128;
dc               1291 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.is_apu = true;
dc               1354 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		init_data.ctx = dc->ctx;
dc               1422 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
dc               1424 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < dc->caps.max_planes; ++i)
dc               1425 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		dc->caps.planes[i] = plane_cap;
dc               1427 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.disable_dp_clk_share = true;
dc               1429 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	if (!resource_construct(num_virtual_links, dc, &pool->base,
dc               1434 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dce80_hw_sequencer_construct(dc);
dc               1445 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	struct dc *dc)
dc               1453 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	if (dce83_construct(num_virtual_links, dc, pool))
dc                 31 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h struct dc;
dc                 36 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h 	struct dc *dc);
dc                 40 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h 	struct dc *dc);
dc                 44 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h 	struct dc *dc);
dc                152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
dc                153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
dc                189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	if (!dpp->ctx->dc->debug.always_scale) {
dc                489 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	if (dpp->base.ctx->dc->debug.use_max_lb)
dc                533 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 			dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
dc                647 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
dc                672 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 			dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
dc                623 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
dc                860 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	struct dc *dc = hubbub1->base.ctx->dc;
dc                870 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	if (dc->debug.disable_dcc == DCC_DISABLE)
dc                913 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
dc                299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h struct dc;
dc                 75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
dc                 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void log_mpc_crc(struct dc *dc,
dc                 87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_context *dc_ctx = dc->ctx;
dc                 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dce_hwseq *hws = dc->hwseq;
dc                 98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
dc                100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_context *dc_ctx = dc->ctx;
dc                105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
dc                126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
dc                128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_context *dc_ctx = dc->ctx;
dc                129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct resource_pool *pool = dc->res_pool;
dc                241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c void dcn10_log_hw_state(struct dc *dc,
dc                244 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_context *dc_ctx = dc->ctx;
dc                245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct resource_pool *pool = dc->res_pool;
dc                250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dcn10_log_hubbub_state(dc, log_ctx);
dc                252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dcn10_log_hubp_states(dc, log_ctx);
dc                391 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->link_count; i++) {
dc                392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct link_encoder *lenc = dc->links[i]->link_enc;
dc                411 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
dc                412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
dc                413 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
dc                414 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
dc                415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
dc                416 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
dc                417 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
dc                419 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	log_mpc_crc(dc, log_ctx);
dc                424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
dc                504 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (hws->ctx->dc->debug.disable_dpp_power_gate)
dc                556 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (hws->ctx->dc->debug.disable_hubp_power_gate)
dc                608 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		hws->ctx->dc->hwss.dpp_pg_control(hws, plane_id, true);
dc                609 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		hws->ctx->dc->hwss.hubp_pg_control(hws, plane_id, true);
dc                617 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void undo_DEGVIDCN10_253_wa(struct dc *dc)
dc                619 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dce_hwseq *hws = dc->hwseq;
dc                620 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubp *hubp = dc->res_pool->hubps[0];
dc                630 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->hwss.hubp_pg_control(hws, 0, false);
dc                637 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void apply_DEGVIDCN10_253_wa(struct dc *dc)
dc                639 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dce_hwseq *hws = dc->hwseq;
dc                640 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubp *hubp = dc->res_pool->hubps[0];
dc                643 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.disable_stutter)
dc                649 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc                650 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (!dc->res_pool->hubps[i]->power_gated)
dc                659 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->hwss.hubp_pg_control(hws, 0, true);
dc                667 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_bios_golden_init(struct dc *dc)
dc                669 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_bios *bp = dc->ctx->dc_bios;
dc                673 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
dc                675 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
dc                689 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc                695 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
dc                697 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))
dc                698 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, true);
dc                703 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dc *dc,
dc                710 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!dc->hwseq->wa.false_optc_underflow)
dc                715 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc                716 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
dc                721 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
dc                734 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dc *dc)
dc                785 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	color_space_to_black_color(dc, color_space, &black_color);
dc                796 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
dc                817 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dc *dc,
dc                822 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc                828 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dc                833 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->hwss.disable_audio_stream(pipe_ctx);
dc                840 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			if (dc->caps.dynamic_audio == true) {
dc                843 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
dc                863 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
dc                864 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
dc                867 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (i == dc->res_pool->pipe_count)
dc                875 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static bool dcn10_hw_wa_force_recovery(struct dc *dc)
dc                881 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!dc->debug.recovery_enabled)
dc                884 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc                886 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&dc->current_state->res_ctx.pipe_ctx[i];
dc                909 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc                911 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&dc->current_state->res_ctx.pipe_ctx[i];
dc                920 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	hubbub1_soft_reset(dc->res_pool->hubbub, true);
dc                922 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc                924 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&dc->current_state->res_ctx.pipe_ctx[i];
dc                932 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc                934 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&dc->current_state->res_ctx.pipe_ctx[i];
dc                943 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	hubbub1_soft_reset(dc->res_pool->hubbub, false);
dc                944 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc                946 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&dc->current_state->res_ctx.pipe_ctx[i];
dc                959 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c void dcn10_verify_allow_pstate_change_high(struct dc *dc)
dc                963 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
dc                965 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dcn10_log_hw_state(dc, NULL);
dc                968 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (dcn10_hw_wa_force_recovery(dc)) {
dc                970 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))
dc                977 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
dc                981 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct mpc *mpc = dc->res_pool->mpc;
dc                997 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->optimized_required = true;
dc               1002 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.sanity_checks)
dc               1003 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_verify_allow_pstate_change_high(dc);
dc               1006 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_plane_atomic_power_down(struct dc *dc,
dc               1010 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dce_hwseq *hws = dc->hwseq;
dc               1011 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc               1016 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.dpp_pg_control(hws, dpp->inst, false);
dc               1017 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.hubp_pg_control(hws, hubp->inst, false);
dc               1029 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
dc               1035 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
dc               1047 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->optimized_required = false; /* We're powering off, no need to optimize */
dc               1049 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->hwss.plane_atomic_power_down(dc,
dc               1061 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
dc               1063 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc               1068 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->hwss.plane_atomic_disable(dc, pipe_ctx);
dc               1070 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	apply_DEGVIDCN10_253_wa(dc);
dc               1076 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
dc               1088 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               1089 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
dc               1103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			if (dc->hwss.init_blank != NULL) {
dc               1104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->hwss.init_blank(dc, tg);
dc               1114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               1121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->res_pool->mpc->funcs->mpc_init_single_inst(
dc               1122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->res_pool->mpc, i);
dc               1125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               1126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
dc               1127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct hubp *hubp = dc->res_pool->hubps[i];
dc               1128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dpp *dpp = dc->res_pool->dpps[i];
dc               1142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
dc               1156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
dc               1157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
dc               1158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
dc               1159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
dc               1161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
dc               1166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.disable_plane(dc, pipe_ctx);
dc               1175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_init_hw(struct dc *dc)
dc               1178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct abm *abm = dc->res_pool->abm;
dc               1179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dmcu *dmcu = dc->res_pool->dmcu;
dc               1180 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dce_hwseq *hws = dc->hwseq;
dc               1181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_bios *dcb = dc->ctx->dc_bios;
dc               1182 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct resource_pool *res_pool = dc->res_pool;
dc               1184 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
dc               1185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
dc               1188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
dc               1189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
dc               1191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dc               1197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (!dc->debug.disable_clock_gate) {
dc               1207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.enable_power_gating_plane(hws, true);
dc               1213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.disable_vga(dc->hwseq);
dc               1215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->hwss.bios_golden_init(dc);
dc               1216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->ctx->dc_bios->fw_info_valid) {
dc               1218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
dc               1220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dc               1224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
dc               1241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->link_count; i++) {
dc               1246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dc_link *link = dc->links[i];
dc               1259 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (dc->hwss.dsc_pg_control != NULL)
dc               1260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
dc               1269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
dc               1270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.init_pipes(dc, dc->current_state);
dc               1293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!dc->debug.disable_clock_gate) {
dc               1302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->hwss.enable_power_gating_plane(dc->hwseq, true);
dc               1306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dc *dc,
dc               1312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
dc               1314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&dc->current_state->res_ctx.pipe_ctx[i];
dc               1327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
dc               1328 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			if (dc->hwss.enable_stream_gating)
dc               1329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->hwss.enable_stream_gating(dc, pipe_ctx);
dc               1364 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
dc               1403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		!dpp_base->ctx->dc->debug.always_use_regamma
dc               1506 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc *dc,
dc               1516 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.sanity_checks)
dc               1517 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_verify_allow_pstate_change_high(dc);
dc               1524 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.sanity_checks)
dc               1525 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_verify_allow_pstate_change_high(dc);
dc               1566 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc *dc,
dc               1571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_context *dc_ctx = dc->ctx;
dc               1596 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc *dc,
dc               1600 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_context *dc_ctx = dc->ctx;
dc               1826 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc *dc,
dc               1830 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dce_hwseq *hws = dc->hwseq;
dc               1832 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.sanity_checks) {
dc               1833 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_verify_allow_pstate_change_high(dc);
dc               1836 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	undo_DEGVIDCN10_253_wa(dc);
dc               1838 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	power_on_plane(dc->hwseq,
dc               1886 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->config.gpu_vm_support)
dc               1889 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.sanity_checks) {
dc               1890 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_verify_allow_pstate_change_high(dc);
dc               1942 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_program_output_csc(struct dc *dc,
dc               2183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
dc               2190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct mpc *mpc = dc->res_pool->mpc;
dc               2193 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
dc               2196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
dc               2201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc, pipe_ctx->stream->output_color_space,
dc               2248 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (dc->debug.sanity_checks)
dc               2250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 					dc->res_pool->mpc, mpcc_id);
dc               2253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
dc               2280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc *dc,
dc               2296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->clk_mgr->clks.dispclk_khz / 2;
dc               2303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (dc->res_pool->dccg)
dc               2304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->res_pool->dccg->funcs->update_dpp_dto(
dc               2305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 					dc->res_pool->dccg,
dc               2310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
dc               2311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 						dc->clk_mgr->clks.dispclk_khz / 2 :
dc               2312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 							dc->clk_mgr->clks.dispclk_khz;
dc               2343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.update_mpcc(dc, pipe_ctx);
dc               2363 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.set_cursor_position(pipe_ctx);
dc               2364 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.set_cursor_attribute(pipe_ctx);
dc               2366 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (dc->hwss.set_cursor_sdr_white_level)
dc               2367 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
dc               2372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.program_gamut_remap(pipe_ctx);
dc               2374 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.program_output_csc(dc,
dc               2403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->hwss.update_plane_addr(dc, pipe_ctx);
dc               2410 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dc *dc,
dc               2421 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	color_space_to_black_color(dc, color_space, &black_color);
dc               2471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dc *dc,
dc               2476 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_enable_plane(dc, pipe_ctx, context);
dc               2478 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	update_dchubp_dpp(dc, pipe_ctx, context);
dc               2485 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
dc               2494 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
dc               2498 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dc *dc,
dc               2515 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
dc               2520 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_program_pipe(dc, pipe_ctx, context);
dc               2523 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
dc               2527 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dc *dc,
dc               2533 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2536 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				&dc->current_state->res_ctx.pipe_ctx[i];
dc               2551 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dc *dc,
dc               2562 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			find_top_pipe_for_stream(dc, context, stream);
dc               2563 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc               2573 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	underflow_check_delay_us = dc->debug.underflow_assert_delay_us;
dc               2575 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
dc               2576 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
dc               2579 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		lock_all_pipes(dc, context, true);
dc               2581 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
dc               2586 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
dc               2587 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
dc               2591 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
dc               2595 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2598 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				&dc->current_state->res_ctx.pipe_ctx[i];
dc               2609 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->hwss.disable_plane(dc, old_pipe_ctx);
dc               2617 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
dc               2626 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		program_all_pipe_in_tree(dc, top_pipe_to_program, context);
dc               2630 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
dc               2631 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context);
dc               2634 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2648 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		lock_all_pipes(dc, context, false);
dc               2650 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
dc               2653 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		false_optc_underflow_wa(dc, stream, tg);
dc               2655 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
dc               2657 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
dc               2659 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
dc               2661 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->hwss.optimize_bandwidth(dc, context);
dc               2665 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->hwseq->wa.DEGVIDCN10_254)
dc               2666 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
dc               2669 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)
dc               2679 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
dc               2686 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dc *dc,
dc               2689 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubbub *hubbub = dc->res_pool->hubbub;
dc               2691 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.sanity_checks)
dc               2692 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_verify_allow_pstate_change_high(dc);
dc               2694 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dc               2698 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->clk_mgr->funcs->update_clocks(
dc               2699 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->clk_mgr,
dc               2706 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
dc               2708 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dcn10_stereo_hw_frame_pack_wa(dc, context);
dc               2710 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
dc               2711 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn_bw_notify_pplib_of_wm_ranges(dc);
dc               2713 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.sanity_checks)
dc               2714 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_verify_allow_pstate_change_high(dc);
dc               2718 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dc *dc,
dc               2721 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubbub *hubbub = dc->res_pool->hubbub;
dc               2723 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.sanity_checks)
dc               2724 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_verify_allow_pstate_change_high(dc);
dc               2726 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dc               2730 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->clk_mgr->funcs->update_clocks(
dc               2731 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->clk_mgr,
dc               2738 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
dc               2740 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dcn10_stereo_hw_frame_pack_wa(dc, context);
dc               2742 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
dc               2743 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn_bw_notify_pplib_of_wm_ranges(dc);
dc               2745 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.sanity_checks)
dc               2746 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_verify_allow_pstate_change_high(dc);
dc               2844 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
dc               2852 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (!dc_set_generic_gpio_for_stereo(true, dc->ctx->gpio_service))
dc               2853 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
dc               2855 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
dc               2884 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dc *dc,
dc               2890 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.sanity_checks) {
dc               2891 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_verify_allow_pstate_change_high(dc);
dc               2907 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->debug.sanity_checks) {
dc               2908 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_verify_allow_pstate_change_high(dc);
dc               2914 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc *dc,
dc               2948 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub;
dc               2961 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,
dc               3104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c void lock_all_pipes(struct dc *dc,
dc               3112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               3243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		link->dc->hwss.edp_backlight_control(link, true);
dc               3258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static enum dc_status dcn10_set_clock(struct dc *dc,
dc               3263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_state *context = dc->current_state;
dc               3267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
dc               3268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->clk_mgr->funcs->get_clock(dc->clk_mgr,
dc               3271 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!dc->clk_mgr->funcs->get_clock)
dc               3291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks)
dc               3292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,
dc               3298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void dcn10_get_clock(struct dc *dc,
dc               3302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_state *context = dc->current_state;
dc               3304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
dc               3305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
dc               3377 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c void dcn10_hw_sequencer_construct(struct dc *dc)
dc               3379 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->hwss = dcn10_funcs;
dc                 31 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h struct dc;
dc                 33 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h void dcn10_hw_sequencer_construct(struct dc *dc);
dc                 40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
dc                 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h void dcn10_verify_allow_pstate_change_high(struct dc *dc);
dc                 45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h 		struct dc *dc,
dc                 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h 		struct dc *dc,
dc                 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);
dc                 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
dc                 77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h 	struct dc *dc,
dc                 82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h 		struct dc *dc,
dc                 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h void lock_all_pipes(struct dc *dc,
dc                 71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned int bufSize)
dc                 73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct dc_context *dc_ctx = dc->ctx;
dc                 80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
dc                 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
dc                109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c static unsigned int dcn10_get_hubp_states(struct dc *dc, char *pBuf, unsigned int bufSize, bool invarOnly)
dc                111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct dc_context *dc_ctx = dc->ctx;
dc                112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
dc                118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
dc                188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c static unsigned int dcn10_get_rq_states(struct dc *dc, char *pBuf, unsigned int bufSize)
dc                190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
dc                230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c static unsigned int dcn10_get_dlg_states(struct dc *dc, char *pBuf, unsigned int bufSize)
dc                232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
dc                287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c static unsigned int dcn10_get_ttu_states(struct dc *dc, char *pBuf, unsigned int bufSize)
dc                289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
dc                327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c static unsigned int dcn10_get_cm_states(struct dc *dc, char *pBuf, unsigned int bufSize)
dc                329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
dc                382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c static unsigned int dcn10_get_mpcc_states(struct dc *dc, char *pBuf, unsigned int bufSize)
dc                384 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
dc                413 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int bufSize)
dc                415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
dc                432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
dc                467 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c static unsigned int dcn10_get_clock_states(struct dc *dc, char *pBuf, unsigned int bufSize)
dc                475 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
dc                476 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
dc                477 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
dc                478 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
dc                479 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
dc                480 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
dc                488 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c static void dcn10_clear_otpc_underflow(struct dc *dc)
dc                490 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
dc                504 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c static void dcn10_clear_hubp_underflow(struct dc *dc)
dc                506 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
dc                520 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c void dcn10_clear_status_bits(struct dc *dc, unsigned int mask)
dc                535 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		dcn10_clear_hubp_underflow(dc);
dc                538 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		dcn10_clear_otpc_underflow(dc);
dc                541 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c void dcn10_get_hw_state(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask)
dc                566 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		chars_printed = dcn10_get_hubbub_state(dc, pBuf, remaining_buf_size);
dc                572 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		chars_printed = dcn10_get_hubp_states(dc, pBuf, remaining_buf_size, mask & DC_HW_STATE_INVAR_ONLY);
dc                578 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		chars_printed = dcn10_get_rq_states(dc, pBuf, remaining_buf_size);
dc                584 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		chars_printed = dcn10_get_dlg_states(dc, pBuf, remaining_buf_size);
dc                590 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		chars_printed = dcn10_get_ttu_states(dc, pBuf, remaining_buf_size);
dc                596 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		chars_printed = dcn10_get_cm_states(dc, pBuf, remaining_buf_size);
dc                602 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		chars_printed = dcn10_get_mpcc_states(dc, pBuf, remaining_buf_size);
dc                608 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		chars_printed = dcn10_get_otg_states(dc, pBuf, remaining_buf_size);
dc                614 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		chars_printed = dcn10_get_clock_states(dc, pBuf, remaining_buf_size);
dc                646 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	if (enc10->base.ctx->dc->debug.hdmi20_disable &&
dc                773 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
dc               1038 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		const struct dc *dc,
dc               1070 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		struct dc *dc,
dc               1076 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
dc               1079 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
dc               1083 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		result = build_mapped_resource(dc, new_ctx, dc_stream);
dc               1118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
dc               1122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
dc               1123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			dc->res_pool->hubbub,
dc               1147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)
dc               1191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			dc->dcn_soc->number_of_channels == 1)
dc               1273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	struct dc *dc,
dc               1278 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	struct dc_context *ctx = dc->ctx;
dc               1302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (dc->ctx->dce_version == DCN_VERSION_1_01)
dc               1304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->caps.max_video_width = 3840;
dc               1305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->caps.max_downscale_ratio = 200;
dc               1306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->caps.i2c_speed_in_khz = 100;
dc               1307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->caps.max_cursor_size = 256;
dc               1308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->caps.max_slave_planes = 1;
dc               1309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->caps.is_apu = true;
dc               1310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->caps.post_blend_color_processing = false;
dc               1312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->caps.force_dp_tps4_for_cp2520 = true;
dc               1314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc               1315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->debug = debug_defaults_drv;
dc               1317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->debug = debug_defaults_diags;
dc               1336 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (dc->ctx->dce_version == DCN_VERSION_1_0) {
dc               1345 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (dc->ctx->dce_version == DCN_VERSION_1_01)
dc               1382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);
dc               1383 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
dc               1384 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
dc               1386 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (dc->ctx->dce_version == DCN_VERSION_1_01) {
dc               1387 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
dc               1388 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		struct dcn_ip_params *dcn_ip = dc->dcn_ip;
dc               1389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		struct display_mode_lib *dml = &dc->dml;
dc               1396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
dc               1397 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->dcn_soc->urgent_latency = 3;
dc               1398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->debug.disable_dmcu = true;
dc               1399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
dc               1403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
dc               1404 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	ASSERT(dc->dcn_soc->number_of_channels < 3);
dc               1405 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
dc               1406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->dcn_soc->number_of_channels = 2;
dc               1408 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (dc->dcn_soc->number_of_channels == 1) {
dc               1409 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
dc               1410 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
dc               1411 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
dc               1412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
dc               1413 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
dc               1414 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
dc               1426 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->debug.az_endpoint_mute_only = false;
dc               1428 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (!dc->debug.disable_pplib_clock_request)
dc               1429 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dcn_bw_update_from_pplib(dc);
dc               1430 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dcn_bw_sync_calcs_and_dml(dc);
dc               1431 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (!dc->debug.disable_pplib_wm_range) {
dc               1432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->res_pool = &pool->base;
dc               1433 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dcn_bw_notify_pplib_of_wm_ranges(dc);
dc               1438 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		init_data.ctx = dc->ctx;
dc               1522 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->dml.ip.max_num_dpp = pool->base.pipe_count;
dc               1523 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
dc               1539 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (!resource_construct(num_virtual_links, dc, &pool->base,
dc               1540 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
dc               1544 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dcn10_hw_sequencer_construct(dc);
dc               1545 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
dc               1547 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	for (i = 0; i < dc->caps.max_planes; ++i)
dc               1548 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->caps.planes[i] = plane_cap;
dc               1550 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->cap_funcs = cap_funcs;
dc               1563 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		struct dc *dc)
dc               1571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (construct(init_data->num_virtual_links, dc, pool))
dc                 34 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h struct dc;
dc                 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h 		struct dc *dc);
dc                125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	switch (dccg_dcn->base.ctx->dc->res_pool->pipe_count) {
dc                394 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 		dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
dc                395 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 		scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
dc                443 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	if (!dpp->ctx->dc->debug.always_scale) {
dc                 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	if (dpp_base->ctx->dc->debug.cm_in_bypass)
dc                219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 	struct dc *dc = hubbub->ctx->dc;
dc                228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 	if (dc->debug.disable_dcc == DCC_DISABLE)
dc                276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 	if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
dc                581 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 	if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true &&
dc                582 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 		hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false)
dc                591 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 	hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
dc                131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c void dcn20_display_init(struct dc *dc)
dc                133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dce_hwseq *hws = dc->hwseq;
dc                182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	const struct dc *dc,
dc                195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc                207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	color_space_to_black_color(dc, color_space, &black_color);
dc                216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
dc                217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	opp = dc->res_pool->opps[opp_id_src0];
dc                221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp);
dc                222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		bottom_opp = dc->res_pool->opps[opp_id_src1];
dc                256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (hws->ctx->dc->debug.disable_dsc_power_gate)
dc                333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (hws->ctx->dc->debug.disable_dpp_power_gate)
dc                407 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (hws->ctx->dc->debug.disable_hubp_power_gate)
dc                476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
dc                481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
dc                487 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
dc                489 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.set_flip_control_gsl(pipe_ctx, false);
dc                497 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.plane_atomic_power_down(dc,
dc                510 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
dc                512 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc                517 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dcn20_plane_atomic_disable(dc, pipe_ctx);
dc                526 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc)
dc                587 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.blank_pixel_data(dc, pipe_ctx, true);
dc                623 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c void dcn20_program_output_csc(struct dc *dc,
dc                629 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct mpc *mpc = dc->res_pool->mpc;
dc                655 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
dc                826 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
dc                848 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc                864 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	color_space_to_black_color(dc, color_space, &black_color);
dc                875 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
dc                892 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
dc                926 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dc *dc,
dc                933 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dcn20_power_on_plane(dc->hwseq, pipe_ctx);
dc                983 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (dc->vm_pa_config.valid) {
dc                988 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
dc                989 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
dc               1002 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc               1010 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dcn20_enable_plane(dc, pipe_ctx, context);
dc               1012 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	update_dchubp_dpp(dc, pipe_ctx, context);
dc               1019 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
dc               1028 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
dc               1032 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc               1049 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
dc               1051 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		if (dc->hwss.update_odm)
dc               1052 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->hwss.update_odm(dc, context, pipe_ctx);
dc               1056 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dcn20_program_pipe(dc, pipe_ctx, context);
dc               1060 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
dc               1063 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dcn20_program_all_pipe_in_tree(dc, pipe_ctx->next_odm_pipe, context);
dc               1068 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc               1090 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dc *dc,
dc               1130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
dc               1146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc               1157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			find_top_pipe_for_stream(dc, context, stream);
dc               1159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			find_top_pipe_for_stream(dc, dc->current_state, stream);
dc               1160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc               1166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               1169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			&dc->current_state->res_ctx.pipe_ctx[i];
dc               1183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		lock_all_pipes(dc, context, true);
dc               1185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dcn20_pipe_control_lock(dc, top_pipe_to_program, true);
dc               1189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
dc               1193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               1196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				&dc->current_state->res_ctx.pipe_ctx[i];
dc               1207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				dc->hwss.disable_plane(dc, old_pipe_ctx);
dc               1215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
dc               1224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dcn20_program_all_pipe_in_tree(dc, top_pipe_to_program, context);
dc               1227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
dc               1228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context);
dc               1231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               1246 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		lock_all_pipes(dc, context, false);
dc               1248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dcn20_pipe_control_lock(dc, top_pipe_to_program, false);
dc               1250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
dc               1252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dcn20_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
dc               1273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc               1276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct hubbub *hubbub = dc->res_pool->hubbub;
dc               1278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->clk_mgr->funcs->update_clocks(
dc               1279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->clk_mgr,
dc               1286 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 					dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
dc               1291 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc               1294 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct hubbub *hubbub = dc->res_pool->hubbub;
dc               1299 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 					dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
dc               1302 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->clk_mgr->funcs->update_clocks(
dc               1303 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->clk_mgr,
dc               1309 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc               1315 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
dc               1319 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.prepare_bandwidth(dc, context);
dc               1322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               1341 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
dc               1356 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc               1367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dc               1368 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
dc               1372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	optc = dc->res_pool->timing_generators[stream_status->primary_otg_inst];
dc               1385 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc               1392 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb = dc->res_pool->dwbc[dwb_pipe_inst];
dc               1393 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
dc               1428 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
dc               1431 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dce_hwseq *hws = dc->hwseq;
dc               1445 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
dc               1448 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dce_hwseq *hws = dc->hwseq;
dc               1489 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc               1506 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
dc               1509 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
dc               1524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
dc               1554 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
dc               1566 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
dc               1608 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		link->dc->hwss.edp_backlight_control(link, true);
dc               1625 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc               1630 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc               1636 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dc               1641 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->hwss.disable_audio_stream(pipe_ctx);
dc               1649 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			if (dc->caps.dynamic_audio == true) {
dc               1652 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
dc               1681 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
dc               1682 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
dc               1685 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (i == dc->res_pool->pipe_count)
dc               1694 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dc *dc,
dc               1700 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
dc               1702 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			&dc->current_state->res_ctx.pipe_ctx[i];
dc               1715 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
dc               1716 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			if (dc->hwss.enable_stream_gating)
dc               1717 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				dc->hwss.enable_stream_gating(dc, pipe_ctx);
dc               1724 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
dc               1731 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct mpc *mpc = dc->res_pool->mpc;
dc               1735 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
dc               1738 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
dc               1785 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		if (dc->debug.sanity_checks)
dc               1787 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 					dc->res_pool->mpc, mpcc_id);
dc               1790 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
dc               1803 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static int find_free_gsl_group(const struct dc *dc)
dc               1805 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (dc->res_pool->gsl_groups.gsl_0 == 0)
dc               1807 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (dc->res_pool->gsl_groups.gsl_1 == 0)
dc               1809 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (dc->res_pool->gsl_groups.gsl_2 == 0)
dc               1831 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		const struct dc *dc,
dc               1847 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		group_idx = find_free_gsl_group(dc);
dc               1855 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->res_pool->gsl_groups.gsl_0 = 1;
dc               1859 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->res_pool->gsl_groups.gsl_1 = 1;
dc               1863 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->res_pool->gsl_groups.gsl_2 = 1;
dc               1881 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->res_pool->gsl_groups.gsl_0 = 0;
dc               1885 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->res_pool->gsl_groups.gsl_1 = 0;
dc               1889 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->res_pool->gsl_groups.gsl_2 = 0;
dc               1941 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (link->dc->hwss.program_dmdata_engine)
dc               1942 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		link->dc->hwss.program_dmdata_engine(pipe_ctx);
dc               1944 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	link->dc->hwss.update_info_frame(pipe_ctx);
dc               1993 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c static void dcn20_fpga_init_hw(struct dc *dc)
dc               1996 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dce_hwseq *hws = dc->hwseq;
dc               1997 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct resource_pool *res_pool = dc->res_pool;
dc               1998 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dc_state  *context = dc->current_state;
dc               2000 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
dc               2001 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
dc               2008 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.enable_power_gating_plane(hws, true);
dc               2024 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
dc               2025 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
dc               2028 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dcn20_init_blank(dc, tg);
dc               2032 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
dc               2038 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2048 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
dc               2055 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2056 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
dc               2058 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct hubp *hubp = dc->res_pool->hubps[i];
dc               2059 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dpp *dpp = dc->res_pool->dpps[i];
dc               2076 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
dc               2077 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
dc               2079 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
dc               2086 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
dc               2087 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
dc               2093 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2096 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->hwss.disable_plane(dc, pipe_ctx);
dc               2102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
dc               2103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
dc               2109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c void dcn20_hw_sequencer_construct(struct dc *dc)
dc               2111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dcn10_hw_sequencer_construct(dc);
dc               2112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.unblank_stream = dcn20_unblank_stream;
dc               2113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.update_plane_addr = dcn20_update_plane_addr;
dc               2114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.enable_stream_timing = dcn20_enable_stream_timing;
dc               2115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer;
dc               2116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func;
dc               2117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.set_output_transfer_func = dcn20_set_output_transfer_func;
dc               2118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.apply_ctx_for_surface = dcn20_apply_ctx_for_surface;
dc               2119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.pipe_control_lock = dcn20_pipe_control_lock;
dc               2120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.pipe_control_lock_global = dcn20_pipe_control_lock_global;
dc               2121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.optimize_bandwidth = dcn20_optimize_bandwidth;
dc               2122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.prepare_bandwidth = dcn20_prepare_bandwidth;
dc               2123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.update_bandwidth = dcn20_update_bandwidth;
dc               2124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.enable_writeback = dcn20_enable_writeback;
dc               2125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.disable_writeback = dcn20_disable_writeback;
dc               2126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.program_output_csc = dcn20_program_output_csc;
dc               2127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.update_odm = dcn20_update_odm;
dc               2128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.blank_pixel_data = dcn20_blank_pixel_data;
dc               2129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.dmdata_status_done = dcn20_dmdata_status_done;
dc               2130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.program_dmdata_engine = dcn20_program_dmdata_engine;
dc               2131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.enable_stream = dcn20_enable_stream;
dc               2132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.disable_stream = dcn20_disable_stream;
dc               2133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.init_sys_ctx = dcn20_init_sys_ctx;
dc               2134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.init_vm_ctx = dcn20_init_vm_ctx;
dc               2135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.disable_stream_gating = dcn20_disable_stream_gating;
dc               2136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.enable_stream_gating = dcn20_enable_stream_gating;
dc               2137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt;
dc               2138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap;
dc               2139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.update_mpcc = dcn20_update_mpcc;
dc               2140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.set_flip_control_gsl = dcn20_set_flip_control_gsl;
dc               2141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.init_blank = dcn20_init_blank;
dc               2142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.disable_plane = dcn20_disable_plane;
dc               2143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.plane_atomic_disable = dcn20_plane_atomic_disable;
dc               2144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
dc               2145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
dc               2146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
dc               2148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
dc               2150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.dsc_pg_control = NULL;
dc               2152 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.disable_vga = dcn20_disable_vga;
dc               2154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
dc               2155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->hwss.init_hw = dcn20_fpga_init_hw;
dc               2156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->hwss.init_pipes = NULL;
dc                 29 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h struct dc;
dc                 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h void dcn20_hw_sequencer_construct(struct dc *dc);
dc                 36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 		struct dc *dc);
dc                 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 		struct dc *dc,
dc                 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h void dcn20_program_output_csc(struct dc *dc,
dc                 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 		struct dc *dc,
dc                 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 		struct dc *dc,
dc                 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 		struct dc *dc,
dc                 62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 		struct dc *dc,
dc                 81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 		const struct dc *dc,
dc                 88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 		struct dc *dc,
dc                 91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h void dcn20_setup_gsl_group_as_lock(const struct dc *dc,
dc                 96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 	   struct dc *dc,
dc                 98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h void dcn20_display_init(struct dc *dc);
dc                252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
dc                458 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
dc                371 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	if (mpc->ctx->dc->debug.cm_in_bypass) {
dc                376 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {
dc                398 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	if (mpc->ctx->dc->debug.cm_in_bypass) {
dc               1497 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
dc               1574 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
dc               1580 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	const struct resource_pool *pool = dc->res_pool;
dc               1583 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               1604 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
dc               1616 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
dc               1628 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
dc               1632 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
dc               1635 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
dc               1640 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
dc               1644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
dc               1650 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
dc               1655 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
dc               1836 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
dc               1840 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
dc               1873 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
dc               1878 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
dc               1886 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable(
dc               1894 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
dc               2123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 					|| dc->debug.always_scale; /*support always scale*/
dc               2165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
dc               2200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		struct dc *dc,
dc               2211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
dc               2258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2288 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
dc               2295 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (dc && primary_pipe) {
dc               2306 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
dc               2307 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
dc               2312 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		} else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
dc               2313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
dc               2327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
dc               2328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL) {
dc               2349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
dc               2365 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		struct dc *dc,
dc               2380 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	int split_threshold = dc->res_pool->pipe_count / 2;
dc               2381 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
dc               2389 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2408 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
dc               2420 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2442 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (dc->res_pool->funcs->populate_dml_pipes)
dc               2443 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
dc               2446 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
dc               2465 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (!dcn20_validate_dsc(dc, context)) {
dc               2477 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if ((context->stream_count > split_threshold && dc->current_state->stream_count <= split_threshold)
dc               2478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		|| (context->stream_count <= split_threshold && dc->current_state->stream_count > split_threshold))
dc               2486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
dc               2493 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (dc->debug.force_single_disp_pipe_split) {
dc               2501 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) {
dc               2517 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
dc               2526 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
dc               2537 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
dc               2545 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
dc               2548 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 					&context->res_ctx, dc->res_pool,
dc               2552 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			dcn20_build_mapped_resource(dc, context, pipe->stream);
dc               2585 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
dc               2592 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 							&context->res_ctx, dc->res_pool,
dc               2595 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 					dcn20_build_mapped_resource(dc, context, pipe->stream);
dc               2598 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 						&context->res_ctx, dc->res_pool,
dc               2609 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (failed_non_odm_dsc && !dcn20_validate_dsc(dc, context)) {
dc               2629 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		struct dc *dc, struct dc_state *context,
dc               2637 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
dc               2641 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
dc               2663 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (dc->config.forced_clocks) {
dc               2667 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
dc               2668 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
dc               2669 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
dc               2670 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
dc               2676 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (dc->res_pool->funcs->populate_dml_pipes)
dc               2677 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
dc               2680 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
dc               2735 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		struct dc *dc, struct dc_state *context,
dc               2744 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
dc               2762 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
dc               2798 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
dc               2815 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
dc               2838 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
dc               2848 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
dc               2849 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc               2853 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
dc               2868 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
dc               2869 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
dc               2891 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
dc               2900 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		return dcn20_validate_bandwidth_internal(dc, context, true);
dc               2904 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
dc               2916 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
dc               2928 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
dc               2961 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c bool dcn20_get_dcc_compression_cap(const struct dc *dc,
dc               2965 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
dc               2966 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			dc->res_pool->hubbub,
dc               3159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
dc               3172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (dc->bb_overrides.min_dcfclk_mhz > 0)
dc               3173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
dc               3217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
dc               3220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
dc               3221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			&& dc->bb_overrides.sr_exit_time_ns) {
dc               3222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
dc               3226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				!= dc->bb_overrides.sr_enter_plus_exit_time_ns
dc               3227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {
dc               3229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
dc               3232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
dc               3233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			&& dc->bb_overrides.urgent_latency_ns) {
dc               3234 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
dc               3238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				!= dc->bb_overrides.dram_clock_change_latency_ns
dc               3239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			&& dc->bb_overrides.dram_clock_change_latency_ns) {
dc               3241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
dc               3273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static bool init_soc_bounding_box(struct dc *dc,
dc               3276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
dc               3278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
dc               3280 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
dc               3282 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc               3419 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
dc               3426 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	patch_bounding_box(dc, loaded_bb);
dc               3433 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	struct dc *dc,
dc               3437 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	struct dc_context *ctx = dc->ctx;
dc               3463 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->caps.max_downscale_ratio = 200;
dc               3464 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->caps.i2c_speed_in_khz = 100;
dc               3465 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->caps.max_cursor_size = 256;
dc               3466 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->caps.dmdata_alloc_size = 2048;
dc               3468 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->caps.max_slave_planes = 1;
dc               3469 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->caps.post_blend_color_processing = true;
dc               3470 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->caps.force_dp_tps4_for_cp2520 = true;
dc               3471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->caps.hw_3d_lut = true;
dc               3473 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
dc               3474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		dc->debug = debug_defaults_drv;
dc               3475 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	} else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
dc               3478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		dc->debug = debug_defaults_diags;
dc               3480 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		dc->debug = debug_defaults_diags;
dc               3483 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->work_arounds.dedcn20_305_wa = true;
dc               3486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (dc->vm_helper)
dc               3487 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		vm_helper_init(dc->vm_helper, 16);
dc               3562 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (!init_soc_bounding_box(dc, pool)) {
dc               3568 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
dc               3570 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (!dc->debug.disable_pplib_wm_range) {
dc               3612 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	init_data.ctx = dc->ctx;
dc               3719 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (!resource_construct(num_virtual_links, dc, &pool->base,
dc               3720 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
dc               3724 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dcn20_hw_sequencer_construct(dc);
dc               3726 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
dc               3728 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->caps.max_planes; ++i)
dc               3729 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		dc->caps.planes[i] = plane_cap;
dc               3731 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->cap_funcs = cap_funcs;
dc               3744 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		struct dc *dc)
dc               3752 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (construct(init_data->num_virtual_links, dc, pool))
dc                 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h struct dc;
dc                 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h 		struct dc *dc);
dc                 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h 		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
dc                 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h 		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
dc                 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h bool dcn20_get_dcc_compression_cap(const struct dc *dc,
dc                114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h 		struct dc *dc,
dc                118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);
dc                120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h 		struct dc *dc,
dc                127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h 		struct dc *dc, struct dc_state *context,
dc                132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
dc                133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
dc                134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
dc                138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h 		struct dc *dc,
dc                509 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 	hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
dc                980 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		struct dc *dc, struct dc_state *context,
dc                989 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
dc                993 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
dc                997 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
dc               1022 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		if (dc->res_pool->funcs->populate_dml_pipes)
dc               1023 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
dc               1026 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
dc               1062 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
dc               1072 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
dc               1073 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	DC_LOGGER_INIT(dc->ctx->logger);
dc               1077 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
dc               1092 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
dc               1093 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
dc               1274 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
dc               1276 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
dc               1439 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	struct dc *dc,
dc               1443 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	struct dc_context *ctx = dc->ctx;
dc               1450 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
dc               1463 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dc->caps.max_downscale_ratio = 200;
dc               1464 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dc->caps.i2c_speed_in_khz = 100;
dc               1465 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dc->caps.max_cursor_size = 256;
dc               1466 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dc->caps.dmdata_alloc_size = 2048;
dc               1467 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dc->caps.hw_3d_lut = true;
dc               1469 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dc->caps.max_slave_planes = 1;
dc               1470 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dc->caps.post_blend_color_processing = true;
dc               1471 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dc->caps.force_dp_tps4_for_cp2520 = true;
dc               1473 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc               1474 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		dc->debug = debug_defaults_drv;
dc               1475 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
dc               1477 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		dc->debug = debug_defaults_diags;
dc               1479 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		dc->debug = debug_defaults_diags;
dc               1482 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	if (dc->vm_helper)
dc               1483 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		vm_helper_init(dc->vm_helper, 16);
dc               1539 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
dc               1541 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	init_data.ctx = dc->ctx;
dc               1649 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	if (!resource_construct(num_virtual_links, dc, &pool->base,
dc               1650 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
dc               1654 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dcn20_hw_sequencer_construct(dc);
dc               1656 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
dc               1658 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < dc->caps.max_planes; ++i)
dc               1659 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		dc->caps.planes[i] = plane_cap;
dc               1661 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dc->cap_funcs = cap_funcs;
dc               1674 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		struct dc *dc)
dc               1682 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	if (construct(init_data->num_virtual_links, dc, pool))
dc                 34 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h struct dc;
dc                 43 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h 		struct dc *dc);
dc                181 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	const struct dc *dc,
dc                186 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	struct display_stream_compressor *dsc = dc->res_pool->dscs[0];
dc                805 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		const struct dc *dc,
dc                817 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	get_dsc_enc_caps(dc, &dsc_enc_caps, timing->pix_clk_100hz);
dc                835 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		const struct dc *dc,
dc                844 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	get_dsc_enc_caps(dc, &dsc_enc_caps, timing->pix_clk_100hz);
dc                 59 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	const struct dc *dc;
dc                100 drivers/gpu/drm/amd/display/dc/inc/core_types.h 					struct dc *dc,
dc                105 drivers/gpu/drm/amd/display/dc/inc/core_types.h 		struct dc *dc,
dc                110 drivers/gpu/drm/amd/display/dc/inc/core_types.h 		struct dc *dc,
dc                121 drivers/gpu/drm/amd/display/dc/inc/core_types.h 			struct dc *dc,
dc                126 drivers/gpu/drm/amd/display/dc/inc/core_types.h 				struct dc *dc,
dc                138 drivers/gpu/drm/amd/display/dc/inc/core_types.h 			struct dc *dc,
dc                143 drivers/gpu/drm/amd/display/dc/inc/core_types.h 			struct dc *dc,
dc                150 drivers/gpu/drm/amd/display/dc/inc/core_types.h 			struct dc *dc,
dc                 36 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct dc;
dc                 37 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h struct dc;
dc                623 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h 		struct dc *dc,
dc                628 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h 	const struct dc *dc,
dc                631 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h void dcn_bw_update_from_pplib(struct dc *dc);
dc                632 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc);
dc                633 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h void dcn_bw_sync_calcs_and_dml(struct dc *dc);
dc                295 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h 		struct dc *dc,
dc                 87 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
dc                 89 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
dc                 91 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*init_hw)(struct dc *dc);
dc                 93 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*init_pipes)(struct dc *dc, struct dc_state *context);
dc                 96 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc, struct dc_state *context);
dc                 99 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc, struct dc_state *context);
dc                102 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc,
dc                110 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*program_output_csc)(struct dc *dc,
dc                118 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 		const struct dc *dc,
dc                127 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 		const struct dc *dc,
dc                131 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 		struct dc *dc,
dc                141 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc,
dc                145 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc,
dc                150 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 		struct dc *dc,
dc                164 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*power_down)(struct dc *dc);
dc                166 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*enable_accelerated_mode)(struct dc *dc, struct dc_state *context);
dc                169 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc,
dc                175 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc,
dc                184 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 					struct dc *dc,
dc                189 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
dc                212 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 				struct dc *dc,
dc                217 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 				struct dc *dc,
dc                221 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc,
dc                226 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc,
dc                229 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc,
dc                234 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc,
dc                253 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc);
dc                257 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc);
dc                261 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*log_hw_state)(struct dc *dc,
dc                263 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*get_hw_state)(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask);
dc                264 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*clear_status_bits)(struct dc *dc, unsigned int mask);
dc                266 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*wait_for_mpcc_disconnect)(struct dc *dc,
dc                284 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
dc                286 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*init_blank)(struct dc *dc, struct timing_generator *tg);
dc                288 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*bios_golden_init)(struct dc *dc);
dc                289 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*plane_atomic_power_down)(struct dc *dc,
dc                294 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc, struct pipe_ctx *pipe_ctx);
dc                317 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
dc                319 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc *dc,
dc                322 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*update_writeback)(struct dc *dc,
dc                326 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*enable_writeback)(struct dc *dc,
dc                330 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*disable_writeback)(struct dc *dc,
dc                333 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	enum dc_status (*set_clock)(struct dc *dc,
dc                338 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	void (*get_clock)(struct dc *dc,
dc                345 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 	const struct dc *dc,
dc                 79 drivers/gpu/drm/amd/display/dc/inc/resource.h 	struct dc *dc,
dc                 83 drivers/gpu/drm/amd/display/dc/inc/resource.h struct resource_pool *dc_create_resource_pool(struct dc  *dc,
dc                 87 drivers/gpu/drm/amd/display/dc/inc/resource.h void dc_destroy_resource_pool(struct dc *dc);
dc                 90 drivers/gpu/drm/amd/display/dc/inc/resource.h 		const struct dc *dc,
dc                 97 drivers/gpu/drm/amd/display/dc/inc/resource.h 		const struct dc *dc,
dc                160 drivers/gpu/drm/amd/display/dc/inc/resource.h 		const struct dc *dc,
dc                165 drivers/gpu/drm/amd/display/dc/inc/resource.h 		const struct dc *dc,
dc                207 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 	struct dc *core_dc = irq_service->ctx->dc;
dc                209 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 			dc_interrupt_to_irq_source(irq_service->ctx->dc,
dc                 46 drivers/gpu/drm/amd/display/include/logger_interface.h 		struct dc *dc,
dc                 51 drivers/gpu/drm/amd/display/include/logger_interface.h 		struct dc *dc,
dc                 55 drivers/gpu/drm/amd/display/include/logger_interface.h void post_surface_trace(struct dc *dc);
dc                 58 drivers/gpu/drm/amd/display/include/logger_interface.h 		struct dc *dc,
dc                 62 drivers/gpu/drm/amd/display/include/logger_interface.h 		struct dc *dc,
dc                141 drivers/gpu/drm/amd/display/include/logger_interface.h 	unsigned long long perf_trc_start_stmp = dm_get_timestamp(dc->ctx)
dc                145 drivers/gpu/drm/amd/display/include/logger_interface.h 		unsigned long long perf_trc_end_stmp = dm_get_timestamp(dc->ctx); \
dc                146 drivers/gpu/drm/amd/display/include/logger_interface.h 		if (dc->debug.performance_trace) { \
dc                 52 drivers/gpu/drm/amd/display/modules/freesync/freesync.c 	struct dc *dc;
dc                 58 drivers/gpu/drm/amd/display/modules/freesync/freesync.c struct mod_freesync *mod_freesync_create(struct dc *dc)
dc                 66 drivers/gpu/drm/amd/display/modules/freesync/freesync.c 	if (dc == NULL)
dc                 69 drivers/gpu/drm/amd/display/modules/freesync/freesync.c 	core_freesync->dc = dc;
dc                477 drivers/gpu/drm/amd/display/modules/freesync/freesync.c 	if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1,
dc                122 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h struct mod_freesync *mod_freesync_create(struct dc *dc);
dc                 39 drivers/gpu/drm/amd/display/modules/inc/mod_stats.h struct mod_stats *mod_stats_create(struct dc *dc);
dc                 40 drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h 		struct dc *dc,
dc                 78 drivers/gpu/drm/amd/display/modules/stats/stats.c 	struct dc *dc;
dc                100 drivers/gpu/drm/amd/display/modules/stats/stats.c 	struct dc *dc = NULL;
dc                106 drivers/gpu/drm/amd/display/modules/stats/stats.c 	dc = core_stats->dc;
dc                111 drivers/gpu/drm/amd/display/modules/stats/stats.c struct mod_stats *mod_stats_create(struct dc *dc)
dc                118 drivers/gpu/drm/amd/display/modules/stats/stats.c 	if (dc == NULL)
dc                126 drivers/gpu/drm/amd/display/modules/stats/stats.c 	core_stats->dc = dc;
dc                129 drivers/gpu/drm/amd/display/modules/stats/stats.c 	if (dm_read_persistent_data(dc->ctx, NULL, NULL,
dc                136 drivers/gpu/drm/amd/display/modules/stats/stats.c 		if (dm_read_persistent_data(dc->ctx, NULL, NULL,
dc                197 drivers/gpu/drm/amd/display/modules/stats/stats.c 	struct dc  *dc = NULL;
dc                211 drivers/gpu/drm/amd/display/modules/stats/stats.c 	dc = core_stats->dc;
dc                212 drivers/gpu/drm/amd/display/modules/stats/stats.c 	logger = dc->ctx->logger;
dc                 30 drivers/gpu/drm/amd/display/modules/vmid/vmid.c 	struct dc *dc;
dc                 56 drivers/gpu/drm/amd/display/modules/vmid/vmid.c 	uint16_t ord = dc_get_vmid_use_vector(core_vmid->dc);
dc                113 drivers/gpu/drm/amd/display/modules/vmid/vmid.c 		dc_setup_vm_context(core_vmid->dc, &va_config, vmid);
dc                128 drivers/gpu/drm/amd/display/modules/vmid/vmid.c 		struct dc *dc,
dc                137 drivers/gpu/drm/amd/display/modules/vmid/vmid.c 	if (dc == NULL)
dc                145 drivers/gpu/drm/amd/display/modules/vmid/vmid.c 	core_vmid->dc = dc;
dc                 54 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	struct atmel_hlcdc_dc *dc;
dc                 68 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	struct regmap *regmap = crtc->dc->hlcdc->regmap;
dc                 78 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
dc                102 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
dc                104 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	if (!crtc->dc->desc->fixed_clksrc) {
dc                155 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
dc                164 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	return atmel_hlcdc_dc_mode_valid(crtc->dc, mode);
dc                172 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	struct regmap *regmap = crtc->dc->hlcdc->regmap;
dc                194 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
dc                207 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	struct regmap *regmap = crtc->dc->hlcdc->regmap;
dc                215 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
dc                312 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 		if (crtc->dc->desc->conflicting_output_formats)
dc                452 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	struct regmap *regmap = crtc->dc->hlcdc->regmap;
dc                463 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	struct regmap *regmap = crtc->dc->hlcdc->regmap;
dc                483 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	struct atmel_hlcdc_dc *dc = dev->dev_private;
dc                492 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	crtc->dc = dc;
dc                495 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 		if (!dc->layers[i])
dc                498 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 		switch (dc->layers[i]->desc->type) {
dc                500 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 			primary = atmel_hlcdc_layer_to_plane(dc->layers[i]);
dc                504 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 			cursor = atmel_hlcdc_layer_to_plane(dc->layers[i]);
dc                523 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 		if (dc->layers[i] &&
dc                524 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 		    dc->layers[i]->desc->type == ATMEL_HLCDC_OVERLAY_LAYER) {
dc                525 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 			overlay = atmel_hlcdc_layer_to_plane(dc->layers[i]);
dc                537 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 	dc->crtc = &crtc->base;
dc                495 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
dc                505 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	if (hsync_len > dc->desc->max_spw + 1 || hsync_len < 1)
dc                508 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	if (vsync_len > dc->desc->max_spw + 1 || vsync_len < 1)
dc                511 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	if (hfront_porch > dc->desc->max_hpw + 1 || hfront_porch < 1 ||
dc                512 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	    hback_porch > dc->desc->max_hpw + 1 || hback_porch < 1 ||
dc                516 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	if (vfront_porch > dc->desc->max_vpw + 1 || vfront_porch < 1 ||
dc                517 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	    vback_porch > dc->desc->max_vpw || vback_porch < 0 ||
dc                538 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	struct atmel_hlcdc_dc *dc = dev->dev_private;
dc                543 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
dc                544 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
dc                550 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 		atmel_hlcdc_crtc_irq(dc->crtc);
dc                554 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 			atmel_hlcdc_layer_irq(dc->layers[i]);
dc                576 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	struct atmel_hlcdc_dc *dc = dev->dev_private;
dc                591 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	spin_lock(&dc->commit.wait.lock);
dc                592 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	dc->commit.pending = false;
dc                593 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	wake_up_all_locked(&dc->commit.wait);
dc                594 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	spin_unlock(&dc->commit.wait.lock);
dc                611 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	struct atmel_hlcdc_dc *dc = dev->dev_private;
dc                630 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	spin_lock(&dc->commit.wait.lock);
dc                631 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	ret = wait_event_interruptible_locked(dc->commit.wait,
dc                632 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 					      !dc->commit.pending);
dc                634 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 		dc->commit.pending = true;
dc                635 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	spin_unlock(&dc->commit.wait.lock);
dc                646 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 		queue_work(dc->wq, &commit->work);
dc                667 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	struct atmel_hlcdc_dc *dc = dev->dev_private;
dc                690 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	dev->mode_config.min_width = dc->desc->min_width;
dc                691 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	dev->mode_config.min_height = dc->desc->min_height;
dc                692 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	dev->mode_config.max_width = dc->desc->max_width;
dc                693 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	dev->mode_config.max_height = dc->desc->max_height;
dc                703 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	struct atmel_hlcdc_dc *dc;
dc                717 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
dc                718 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	if (!dc)
dc                721 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0);
dc                722 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	if (!dc->wq)
dc                725 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	init_waitqueue_head(&dc->commit.wait);
dc                726 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	dc->desc = match->data;
dc                727 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	dc->hlcdc = dev_get_drvdata(dev->dev->parent);
dc                728 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	dev->dev_private = dc;
dc                730 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	if (dc->desc->fixed_clksrc) {
dc                731 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 		ret = clk_prepare_enable(dc->hlcdc->sys_clk);
dc                738 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	ret = clk_prepare_enable(dc->hlcdc->periph_clk);
dc                761 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	ret = drm_irq_install(dev, dc->hlcdc->irq);
dc                776 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	clk_disable_unprepare(dc->hlcdc->periph_clk);
dc                778 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	if (dc->desc->fixed_clksrc)
dc                779 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 		clk_disable_unprepare(dc->hlcdc->sys_clk);
dc                782 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	destroy_workqueue(dc->wq);
dc                789 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	struct atmel_hlcdc_dc *dc = dev->dev_private;
dc                791 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	flush_workqueue(dc->wq);
dc                803 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	clk_disable_unprepare(dc->hlcdc->periph_clk);
dc                804 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	if (dc->desc->fixed_clksrc)
dc                805 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 		clk_disable_unprepare(dc->hlcdc->sys_clk);
dc                806 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	destroy_workqueue(dc->wq);
dc                811 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	struct atmel_hlcdc_dc *dc = dev->dev_private;
dc                817 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 		if (dc->layers[i])
dc                821 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
dc                828 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	struct atmel_hlcdc_dc *dc = dev->dev_private;
dc                831 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
dc                832 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
dc                906 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	struct atmel_hlcdc_dc *dc = drm_dev->dev_private;
dc                907 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	struct regmap *regmap = dc->hlcdc->regmap;
dc                914 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	dc->suspend.state = state;
dc                916 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	regmap_read(regmap, ATMEL_HLCDC_IMR, &dc->suspend.imr);
dc                917 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	regmap_write(regmap, ATMEL_HLCDC_IDR, dc->suspend.imr);
dc                918 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	clk_disable_unprepare(dc->hlcdc->periph_clk);
dc                919 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	if (dc->desc->fixed_clksrc)
dc                920 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 		clk_disable_unprepare(dc->hlcdc->sys_clk);
dc                928 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	struct atmel_hlcdc_dc *dc = drm_dev->dev_private;
dc                930 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	if (dc->desc->fixed_clksrc)
dc                931 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 		clk_prepare_enable(dc->hlcdc->sys_clk);
dc                932 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	clk_prepare_enable(dc->hlcdc->periph_clk);
dc                933 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, dc->suspend.imr);
dc                935 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 	return drm_atomic_helper_resume(drm_dev, dc->suspend.state);
dc                407 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
dc                844 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 	struct atmel_hlcdc_dc *dc = p->dev->dev_private;
dc                851 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 		dscr = dma_pool_alloc(dc->dscrpool, GFP_KERNEL, &dscr_dma);
dc                867 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 		dma_pool_free(dc->dscrpool, state->dscrs[i],
dc                927 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 	struct atmel_hlcdc_dc *dc = p->dev->dev_private;
dc                931 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 		dma_pool_free(dc->dscrpool, state->dscrs[i],
dc                953 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 	struct atmel_hlcdc_dc *dc = dev->dev_private;
dc                962 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 	atmel_hlcdc_layer_init(&plane->layer, desc, dc->hlcdc->regmap);
dc                987 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 	dc->layers[desc->id] = &plane->layer;
dc                994 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 	struct atmel_hlcdc_dc *dc = dev->dev_private;
dc                995 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 	const struct atmel_hlcdc_layer_desc *descs = dc->desc->layers;
dc                996 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 	int nlayers = dc->desc->nlayers;
dc                999 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 	dc->dscrpool = dmam_pool_create("atmel-hlcdc-dscr", dev->dev,
dc               1002 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 	if (!dc->dscrpool)
dc                264 drivers/gpu/drm/drm_mipi_dbi.c 	if (!dbi->dc || !full || swap ||
dc                770 drivers/gpu/drm/drm_mipi_dbi.c static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
dc                788 drivers/gpu/drm/drm_mipi_dbi.c 			 __func__, dc, max_chunk);
dc                793 drivers/gpu/drm/drm_mipi_dbi.c 	if (!dc) {
dc                888 drivers/gpu/drm/drm_mipi_dbi.c static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
dc                904 drivers/gpu/drm/drm_mipi_dbi.c 		return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
dc                912 drivers/gpu/drm/drm_mipi_dbi.c 			 __func__, dc, max_chunk);
dc                927 drivers/gpu/drm/drm_mipi_dbi.c 				if (dc) {
dc                935 drivers/gpu/drm/drm_mipi_dbi.c 				if (dc)
dc               1011 drivers/gpu/drm/drm_mipi_dbi.c 	gpiod_set_value_cansleep(dbi->dc, 0);
dc               1048 drivers/gpu/drm/drm_mipi_dbi.c 	gpiod_set_value_cansleep(dbi->dc, 0);
dc               1057 drivers/gpu/drm/drm_mipi_dbi.c 	gpiod_set_value_cansleep(dbi->dc, 1);
dc               1086 drivers/gpu/drm/drm_mipi_dbi.c 		      struct gpio_desc *dc)
dc               1112 drivers/gpu/drm/drm_mipi_dbi.c 	if (dc) {
dc               1114 drivers/gpu/drm/drm_mipi_dbi.c 		dbi->dc = dc;
dc                 38 drivers/gpu/drm/imx/ipuv3-crtc.c 	struct ipu_dc		*dc;
dc                 57 drivers/gpu/drm/imx/ipuv3-crtc.c 	ipu_dc_enable_channel(ipu_crtc->dc);
dc                 87 drivers/gpu/drm/imx/ipuv3-crtc.c 	ipu_dc_disable_channel(ipu_crtc->dc);
dc                310 drivers/gpu/drm/imx/ipuv3-crtc.c 	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
dc                328 drivers/gpu/drm/imx/ipuv3-crtc.c 	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
dc                329 drivers/gpu/drm/imx/ipuv3-crtc.c 		ipu_dc_put(ipu_crtc->dc);
dc                340 drivers/gpu/drm/imx/ipuv3-crtc.c 	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
dc                341 drivers/gpu/drm/imx/ipuv3-crtc.c 	if (IS_ERR(ipu_crtc->dc)) {
dc                342 drivers/gpu/drm/imx/ipuv3-crtc.c 		ret = PTR_ERR(ipu_crtc->dc);
dc               1565 drivers/gpu/drm/meson/meson_registers.h #define		VPU_RDARB_SLAVE_TO_MASTER_PORT(dc, port) (port << (16 + dc))
dc                 25 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h 	u8 dc;
dc                122 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 		ior->func->dp.drive(ior, i, ocfg.pc, ocfg.dc,
dc                 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h 			      int dc, int pe, int tx_pu);
dc                 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c g94_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
dc                 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));
dc                 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
dc                 83 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c 	nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));
dc                 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c gm200_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
dc                 41 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c 	nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));
dc                181 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c 			info->dc    = nvbios_rd08(bios, data + 0x02);
dc                189 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c 			info->dc    = nvbios_rd08(bios, data + 0x01);
dc                194 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c 			info->dc    = nvbios_rd08(bios, data + 0x00);
dc                 43 drivers/gpu/drm/tegra/dc.c static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
dc                 47 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
dc                 48 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, offset);
dc                 49 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
dc                 72 drivers/gpu/drm/tegra/dc.c 	dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
dc                 80 drivers/gpu/drm/tegra/dc.c 	return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
dc                 86 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
dc                 89 drivers/gpu/drm/tegra/dc.c bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
dc                 91 drivers/gpu/drm/tegra/dc.c 	struct device_node *np = dc->dev->of_node;
dc                114 drivers/gpu/drm/tegra/dc.c void tegra_dc_commit(struct tegra_dc *dc)
dc                116 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
dc                117 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
dc                310 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = plane->dc;
dc                315 drivers/gpu/drm/tegra/dc.c 	if (plane->index == 0 && dc->soc->has_win_a_without_filters)
dc                325 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = plane->dc;
dc                330 drivers/gpu/drm/tegra/dc.c 	if (plane->index == 0 && dc->soc->has_win_a_without_filters)
dc                333 drivers/gpu/drm/tegra/dc.c 	if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
dc                343 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = plane->dc;
dc                413 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->supports_block_linear) {
dc                516 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->has_legacy_blending)
dc                607 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = to_tegra_dc(state->crtc);
dc                626 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->has_legacy_blending) {
dc                637 drivers/gpu/drm/tegra/dc.c 	    !dc->soc->supports_block_linear) {
dc                758 drivers/gpu/drm/tegra/dc.c 						    struct tegra_dc *dc)
dc                775 drivers/gpu/drm/tegra/dc.c 	plane->dc = dc;
dc                777 drivers/gpu/drm/tegra/dc.c 	num_formats = dc->soc->num_primary_formats;
dc                778 drivers/gpu/drm/tegra/dc.c 	formats = dc->soc->primary_formats;
dc                779 drivers/gpu/drm/tegra/dc.c 	modifiers = dc->soc->modifiers;
dc                797 drivers/gpu/drm/tegra/dc.c 		dev_err(dc->dev, "failed to create rotation property: %d\n",
dc                841 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
dc                873 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
dc                877 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
dc                881 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
dc                883 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
dc                885 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
dc                892 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
dc                896 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
dc                902 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc;
dc                909 drivers/gpu/drm/tegra/dc.c 	dc = to_tegra_dc(old_state->crtc);
dc                911 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
dc                913 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
dc                923 drivers/gpu/drm/tegra/dc.c 						      struct tegra_dc *dc)
dc                943 drivers/gpu/drm/tegra/dc.c 	plane->dc = dc;
dc               1039 drivers/gpu/drm/tegra/dc.c 						       struct tegra_dc *dc,
dc               1056 drivers/gpu/drm/tegra/dc.c 	plane->dc = dc;
dc               1058 drivers/gpu/drm/tegra/dc.c 	num_formats = dc->soc->num_overlay_formats;
dc               1059 drivers/gpu/drm/tegra/dc.c 	formats = dc->soc->overlay_formats;
dc               1082 drivers/gpu/drm/tegra/dc.c 		dev_err(dc->dev, "failed to create rotation property: %d\n",
dc               1089 drivers/gpu/drm/tegra/dc.c 						    struct tegra_dc *dc)
dc               1094 drivers/gpu/drm/tegra/dc.c 	for (i = 0; i < dc->soc->num_wgrps; i++) {
dc               1095 drivers/gpu/drm/tegra/dc.c 		const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
dc               1097 drivers/gpu/drm/tegra/dc.c 		if (wgrp->dc == dc->pipe) {
dc               1101 drivers/gpu/drm/tegra/dc.c 				plane = tegra_shared_plane_create(drm, dc,
dc               1123 drivers/gpu/drm/tegra/dc.c 					     struct tegra_dc *dc)
dc               1130 drivers/gpu/drm/tegra/dc.c 	primary = tegra_primary_plane_create(drm, dc);
dc               1134 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->supports_cursor)
dc               1140 drivers/gpu/drm/tegra/dc.c 		planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
dc               1418 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = node->info_ent->data;
dc               1422 drivers/gpu/drm/tegra/dc.c 	drm_modeset_lock(&dc->base.mutex, NULL);
dc               1424 drivers/gpu/drm/tegra/dc.c 	if (!dc->base.state->active) {
dc               1433 drivers/gpu/drm/tegra/dc.c 			   offset, tegra_dc_readl(dc, offset));
dc               1437 drivers/gpu/drm/tegra/dc.c 	drm_modeset_unlock(&dc->base.mutex);
dc               1444 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = node->info_ent->data;
dc               1448 drivers/gpu/drm/tegra/dc.c 	drm_modeset_lock(&dc->base.mutex, NULL);
dc               1450 drivers/gpu/drm/tegra/dc.c 	if (!dc->base.state->active) {
dc               1456 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
dc               1457 drivers/gpu/drm/tegra/dc.c 	tegra_dc_commit(dc);
dc               1459 drivers/gpu/drm/tegra/dc.c 	drm_crtc_wait_one_vblank(&dc->base);
dc               1460 drivers/gpu/drm/tegra/dc.c 	drm_crtc_wait_one_vblank(&dc->base);
dc               1462 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
dc               1465 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
dc               1468 drivers/gpu/drm/tegra/dc.c 	drm_modeset_unlock(&dc->base.mutex);
dc               1475 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = node->info_ent->data;
dc               1477 drivers/gpu/drm/tegra/dc.c 	seq_printf(s, "frames: %lu\n", dc->stats.frames);
dc               1478 drivers/gpu/drm/tegra/dc.c 	seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
dc               1479 drivers/gpu/drm/tegra/dc.c 	seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
dc               1480 drivers/gpu/drm/tegra/dc.c 	seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
dc               1496 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = to_tegra_dc(crtc);
dc               1505 drivers/gpu/drm/tegra/dc.c 	dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
dc               1507 drivers/gpu/drm/tegra/dc.c 	if (!dc->debugfs_files)
dc               1511 drivers/gpu/drm/tegra/dc.c 		dc->debugfs_files[i].data = dc;
dc               1513 drivers/gpu/drm/tegra/dc.c 	err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
dc               1520 drivers/gpu/drm/tegra/dc.c 	kfree(dc->debugfs_files);
dc               1521 drivers/gpu/drm/tegra/dc.c 	dc->debugfs_files = NULL;
dc               1530 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = to_tegra_dc(crtc);
dc               1532 drivers/gpu/drm/tegra/dc.c 	drm_debugfs_remove_files(dc->debugfs_files, count, minor);
dc               1533 drivers/gpu/drm/tegra/dc.c 	kfree(dc->debugfs_files);
dc               1534 drivers/gpu/drm/tegra/dc.c 	dc->debugfs_files = NULL;
dc               1539 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = to_tegra_dc(crtc);
dc               1542 drivers/gpu/drm/tegra/dc.c 	if (dc->syncpt && !dc->soc->has_nvdisplay)
dc               1543 drivers/gpu/drm/tegra/dc.c 		return host1x_syncpt_read(dc->syncpt);
dc               1546 drivers/gpu/drm/tegra/dc.c 	return (u32)drm_crtc_vblank_count(&dc->base);
dc               1551 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = to_tegra_dc(crtc);
dc               1554 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
dc               1556 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
dc               1563 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = to_tegra_dc(crtc);
dc               1566 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
dc               1568 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
dc               1585 drivers/gpu/drm/tegra/dc.c static int tegra_dc_set_timings(struct tegra_dc *dc,
dc               1592 drivers/gpu/drm/tegra/dc.c 	if (!dc->soc->has_nvdisplay) {
dc               1593 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
dc               1596 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
dc               1601 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
dc               1605 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
dc               1609 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
dc               1612 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
dc               1629 drivers/gpu/drm/tegra/dc.c int tegra_dc_state_setup_clock(struct tegra_dc *dc,
dc               1636 drivers/gpu/drm/tegra/dc.c 	if (!clk_has_parent(dc->clk, clk))
dc               1646 drivers/gpu/drm/tegra/dc.c static void tegra_dc_commit_state(struct tegra_dc *dc,
dc               1652 drivers/gpu/drm/tegra/dc.c 	err = clk_set_parent(dc->clk, state->clk);
dc               1654 drivers/gpu/drm/tegra/dc.c 		dev_err(dc->dev, "failed to set parent clock: %d\n", err);
dc               1667 drivers/gpu/drm/tegra/dc.c 			dev_err(dc->dev,
dc               1672 drivers/gpu/drm/tegra/dc.c 	DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
dc               1676 drivers/gpu/drm/tegra/dc.c 	if (!dc->soc->has_nvdisplay) {
dc               1678 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
dc               1681 drivers/gpu/drm/tegra/dc.c 	err = clk_set_rate(dc->clk, state->pclk);
dc               1683 drivers/gpu/drm/tegra/dc.c 		dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
dc               1684 drivers/gpu/drm/tegra/dc.c 			dc->clk, state->pclk, err);
dc               1687 drivers/gpu/drm/tegra/dc.c static void tegra_dc_stop(struct tegra_dc *dc)
dc               1692 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
dc               1694 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
dc               1696 drivers/gpu/drm/tegra/dc.c 	tegra_dc_commit(dc);
dc               1699 drivers/gpu/drm/tegra/dc.c static bool tegra_dc_idle(struct tegra_dc *dc)
dc               1703 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
dc               1708 drivers/gpu/drm/tegra/dc.c static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
dc               1713 drivers/gpu/drm/tegra/dc.c 		if (tegra_dc_idle(dc))
dc               1719 drivers/gpu/drm/tegra/dc.c 	dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
dc               1726 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = to_tegra_dc(crtc);
dc               1729 drivers/gpu/drm/tegra/dc.c 	if (!tegra_dc_idle(dc)) {
dc               1730 drivers/gpu/drm/tegra/dc.c 		tegra_dc_stop(dc);
dc               1736 drivers/gpu/drm/tegra/dc.c 		tegra_dc_wait_idle(dc, 100);
dc               1755 drivers/gpu/drm/tegra/dc.c 	if (dc->rgb) {
dc               1756 drivers/gpu/drm/tegra/dc.c 		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
dc               1759 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
dc               1762 drivers/gpu/drm/tegra/dc.c 	tegra_dc_stats_reset(&dc->stats);
dc               1774 drivers/gpu/drm/tegra/dc.c 	pm_runtime_put_sync(dc->dev);
dc               1782 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = to_tegra_dc(crtc);
dc               1785 drivers/gpu/drm/tegra/dc.c 	pm_runtime_get_sync(dc->dev);
dc               1788 drivers/gpu/drm/tegra/dc.c 	if (dc->syncpt) {
dc               1789 drivers/gpu/drm/tegra/dc.c 		u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
dc               1791 drivers/gpu/drm/tegra/dc.c 		if (dc->soc->has_nvdisplay)
dc               1797 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
dc               1800 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
dc               1803 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->has_nvdisplay) {
dc               1806 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
dc               1813 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
dc               1817 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
dc               1820 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
dc               1822 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
dc               1826 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
dc               1830 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
dc               1835 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
dc               1839 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
dc               1843 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
dc               1847 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
dc               1850 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->supports_background_color)
dc               1851 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
dc               1853 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
dc               1856 drivers/gpu/drm/tegra/dc.c 	tegra_dc_commit_state(dc, state);
dc               1859 drivers/gpu/drm/tegra/dc.c 	tegra_dc_set_timings(dc, mode);
dc               1862 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->supports_interlacing) {
dc               1863 drivers/gpu/drm/tegra/dc.c 		value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
dc               1865 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
dc               1868 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
dc               1871 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
dc               1873 drivers/gpu/drm/tegra/dc.c 	if (!dc->soc->has_nvdisplay) {
dc               1874 drivers/gpu/drm/tegra/dc.c 		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
dc               1877 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
dc               1881 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->has_nvdisplay) {
dc               1883 drivers/gpu/drm/tegra/dc.c 		tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
dc               1886 drivers/gpu/drm/tegra/dc.c 	tegra_dc_commit(dc);
dc               1914 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = to_tegra_dc(crtc);
dc               1918 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
dc               1919 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
dc               1922 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
dc               1923 drivers/gpu/drm/tegra/dc.c 	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
dc               1935 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = data;
dc               1938 drivers/gpu/drm/tegra/dc.c 	status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
dc               1939 drivers/gpu/drm/tegra/dc.c 	tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
dc               1945 drivers/gpu/drm/tegra/dc.c 		dc->stats.frames++;
dc               1952 drivers/gpu/drm/tegra/dc.c 		drm_crtc_handle_vblank(&dc->base);
dc               1953 drivers/gpu/drm/tegra/dc.c 		dc->stats.vblank++;
dc               1960 drivers/gpu/drm/tegra/dc.c 		dc->stats.underflow++;
dc               1967 drivers/gpu/drm/tegra/dc.c 		dc->stats.overflow++;
dc               1971 drivers/gpu/drm/tegra/dc.c 		dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
dc               1972 drivers/gpu/drm/tegra/dc.c 		dc->stats.underflow++;
dc               1978 drivers/gpu/drm/tegra/dc.c static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
dc               1982 drivers/gpu/drm/tegra/dc.c 	if (!dc->soc->wgrps)
dc               1985 drivers/gpu/drm/tegra/dc.c 	for (i = 0; i < dc->soc->num_wgrps; i++) {
dc               1986 drivers/gpu/drm/tegra/dc.c 		const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
dc               1988 drivers/gpu/drm/tegra/dc.c 		if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
dc               1999 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = host1x_client_to_dc(client);
dc               2010 drivers/gpu/drm/tegra/dc.c 	if (!tegra_dc_has_window_groups(dc))
dc               2013 drivers/gpu/drm/tegra/dc.c 	dc->syncpt = host1x_syncpt_request(client, flags);
dc               2014 drivers/gpu/drm/tegra/dc.c 	if (!dc->syncpt)
dc               2015 drivers/gpu/drm/tegra/dc.c 		dev_warn(dc->dev, "failed to allocate syncpoint\n");
dc               2017 drivers/gpu/drm/tegra/dc.c 	dc->group = host1x_client_iommu_attach(client, true);
dc               2018 drivers/gpu/drm/tegra/dc.c 	if (IS_ERR(dc->group)) {
dc               2019 drivers/gpu/drm/tegra/dc.c 		err = PTR_ERR(dc->group);
dc               2024 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->wgrps)
dc               2025 drivers/gpu/drm/tegra/dc.c 		primary = tegra_dc_add_shared_planes(drm, dc);
dc               2027 drivers/gpu/drm/tegra/dc.c 		primary = tegra_dc_add_planes(drm, dc);
dc               2034 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->supports_cursor) {
dc               2035 drivers/gpu/drm/tegra/dc.c 		cursor = tegra_dc_cursor_plane_create(drm, dc);
dc               2042 drivers/gpu/drm/tegra/dc.c 		cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
dc               2049 drivers/gpu/drm/tegra/dc.c 	err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
dc               2054 drivers/gpu/drm/tegra/dc.c 	drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
dc               2060 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->pitch_align > tegra->pitch_align)
dc               2061 drivers/gpu/drm/tegra/dc.c 		tegra->pitch_align = dc->soc->pitch_align;
dc               2063 drivers/gpu/drm/tegra/dc.c 	err = tegra_dc_rgb_init(drm, dc);
dc               2065 drivers/gpu/drm/tegra/dc.c 		dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
dc               2069 drivers/gpu/drm/tegra/dc.c 	err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
dc               2070 drivers/gpu/drm/tegra/dc.c 			       dev_name(dc->dev), dc);
dc               2072 drivers/gpu/drm/tegra/dc.c 		dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
dc               2086 drivers/gpu/drm/tegra/dc.c 	host1x_client_iommu_detach(client, dc->group);
dc               2087 drivers/gpu/drm/tegra/dc.c 	host1x_syncpt_free(dc->syncpt);
dc               2094 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = host1x_client_to_dc(client);
dc               2097 drivers/gpu/drm/tegra/dc.c 	if (!tegra_dc_has_window_groups(dc))
dc               2100 drivers/gpu/drm/tegra/dc.c 	devm_free_irq(dc->dev, dc->irq, dc);
dc               2102 drivers/gpu/drm/tegra/dc.c 	err = tegra_dc_rgb_exit(dc);
dc               2104 drivers/gpu/drm/tegra/dc.c 		dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
dc               2108 drivers/gpu/drm/tegra/dc.c 	host1x_client_iommu_detach(client, dc->group);
dc               2109 drivers/gpu/drm/tegra/dc.c 	host1x_syncpt_free(dc->syncpt);
dc               2217 drivers/gpu/drm/tegra/dc.c 		.dc = 0,
dc               2222 drivers/gpu/drm/tegra/dc.c 		.dc = 1,
dc               2227 drivers/gpu/drm/tegra/dc.c 		.dc = 1,
dc               2232 drivers/gpu/drm/tegra/dc.c 		.dc = 2,
dc               2237 drivers/gpu/drm/tegra/dc.c 		.dc = 2,
dc               2242 drivers/gpu/drm/tegra/dc.c 		.dc = 2,
dc               2265 drivers/gpu/drm/tegra/dc.c 		.dc = 0,
dc               2270 drivers/gpu/drm/tegra/dc.c 		.dc = 1,
dc               2275 drivers/gpu/drm/tegra/dc.c 		.dc = 1,
dc               2280 drivers/gpu/drm/tegra/dc.c 		.dc = 2,
dc               2285 drivers/gpu/drm/tegra/dc.c 		.dc = 2,
dc               2290 drivers/gpu/drm/tegra/dc.c 		.dc = 2,
dc               2338 drivers/gpu/drm/tegra/dc.c static int tegra_dc_parse_dt(struct tegra_dc *dc)
dc               2344 drivers/gpu/drm/tegra/dc.c 	err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
dc               2346 drivers/gpu/drm/tegra/dc.c 		dev_err(dc->dev, "missing \"nvidia,head\" property\n");
dc               2361 drivers/gpu/drm/tegra/dc.c 			if (np == dc->dev->of_node) {
dc               2370 drivers/gpu/drm/tegra/dc.c 	dc->pipe = value;
dc               2377 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = dev_get_drvdata(dev);
dc               2380 drivers/gpu/drm/tegra/dc.c 	return dc->pipe == pipe;
dc               2383 drivers/gpu/drm/tegra/dc.c static int tegra_dc_couple(struct tegra_dc *dc)
dc               2390 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->coupled_pm && dc->pipe == 1) {
dc               2395 drivers/gpu/drm/tegra/dc.c 		partner = driver_find_device(dc->dev->driver, NULL, NULL,
dc               2400 drivers/gpu/drm/tegra/dc.c 		link = device_link_add(dc->dev, partner, flags);
dc               2402 drivers/gpu/drm/tegra/dc.c 			dev_err(dc->dev, "failed to link controllers\n");
dc               2406 drivers/gpu/drm/tegra/dc.c 		dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
dc               2415 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc;
dc               2418 drivers/gpu/drm/tegra/dc.c 	dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
dc               2419 drivers/gpu/drm/tegra/dc.c 	if (!dc)
dc               2422 drivers/gpu/drm/tegra/dc.c 	dc->soc = of_device_get_match_data(&pdev->dev);
dc               2424 drivers/gpu/drm/tegra/dc.c 	INIT_LIST_HEAD(&dc->list);
dc               2425 drivers/gpu/drm/tegra/dc.c 	dc->dev = &pdev->dev;
dc               2427 drivers/gpu/drm/tegra/dc.c 	err = tegra_dc_parse_dt(dc);
dc               2431 drivers/gpu/drm/tegra/dc.c 	err = tegra_dc_couple(dc);
dc               2435 drivers/gpu/drm/tegra/dc.c 	dc->clk = devm_clk_get(&pdev->dev, NULL);
dc               2436 drivers/gpu/drm/tegra/dc.c 	if (IS_ERR(dc->clk)) {
dc               2438 drivers/gpu/drm/tegra/dc.c 		return PTR_ERR(dc->clk);
dc               2441 drivers/gpu/drm/tegra/dc.c 	dc->rst = devm_reset_control_get(&pdev->dev, "dc");
dc               2442 drivers/gpu/drm/tegra/dc.c 	if (IS_ERR(dc->rst)) {
dc               2444 drivers/gpu/drm/tegra/dc.c 		return PTR_ERR(dc->rst);
dc               2448 drivers/gpu/drm/tegra/dc.c 	err = clk_prepare_enable(dc->clk);
dc               2454 drivers/gpu/drm/tegra/dc.c 	err = reset_control_assert(dc->rst);
dc               2460 drivers/gpu/drm/tegra/dc.c 	clk_disable_unprepare(dc->clk);
dc               2462 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->has_powergate) {
dc               2463 drivers/gpu/drm/tegra/dc.c 		if (dc->pipe == 0)
dc               2464 drivers/gpu/drm/tegra/dc.c 			dc->powergate = TEGRA_POWERGATE_DIS;
dc               2466 drivers/gpu/drm/tegra/dc.c 			dc->powergate = TEGRA_POWERGATE_DISB;
dc               2468 drivers/gpu/drm/tegra/dc.c 		tegra_powergate_power_off(dc->powergate);
dc               2472 drivers/gpu/drm/tegra/dc.c 	dc->regs = devm_ioremap_resource(&pdev->dev, regs);
dc               2473 drivers/gpu/drm/tegra/dc.c 	if (IS_ERR(dc->regs))
dc               2474 drivers/gpu/drm/tegra/dc.c 		return PTR_ERR(dc->regs);
dc               2476 drivers/gpu/drm/tegra/dc.c 	dc->irq = platform_get_irq(pdev, 0);
dc               2477 drivers/gpu/drm/tegra/dc.c 	if (dc->irq < 0) {
dc               2482 drivers/gpu/drm/tegra/dc.c 	err = tegra_dc_rgb_probe(dc);
dc               2488 drivers/gpu/drm/tegra/dc.c 	platform_set_drvdata(pdev, dc);
dc               2491 drivers/gpu/drm/tegra/dc.c 	INIT_LIST_HEAD(&dc->client.list);
dc               2492 drivers/gpu/drm/tegra/dc.c 	dc->client.ops = &dc_client_ops;
dc               2493 drivers/gpu/drm/tegra/dc.c 	dc->client.dev = &pdev->dev;
dc               2495 drivers/gpu/drm/tegra/dc.c 	err = host1x_client_register(&dc->client);
dc               2507 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = platform_get_drvdata(pdev);
dc               2510 drivers/gpu/drm/tegra/dc.c 	err = host1x_client_unregister(&dc->client);
dc               2517 drivers/gpu/drm/tegra/dc.c 	err = tegra_dc_rgb_remove(dc);
dc               2531 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = dev_get_drvdata(dev);
dc               2534 drivers/gpu/drm/tegra/dc.c 	err = reset_control_assert(dc->rst);
dc               2540 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->has_powergate)
dc               2541 drivers/gpu/drm/tegra/dc.c 		tegra_powergate_power_off(dc->powergate);
dc               2543 drivers/gpu/drm/tegra/dc.c 	clk_disable_unprepare(dc->clk);
dc               2550 drivers/gpu/drm/tegra/dc.c 	struct tegra_dc *dc = dev_get_drvdata(dev);
dc               2553 drivers/gpu/drm/tegra/dc.c 	if (dc->soc->has_powergate) {
dc               2554 drivers/gpu/drm/tegra/dc.c 		err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
dc               2555 drivers/gpu/drm/tegra/dc.c 							dc->rst);
dc               2561 drivers/gpu/drm/tegra/dc.c 		err = clk_prepare_enable(dc->clk);
dc               2567 drivers/gpu/drm/tegra/dc.c 		err = reset_control_deassert(dc->rst);
dc                 45 drivers/gpu/drm/tegra/dc.h 	unsigned int dc;
dc                108 drivers/gpu/drm/tegra/dc.h static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value,
dc                111 drivers/gpu/drm/tegra/dc.h 	trace_dc_writel(dc->dev, offset, value);
dc                112 drivers/gpu/drm/tegra/dc.h 	writel(value, dc->regs + (offset << 2));
dc                115 drivers/gpu/drm/tegra/dc.h static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset)
dc                117 drivers/gpu/drm/tegra/dc.h 	u32 value = readl(dc->regs + (offset << 2));
dc                119 drivers/gpu/drm/tegra/dc.h 	trace_dc_readl(dc->dev, offset, value);
dc                149 drivers/gpu/drm/tegra/dc.h bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev);
dc                150 drivers/gpu/drm/tegra/dc.h void tegra_dc_commit(struct tegra_dc *dc);
dc                151 drivers/gpu/drm/tegra/dc.h int tegra_dc_state_setup_clock(struct tegra_dc *dc,
dc                157 drivers/gpu/drm/tegra/dc.h int tegra_dc_rgb_probe(struct tegra_dc *dc);
dc                158 drivers/gpu/drm/tegra/dc.h int tegra_dc_rgb_remove(struct tegra_dc *dc);
dc                159 drivers/gpu/drm/tegra/dc.h int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);
dc                160 drivers/gpu/drm/tegra/dc.h int tegra_dc_rgb_exit(struct tegra_dc *dc);
dc                849 drivers/gpu/drm/tegra/dsi.c 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
dc                863 drivers/gpu/drm/tegra/dsi.c 	if (dc) {
dc                864 drivers/gpu/drm/tegra/dsi.c 		value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
dc                866 drivers/gpu/drm/tegra/dsi.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
dc                868 drivers/gpu/drm/tegra/dsi.c 		tegra_dc_commit(dc);
dc                908 drivers/gpu/drm/tegra/dsi.c 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
dc                928 drivers/gpu/drm/tegra/dsi.c 	tegra_dsi_configure(dsi, dc->pipe, mode);
dc                931 drivers/gpu/drm/tegra/dsi.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
dc                933 drivers/gpu/drm/tegra/dsi.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
dc                935 drivers/gpu/drm/tegra/dsi.c 	tegra_dc_commit(dc);
dc                951 drivers/gpu/drm/tegra/dsi.c 	struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
dc               1015 drivers/gpu/drm/tegra/dsi.c 	err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
dc               1146 drivers/gpu/drm/tegra/hdmi.c 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
dc               1154 drivers/gpu/drm/tegra/hdmi.c 	if (dc) {
dc               1155 drivers/gpu/drm/tegra/hdmi.c 		value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
dc               1157 drivers/gpu/drm/tegra/hdmi.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
dc               1159 drivers/gpu/drm/tegra/hdmi.c 		tegra_dc_commit(dc);
dc               1182 drivers/gpu/drm/tegra/hdmi.c 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
dc               1223 drivers/gpu/drm/tegra/hdmi.c 	tegra_dc_writel(dc, VSYNC_H_POSITION(1),
dc               1225 drivers/gpu/drm/tegra/hdmi.c 	tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
dc               1231 drivers/gpu/drm/tegra/hdmi.c 	tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
dc               1235 drivers/gpu/drm/tegra/hdmi.c 	tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
dc               1238 drivers/gpu/drm/tegra/hdmi.c 	tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
dc               1244 drivers/gpu/drm/tegra/hdmi.c 	if (dc->pipe)
dc               1380 drivers/gpu/drm/tegra/hdmi.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
dc               1382 drivers/gpu/drm/tegra/hdmi.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
dc               1384 drivers/gpu/drm/tegra/hdmi.c 	tegra_dc_commit(dc);
dc               1404 drivers/gpu/drm/tegra/hdmi.c 	struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
dc               1409 drivers/gpu/drm/tegra/hdmi.c 	err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
dc                 79 drivers/gpu/drm/tegra/hub.c 	dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
dc                 87 drivers/gpu/drm/tegra/hub.c 	return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
dc                 93 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
dc                167 drivers/gpu/drm/tegra/hub.c 	struct tegra_dc *dc = plane->dc;
dc                172 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
dc                177 drivers/gpu/drm/tegra/hub.c 		value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
dc                187 drivers/gpu/drm/tegra/hub.c 	struct tegra_dc *dc = plane->dc;
dc                192 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
dc                197 drivers/gpu/drm/tegra/hub.c 		value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
dc                206 drivers/gpu/drm/tegra/hub.c tegra_shared_plane_get_owner(struct tegra_plane *plane, struct tegra_dc *dc)
dc                211 drivers/gpu/drm/tegra/hub.c 	return tegra_dc_readl(dc, offset) & OWNER_MASK;
dc                214 drivers/gpu/drm/tegra/hub.c static bool tegra_dc_owns_shared_plane(struct tegra_dc *dc,
dc                217 drivers/gpu/drm/tegra/hub.c 	struct device *dev = dc->dev;
dc                219 drivers/gpu/drm/tegra/hub.c 	if (tegra_shared_plane_get_owner(plane, dc) == dc->pipe) {
dc                220 drivers/gpu/drm/tegra/hub.c 		if (plane->dc == dc)
dc                224 drivers/gpu/drm/tegra/hub.c 			 dc->pipe, plane->index);
dc                235 drivers/gpu/drm/tegra/hub.c 	struct tegra_dc *old = plane->dc, *dc = new ? new : old;
dc                240 drivers/gpu/drm/tegra/hub.c 	value = tegra_dc_readl(dc, offset);
dc                264 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, value, offset);
dc                266 drivers/gpu/drm/tegra/hub.c 	plane->dc = new;
dc                271 drivers/gpu/drm/tegra/hub.c static void tegra_dc_assign_shared_plane(struct tegra_dc *dc,
dc                277 drivers/gpu/drm/tegra/hub.c 	if (!tegra_dc_owns_shared_plane(dc, plane)) {
dc                278 drivers/gpu/drm/tegra/hub.c 		err = tegra_shared_plane_set_owner(plane, dc);
dc                320 drivers/gpu/drm/tegra/hub.c static void tegra_dc_remove_shared_plane(struct tegra_dc *dc,
dc                332 drivers/gpu/drm/tegra/hub.c 	struct tegra_dc *dc = to_tegra_dc(state->crtc);
dc                350 drivers/gpu/drm/tegra/hub.c 	    !dc->soc->supports_block_linear) {
dc                380 drivers/gpu/drm/tegra/hub.c 	struct tegra_dc *dc;
dc                387 drivers/gpu/drm/tegra/hub.c 	dc = to_tegra_dc(old_state->crtc);
dc                394 drivers/gpu/drm/tegra/hub.c 	if (WARN_ON(p->dc == NULL))
dc                395 drivers/gpu/drm/tegra/hub.c 		p->dc = dc;
dc                397 drivers/gpu/drm/tegra/hub.c 	pm_runtime_get_sync(dc->dev);
dc                403 drivers/gpu/drm/tegra/hub.c 	tegra_dc_remove_shared_plane(dc, p);
dc                405 drivers/gpu/drm/tegra/hub.c 	pm_runtime_put(dc->dev);
dc                412 drivers/gpu/drm/tegra/hub.c 	struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
dc                429 drivers/gpu/drm/tegra/hub.c 	pm_runtime_get_sync(dc->dev);
dc                431 drivers/gpu/drm/tegra/hub.c 	tegra_dc_assign_shared_plane(dc, p);
dc                491 drivers/gpu/drm/tegra/hub.c 	if (dc->soc->supports_block_linear) {
dc                520 drivers/gpu/drm/tegra/hub.c 	pm_runtime_put(dc->dev);
dc                530 drivers/gpu/drm/tegra/hub.c 					    struct tegra_dc *dc,
dc                554 drivers/gpu/drm/tegra/hub.c 	plane->wgrp->parent = dc->dev;
dc                645 drivers/gpu/drm/tegra/hub.c 		struct tegra_dc_state *dc = to_dc_state(new);
dc                648 drivers/gpu/drm/tegra/hub.c 			if (!hub_state->clk || dc->pclk > hub_state->rate) {
dc                649 drivers/gpu/drm/tegra/hub.c 				hub_state->dc = to_tegra_dc(dc->base.crtc);
dc                650 drivers/gpu/drm/tegra/hub.c 				hub_state->clk = hub_state->dc->clk;
dc                651 drivers/gpu/drm/tegra/hub.c 				hub_state->rate = dc->pclk;
dc                659 drivers/gpu/drm/tegra/hub.c static void tegra_display_hub_update(struct tegra_dc *dc)
dc                663 drivers/gpu/drm/tegra/hub.c 	pm_runtime_get_sync(dc->dev);
dc                665 drivers/gpu/drm/tegra/hub.c 	value = tegra_dc_readl(dc, DC_CMD_IHUB_COMMON_MISC_CTL);
dc                667 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL);
dc                669 drivers/gpu/drm/tegra/hub.c 	value = tegra_dc_readl(dc, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
dc                671 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
dc                673 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL);
dc                674 drivers/gpu/drm/tegra/hub.c 	tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
dc                675 drivers/gpu/drm/tegra/hub.c 	tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL);
dc                676 drivers/gpu/drm/tegra/hub.c 	tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
dc                678 drivers/gpu/drm/tegra/hub.c 	pm_runtime_put(dc->dev);
dc                704 drivers/gpu/drm/tegra/hub.c 	if (hub_state->dc)
dc                705 drivers/gpu/drm/tegra/hub.c 		tegra_display_hub_update(hub_state->dc);
dc                 64 drivers/gpu/drm/tegra/hub.h 	struct tegra_dc *dc;
dc                 82 drivers/gpu/drm/tegra/hub.h 					    struct tegra_dc *dc,
dc                226 drivers/gpu/drm/tegra/output.c 		struct tegra_dc *dc = to_tegra_dc(crtc);
dc                228 drivers/gpu/drm/tegra/output.c 		if (tegra_dc_has_output(dc, dev))
dc                354 drivers/gpu/drm/tegra/plane.c 		if (p == tegra || p->dc != tegra->dc)
dc                398 drivers/gpu/drm/tegra/plane.c 		if (p == tegra || p->dc != tegra->dc)
dc                449 drivers/gpu/drm/tegra/plane.c 		if (p->dc != tegra->dc)
dc                 16 drivers/gpu/drm/tegra/plane.h 	struct tegra_dc *dc;
dc                 17 drivers/gpu/drm/tegra/rgb.c 	struct tegra_dc *dc;
dc                 77 drivers/gpu/drm/tegra/rgb.c static void tegra_dc_write_regs(struct tegra_dc *dc,
dc                 84 drivers/gpu/drm/tegra/rgb.c 		tegra_dc_writel(dc, table[i].value, table[i].offset);
dc                125 drivers/gpu/drm/tegra/rgb.c 	tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
dc                126 drivers/gpu/drm/tegra/rgb.c 	tegra_dc_commit(rgb->dc);
dc                141 drivers/gpu/drm/tegra/rgb.c 	tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
dc                144 drivers/gpu/drm/tegra/rgb.c 	tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
dc                147 drivers/gpu/drm/tegra/rgb.c 	value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
dc                150 drivers/gpu/drm/tegra/rgb.c 	tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
dc                155 drivers/gpu/drm/tegra/rgb.c 	tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
dc                159 drivers/gpu/drm/tegra/rgb.c 	tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
dc                161 drivers/gpu/drm/tegra/rgb.c 	tegra_dc_commit(rgb->dc);
dc                173 drivers/gpu/drm/tegra/rgb.c 	struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
dc                198 drivers/gpu/drm/tegra/rgb.c 	err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,
dc                214 drivers/gpu/drm/tegra/rgb.c int tegra_dc_rgb_probe(struct tegra_dc *dc)
dc                220 drivers/gpu/drm/tegra/rgb.c 	np = of_get_child_by_name(dc->dev->of_node, "rgb");
dc                224 drivers/gpu/drm/tegra/rgb.c 	rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
dc                228 drivers/gpu/drm/tegra/rgb.c 	rgb->output.dev = dc->dev;
dc                230 drivers/gpu/drm/tegra/rgb.c 	rgb->dc = dc;
dc                236 drivers/gpu/drm/tegra/rgb.c 	rgb->clk = devm_clk_get(dc->dev, NULL);
dc                238 drivers/gpu/drm/tegra/rgb.c 		dev_err(dc->dev, "failed to get clock\n");
dc                242 drivers/gpu/drm/tegra/rgb.c 	rgb->clk_parent = devm_clk_get(dc->dev, "parent");
dc                244 drivers/gpu/drm/tegra/rgb.c 		dev_err(dc->dev, "failed to get parent clock\n");
dc                250 drivers/gpu/drm/tegra/rgb.c 		dev_err(dc->dev, "failed to set parent clock: %d\n", err);
dc                254 drivers/gpu/drm/tegra/rgb.c 	dc->rgb = &rgb->output;
dc                259 drivers/gpu/drm/tegra/rgb.c int tegra_dc_rgb_remove(struct tegra_dc *dc)
dc                261 drivers/gpu/drm/tegra/rgb.c 	if (!dc->rgb)
dc                264 drivers/gpu/drm/tegra/rgb.c 	tegra_output_remove(dc->rgb);
dc                265 drivers/gpu/drm/tegra/rgb.c 	dc->rgb = NULL;
dc                270 drivers/gpu/drm/tegra/rgb.c int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
dc                272 drivers/gpu/drm/tegra/rgb.c 	struct tegra_output *output = dc->rgb;
dc                275 drivers/gpu/drm/tegra/rgb.c 	if (!dc->rgb)
dc                304 drivers/gpu/drm/tegra/rgb.c 	output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);
dc                309 drivers/gpu/drm/tegra/rgb.c int tegra_dc_rgb_exit(struct tegra_dc *dc)
dc                311 drivers/gpu/drm/tegra/rgb.c 	if (dc->rgb)
dc                312 drivers/gpu/drm/tegra/rgb.c 		tegra_output_exit(dc->rgb);
dc               1039 drivers/gpu/drm/tegra/sor.c 	struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
dc               1049 drivers/gpu/drm/tegra/sor.c 		 SOR_STATE_ASY_OWNER(dc->pipe + 1);
dc               1097 drivers/gpu/drm/tegra/sor.c 	tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
dc               1104 drivers/gpu/drm/tegra/sor.c 	tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
dc               1111 drivers/gpu/drm/tegra/sor.c 	tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
dc               1118 drivers/gpu/drm/tegra/sor.c 	tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
dc               1121 drivers/gpu/drm/tegra/sor.c 	tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
dc               1590 drivers/gpu/drm/tegra/sor.c 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
dc               1609 drivers/gpu/drm/tegra/sor.c 	if (dc) {
dc               1610 drivers/gpu/drm/tegra/sor.c 		value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
dc               1612 drivers/gpu/drm/tegra/sor.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
dc               1614 drivers/gpu/drm/tegra/sor.c 		tegra_dc_commit(dc);
dc               1683 drivers/gpu/drm/tegra/sor.c 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
dc               1966 drivers/gpu/drm/tegra/sor.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
dc               1968 drivers/gpu/drm/tegra/sor.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
dc               1970 drivers/gpu/drm/tegra/sor.c 	tegra_dc_commit(dc);
dc               1991 drivers/gpu/drm/tegra/sor.c 	struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
dc               2011 drivers/gpu/drm/tegra/sor.c 	err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
dc               2383 drivers/gpu/drm/tegra/sor.c 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
dc               2399 drivers/gpu/drm/tegra/sor.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
dc               2406 drivers/gpu/drm/tegra/sor.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
dc               2408 drivers/gpu/drm/tegra/sor.c 	tegra_dc_commit(dc);
dc               2425 drivers/gpu/drm/tegra/sor.c 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
dc               2586 drivers/gpu/drm/tegra/sor.c 		value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
dc               2601 drivers/gpu/drm/tegra/sor.c 	if (!dc->soc->has_nvdisplay) {
dc               2609 drivers/gpu/drm/tegra/sor.c 		tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
dc               2612 drivers/gpu/drm/tegra/sor.c 		tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
dc               2614 drivers/gpu/drm/tegra/sor.c 		value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
dc               2616 drivers/gpu/drm/tegra/sor.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
dc               2703 drivers/gpu/drm/tegra/sor.c 	if (!dc->soc->has_nvdisplay) {
dc               2706 drivers/gpu/drm/tegra/sor.c 		tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
dc               2709 drivers/gpu/drm/tegra/sor.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
dc               2736 drivers/gpu/drm/tegra/sor.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
dc               2741 drivers/gpu/drm/tegra/sor.c 	value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
dc               2749 drivers/gpu/drm/tegra/sor.c 	value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
dc               2752 drivers/gpu/drm/tegra/sor.c 	tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
dc               2755 drivers/gpu/drm/tegra/sor.c 	value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
dc               2758 drivers/gpu/drm/tegra/sor.c 	tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
dc               2774 drivers/gpu/drm/tegra/sor.c 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
dc               2781 drivers/gpu/drm/tegra/sor.c 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
dc               2783 drivers/gpu/drm/tegra/sor.c 	if (dc->soc->has_nvdisplay) {
dc               2784 drivers/gpu/drm/tegra/sor.c 		value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
dc               2787 drivers/gpu/drm/tegra/sor.c 		tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
dc               2790 drivers/gpu/drm/tegra/sor.c 	tegra_dc_commit(dc);
dc                225 drivers/gpu/drm/tiny/hx8357d.c 	struct gpio_desc *dc;
dc                242 drivers/gpu/drm/tiny/hx8357d.c 	dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
dc                243 drivers/gpu/drm/tiny/hx8357d.c 	if (IS_ERR(dc)) {
dc                245 drivers/gpu/drm/tiny/hx8357d.c 		return PTR_ERR(dc);
dc                254 drivers/gpu/drm/tiny/hx8357d.c 	ret = mipi_dbi_spi_init(spi, &dbidev->dbi, dc);
dc                102 drivers/gpu/drm/tiny/ili9225.c 	if (!dbi->dc || !full || swap ||
dc                326 drivers/gpu/drm/tiny/ili9225.c 	gpiod_set_value_cansleep(dbi->dc, 0);
dc                335 drivers/gpu/drm/tiny/ili9225.c 	gpiod_set_value_cansleep(dbi->dc, 1);
dc                182 drivers/gpu/drm/tiny/ili9341.c 	struct gpio_desc *dc;
dc                206 drivers/gpu/drm/tiny/ili9341.c 	dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
dc                207 drivers/gpu/drm/tiny/ili9341.c 	if (IS_ERR(dc)) {
dc                209 drivers/gpu/drm/tiny/ili9341.c 		return PTR_ERR(dc);
dc                218 drivers/gpu/drm/tiny/ili9341.c 	ret = mipi_dbi_spi_init(spi, dbi, dc);
dc                186 drivers/gpu/drm/tiny/mi0283qt.c 	struct gpio_desc *dc;
dc                210 drivers/gpu/drm/tiny/mi0283qt.c 	dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
dc                211 drivers/gpu/drm/tiny/mi0283qt.c 	if (IS_ERR(dc)) {
dc                213 drivers/gpu/drm/tiny/mi0283qt.c 		return PTR_ERR(dc);
dc                226 drivers/gpu/drm/tiny/mi0283qt.c 	ret = mipi_dbi_spi_init(spi, dbi, dc);
dc                156 drivers/gpu/drm/tiny/st7735r.c 	struct gpio_desc *dc;
dc                180 drivers/gpu/drm/tiny/st7735r.c 	dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
dc                181 drivers/gpu/drm/tiny/st7735r.c 	if (IS_ERR(dc)) {
dc                183 drivers/gpu/drm/tiny/st7735r.c 		return PTR_ERR(dc);
dc                192 drivers/gpu/drm/tiny/st7735r.c 	ret = mipi_dbi_spi_init(spi, dbi, dc);
dc               1186 drivers/gpu/ipu-v3/ipu-common.c 			.dc = 5,
dc               1195 drivers/gpu/ipu-v3/ipu-common.c 			.dc = 1,
dc                109 drivers/gpu/ipu-v3/ipu-dc.c static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
dc                113 drivers/gpu/ipu-v3/ipu-dc.c 	reg = readl(dc->base + DC_RL_CH(event));
dc                116 drivers/gpu/ipu-v3/ipu-dc.c 	writel(reg, dc->base + DC_RL_CH(event));
dc                119 drivers/gpu/ipu-v3/ipu-dc.c static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
dc                122 drivers/gpu/ipu-v3/ipu-dc.c 	struct ipu_dc_priv *priv = dc->priv;
dc                160 drivers/gpu/ipu-v3/ipu-dc.c int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
dc                163 drivers/gpu/ipu-v3/ipu-dc.c 	struct ipu_dc_priv *priv = dc->priv;
dc                168 drivers/gpu/ipu-v3/ipu-dc.c 	dc->di = ipu_di_get_num(di);
dc                181 drivers/gpu/ipu-v3/ipu-dc.c 	if (dc->di)
dc                187 drivers/gpu/ipu-v3/ipu-dc.c 		dc_link_event(dc, DC_EVT_NL, addr, 3);
dc                188 drivers/gpu/ipu-v3/ipu-dc.c 		dc_link_event(dc, DC_EVT_EOL, addr, 2);
dc                189 drivers/gpu/ipu-v3/ipu-dc.c 		dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1);
dc                192 drivers/gpu/ipu-v3/ipu-dc.c 		dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
dc                194 drivers/gpu/ipu-v3/ipu-dc.c 		dc_link_event(dc, DC_EVT_NL, addr + 2, 3);
dc                195 drivers/gpu/ipu-v3/ipu-dc.c 		dc_link_event(dc, DC_EVT_EOL, addr + 3, 2);
dc                196 drivers/gpu/ipu-v3/ipu-dc.c 		dc_link_event(dc, DC_EVT_NEW_DATA, addr + 1, 1);
dc                199 drivers/gpu/ipu-v3/ipu-dc.c 		dc_write_tmpl(dc, addr + 2, WROD(0), 0, map, SYNC_WAVE, 8, sync, 1);
dc                200 drivers/gpu/ipu-v3/ipu-dc.c 		dc_write_tmpl(dc, addr + 3, WROD(0), 0, map, SYNC_WAVE, 4, sync, 0);
dc                201 drivers/gpu/ipu-v3/ipu-dc.c 		dc_write_tmpl(dc, addr + 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
dc                202 drivers/gpu/ipu-v3/ipu-dc.c 		dc_write_tmpl(dc, addr + 1, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
dc                205 drivers/gpu/ipu-v3/ipu-dc.c 	dc_link_event(dc, DC_EVT_NF, 0, 0);
dc                206 drivers/gpu/ipu-v3/ipu-dc.c 	dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
dc                207 drivers/gpu/ipu-v3/ipu-dc.c 	dc_link_event(dc, DC_EVT_EOF, 0, 0);
dc                208 drivers/gpu/ipu-v3/ipu-dc.c 	dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
dc                209 drivers/gpu/ipu-v3/ipu-dc.c 	dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
dc                210 drivers/gpu/ipu-v3/ipu-dc.c 	dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
dc                212 drivers/gpu/ipu-v3/ipu-dc.c 	reg = readl(dc->base + DC_WR_CH_CONF);
dc                217 drivers/gpu/ipu-v3/ipu-dc.c 	writel(reg, dc->base + DC_WR_CH_CONF);
dc                219 drivers/gpu/ipu-v3/ipu-dc.c 	writel(0x0, dc->base + DC_WR_CH_ADDR);
dc                220 drivers/gpu/ipu-v3/ipu-dc.c 	writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
dc                241 drivers/gpu/ipu-v3/ipu-dc.c void ipu_dc_enable_channel(struct ipu_dc *dc)
dc                245 drivers/gpu/ipu-v3/ipu-dc.c 	reg = readl(dc->base + DC_WR_CH_CONF);
dc                247 drivers/gpu/ipu-v3/ipu-dc.c 	writel(reg, dc->base + DC_WR_CH_CONF);
dc                251 drivers/gpu/ipu-v3/ipu-dc.c void ipu_dc_disable_channel(struct ipu_dc *dc)
dc                255 drivers/gpu/ipu-v3/ipu-dc.c 	val = readl(dc->base + DC_WR_CH_CONF);
dc                257 drivers/gpu/ipu-v3/ipu-dc.c 	writel(val, dc->base + DC_WR_CH_CONF);
dc                306 drivers/gpu/ipu-v3/ipu-dc.c 	struct ipu_dc *dc;
dc                311 drivers/gpu/ipu-v3/ipu-dc.c 	dc = &priv->channels[channel];
dc                315 drivers/gpu/ipu-v3/ipu-dc.c 	if (dc->in_use) {
dc                320 drivers/gpu/ipu-v3/ipu-dc.c 	dc->in_use = true;
dc                324 drivers/gpu/ipu-v3/ipu-dc.c 	return dc;
dc                328 drivers/gpu/ipu-v3/ipu-dc.c void ipu_dc_put(struct ipu_dc *dc)
dc                330 drivers/gpu/ipu-v3/ipu-dc.c 	struct ipu_dc_priv *priv = dc->priv;
dc                333 drivers/gpu/ipu-v3/ipu-dc.c 	dc->in_use = false;
dc                181 drivers/i2c/busses/i2c-ibm_iic.c 	u8 dc;
dc                190 drivers/i2c/busses/i2c-ibm_iic.c 	dc = in_8(&iic->directcntl);
dc                191 drivers/i2c/busses/i2c-ibm_iic.c 	if (!DIRCTNL_FREE(dc)){
dc                199 drivers/i2c/busses/i2c-ibm_iic.c 			dc = in_8(&iic->directcntl);
dc                200 drivers/i2c/busses/i2c-ibm_iic.c 			if (DIRCTNL_FREE(dc))
dc                204 drivers/i2c/busses/i2c-ibm_iic.c 			dc ^= DIRCNTL_SCC;
dc                205 drivers/i2c/busses/i2c-ibm_iic.c 			out_8(&iic->directcntl, dc);
dc                207 drivers/i2c/busses/i2c-ibm_iic.c 			dc ^= DIRCNTL_SCC;
dc                208 drivers/i2c/busses/i2c-ibm_iic.c 			out_8(&iic->directcntl, dc);
dc                 80 drivers/infiniband/hw/qib/qib_diag.c 	struct qib_diag_client *dc;
dc                 82 drivers/infiniband/hw/qib/qib_diag.c 	dc = client_pool;
dc                 83 drivers/infiniband/hw/qib/qib_diag.c 	if (dc)
dc                 85 drivers/infiniband/hw/qib/qib_diag.c 		client_pool = dc->next;
dc                 88 drivers/infiniband/hw/qib/qib_diag.c 		dc = kmalloc(sizeof(*dc), GFP_KERNEL);
dc                 90 drivers/infiniband/hw/qib/qib_diag.c 	if (dc) {
dc                 91 drivers/infiniband/hw/qib/qib_diag.c 		dc->next = NULL;
dc                 92 drivers/infiniband/hw/qib/qib_diag.c 		dc->dd = dd;
dc                 93 drivers/infiniband/hw/qib/qib_diag.c 		dc->pid = current->pid;
dc                 94 drivers/infiniband/hw/qib/qib_diag.c 		dc->state = OPENED;
dc                 96 drivers/infiniband/hw/qib/qib_diag.c 	return dc;
dc                102 drivers/infiniband/hw/qib/qib_diag.c static void return_client(struct qib_diag_client *dc)
dc                104 drivers/infiniband/hw/qib/qib_diag.c 	struct qib_devdata *dd = dc->dd;
dc                108 drivers/infiniband/hw/qib/qib_diag.c 	if (dc == dd->diag_client) {
dc                109 drivers/infiniband/hw/qib/qib_diag.c 		dd->diag_client = dc->next;
dc                110 drivers/infiniband/hw/qib/qib_diag.c 		rdc = dc;
dc                112 drivers/infiniband/hw/qib/qib_diag.c 		tdc = dc->dd->diag_client;
dc                114 drivers/infiniband/hw/qib/qib_diag.c 			if (dc == tdc->next) {
dc                115 drivers/infiniband/hw/qib/qib_diag.c 				tdc->next = dc->next;
dc                116 drivers/infiniband/hw/qib/qib_diag.c 				rdc = dc;
dc                185 drivers/infiniband/hw/qib/qib_diag.c 	struct qib_diag_client *dc;
dc                201 drivers/infiniband/hw/qib/qib_diag.c 		dc = client_pool;
dc                202 drivers/infiniband/hw/qib/qib_diag.c 		client_pool = dc->next;
dc                203 drivers/infiniband/hw/qib/qib_diag.c 		kfree(dc);
dc                512 drivers/infiniband/hw/qib/qib_diag.c 	struct qib_diag_client *dc;
dc                525 drivers/infiniband/hw/qib/qib_diag.c 	dc = get_client(dd);
dc                526 drivers/infiniband/hw/qib/qib_diag.c 	if (!dc) {
dc                530 drivers/infiniband/hw/qib/qib_diag.c 	dc->next = dd->diag_client;
dc                531 drivers/infiniband/hw/qib/qib_diag.c 	dd->diag_client = dc;
dc                532 drivers/infiniband/hw/qib/qib_diag.c 	fp->private_data = dc;
dc                762 drivers/infiniband/hw/qib/qib_diag.c 	struct qib_diag_client *dc = fp->private_data;
dc                763 drivers/infiniband/hw/qib/qib_diag.c 	struct qib_devdata *dd = dc->dd;
dc                766 drivers/infiniband/hw/qib/qib_diag.c 	if (dc->pid != current->pid) {
dc                776 drivers/infiniband/hw/qib/qib_diag.c 	else if (dc->state < READY && (*off || count != 8))
dc                826 drivers/infiniband/hw/qib/qib_diag.c 		if (dc->state == OPENED)
dc                827 drivers/infiniband/hw/qib/qib_diag.c 			dc->state = INIT;
dc                836 drivers/infiniband/hw/qib/qib_diag.c 	struct qib_diag_client *dc = fp->private_data;
dc                837 drivers/infiniband/hw/qib/qib_diag.c 	struct qib_devdata *dd = dc->dd;
dc                840 drivers/infiniband/hw/qib/qib_diag.c 	if (dc->pid != current->pid) {
dc                850 drivers/infiniband/hw/qib/qib_diag.c 	else if (dc->state < READY &&
dc                851 drivers/infiniband/hw/qib/qib_diag.c 		((*off || count != 8) || dc->state != INIT))
dc                901 drivers/infiniband/hw/qib/qib_diag.c 		if (dc->state == INIT)
dc                902 drivers/infiniband/hw/qib/qib_diag.c 			dc->state = READY; /* all read/write OK now */
dc                 60 drivers/ipack/devices/scc2698.h 		u8 dc, r3;   /* reserved */
dc                 78 drivers/ipack/devices/scc2698.h 		u8 dc, r1;   /* reserved */
dc                874 drivers/md/bcache/bcache.h static inline void cached_dev_put(struct cached_dev *dc)
dc                876 drivers/md/bcache/bcache.h 	if (refcount_dec_and_test(&dc->count))
dc                877 drivers/md/bcache/bcache.h 		schedule_work(&dc->detach);
dc                880 drivers/md/bcache/bcache.h static inline bool cached_dev_get(struct cached_dev *dc)
dc                882 drivers/md/bcache/bcache.h 	if (!refcount_inc_not_zero(&dc->count))
dc                947 drivers/md/bcache/bcache.h void bch_count_backing_io_errors(struct cached_dev *dc, struct bio *bio);
dc                978 drivers/md/bcache/bcache.h bool bch_cached_dev_error(struct cached_dev *dc);
dc                984 drivers/md/bcache/bcache.h void bch_write_bdev_super(struct cached_dev *dc, struct closure *parent);
dc               1007 drivers/md/bcache/bcache.h int bch_cached_dev_attach(struct cached_dev *dc, struct cache_set *c,
dc               1009 drivers/md/bcache/bcache.h void bch_cached_dev_detach(struct cached_dev *dc);
dc               1010 drivers/md/bcache/bcache.h int bch_cached_dev_run(struct cached_dev *dc);
dc               1781 drivers/md/bcache/btree.c 		struct cached_dev *dc;
dc               1787 drivers/md/bcache/btree.c 		dc = container_of(d, struct cached_dev, disk);
dc               1789 drivers/md/bcache/btree.c 		spin_lock(&dc->writeback_keys.lock);
dc               1791 drivers/md/bcache/btree.c 					&dc->writeback_keys.keys, node)
dc               1795 drivers/md/bcache/btree.c 		spin_unlock(&dc->writeback_keys.lock);
dc                108 drivers/md/bcache/debug.c void bch_data_verify(struct cached_dev *dc, struct bio *bio)
dc                139 drivers/md/bcache/debug.c 				 dc->disk.c,
dc                141 drivers/md/bcache/debug.c 				 dc->backing_dev_name,
dc                 12 drivers/md/bcache/debug.h void bch_data_verify(struct cached_dev *dc, struct bio *bio);
dc                 21 drivers/md/bcache/debug.h static inline void bch_data_verify(struct cached_dev *dc, struct bio *bio) {}
dc                 55 drivers/md/bcache/io.c void bch_count_backing_io_errors(struct cached_dev *dc, struct bio *bio)
dc                 59 drivers/md/bcache/io.c 	WARN_ONCE(!dc, "NULL pointer of struct cached_dev");
dc                 69 drivers/md/bcache/io.c 				    dc->backing_dev_name);
dc                 73 drivers/md/bcache/io.c 	errors = atomic_add_return(1, &dc->io_errors);
dc                 74 drivers/md/bcache/io.c 	if (errors < dc->error_limit)
dc                 76 drivers/md/bcache/io.c 			dc->backing_dev_name);
dc                 78 drivers/md/bcache/io.c 		bch_cached_dev_error(dc);
dc                 30 drivers/md/bcache/request.c static unsigned int cache_mode(struct cached_dev *dc)
dc                 32 drivers/md/bcache/request.c 	return BDEV_CACHE_MODE(&dc->sb);
dc                 35 drivers/md/bcache/request.c static bool verify(struct cached_dev *dc)
dc                 37 drivers/md/bcache/request.c 	return dc->verify;
dc                370 drivers/md/bcache/request.c static struct hlist_head *iohash(struct cached_dev *dc, uint64_t k)
dc                372 drivers/md/bcache/request.c 	return &dc->io_hash[hash_64(k, RECENT_IO_BITS)];
dc                375 drivers/md/bcache/request.c static bool check_should_bypass(struct cached_dev *dc, struct bio *bio)
dc                377 drivers/md/bcache/request.c 	struct cache_set *c = dc->disk.c;
dc                378 drivers/md/bcache/request.c 	unsigned int mode = cache_mode(dc);
dc                383 drivers/md/bcache/request.c 	if (test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags) ||
dc                405 drivers/md/bcache/request.c 		    (dc->cache_readahead_policy != BCH_CACHE_READA_ALL))
dc                415 drivers/md/bcache/request.c 	if (bypass_torture_test(dc)) {
dc                423 drivers/md/bcache/request.c 	if (!congested && !dc->sequential_cutoff)
dc                426 drivers/md/bcache/request.c 	spin_lock(&dc->io_lock);
dc                428 drivers/md/bcache/request.c 	hlist_for_each_entry(i, iohash(dc, bio->bi_iter.bi_sector), hash)
dc                433 drivers/md/bcache/request.c 	i = list_first_entry(&dc->io_lru, struct io, lru);
dc                446 drivers/md/bcache/request.c 	hlist_add_head(&i->hash, iohash(dc, i->last));
dc                447 drivers/md/bcache/request.c 	list_move_tail(&i->lru, &dc->io_lru);
dc                449 drivers/md/bcache/request.c 	spin_unlock(&dc->io_lock);
dc                454 drivers/md/bcache/request.c 	if (dc->sequential_cutoff &&
dc                455 drivers/md/bcache/request.c 	    sectors >= dc->sequential_cutoff >> 9) {
dc                469 drivers/md/bcache/request.c 	bch_mark_sectors_bypassed(c, dc, bio_sectors(bio));
dc                593 drivers/md/bcache/request.c 	struct cached_dev *dc;
dc                619 drivers/md/bcache/request.c 			dc = container_of(s->d, struct cached_dev, disk);
dc                620 drivers/md/bcache/request.c 			if (dc && atomic_read(&dc->has_dirty))
dc                654 drivers/md/bcache/request.c 		struct cached_dev *dc = container_of(s->d,
dc                666 drivers/md/bcache/request.c 				dc->backing_dev_name, bio->bi_status);
dc                673 drivers/md/bcache/request.c 		bch_count_backing_io_errors(dc, bio);
dc                765 drivers/md/bcache/request.c 	struct cached_dev *dc = container_of(s->d, struct cached_dev, disk);
dc                767 drivers/md/bcache/request.c 	cached_dev_put(dc);
dc                832 drivers/md/bcache/request.c 	struct cached_dev *dc = container_of(s->d, struct cached_dev, disk);
dc                856 drivers/md/bcache/request.c 	if (verify(dc) && s->recoverable && !s->read_dirty_data)
dc                857 drivers/md/bcache/request.c 		bch_data_verify(dc, s->orig_bio);
dc                859 drivers/md/bcache/request.c 	closure_get(&dc->disk.cl);
dc                874 drivers/md/bcache/request.c 	struct cached_dev *dc = container_of(s->d, struct cached_dev, disk);
dc                882 drivers/md/bcache/request.c 	else if (s->iop.bio || verify(dc))
dc                893 drivers/md/bcache/request.c 	struct cached_dev *dc = container_of(s->d, struct cached_dev, disk);
dc                907 drivers/md/bcache/request.c 		reada = min_t(sector_t, dc->readahead >> 9,
dc                929 drivers/md/bcache/request.c 			&dc->disk.bio_split);
dc                964 drivers/md/bcache/request.c static void cached_dev_read(struct cached_dev *dc, struct search *s)
dc                977 drivers/md/bcache/request.c 	struct cached_dev *dc = container_of(s->d, struct cached_dev, disk);
dc                979 drivers/md/bcache/request.c 	up_read_non_owner(&dc->writeback_lock);
dc                983 drivers/md/bcache/request.c static void cached_dev_write(struct cached_dev *dc, struct search *s)
dc                987 drivers/md/bcache/request.c 	struct bkey start = KEY(dc->disk.id, bio->bi_iter.bi_sector, 0);
dc                988 drivers/md/bcache/request.c 	struct bkey end = KEY(dc->disk.id, bio_end_sector(bio), 0);
dc                992 drivers/md/bcache/request.c 	down_read_non_owner(&dc->writeback_lock);
dc                993 drivers/md/bcache/request.c 	if (bch_keybuf_check_overlapping(&dc->writeback_keys, &start, &end)) {
dc               1012 drivers/md/bcache/request.c 	if (should_writeback(dc, s->orig_bio,
dc               1013 drivers/md/bcache/request.c 			     cache_mode(dc),
dc               1024 drivers/md/bcache/request.c 		    !blk_queue_discard(bdev_get_queue(dc->bdev)))
dc               1032 drivers/md/bcache/request.c 		bch_writeback_add(dc);
dc               1043 drivers/md/bcache/request.c 						 &dc->disk.bio_split);
dc               1056 drivers/md/bcache/request.c 		s->iop.bio = bio_clone_fast(bio, GFP_NOIO, &dc->disk.bio_split);
dc               1101 drivers/md/bcache/request.c 		struct cached_dev *dc = container_of(ddip->d,
dc               1104 drivers/md/bcache/request.c 		bch_count_backing_io_errors(dc, bio);
dc               1114 drivers/md/bcache/request.c 	struct cached_dev *dc = container_of(d, struct cached_dev, disk);
dc               1130 drivers/md/bcache/request.c 	    !blk_queue_discard(bdev_get_queue(dc->bdev)))
dc               1141 drivers/md/bcache/request.c 	struct cached_dev *dc;
dc               1161 drivers/md/bcache/request.c 			dc = container_of(d, struct cached_dev, disk);
dc               1167 drivers/md/bcache/request.c 			atomic_long_set(&dc->writeback_rate.rate, 1);
dc               1181 drivers/md/bcache/request.c 	struct cached_dev *dc = container_of(d, struct cached_dev, disk);
dc               1185 drivers/md/bcache/request.c 		     dc->io_disable)) {
dc               1202 drivers/md/bcache/request.c 			quit_max_writeback_rate(d->c, dc);
dc               1211 drivers/md/bcache/request.c 	bio_set_dev(bio, dc->bdev);
dc               1212 drivers/md/bcache/request.c 	bio->bi_iter.bi_sector += dc->sb.data_offset;
dc               1214 drivers/md/bcache/request.c 	if (cached_dev_get(dc)) {
dc               1227 drivers/md/bcache/request.c 			s->iop.bypass = check_should_bypass(dc, bio);
dc               1230 drivers/md/bcache/request.c 				cached_dev_write(dc, s);
dc               1232 drivers/md/bcache/request.c 				cached_dev_read(dc, s);
dc               1244 drivers/md/bcache/request.c 	struct cached_dev *dc = container_of(d, struct cached_dev, disk);
dc               1246 drivers/md/bcache/request.c 	if (dc->io_disable)
dc               1249 drivers/md/bcache/request.c 	return __blkdev_driver_ioctl(dc->bdev, mode, cmd, arg);
dc               1255 drivers/md/bcache/request.c 	struct cached_dev *dc = container_of(d, struct cached_dev, disk);
dc               1256 drivers/md/bcache/request.c 	struct request_queue *q = bdev_get_queue(dc->bdev);
dc               1262 drivers/md/bcache/request.c 	if (cached_dev_get(dc)) {
dc               1271 drivers/md/bcache/request.c 		cached_dev_put(dc);
dc               1277 drivers/md/bcache/request.c void bch_cached_dev_request_init(struct cached_dev *dc)
dc               1279 drivers/md/bcache/request.c 	struct gendisk *g = dc->disk.disk;
dc               1283 drivers/md/bcache/request.c 	dc->disk.cache_miss			= cached_dev_cache_miss;
dc               1284 drivers/md/bcache/request.c 	dc->disk.ioctl				= cached_dev_ioctl;
dc                 39 drivers/md/bcache/request.h void bch_cached_dev_request_init(struct cached_dev *dc);
dc                206 drivers/md/bcache/stats.c 	struct cached_dev *dc = container_of(d, struct cached_dev, disk);
dc                208 drivers/md/bcache/stats.c 	mark_cache_stats(&dc->accounting.collector, hit, bypass);
dc                214 drivers/md/bcache/stats.c 	struct cached_dev *dc = container_of(d, struct cached_dev, disk);
dc                216 drivers/md/bcache/stats.c 	atomic_inc(&dc->accounting.collector.cache_readaheads);
dc                222 drivers/md/bcache/stats.c 	struct cached_dev *dc = container_of(d, struct cached_dev, disk);
dc                224 drivers/md/bcache/stats.c 	atomic_inc(&dc->accounting.collector.cache_miss_collisions);
dc                228 drivers/md/bcache/stats.c void bch_mark_sectors_bypassed(struct cache_set *c, struct cached_dev *dc,
dc                231 drivers/md/bcache/stats.c 	atomic_add(sectors, &dc->accounting.collector.sectors_bypassed);
dc                 62 drivers/md/bcache/stats.h 			       struct cached_dev *dc,
dc                201 drivers/md/bcache/super.c 	struct cached_dev *dc = bio->bi_private;
dc                204 drivers/md/bcache/super.c 		bch_count_backing_io_errors(dc, bio);
dc                206 drivers/md/bcache/super.c 	closure_put(&dc->sb_write);
dc                246 drivers/md/bcache/super.c 	struct cached_dev *dc = container_of(cl, struct cached_dev, sb_write);
dc                248 drivers/md/bcache/super.c 	up(&dc->sb_write_mutex);
dc                251 drivers/md/bcache/super.c void bch_write_bdev_super(struct cached_dev *dc, struct closure *parent)
dc                253 drivers/md/bcache/super.c 	struct closure *cl = &dc->sb_write;
dc                254 drivers/md/bcache/super.c 	struct bio *bio = &dc->sb_bio;
dc                256 drivers/md/bcache/super.c 	down(&dc->sb_write_mutex);
dc                260 drivers/md/bcache/super.c 	bio_set_dev(bio, dc->bdev);
dc                262 drivers/md/bcache/super.c 	bio->bi_private = dc;
dc                266 drivers/md/bcache/super.c 	__write_super(&dc->sb, bio);
dc                897 drivers/md/bcache/super.c 	struct cached_dev *dc;
dc                899 drivers/md/bcache/super.c 	list_for_each_entry(dc, &c->cached_devs, list)
dc                900 drivers/md/bcache/super.c 		sectors += bdev_sectors(dc->bdev);
dc                908 drivers/md/bcache/super.c 	struct cached_dev *dc = arg;
dc                916 drivers/md/bcache/super.c 	while (!kthread_should_stop() && !dc->io_disable) {
dc                917 drivers/md/bcache/super.c 		q = bdev_get_queue(dc->bdev);
dc                919 drivers/md/bcache/super.c 			dc->offline_seconds++;
dc                921 drivers/md/bcache/super.c 			dc->offline_seconds = 0;
dc                923 drivers/md/bcache/super.c 		if (dc->offline_seconds >= BACKING_DEV_OFFLINE_TIMEOUT) {
dc                925 drivers/md/bcache/super.c 			       dc->backing_dev_name,
dc                928 drivers/md/bcache/super.c 			       "device offline", dc->disk.name);
dc                929 drivers/md/bcache/super.c 			dc->io_disable = true;
dc                932 drivers/md/bcache/super.c 			bcache_device_stop(&dc->disk);
dc                943 drivers/md/bcache/super.c int bch_cached_dev_run(struct cached_dev *dc)
dc                945 drivers/md/bcache/super.c 	struct bcache_device *d = &dc->disk;
dc                946 drivers/md/bcache/super.c 	char *buf = kmemdup_nul(dc->sb.label, SB_LABEL_SIZE, GFP_KERNEL);
dc                949 drivers/md/bcache/super.c 		kasprintf(GFP_KERNEL, "CACHED_UUID=%pU", dc->sb.uuid),
dc                954 drivers/md/bcache/super.c 	if (dc->io_disable) {
dc                956 drivers/md/bcache/super.c 		       dc->backing_dev_name);
dc                963 drivers/md/bcache/super.c 	if (atomic_xchg(&dc->running, 1)) {
dc                968 drivers/md/bcache/super.c 		       dc->backing_dev_name);
dc                973 drivers/md/bcache/super.c 	    BDEV_STATE(&dc->sb) != BDEV_STATE_NONE) {
dc                978 drivers/md/bcache/super.c 		SET_BDEV_STATE(&dc->sb, BDEV_STATE_STALE);
dc                979 drivers/md/bcache/super.c 		bch_write_bdev_super(dc, &cl);
dc                984 drivers/md/bcache/super.c 	bd_link_disk_holder(dc->bdev, dc->disk.disk);
dc               1001 drivers/md/bcache/super.c 	dc->status_update_thread = kthread_run(cached_dev_status_update,
dc               1002 drivers/md/bcache/super.c 					       dc, "bcache_status_update");
dc               1003 drivers/md/bcache/super.c 	if (IS_ERR(dc->status_update_thread)) {
dc               1019 drivers/md/bcache/super.c static void cancel_writeback_rate_update_dwork(struct cached_dev *dc)
dc               1025 drivers/md/bcache/super.c 			      &dc->disk.flags))
dc               1034 drivers/md/bcache/super.c 	cancel_delayed_work_sync(&dc->writeback_rate_update);
dc               1039 drivers/md/bcache/super.c 	struct cached_dev *dc = container_of(w, struct cached_dev, detach);
dc               1044 drivers/md/bcache/super.c 	BUG_ON(!test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags));
dc               1045 drivers/md/bcache/super.c 	BUG_ON(refcount_read(&dc->count));
dc               1048 drivers/md/bcache/super.c 	if (test_and_clear_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags))
dc               1049 drivers/md/bcache/super.c 		cancel_writeback_rate_update_dwork(dc);
dc               1051 drivers/md/bcache/super.c 	if (!IS_ERR_OR_NULL(dc->writeback_thread)) {
dc               1052 drivers/md/bcache/super.c 		kthread_stop(dc->writeback_thread);
dc               1053 drivers/md/bcache/super.c 		dc->writeback_thread = NULL;
dc               1056 drivers/md/bcache/super.c 	memset(&dc->sb.set_uuid, 0, 16);
dc               1057 drivers/md/bcache/super.c 	SET_BDEV_STATE(&dc->sb, BDEV_STATE_NONE);
dc               1059 drivers/md/bcache/super.c 	bch_write_bdev_super(dc, &cl);
dc               1064 drivers/md/bcache/super.c 	calc_cached_dev_sectors(dc->disk.c);
dc               1065 drivers/md/bcache/super.c 	bcache_device_detach(&dc->disk);
dc               1066 drivers/md/bcache/super.c 	list_move(&dc->list, &uncached_devices);
dc               1068 drivers/md/bcache/super.c 	clear_bit(BCACHE_DEV_DETACHING, &dc->disk.flags);
dc               1069 drivers/md/bcache/super.c 	clear_bit(BCACHE_DEV_UNLINK_DONE, &dc->disk.flags);
dc               1073 drivers/md/bcache/super.c 	pr_info("Caching disabled for %s", dc->backing_dev_name);
dc               1076 drivers/md/bcache/super.c 	closure_put(&dc->disk.cl);
dc               1079 drivers/md/bcache/super.c void bch_cached_dev_detach(struct cached_dev *dc)
dc               1083 drivers/md/bcache/super.c 	if (test_bit(BCACHE_DEV_CLOSING, &dc->disk.flags))
dc               1086 drivers/md/bcache/super.c 	if (test_and_set_bit(BCACHE_DEV_DETACHING, &dc->disk.flags))
dc               1093 drivers/md/bcache/super.c 	closure_get(&dc->disk.cl);
dc               1095 drivers/md/bcache/super.c 	bch_writeback_queue(dc);
dc               1097 drivers/md/bcache/super.c 	cached_dev_put(dc);
dc               1100 drivers/md/bcache/super.c int bch_cached_dev_attach(struct cached_dev *dc, struct cache_set *c,
dc               1109 drivers/md/bcache/super.c 	    (!set_uuid && memcmp(dc->sb.set_uuid, c->sb.set_uuid, 16)))
dc               1112 drivers/md/bcache/super.c 	if (dc->disk.c) {
dc               1114 drivers/md/bcache/super.c 		       dc->backing_dev_name);
dc               1120 drivers/md/bcache/super.c 		       dc->backing_dev_name);
dc               1124 drivers/md/bcache/super.c 	if (dc->sb.block_size < c->sb.block_size) {
dc               1127 drivers/md/bcache/super.c 		       dc->backing_dev_name);
dc               1133 drivers/md/bcache/super.c 		if (!memcmp(dc->sb.uuid, exist_dc->sb.uuid, 16)) {
dc               1135 drivers/md/bcache/super.c 				dc->backing_dev_name);
dc               1141 drivers/md/bcache/super.c 	u = uuid_find(c, dc->sb.uuid);
dc               1144 drivers/md/bcache/super.c 	    (BDEV_STATE(&dc->sb) == BDEV_STATE_STALE ||
dc               1145 drivers/md/bcache/super.c 	     BDEV_STATE(&dc->sb) == BDEV_STATE_NONE)) {
dc               1152 drivers/md/bcache/super.c 		if (BDEV_STATE(&dc->sb) == BDEV_STATE_DIRTY) {
dc               1154 drivers/md/bcache/super.c 			       dc->backing_dev_name);
dc               1161 drivers/md/bcache/super.c 			       dc->backing_dev_name);
dc               1176 drivers/md/bcache/super.c 		memcpy(u->uuid, dc->sb.uuid, 16);
dc               1177 drivers/md/bcache/super.c 		memcpy(u->label, dc->sb.label, SB_LABEL_SIZE);
dc               1181 drivers/md/bcache/super.c 		memcpy(dc->sb.set_uuid, c->sb.set_uuid, 16);
dc               1182 drivers/md/bcache/super.c 		SET_BDEV_STATE(&dc->sb, BDEV_STATE_CLEAN);
dc               1184 drivers/md/bcache/super.c 		bch_write_bdev_super(dc, &cl);
dc               1191 drivers/md/bcache/super.c 	bcache_device_attach(&dc->disk, c, u - c->uuids);
dc               1192 drivers/md/bcache/super.c 	list_move(&dc->list, &c->cached_devs);
dc               1200 drivers/md/bcache/super.c 	refcount_set(&dc->count, 1);
dc               1203 drivers/md/bcache/super.c 	down_write(&dc->writeback_lock);
dc               1204 drivers/md/bcache/super.c 	if (bch_cached_dev_writeback_start(dc)) {
dc               1205 drivers/md/bcache/super.c 		up_write(&dc->writeback_lock);
dc               1207 drivers/md/bcache/super.c 		       dc->disk.disk->disk_name);
dc               1211 drivers/md/bcache/super.c 	if (BDEV_STATE(&dc->sb) == BDEV_STATE_DIRTY) {
dc               1212 drivers/md/bcache/super.c 		atomic_set(&dc->has_dirty, 1);
dc               1213 drivers/md/bcache/super.c 		bch_writeback_queue(dc);
dc               1216 drivers/md/bcache/super.c 	bch_sectors_dirty_init(&dc->disk);
dc               1218 drivers/md/bcache/super.c 	ret = bch_cached_dev_run(dc);
dc               1220 drivers/md/bcache/super.c 		up_write(&dc->writeback_lock);
dc               1227 drivers/md/bcache/super.c 		kthread_stop(dc->writeback_thread);
dc               1228 drivers/md/bcache/super.c 		cancel_writeback_rate_update_dwork(dc);
dc               1230 drivers/md/bcache/super.c 		       dc->backing_dev_name);
dc               1234 drivers/md/bcache/super.c 	bcache_device_link(&dc->disk, c, "bdev");
dc               1238 drivers/md/bcache/super.c 	up_write(&dc->writeback_lock);
dc               1241 drivers/md/bcache/super.c 		dc->backing_dev_name,
dc               1242 drivers/md/bcache/super.c 		dc->disk.disk->disk_name,
dc               1243 drivers/md/bcache/super.c 		dc->disk.c->sb.set_uuid);
dc               1250 drivers/md/bcache/super.c 	struct cached_dev *dc = container_of(kobj, struct cached_dev,
dc               1252 drivers/md/bcache/super.c 	kfree(dc);
dc               1258 drivers/md/bcache/super.c 	struct cached_dev *dc = container_of(cl, struct cached_dev, disk.cl);
dc               1260 drivers/md/bcache/super.c 	if (test_and_clear_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags))
dc               1261 drivers/md/bcache/super.c 		cancel_writeback_rate_update_dwork(dc);
dc               1263 drivers/md/bcache/super.c 	if (!IS_ERR_OR_NULL(dc->writeback_thread))
dc               1264 drivers/md/bcache/super.c 		kthread_stop(dc->writeback_thread);
dc               1265 drivers/md/bcache/super.c 	if (!IS_ERR_OR_NULL(dc->status_update_thread))
dc               1266 drivers/md/bcache/super.c 		kthread_stop(dc->status_update_thread);
dc               1270 drivers/md/bcache/super.c 	if (atomic_read(&dc->running))
dc               1271 drivers/md/bcache/super.c 		bd_unlink_disk_holder(dc->bdev, dc->disk.disk);
dc               1272 drivers/md/bcache/super.c 	bcache_device_free(&dc->disk);
dc               1273 drivers/md/bcache/super.c 	list_del(&dc->list);
dc               1277 drivers/md/bcache/super.c 	if (dc->sb_bio.bi_inline_vecs[0].bv_page)
dc               1278 drivers/md/bcache/super.c 		put_page(bio_first_page_all(&dc->sb_bio));
dc               1280 drivers/md/bcache/super.c 	if (!IS_ERR_OR_NULL(dc->bdev))
dc               1281 drivers/md/bcache/super.c 		blkdev_put(dc->bdev, FMODE_READ|FMODE_WRITE|FMODE_EXCL);
dc               1285 drivers/md/bcache/super.c 	kobject_put(&dc->disk.kobj);
dc               1290 drivers/md/bcache/super.c 	struct cached_dev *dc = container_of(cl, struct cached_dev, disk.cl);
dc               1291 drivers/md/bcache/super.c 	struct bcache_device *d = &dc->disk;
dc               1297 drivers/md/bcache/super.c 	bch_cache_accounting_destroy(&dc->accounting);
dc               1303 drivers/md/bcache/super.c static int cached_dev_init(struct cached_dev *dc, unsigned int block_size)
dc               1307 drivers/md/bcache/super.c 	struct request_queue *q = bdev_get_queue(dc->bdev);
dc               1310 drivers/md/bcache/super.c 	INIT_LIST_HEAD(&dc->list);
dc               1311 drivers/md/bcache/super.c 	closure_init(&dc->disk.cl, NULL);
dc               1312 drivers/md/bcache/super.c 	set_closure_fn(&dc->disk.cl, cached_dev_flush, system_wq);
dc               1313 drivers/md/bcache/super.c 	kobject_init(&dc->disk.kobj, &bch_cached_dev_ktype);
dc               1314 drivers/md/bcache/super.c 	INIT_WORK(&dc->detach, cached_dev_detach_finish);
dc               1315 drivers/md/bcache/super.c 	sema_init(&dc->sb_write_mutex, 1);
dc               1316 drivers/md/bcache/super.c 	INIT_LIST_HEAD(&dc->io_lru);
dc               1317 drivers/md/bcache/super.c 	spin_lock_init(&dc->io_lock);
dc               1318 drivers/md/bcache/super.c 	bch_cache_accounting_init(&dc->accounting, &dc->disk.cl);
dc               1320 drivers/md/bcache/super.c 	dc->sequential_cutoff		= 4 << 20;
dc               1322 drivers/md/bcache/super.c 	for (io = dc->io; io < dc->io + RECENT_IO; io++) {
dc               1323 drivers/md/bcache/super.c 		list_add(&io->lru, &dc->io_lru);
dc               1324 drivers/md/bcache/super.c 		hlist_add_head(&io->hash, dc->io_hash + RECENT_IO);
dc               1327 drivers/md/bcache/super.c 	dc->disk.stripe_size = q->limits.io_opt >> 9;
dc               1329 drivers/md/bcache/super.c 	if (dc->disk.stripe_size)
dc               1330 drivers/md/bcache/super.c 		dc->partial_stripes_expensive =
dc               1333 drivers/md/bcache/super.c 	ret = bcache_device_init(&dc->disk, block_size,
dc               1334 drivers/md/bcache/super.c 			 dc->bdev->bd_part->nr_sects - dc->sb.data_offset);
dc               1338 drivers/md/bcache/super.c 	dc->disk.disk->queue->backing_dev_info->ra_pages =
dc               1339 drivers/md/bcache/super.c 		max(dc->disk.disk->queue->backing_dev_info->ra_pages,
dc               1342 drivers/md/bcache/super.c 	atomic_set(&dc->io_errors, 0);
dc               1343 drivers/md/bcache/super.c 	dc->io_disable = false;
dc               1344 drivers/md/bcache/super.c 	dc->error_limit = DEFAULT_CACHED_DEV_ERROR_LIMIT;
dc               1346 drivers/md/bcache/super.c 	dc->stop_when_cache_set_failed = BCH_CACHED_DEV_STOP_AUTO;
dc               1348 drivers/md/bcache/super.c 	bch_cached_dev_request_init(dc);
dc               1349 drivers/md/bcache/super.c 	bch_cached_dev_writeback_init(dc);
dc               1357 drivers/md/bcache/super.c 				 struct cached_dev *dc)
dc               1363 drivers/md/bcache/super.c 	bdevname(bdev, dc->backing_dev_name);
dc               1364 drivers/md/bcache/super.c 	memcpy(&dc->sb, sb, sizeof(struct cache_sb));
dc               1365 drivers/md/bcache/super.c 	dc->bdev = bdev;
dc               1366 drivers/md/bcache/super.c 	dc->bdev->bd_holder = dc;
dc               1368 drivers/md/bcache/super.c 	bio_init(&dc->sb_bio, dc->sb_bio.bi_inline_vecs, 1);
dc               1369 drivers/md/bcache/super.c 	bio_first_bvec_all(&dc->sb_bio)->bv_page = sb_page;
dc               1373 drivers/md/bcache/super.c 	if (cached_dev_init(dc, sb->block_size << 9))
dc               1377 drivers/md/bcache/super.c 	if (kobject_add(&dc->disk.kobj, &part_to_dev(bdev->bd_part)->kobj,
dc               1380 drivers/md/bcache/super.c 	if (bch_cache_accounting_add_kobjs(&dc->accounting, &dc->disk.kobj))
dc               1383 drivers/md/bcache/super.c 	pr_info("registered backing device %s", dc->backing_dev_name);
dc               1385 drivers/md/bcache/super.c 	list_add(&dc->list, &uncached_devices);
dc               1388 drivers/md/bcache/super.c 		bch_cached_dev_attach(dc, c, NULL);
dc               1390 drivers/md/bcache/super.c 	if (BDEV_STATE(&dc->sb) == BDEV_STATE_NONE ||
dc               1391 drivers/md/bcache/super.c 	    BDEV_STATE(&dc->sb) == BDEV_STATE_STALE) {
dc               1393 drivers/md/bcache/super.c 		ret = bch_cached_dev_run(dc);
dc               1400 drivers/md/bcache/super.c 	pr_notice("error %s: %s", dc->backing_dev_name, err);
dc               1401 drivers/md/bcache/super.c 	bcache_device_stop(&dc->disk);
dc               1511 drivers/md/bcache/super.c bool bch_cached_dev_error(struct cached_dev *dc)
dc               1513 drivers/md/bcache/super.c 	if (!dc || test_bit(BCACHE_DEV_CLOSING, &dc->disk.flags))
dc               1516 drivers/md/bcache/super.c 	dc->io_disable = true;
dc               1521 drivers/md/bcache/super.c 		dc->disk.disk->disk_name, dc->backing_dev_name);
dc               1523 drivers/md/bcache/super.c 	bcache_device_stop(&dc->disk);
dc               1672 drivers/md/bcache/super.c 					   struct cached_dev *dc)
dc               1674 drivers/md/bcache/super.c 	if (dc->stop_when_cache_set_failed == BCH_CACHED_DEV_STOP_ALWAYS) {
dc               1678 drivers/md/bcache/super.c 	} else if (atomic_read(&dc->has_dirty)) {
dc               1696 drivers/md/bcache/super.c 		dc->io_disable = true;
dc               1713 drivers/md/bcache/super.c 	struct cached_dev *dc;
dc               1726 drivers/md/bcache/super.c 			dc = container_of(d, struct cached_dev, disk);
dc               1727 drivers/md/bcache/super.c 			bch_cached_dev_detach(dc);
dc               1729 drivers/md/bcache/super.c 				conditional_stop_bcache_device(c, d, dc);
dc               1849 drivers/md/bcache/super.c 	struct cached_dev *dc, *t;
dc               2022 drivers/md/bcache/super.c 	list_for_each_entry_safe(dc, t, &uncached_devices, list)
dc               2023 drivers/md/bcache/super.c 		bch_cached_dev_attach(dc, c, NULL);
dc               2342 drivers/md/bcache/super.c 	struct cached_dev *dc, *t;
dc               2345 drivers/md/bcache/super.c 		list_for_each_entry_safe(dc, t, &c->cached_devs, list)
dc               2346 drivers/md/bcache/super.c 			if (dc->bdev == bdev)
dc               2348 drivers/md/bcache/super.c 	list_for_each_entry_safe(dc, t, &uncached_devices, list)
dc               2349 drivers/md/bcache/super.c 		if (dc->bdev == bdev)
dc               2435 drivers/md/bcache/super.c 		struct cached_dev *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
dc               2437 drivers/md/bcache/super.c 		if (!dc)
dc               2441 drivers/md/bcache/super.c 		ret = register_bdev(sb, sb_page, bdev, dc);
dc               2488 drivers/md/bcache/super.c 	struct cached_dev *dc;
dc               2498 drivers/md/bcache/super.c 	struct cached_dev *dc, *tdc;
dc               2503 drivers/md/bcache/super.c 	list_for_each_entry_safe(dc, tdc, &uncached_devices, list) {
dc               2507 drivers/md/bcache/super.c 		pdev->dc = dc;
dc               2513 drivers/md/bcache/super.c 			char *pdev_set_uuid = pdev->dc->sb.set_uuid;
dc               2528 drivers/md/bcache/super.c 		bcache_device_stop(&pdev->dc->disk);
dc               2548 drivers/md/bcache/super.c 		struct cached_dev *dc, *tdc;
dc               2588 drivers/md/bcache/super.c 		list_for_each_entry_safe(dc, tdc, &uncached_devices, list)
dc               2589 drivers/md/bcache/super.c 			bcache_device_stop(&dc->disk);
dc                165 drivers/md/bcache/sysfs.c 	struct cached_dev *dc = container_of(kobj, struct cached_dev,
dc                168 drivers/md/bcache/sysfs.c 	int wb = dc->writeback_running;
dc                170 drivers/md/bcache/sysfs.c #define var(stat)		(dc->stat)
dc                175 drivers/md/bcache/sysfs.c 					       BDEV_CACHE_MODE(&dc->sb));
dc                180 drivers/md/bcache/sysfs.c 					      dc->cache_readahead_policy);
dc                185 drivers/md/bcache/sysfs.c 					       dc->stop_when_cache_set_failed);
dc                188 drivers/md/bcache/sysfs.c 	sysfs_printf(data_csum,		"%i", dc->disk.data_csum);
dc                196 drivers/md/bcache/sysfs.c 		     wb ? atomic_long_read(&dc->writeback_rate.rate) << 9 : 0);
dc                197 drivers/md/bcache/sysfs.c 	sysfs_printf(io_errors,		"%i", atomic_read(&dc->io_errors));
dc                198 drivers/md/bcache/sysfs.c 	sysfs_printf(io_error_limit,	"%i", dc->error_limit);
dc                199 drivers/md/bcache/sysfs.c 	sysfs_printf(io_disable,	"%i", dc->io_disable);
dc                219 drivers/md/bcache/sysfs.c 			   wb ? atomic_long_read(&dc->writeback_rate.rate) << 9
dc                221 drivers/md/bcache/sysfs.c 		bch_hprint(dirty, bcache_dev_sectors_dirty(&dc->disk) << 9);
dc                222 drivers/md/bcache/sysfs.c 		bch_hprint(target, dc->writeback_rate_target << 9);
dc                224 drivers/md/bcache/sysfs.c 			   wb ? dc->writeback_rate_proportional << 9 : 0);
dc                226 drivers/md/bcache/sysfs.c 			   wb ? dc->writeback_rate_integral_scaled << 9 : 0);
dc                227 drivers/md/bcache/sysfs.c 		bch_hprint(change, wb ? dc->writeback_rate_change << 9 : 0);
dc                228 drivers/md/bcache/sysfs.c 		next_io = wb ? div64_s64(dc->writeback_rate.next-local_clock(),
dc                244 drivers/md/bcache/sysfs.c 		     bcache_dev_sectors_dirty(&dc->disk) << 9);
dc                246 drivers/md/bcache/sysfs.c 	sysfs_hprint(stripe_size,	 ((uint64_t)dc->disk.stripe_size) << 9);
dc                252 drivers/md/bcache/sysfs.c 	sysfs_print(running,		atomic_read(&dc->running));
dc                253 drivers/md/bcache/sysfs.c 	sysfs_print(state,		states[BDEV_STATE(&dc->sb)]);
dc                256 drivers/md/bcache/sysfs.c 		memcpy(buf, dc->sb.label, SB_LABEL_SIZE);
dc                263 drivers/md/bcache/sysfs.c 		snprintf(buf, BDEVNAME_SIZE + 1, "%s", dc->backing_dev_name);
dc                270 drivers/md/bcache/sysfs.c 		snprintf(buf, 36+1, "%pU", dc->sb.uuid);
dc                282 drivers/md/bcache/sysfs.c 	struct cached_dev *dc = container_of(kobj, struct cached_dev,
dc                292 drivers/md/bcache/sysfs.c #define d_strtoul(var)		sysfs_strtoul(var, dc->var)
dc                293 drivers/md/bcache/sysfs.c #define d_strtoul_nonzero(var)	sysfs_strtoul_clamp(var, dc->var, 1, INT_MAX)
dc                294 drivers/md/bcache/sysfs.c #define d_strtoi_h(var)		sysfs_hatoi(var, dc->var)
dc                296 drivers/md/bcache/sysfs.c 	sysfs_strtoul(data_csum,	dc->disk.data_csum);
dc                298 drivers/md/bcache/sysfs.c 	sysfs_strtoul_bool(bypass_torture_test, dc->bypass_torture_test);
dc                299 drivers/md/bcache/sysfs.c 	sysfs_strtoul_bool(writeback_metadata, dc->writeback_metadata);
dc                300 drivers/md/bcache/sysfs.c 	sysfs_strtoul_bool(writeback_running, dc->writeback_running);
dc                301 drivers/md/bcache/sysfs.c 	sysfs_strtoul_clamp(writeback_delay, dc->writeback_delay, 0, UINT_MAX);
dc                303 drivers/md/bcache/sysfs.c 	sysfs_strtoul_clamp(writeback_percent, dc->writeback_percent,
dc                308 drivers/md/bcache/sysfs.c 		long int v = atomic_long_read(&dc->writeback_rate.rate);
dc                313 drivers/md/bcache/sysfs.c 			atomic_long_set(&dc->writeback_rate.rate, v);
dc                321 drivers/md/bcache/sysfs.c 			    dc->writeback_rate_update_seconds,
dc                324 drivers/md/bcache/sysfs.c 			    dc->writeback_rate_i_term_inverse,
dc                327 drivers/md/bcache/sysfs.c 			    dc->writeback_rate_p_term_inverse,
dc                330 drivers/md/bcache/sysfs.c 			    dc->writeback_rate_minimum,
dc                333 drivers/md/bcache/sysfs.c 	sysfs_strtoul_clamp(io_error_limit, dc->error_limit, 0, INT_MAX);
dc                338 drivers/md/bcache/sysfs.c 		dc->io_disable = v ? 1 : 0;
dc                342 drivers/md/bcache/sysfs.c 			    dc->sequential_cutoff,
dc                347 drivers/md/bcache/sysfs.c 		bch_cache_accounting_clear(&dc->accounting);
dc                351 drivers/md/bcache/sysfs.c 		v = bch_cached_dev_run(dc);
dc                361 drivers/md/bcache/sysfs.c 		if ((unsigned int) v != BDEV_CACHE_MODE(&dc->sb)) {
dc                362 drivers/md/bcache/sysfs.c 			SET_BDEV_CACHE_MODE(&dc->sb, v);
dc                363 drivers/md/bcache/sysfs.c 			bch_write_bdev_super(dc, NULL);
dc                372 drivers/md/bcache/sysfs.c 		if ((unsigned int) v != dc->cache_readahead_policy)
dc                373 drivers/md/bcache/sysfs.c 			dc->cache_readahead_policy = v;
dc                381 drivers/md/bcache/sysfs.c 		dc->stop_when_cache_set_failed = v;
dc                387 drivers/md/bcache/sysfs.c 		memcpy(dc->sb.label, buf, size);
dc                389 drivers/md/bcache/sysfs.c 			dc->sb.label[size] = '\0';
dc                390 drivers/md/bcache/sysfs.c 		if (size && dc->sb.label[size - 1] == '\n')
dc                391 drivers/md/bcache/sysfs.c 			dc->sb.label[size - 1] = '\0';
dc                392 drivers/md/bcache/sysfs.c 		bch_write_bdev_super(dc, NULL);
dc                393 drivers/md/bcache/sysfs.c 		if (dc->disk.c) {
dc                394 drivers/md/bcache/sysfs.c 			memcpy(dc->disk.c->uuids[dc->disk.id].label,
dc                396 drivers/md/bcache/sysfs.c 			bch_uuid_write(dc->disk.c);
dc                402 drivers/md/bcache/sysfs.c 		add_uevent_var(env, "CACHED_UUID=%pU", dc->sb.uuid),
dc                404 drivers/md/bcache/sysfs.c 		kobject_uevent_env(&disk_to_dev(dc->disk.disk)->kobj,
dc                418 drivers/md/bcache/sysfs.c 			v = bch_cached_dev_attach(dc, c, set_uuid);
dc                427 drivers/md/bcache/sysfs.c 	if (attr == &sysfs_detach && dc->disk.c)
dc                428 drivers/md/bcache/sysfs.c 		bch_cached_dev_detach(dc);
dc                431 drivers/md/bcache/sysfs.c 		bcache_device_stop(&dc->disk);
dc                438 drivers/md/bcache/sysfs.c 	struct cached_dev *dc = container_of(kobj, struct cached_dev,
dc                450 drivers/md/bcache/sysfs.c 		if (IS_ERR_OR_NULL(dc->writeback_thread)) {
dc                455 drivers/md/bcache/sysfs.c 			if (dc->writeback_running) {
dc                456 drivers/md/bcache/sysfs.c 				dc->writeback_running = false;
dc                458 drivers/md/bcache/sysfs.c 						dc->disk.disk->disk_name);
dc                465 drivers/md/bcache/sysfs.c 			bch_writeback_queue(dc);
dc                473 drivers/md/bcache/sysfs.c 		if ((dc->disk.c != NULL) &&
dc                474 drivers/md/bcache/sysfs.c 		    (!test_and_set_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags)))
dc                475 drivers/md/bcache/sysfs.c 			schedule_delayed_work(&dc->writeback_rate_update,
dc                476 drivers/md/bcache/sysfs.c 				      dc->writeback_rate_update_seconds * HZ);
dc                 30 drivers/md/bcache/writeback.c static uint64_t __calc_target_rate(struct cached_dev *dc)
dc                 32 drivers/md/bcache/writeback.c 	struct cache_set *c = dc->disk.c;
dc                 48 drivers/md/bcache/writeback.c 		div64_u64(bdev_sectors(dc->bdev) << WRITEBACK_SHARE_SHIFT,
dc                 52 drivers/md/bcache/writeback.c 		div_u64(cache_sectors * dc->writeback_percent, 100);
dc                 61 drivers/md/bcache/writeback.c static void __update_writeback_rate(struct cached_dev *dc)
dc                 83 drivers/md/bcache/writeback.c 	int64_t target = __calc_target_rate(dc);
dc                 84 drivers/md/bcache/writeback.c 	int64_t dirty = bcache_dev_sectors_dirty(&dc->disk);
dc                 87 drivers/md/bcache/writeback.c 		div_s64(error, dc->writeback_rate_p_term_inverse);
dc                 91 drivers/md/bcache/writeback.c 	if ((error < 0 && dc->writeback_rate_integral > 0) ||
dc                 93 drivers/md/bcache/writeback.c 			 dc->writeback_rate.next + NSEC_PER_MSEC))) {
dc                104 drivers/md/bcache/writeback.c 		dc->writeback_rate_integral += error *
dc                105 drivers/md/bcache/writeback.c 			dc->writeback_rate_update_seconds;
dc                108 drivers/md/bcache/writeback.c 	integral_scaled = div_s64(dc->writeback_rate_integral,
dc                109 drivers/md/bcache/writeback.c 			dc->writeback_rate_i_term_inverse);
dc                112 drivers/md/bcache/writeback.c 			dc->writeback_rate_minimum, NSEC_PER_SEC);
dc                114 drivers/md/bcache/writeback.c 	dc->writeback_rate_proportional = proportional_scaled;
dc                115 drivers/md/bcache/writeback.c 	dc->writeback_rate_integral_scaled = integral_scaled;
dc                116 drivers/md/bcache/writeback.c 	dc->writeback_rate_change = new_rate -
dc                117 drivers/md/bcache/writeback.c 			atomic_long_read(&dc->writeback_rate.rate);
dc                118 drivers/md/bcache/writeback.c 	atomic_long_set(&dc->writeback_rate.rate, new_rate);
dc                119 drivers/md/bcache/writeback.c 	dc->writeback_rate_target = target;
dc                123 drivers/md/bcache/writeback.c 				       struct cached_dev *dc)
dc                148 drivers/md/bcache/writeback.c 	atomic_long_set(&dc->writeback_rate.rate, INT_MAX);
dc                151 drivers/md/bcache/writeback.c 	dc->writeback_rate_proportional = 0;
dc                152 drivers/md/bcache/writeback.c 	dc->writeback_rate_integral_scaled = 0;
dc                153 drivers/md/bcache/writeback.c 	dc->writeback_rate_change = 0;
dc                171 drivers/md/bcache/writeback.c 	struct cached_dev *dc = container_of(to_delayed_work(work),
dc                174 drivers/md/bcache/writeback.c 	struct cache_set *c = dc->disk.c;
dc                180 drivers/md/bcache/writeback.c 	set_bit(BCACHE_DEV_RATE_DW_RUNNING, &dc->disk.flags);
dc                188 drivers/md/bcache/writeback.c 	if (!test_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags) ||
dc                190 drivers/md/bcache/writeback.c 		clear_bit(BCACHE_DEV_RATE_DW_RUNNING, &dc->disk.flags);
dc                196 drivers/md/bcache/writeback.c 	if (atomic_read(&dc->has_dirty) && dc->writeback_percent) {
dc                203 drivers/md/bcache/writeback.c 		if (!set_at_max_writeback_rate(c, dc)) {
dc                204 drivers/md/bcache/writeback.c 			down_read(&dc->writeback_lock);
dc                205 drivers/md/bcache/writeback.c 			__update_writeback_rate(dc);
dc                207 drivers/md/bcache/writeback.c 			up_read(&dc->writeback_lock);
dc                216 drivers/md/bcache/writeback.c 	if (test_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags) &&
dc                218 drivers/md/bcache/writeback.c 		schedule_delayed_work(&dc->writeback_rate_update,
dc                219 drivers/md/bcache/writeback.c 			      dc->writeback_rate_update_seconds * HZ);
dc                226 drivers/md/bcache/writeback.c 	clear_bit(BCACHE_DEV_RATE_DW_RUNNING, &dc->disk.flags);
dc                231 drivers/md/bcache/writeback.c static unsigned int writeback_delay(struct cached_dev *dc,
dc                234 drivers/md/bcache/writeback.c 	if (test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags) ||
dc                235 drivers/md/bcache/writeback.c 	    !dc->writeback_percent)
dc                238 drivers/md/bcache/writeback.c 	return bch_next_delay(&dc->writeback_rate, sectors);
dc                243 drivers/md/bcache/writeback.c 	struct cached_dev	*dc;
dc                255 drivers/md/bcache/writeback.c 	if (!io->dc->writeback_percent)
dc                274 drivers/md/bcache/writeback.c 	struct cached_dev *dc = io->dc;
dc                291 drivers/md/bcache/writeback.c 			atomic_inc(&PTR_BUCKET(dc->disk.c, &w->key, i)->pin);
dc                293 drivers/md/bcache/writeback.c 		ret = bch_btree_insert(dc->disk.c, &keys, NULL, &w->key);
dc                299 drivers/md/bcache/writeback.c 				? &dc->disk.c->writeback_keys_failed
dc                300 drivers/md/bcache/writeback.c 				: &dc->disk.c->writeback_keys_done);
dc                303 drivers/md/bcache/writeback.c 	bch_keybuf_del(&dc->writeback_keys, w);
dc                304 drivers/md/bcache/writeback.c 	up(&dc->in_flight);
dc                316 drivers/md/bcache/writeback.c 		bch_count_backing_io_errors(io->dc, bio);
dc                326 drivers/md/bcache/writeback.c 	struct cached_dev *dc = io->dc;
dc                330 drivers/md/bcache/writeback.c 	if (atomic_read(&dc->writeback_sequence_next) != io->sequence) {
dc                332 drivers/md/bcache/writeback.c 		closure_wait(&dc->writeback_ordering_wait, cl);
dc                334 drivers/md/bcache/writeback.c 		if (atomic_read(&dc->writeback_sequence_next) == io->sequence) {
dc                339 drivers/md/bcache/writeback.c 			closure_wake_up(&dc->writeback_ordering_wait);
dc                342 drivers/md/bcache/writeback.c 		continue_at(cl, write_dirty, io->dc->writeback_write_wq);
dc                358 drivers/md/bcache/writeback.c 		bio_set_dev(&io->bio, io->dc->bdev);
dc                362 drivers/md/bcache/writeback.c 		closure_bio_submit(io->dc->disk.c, &io->bio, cl);
dc                365 drivers/md/bcache/writeback.c 	atomic_set(&dc->writeback_sequence_next, next_sequence);
dc                366 drivers/md/bcache/writeback.c 	closure_wake_up(&dc->writeback_ordering_wait);
dc                368 drivers/md/bcache/writeback.c 	continue_at(cl, write_dirty_finish, io->dc->writeback_write_wq);
dc                377 drivers/md/bcache/writeback.c 	bch_count_io_errors(PTR_CACHE(io->dc->disk.c, &w->key, 0),
dc                388 drivers/md/bcache/writeback.c 	closure_bio_submit(io->dc->disk.c, &io->bio, cl);
dc                390 drivers/md/bcache/writeback.c 	continue_at(cl, write_dirty, io->dc->writeback_write_wq);
dc                393 drivers/md/bcache/writeback.c static void read_dirty(struct cached_dev *dc)
dc                403 drivers/md/bcache/writeback.c 	BUG_ON(!llist_empty(&dc->writeback_ordering_wait.list));
dc                404 drivers/md/bcache/writeback.c 	atomic_set(&dc->writeback_sequence_next, sequence);
dc                412 drivers/md/bcache/writeback.c 	next = bch_keybuf_next(&dc->writeback_keys);
dc                415 drivers/md/bcache/writeback.c 	       !test_bit(CACHE_SET_IO_DISABLE, &dc->disk.c->flags) &&
dc                421 drivers/md/bcache/writeback.c 			BUG_ON(ptr_stale(dc->disk.c, &next->key, 0));
dc                452 drivers/md/bcache/writeback.c 		} while ((next = bch_keybuf_next(&dc->writeback_keys)));
dc                467 drivers/md/bcache/writeback.c 			io->dc		= dc;
dc                474 drivers/md/bcache/writeback.c 				    PTR_CACHE(dc->disk.c, &w->key, 0)->bdev);
dc                482 drivers/md/bcache/writeback.c 			down(&dc->in_flight);
dc                492 drivers/md/bcache/writeback.c 		delay = writeback_delay(dc, size);
dc                495 drivers/md/bcache/writeback.c 		       !test_bit(CACHE_SET_IO_DISABLE, &dc->disk.c->flags) &&
dc                498 drivers/md/bcache/writeback.c 			delay = writeback_delay(dc, 0);
dc                506 drivers/md/bcache/writeback.c 		bch_keybuf_del(&dc->writeback_keys, w);
dc                558 drivers/md/bcache/writeback.c 	struct cached_dev *dc = container_of(buf,
dc                562 drivers/md/bcache/writeback.c 	BUG_ON(KEY_INODE(k) != dc->disk.id);
dc                567 drivers/md/bcache/writeback.c static void refill_full_stripes(struct cached_dev *dc)
dc                569 drivers/md/bcache/writeback.c 	struct keybuf *buf = &dc->writeback_keys;
dc                573 drivers/md/bcache/writeback.c 	stripe = offset_to_stripe(&dc->disk, KEY_OFFSET(&buf->last_scanned));
dc                575 drivers/md/bcache/writeback.c 	if (stripe >= dc->disk.nr_stripes)
dc                581 drivers/md/bcache/writeback.c 		stripe = find_next_bit(dc->disk.full_dirty_stripes,
dc                582 drivers/md/bcache/writeback.c 				       dc->disk.nr_stripes, stripe);
dc                584 drivers/md/bcache/writeback.c 		if (stripe == dc->disk.nr_stripes)
dc                587 drivers/md/bcache/writeback.c 		next_stripe = find_next_zero_bit(dc->disk.full_dirty_stripes,
dc                588 drivers/md/bcache/writeback.c 						 dc->disk.nr_stripes, stripe);
dc                590 drivers/md/bcache/writeback.c 		buf->last_scanned = KEY(dc->disk.id,
dc                591 drivers/md/bcache/writeback.c 					stripe * dc->disk.stripe_size, 0);
dc                593 drivers/md/bcache/writeback.c 		bch_refill_keybuf(dc->disk.c, buf,
dc                594 drivers/md/bcache/writeback.c 				  &KEY(dc->disk.id,
dc                595 drivers/md/bcache/writeback.c 				       next_stripe * dc->disk.stripe_size, 0),
dc                606 drivers/md/bcache/writeback.c 		if (stripe == dc->disk.nr_stripes) {
dc                616 drivers/md/bcache/writeback.c static bool refill_dirty(struct cached_dev *dc)
dc                618 drivers/md/bcache/writeback.c 	struct keybuf *buf = &dc->writeback_keys;
dc                619 drivers/md/bcache/writeback.c 	struct bkey start = KEY(dc->disk.id, 0, 0);
dc                620 drivers/md/bcache/writeback.c 	struct bkey end = KEY(dc->disk.id, MAX_KEY_OFFSET, 0);
dc                632 drivers/md/bcache/writeback.c 	if (dc->partial_stripes_expensive) {
dc                633 drivers/md/bcache/writeback.c 		refill_full_stripes(dc);
dc                639 drivers/md/bcache/writeback.c 	bch_refill_keybuf(dc->disk.c, buf, &end, dirty_pred);
dc                649 drivers/md/bcache/writeback.c 	bch_refill_keybuf(dc->disk.c, buf, &start_pos, dirty_pred);
dc                656 drivers/md/bcache/writeback.c 	struct cached_dev *dc = arg;
dc                657 drivers/md/bcache/writeback.c 	struct cache_set *c = dc->disk.c;
dc                660 drivers/md/bcache/writeback.c 	bch_ratelimit_reset(&dc->writeback_rate);
dc                664 drivers/md/bcache/writeback.c 		down_write(&dc->writeback_lock);
dc                673 drivers/md/bcache/writeback.c 		if (!test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags) &&
dc                674 drivers/md/bcache/writeback.c 		    (!atomic_read(&dc->has_dirty) || !dc->writeback_running)) {
dc                675 drivers/md/bcache/writeback.c 			up_write(&dc->writeback_lock);
dc                688 drivers/md/bcache/writeback.c 		searched_full_index = refill_dirty(dc);
dc                691 drivers/md/bcache/writeback.c 		    RB_EMPTY_ROOT(&dc->writeback_keys.keys)) {
dc                692 drivers/md/bcache/writeback.c 			atomic_set(&dc->has_dirty, 0);
dc                693 drivers/md/bcache/writeback.c 			SET_BDEV_STATE(&dc->sb, BDEV_STATE_CLEAN);
dc                694 drivers/md/bcache/writeback.c 			bch_write_bdev_super(dc, NULL);
dc                701 drivers/md/bcache/writeback.c 			if (test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags)) {
dc                702 drivers/md/bcache/writeback.c 				up_write(&dc->writeback_lock);
dc                724 drivers/md/bcache/writeback.c 		up_write(&dc->writeback_lock);
dc                726 drivers/md/bcache/writeback.c 		read_dirty(dc);
dc                729 drivers/md/bcache/writeback.c 			unsigned int delay = dc->writeback_delay * HZ;
dc                734 drivers/md/bcache/writeback.c 			       !test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags))
dc                737 drivers/md/bcache/writeback.c 			bch_ratelimit_reset(&dc->writeback_rate);
dc                741 drivers/md/bcache/writeback.c 	if (dc->writeback_write_wq) {
dc                742 drivers/md/bcache/writeback.c 		flush_workqueue(dc->writeback_write_wq);
dc                743 drivers/md/bcache/writeback.c 		destroy_workqueue(dc->writeback_write_wq);
dc                745 drivers/md/bcache/writeback.c 	cached_dev_put(dc);
dc                807 drivers/md/bcache/writeback.c void bch_cached_dev_writeback_init(struct cached_dev *dc)
dc                809 drivers/md/bcache/writeback.c 	sema_init(&dc->in_flight, 64);
dc                810 drivers/md/bcache/writeback.c 	init_rwsem(&dc->writeback_lock);
dc                811 drivers/md/bcache/writeback.c 	bch_keybuf_init(&dc->writeback_keys);
dc                813 drivers/md/bcache/writeback.c 	dc->writeback_metadata		= true;
dc                814 drivers/md/bcache/writeback.c 	dc->writeback_running		= false;
dc                815 drivers/md/bcache/writeback.c 	dc->writeback_percent		= 10;
dc                816 drivers/md/bcache/writeback.c 	dc->writeback_delay		= 30;
dc                817 drivers/md/bcache/writeback.c 	atomic_long_set(&dc->writeback_rate.rate, 1024);
dc                818 drivers/md/bcache/writeback.c 	dc->writeback_rate_minimum	= 8;
dc                820 drivers/md/bcache/writeback.c 	dc->writeback_rate_update_seconds = WRITEBACK_RATE_UPDATE_SECS_DEFAULT;
dc                821 drivers/md/bcache/writeback.c 	dc->writeback_rate_p_term_inverse = 40;
dc                822 drivers/md/bcache/writeback.c 	dc->writeback_rate_i_term_inverse = 10000;
dc                824 drivers/md/bcache/writeback.c 	WARN_ON(test_and_clear_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags));
dc                825 drivers/md/bcache/writeback.c 	INIT_DELAYED_WORK(&dc->writeback_rate_update, update_writeback_rate);
dc                828 drivers/md/bcache/writeback.c int bch_cached_dev_writeback_start(struct cached_dev *dc)
dc                830 drivers/md/bcache/writeback.c 	dc->writeback_write_wq = alloc_workqueue("bcache_writeback_wq",
dc                832 drivers/md/bcache/writeback.c 	if (!dc->writeback_write_wq)
dc                835 drivers/md/bcache/writeback.c 	cached_dev_get(dc);
dc                836 drivers/md/bcache/writeback.c 	dc->writeback_thread = kthread_create(bch_writeback_thread, dc,
dc                838 drivers/md/bcache/writeback.c 	if (IS_ERR(dc->writeback_thread)) {
dc                839 drivers/md/bcache/writeback.c 		cached_dev_put(dc);
dc                840 drivers/md/bcache/writeback.c 		destroy_workqueue(dc->writeback_write_wq);
dc                841 drivers/md/bcache/writeback.c 		return PTR_ERR(dc->writeback_thread);
dc                843 drivers/md/bcache/writeback.c 	dc->writeback_running = true;
dc                845 drivers/md/bcache/writeback.c 	WARN_ON(test_and_set_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags));
dc                846 drivers/md/bcache/writeback.c 	schedule_delayed_work(&dc->writeback_rate_update,
dc                847 drivers/md/bcache/writeback.c 			      dc->writeback_rate_update_seconds * HZ);
dc                849 drivers/md/bcache/writeback.c 	bch_writeback_queue(dc);
dc                 43 drivers/md/bcache/writeback.h static inline bool bcache_dev_stripe_dirty(struct cached_dev *dc,
dc                 47 drivers/md/bcache/writeback.h 	unsigned int stripe = offset_to_stripe(&dc->disk, offset);
dc                 50 drivers/md/bcache/writeback.h 		if (atomic_read(dc->disk.stripe_sectors_dirty + stripe))
dc                 53 drivers/md/bcache/writeback.h 		if (nr_sectors <= dc->disk.stripe_size)
dc                 56 drivers/md/bcache/writeback.h 		nr_sectors -= dc->disk.stripe_size;
dc                 64 drivers/md/bcache/writeback.h static inline bool should_writeback(struct cached_dev *dc, struct bio *bio,
dc                 67 drivers/md/bcache/writeback.h 	unsigned int in_use = dc->disk.c->gc_stats.in_use;
dc                 70 drivers/md/bcache/writeback.h 	    test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags) ||
dc                 77 drivers/md/bcache/writeback.h 	if (dc->partial_stripes_expensive &&
dc                 78 drivers/md/bcache/writeback.h 	    bcache_dev_stripe_dirty(dc, bio->bi_iter.bi_sector,
dc                 90 drivers/md/bcache/writeback.h static inline void bch_writeback_queue(struct cached_dev *dc)
dc                 92 drivers/md/bcache/writeback.h 	if (!IS_ERR_OR_NULL(dc->writeback_thread))
dc                 93 drivers/md/bcache/writeback.h 		wake_up_process(dc->writeback_thread);
dc                 96 drivers/md/bcache/writeback.h static inline void bch_writeback_add(struct cached_dev *dc)
dc                 98 drivers/md/bcache/writeback.h 	if (!atomic_read(&dc->has_dirty) &&
dc                 99 drivers/md/bcache/writeback.h 	    !atomic_xchg(&dc->has_dirty, 1)) {
dc                100 drivers/md/bcache/writeback.h 		if (BDEV_STATE(&dc->sb) != BDEV_STATE_DIRTY) {
dc                101 drivers/md/bcache/writeback.h 			SET_BDEV_STATE(&dc->sb, BDEV_STATE_DIRTY);
dc                103 drivers/md/bcache/writeback.h 			bch_write_bdev_super(dc, NULL);
dc                106 drivers/md/bcache/writeback.h 		bch_writeback_queue(dc);
dc                114 drivers/md/bcache/writeback.h void bch_cached_dev_writeback_init(struct cached_dev *dc);
dc                115 drivers/md/bcache/writeback.h int bch_cached_dev_writeback_start(struct cached_dev *dc);
dc                 53 drivers/md/dm-delay.c 	struct delay_c *dc = from_timer(dc, t, delay_timer);
dc                 55 drivers/md/dm-delay.c 	queue_work(dc->kdelayd_wq, &dc->flush_expired_bios);
dc                 58 drivers/md/dm-delay.c static void queue_timeout(struct delay_c *dc, unsigned long expires)
dc                 60 drivers/md/dm-delay.c 	mutex_lock(&dc->timer_lock);
dc                 62 drivers/md/dm-delay.c 	if (!timer_pending(&dc->delay_timer) || expires < dc->delay_timer.expires)
dc                 63 drivers/md/dm-delay.c 		mod_timer(&dc->delay_timer, expires);
dc                 65 drivers/md/dm-delay.c 	mutex_unlock(&dc->timer_lock);
dc                 80 drivers/md/dm-delay.c static struct bio *flush_delayed_bios(struct delay_c *dc, int flush_all)
dc                 88 drivers/md/dm-delay.c 	list_for_each_entry_safe(delayed, next, &dc->delayed_bios, list) {
dc                107 drivers/md/dm-delay.c 		queue_timeout(dc, next_expires);
dc                114 drivers/md/dm-delay.c 	struct delay_c *dc;
dc                116 drivers/md/dm-delay.c 	dc = container_of(work, struct delay_c, flush_expired_bios);
dc                117 drivers/md/dm-delay.c 	flush_bios(flush_delayed_bios(dc, 0));
dc                122 drivers/md/dm-delay.c 	struct delay_c *dc = ti->private;
dc                124 drivers/md/dm-delay.c 	if (dc->kdelayd_wq)
dc                125 drivers/md/dm-delay.c 		destroy_workqueue(dc->kdelayd_wq);
dc                127 drivers/md/dm-delay.c 	if (dc->read.dev)
dc                128 drivers/md/dm-delay.c 		dm_put_device(ti, dc->read.dev);
dc                129 drivers/md/dm-delay.c 	if (dc->write.dev)
dc                130 drivers/md/dm-delay.c 		dm_put_device(ti, dc->write.dev);
dc                131 drivers/md/dm-delay.c 	if (dc->flush.dev)
dc                132 drivers/md/dm-delay.c 		dm_put_device(ti, dc->flush.dev);
dc                134 drivers/md/dm-delay.c 	mutex_destroy(&dc->timer_lock);
dc                136 drivers/md/dm-delay.c 	kfree(dc);
dc                175 drivers/md/dm-delay.c 	struct delay_c *dc;
dc                183 drivers/md/dm-delay.c 	dc = kzalloc(sizeof(*dc), GFP_KERNEL);
dc                184 drivers/md/dm-delay.c 	if (!dc) {
dc                189 drivers/md/dm-delay.c 	ti->private = dc;
dc                190 drivers/md/dm-delay.c 	timer_setup(&dc->delay_timer, handle_delayed_timer, 0);
dc                191 drivers/md/dm-delay.c 	INIT_WORK(&dc->flush_expired_bios, flush_expired_bios);
dc                192 drivers/md/dm-delay.c 	INIT_LIST_HEAD(&dc->delayed_bios);
dc                193 drivers/md/dm-delay.c 	mutex_init(&dc->timer_lock);
dc                194 drivers/md/dm-delay.c 	atomic_set(&dc->may_delay, 1);
dc                195 drivers/md/dm-delay.c 	dc->argc = argc;
dc                197 drivers/md/dm-delay.c 	ret = delay_class_ctr(ti, &dc->read, argv);
dc                202 drivers/md/dm-delay.c 		ret = delay_class_ctr(ti, &dc->write, argv);
dc                205 drivers/md/dm-delay.c 		ret = delay_class_ctr(ti, &dc->flush, argv);
dc                211 drivers/md/dm-delay.c 	ret = delay_class_ctr(ti, &dc->write, argv + 3);
dc                215 drivers/md/dm-delay.c 		ret = delay_class_ctr(ti, &dc->flush, argv + 3);
dc                221 drivers/md/dm-delay.c 	ret = delay_class_ctr(ti, &dc->flush, argv + 6);
dc                226 drivers/md/dm-delay.c 	dc->kdelayd_wq = alloc_workqueue("kdelayd", WQ_MEM_RECLAIM, 0);
dc                227 drivers/md/dm-delay.c 	if (!dc->kdelayd_wq) {
dc                243 drivers/md/dm-delay.c static int delay_bio(struct delay_c *dc, struct delay_class *c, struct bio *bio)
dc                248 drivers/md/dm-delay.c 	if (!c->delay || !atomic_read(&dc->may_delay))
dc                253 drivers/md/dm-delay.c 	delayed->context = dc;
dc                258 drivers/md/dm-delay.c 	list_add_tail(&delayed->list, &dc->delayed_bios);
dc                261 drivers/md/dm-delay.c 	queue_timeout(dc, expires);
dc                268 drivers/md/dm-delay.c 	struct delay_c *dc = ti->private;
dc                270 drivers/md/dm-delay.c 	atomic_set(&dc->may_delay, 0);
dc                271 drivers/md/dm-delay.c 	del_timer_sync(&dc->delay_timer);
dc                272 drivers/md/dm-delay.c 	flush_bios(flush_delayed_bios(dc, 1));
dc                277 drivers/md/dm-delay.c 	struct delay_c *dc = ti->private;
dc                279 drivers/md/dm-delay.c 	atomic_set(&dc->may_delay, 1);
dc                284 drivers/md/dm-delay.c 	struct delay_c *dc = ti->private;
dc                290 drivers/md/dm-delay.c 			c = &dc->flush;
dc                292 drivers/md/dm-delay.c 			c = &dc->write;
dc                294 drivers/md/dm-delay.c 		c = &dc->read;
dc                301 drivers/md/dm-delay.c 	return delay_bio(dc, c, bio);
dc                310 drivers/md/dm-delay.c 	struct delay_c *dc = ti->private;
dc                315 drivers/md/dm-delay.c 		DMEMIT("%u %u %u", dc->read.ops, dc->write.ops, dc->flush.ops);
dc                319 drivers/md/dm-delay.c 		DMEMIT_DELAY_CLASS(&dc->read);
dc                320 drivers/md/dm-delay.c 		if (dc->argc >= 6) {
dc                322 drivers/md/dm-delay.c 			DMEMIT_DELAY_CLASS(&dc->write);
dc                324 drivers/md/dm-delay.c 		if (dc->argc >= 9) {
dc                326 drivers/md/dm-delay.c 			DMEMIT_DELAY_CLASS(&dc->flush);
dc                335 drivers/md/dm-delay.c 	struct delay_c *dc = ti->private;
dc                338 drivers/md/dm-delay.c 	ret = fn(ti, dc->read.dev, dc->read.start, ti->len, data);
dc                341 drivers/md/dm-delay.c 	ret = fn(ti, dc->write.dev, dc->write.start, ti->len, data);
dc                344 drivers/md/dm-delay.c 	ret = fn(ti, dc->flush.dev, dc->flush.start, ti->len, data);
dc                157 drivers/media/dvb-frontends/dib0090.c 	const struct dc_calibration *dc;
dc               1659 drivers/media/dvb-frontends/dib0090.c 	if (state->dc->addr == 0x07)
dc               1664 drivers/media/dvb-frontends/dib0090.c 	*val &= ~(0x1f << state->dc->offset);
dc               1665 drivers/media/dvb-frontends/dib0090.c 	*val |= state->step << state->dc->offset;
dc               1667 drivers/media/dvb-frontends/dib0090.c 	dib0090_write_reg(state, state->dc->addr, *val);
dc               1691 drivers/media/dvb-frontends/dib0090.c 		state->dc = dc_table;
dc               1694 drivers/media/dvb-frontends/dib0090.c 			state->dc = dc_p1g_table;
dc               1699 drivers/media/dvb-frontends/dib0090.c 			(state->dc->i == 1) ? "I" : "Q");
dc               1700 drivers/media/dvb-frontends/dib0090.c 		dib0090_write_reg(state, 0x01, state->dc->bb1);
dc               1701 drivers/media/dvb-frontends/dib0090.c 		dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));
dc               1731 drivers/media/dvb-frontends/dib0090.c 			if (state->dc->pga && state->adc_diff < 0)
dc               1733 drivers/media/dvb-frontends/dib0090.c 			if (state->dc->pga == 0 && state->adc_diff > 0)
dc               1751 drivers/media/dvb-frontends/dib0090.c 			dprintk("BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd\n", state->dc->addr, state->adc_diff, state->step);
dc               1753 drivers/media/dvb-frontends/dib0090.c 			state->dc++;
dc               1754 drivers/media/dvb-frontends/dib0090.c 			if (state->dc->addr == 0)	/* done */
dc                237 drivers/media/pci/ivtv/ivtv-ioctl.c 		struct v4l2_decoder_cmd *dc, int try)
dc                244 drivers/media/pci/ivtv/ivtv-ioctl.c 	switch (dc->cmd) {
dc                246 drivers/media/pci/ivtv/ivtv-ioctl.c 		dc->flags &= V4L2_DEC_CMD_START_MUTE_AUDIO;
dc                247 drivers/media/pci/ivtv/ivtv-ioctl.c 		dc->start.speed = ivtv_validate_speed(itv->speed, dc->start.speed);
dc                248 drivers/media/pci/ivtv/ivtv-ioctl.c 		if (dc->start.speed < 0)
dc                249 drivers/media/pci/ivtv/ivtv-ioctl.c 			dc->start.format = V4L2_DEC_START_FMT_GOP;
dc                251 drivers/media/pci/ivtv/ivtv-ioctl.c 			dc->start.format = V4L2_DEC_START_FMT_NONE;
dc                252 drivers/media/pci/ivtv/ivtv-ioctl.c 		if (dc->start.speed != 500 && dc->start.speed != 1500)
dc                253 drivers/media/pci/ivtv/ivtv-ioctl.c 			dc->flags = dc->start.speed == 1000 ? 0 :
dc                257 drivers/media/pci/ivtv/ivtv-ioctl.c 		itv->speed_mute_audio = dc->flags & V4L2_DEC_CMD_START_MUTE_AUDIO;
dc                264 drivers/media/pci/ivtv/ivtv-ioctl.c 		return ivtv_start_decoding(id, dc->start.speed);
dc                268 drivers/media/pci/ivtv/ivtv-ioctl.c 		dc->flags &= V4L2_DEC_CMD_STOP_IMMEDIATELY | V4L2_DEC_CMD_STOP_TO_BLACK;
dc                269 drivers/media/pci/ivtv/ivtv-ioctl.c 		if (dc->flags & V4L2_DEC_CMD_STOP_IMMEDIATELY)
dc                270 drivers/media/pci/ivtv/ivtv-ioctl.c 			dc->stop.pts = 0;
dc                278 drivers/media/pci/ivtv/ivtv-ioctl.c 		return ivtv_stop_v4l2_decode_stream(s, dc->flags, dc->stop.pts);
dc                281 drivers/media/pci/ivtv/ivtv-ioctl.c 		dc->flags &= V4L2_DEC_CMD_PAUSE_TO_BLACK;
dc                289 drivers/media/pci/ivtv/ivtv-ioctl.c 				(dc->flags & V4L2_DEC_CMD_PAUSE_TO_BLACK) ? 1 : 0);
dc                295 drivers/media/pci/ivtv/ivtv-ioctl.c 		dc->flags = 0;
dc               1700 drivers/media/pci/ivtv/ivtv-ioctl.c 		struct v4l2_decoder_cmd dc;
dc               1703 drivers/media/pci/ivtv/ivtv-ioctl.c 		memset(&dc, 0, sizeof(dc));
dc               1704 drivers/media/pci/ivtv/ivtv-ioctl.c 		dc.cmd = V4L2_DEC_CMD_START;
dc               1705 drivers/media/pci/ivtv/ivtv-ioctl.c 		return ivtv_video_command(itv, id, &dc, 0);
dc               1709 drivers/media/pci/ivtv/ivtv-ioctl.c 		struct v4l2_decoder_cmd dc;
dc               1712 drivers/media/pci/ivtv/ivtv-ioctl.c 		memset(&dc, 0, sizeof(dc));
dc               1713 drivers/media/pci/ivtv/ivtv-ioctl.c 		dc.cmd = V4L2_DEC_CMD_STOP;
dc               1714 drivers/media/pci/ivtv/ivtv-ioctl.c 		dc.flags = V4L2_DEC_CMD_STOP_TO_BLACK | V4L2_DEC_CMD_STOP_IMMEDIATELY;
dc               1715 drivers/media/pci/ivtv/ivtv-ioctl.c 		return ivtv_video_command(itv, id, &dc, 0);
dc               1719 drivers/media/pci/ivtv/ivtv-ioctl.c 		struct v4l2_decoder_cmd dc;
dc               1722 drivers/media/pci/ivtv/ivtv-ioctl.c 		memset(&dc, 0, sizeof(dc));
dc               1723 drivers/media/pci/ivtv/ivtv-ioctl.c 		dc.cmd = V4L2_DEC_CMD_PAUSE;
dc               1724 drivers/media/pci/ivtv/ivtv-ioctl.c 		return ivtv_video_command(itv, id, &dc, 0);
dc               1728 drivers/media/pci/ivtv/ivtv-ioctl.c 		struct v4l2_decoder_cmd dc;
dc               1731 drivers/media/pci/ivtv/ivtv-ioctl.c 		memset(&dc, 0, sizeof(dc));
dc               1732 drivers/media/pci/ivtv/ivtv-ioctl.c 		dc.cmd = V4L2_DEC_CMD_RESUME;
dc               1733 drivers/media/pci/ivtv/ivtv-ioctl.c 		return ivtv_video_command(itv, id, &dc, 0);
dc               1740 drivers/media/pci/ivtv/ivtv-ioctl.c 		struct v4l2_decoder_cmd *dc = arg;
dc               1747 drivers/media/pci/ivtv/ivtv-ioctl.c 		return ivtv_video_command(itv, id, dc, try);
dc               1042 drivers/media/pci/ttpci/av7110_hw.c int av7110_osd_cmd(struct av7110 *av7110, osd_cmd_t *dc)
dc               1049 drivers/media/pci/ttpci/av7110_hw.c 	switch (dc->cmd) {
dc               1054 drivers/media/pci/ttpci/av7110_hw.c 		av7110->osdbpp[av7110->osdwin] = (dc->color - 1) & 7;
dc               1057 drivers/media/pci/ttpci/av7110_hw.c 				dc->x1 - dc->x0 + 1, dc->y1 - dc->y0 + 1);
dc               1060 drivers/media/pci/ttpci/av7110_hw.c 		if (!dc->data) {
dc               1061 drivers/media/pci/ttpci/av7110_hw.c 			ret = MoveWindowAbs(av7110, av7110->osdwin, dc->x0, dc->y0);
dc               1077 drivers/media/pci/ttpci/av7110_hw.c 		ret = DrawBlock(av7110, av7110->osdwin, 0, 0, 720, 576, dc->color);
dc               1080 drivers/media/pci/ttpci/av7110_hw.c 		ret = OSDSetColor(av7110, dc->color, dc->x0, dc->y0, dc->x1, dc->y1);
dc               1084 drivers/media/pci/ttpci/av7110_hw.c 			ret = OSDSetPalette(av7110, dc->data, dc->color, dc->x0);
dc               1086 drivers/media/pci/ttpci/av7110_hw.c 			int i, len = dc->x0-dc->color+1;
dc               1087 drivers/media/pci/ttpci/av7110_hw.c 			u8 __user *colors = (u8 __user *)dc->data;
dc               1098 drivers/media/pci/ttpci/av7110_hw.c 				ret = OSDSetColor(av7110, dc->color + i, r, g, b, blend);
dc               1106 drivers/media/pci/ttpci/av7110_hw.c 			 dc->x0, dc->y0, 0, 0, dc->color);
dc               1109 drivers/media/pci/ttpci/av7110_hw.c 		dc->y1 = dc->y0;
dc               1112 drivers/media/pci/ttpci/av7110_hw.c 		ret = OSDSetBlock(av7110, dc->x0, dc->y0, dc->x1, dc->y1, dc->color, dc->data);
dc               1115 drivers/media/pci/ttpci/av7110_hw.c 		ret = DrawBlock(av7110, av7110->osdwin, dc->x0, dc->y0,
dc               1116 drivers/media/pci/ttpci/av7110_hw.c 			  dc->x1-dc->x0+1, dc->y1, dc->color);
dc               1119 drivers/media/pci/ttpci/av7110_hw.c 		ret = DrawBlock(av7110, av7110->osdwin, dc->x0, dc->y0,
dc               1120 drivers/media/pci/ttpci/av7110_hw.c 			  dc->x1 - dc->x0 + 1, dc->y1 - dc->y0 + 1, dc->color);
dc               1124 drivers/media/pci/ttpci/av7110_hw.c 			 dc->x0, dc->y0, dc->x1 - dc->x0, dc->y1 - dc->y0, dc->color);
dc               1130 drivers/media/pci/ttpci/av7110_hw.c 		if (strncpy_from_user(textbuf, dc->data, 240) < 0) {
dc               1135 drivers/media/pci/ttpci/av7110_hw.c 		if (dc->x1 > 3)
dc               1136 drivers/media/pci/ttpci/av7110_hw.c 			dc->x1 = 3;
dc               1137 drivers/media/pci/ttpci/av7110_hw.c 		ret = SetFont(av7110, av7110->osdwin, dc->x1,
dc               1138 drivers/media/pci/ttpci/av7110_hw.c 			(u16) (dc->color & 0xffff), (u16) (dc->color >> 16));
dc               1142 drivers/media/pci/ttpci/av7110_hw.c 			ret = WriteText(av7110, av7110->osdwin, dc->x0, dc->y0, textbuf);
dc               1146 drivers/media/pci/ttpci/av7110_hw.c 		if (dc->x0 < 1 || dc->x0 > 7)
dc               1149 drivers/media/pci/ttpci/av7110_hw.c 			av7110->osdwin = dc->x0;
dc               1154 drivers/media/pci/ttpci/av7110_hw.c 		ret = MoveWindowAbs(av7110, av7110->osdwin, dc->x0, dc->y0);
dc               1159 drivers/media/pci/ttpci/av7110_hw.c 		if (dc->color < OSD_BITMAP1 || dc->color > OSD_CURSOR) {
dc               1163 drivers/media/pci/ttpci/av7110_hw.c 		if (dc->color >= OSD_BITMAP1 && dc->color <= OSD_BITMAP8HR)
dc               1164 drivers/media/pci/ttpci/av7110_hw.c 			av7110->osdbpp[av7110->osdwin] = (1 << (dc->color & 3)) - 1;
dc               1167 drivers/media/pci/ttpci/av7110_hw.c 		ret = CreateOSDWindow(av7110, av7110->osdwin, (osd_raw_window_t)dc->color,
dc               1168 drivers/media/pci/ttpci/av7110_hw.c 				dc->x1 - dc->x0 + 1, dc->y1 - dc->y0 + 1);
dc               1171 drivers/media/pci/ttpci/av7110_hw.c 		if (!dc->data) {
dc               1172 drivers/media/pci/ttpci/av7110_hw.c 			ret = MoveWindowAbs(av7110, av7110->osdwin, dc->x0, dc->y0);
dc               1184 drivers/media/pci/ttpci/av7110_hw.c 		dprintk(1, "av7110_osd_cmd(%d) returns with -ERESTARTSYS\n",dc->cmd);
dc               1186 drivers/media/pci/ttpci/av7110_hw.c 		dprintk(1, "av7110_osd_cmd(%d) returns with %d\n",dc->cmd,ret);
dc                490 drivers/media/pci/ttpci/av7110_hw.h extern int av7110_osd_cmd(struct av7110 *av7110, osd_cmd_t *dc);
dc               1060 drivers/media/platform/coda/coda-common.c 				struct v4l2_decoder_cmd *dc)
dc               1067 drivers/media/platform/coda/coda-common.c 	return v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dc);
dc               1071 drivers/media/platform/coda/coda-common.c 			    struct v4l2_decoder_cmd *dc)
dc               1081 drivers/media/platform/coda/coda-common.c 	ret = coda_try_decoder_cmd(file, fh, dc);
dc               1085 drivers/media/platform/coda/coda-common.c 	switch (dc->cmd) {
dc               1286 drivers/media/platform/vicodec/vicodec-core.c 			    struct v4l2_decoder_cmd *dc)
dc               1291 drivers/media/platform/vicodec/vicodec-core.c 	ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dc);
dc               1299 drivers/media/platform/vicodec/vicodec-core.c 	if (dc->cmd == V4L2_DEC_CMD_STOP)
dc                115 drivers/media/rc/ir-spi.c 	u8 dc;
dc                140 drivers/media/rc/ir-spi.c 	ret = of_property_read_u8(spi->dev.of_node, "duty-cycle", &dc);
dc                142 drivers/media/rc/ir-spi.c 		dc = 50;
dc                148 drivers/media/rc/ir-spi.c 	ir_spi_set_duty_cycle(idata->rc, dc);
dc               1140 drivers/media/v4l2-core/v4l2-mem2mem.c 				   struct v4l2_decoder_cmd *dc)
dc               1142 drivers/media/v4l2-core/v4l2-mem2mem.c 	if (dc->cmd != V4L2_DEC_CMD_STOP && dc->cmd != V4L2_DEC_CMD_START)
dc               1145 drivers/media/v4l2-core/v4l2-mem2mem.c 	dc->flags = 0;
dc               1147 drivers/media/v4l2-core/v4l2-mem2mem.c 	if (dc->cmd == V4L2_DEC_CMD_STOP) {
dc               1148 drivers/media/v4l2-core/v4l2-mem2mem.c 		dc->stop.pts = 0;
dc               1149 drivers/media/v4l2-core/v4l2-mem2mem.c 	} else if (dc->cmd == V4L2_DEC_CMD_START) {
dc               1150 drivers/media/v4l2-core/v4l2-mem2mem.c 		dc->start.speed = 0;
dc               1151 drivers/media/v4l2-core/v4l2-mem2mem.c 		dc->start.format = V4L2_DEC_START_FMT_NONE;
dc                 17 drivers/misc/mic/vop/vop_debugfs.c 	struct mic_device_ctrl *dc;
dc                 44 drivers/misc/mic/vop/vop_debugfs.c 		dc = (void *)d + mic_aligned_desc_size(d);
dc                 78 drivers/misc/mic/vop/vop_debugfs.c 		seq_printf(s, "Config Change %d ", dc->config_change);
dc                 79 drivers/misc/mic/vop/vop_debugfs.c 		seq_printf(s, "Vdev reset %d\n", dc->vdev_reset);
dc                 80 drivers/misc/mic/vop/vop_debugfs.c 		seq_printf(s, "Guest Ack %d ", dc->guest_ack);
dc                 81 drivers/misc/mic/vop/vop_debugfs.c 		seq_printf(s, "Host ack %d\n", dc->host_ack);
dc                 83 drivers/misc/mic/vop/vop_debugfs.c 			   dc->used_address_updated);
dc                 84 drivers/misc/mic/vop/vop_debugfs.c 		seq_printf(s, "Vdev 0x%llx\n", dc->vdev);
dc                 85 drivers/misc/mic/vop/vop_debugfs.c 		seq_printf(s, "c2h doorbell %d ", dc->c2h_vdev_db);
dc                 86 drivers/misc/mic/vop/vop_debugfs.c 		seq_printf(s, "h2c doorbell %d\n", dc->h2c_vdev_db);
dc                 47 drivers/misc/mic/vop/vop_main.c 	struct mic_device_ctrl __iomem *dc;
dc                203 drivers/misc/mic/vop/vop_main.c 	struct mic_device_ctrl __iomem *dc = vdev->dc;
dc                207 drivers/misc/mic/vop/vop_main.c 	iowrite8(0, &dc->host_ack);
dc                208 drivers/misc/mic/vop/vop_main.c 	iowrite8(1, &dc->vdev_reset);
dc                213 drivers/misc/mic/vop/vop_main.c 		if (ioread8(&dc->host_ack))
dc                391 drivers/misc/mic/vop/vop_main.c 	struct mic_device_ctrl __iomem *dc = vdev->dc;
dc                414 drivers/misc/mic/vop/vop_main.c 	iowrite8(1, &dc->used_address_updated);
dc                421 drivers/misc/mic/vop/vop_main.c 		if (!ioread8(&dc->used_address_updated))
dc                498 drivers/misc/mic/vop/vop_main.c 	vdev->dc = (void __iomem *)d + _vop_aligned_desc_size(d);
dc                511 drivers/misc/mic/vop/vop_main.c 	iowrite8((u8)vdev->h2c_vdev_db, &vdev->dc->h2c_vdev_db);
dc                512 drivers/misc/mic/vop/vop_main.c 	vdev->c2h_vdev_db = ioread8(&vdev->dc->c2h_vdev_db);
dc                522 drivers/misc/mic/vop/vop_main.c 	writeq((unsigned long)vdev, &vdev->dc->vdev);
dc                549 drivers/misc/mic/vop/vop_main.c static struct _vop_vdev *vop_dc_to_vdev(struct mic_device_ctrl *dc)
dc                551 drivers/misc/mic/vop/vop_main.c 	return (struct _vop_vdev *)(unsigned long)readq(&dc->vdev);
dc                558 drivers/misc/mic/vop/vop_main.c 	struct mic_device_ctrl __iomem *dc
dc                560 drivers/misc/mic/vop/vop_main.c 	struct _vop_vdev *vdev = vop_dc_to_vdev(dc);
dc                562 drivers/misc/mic/vop/vop_main.c 	if (ioread8(&dc->config_change) != MIC_VIRTIO_PARAM_CONFIG_CHANGED)
dc                567 drivers/misc/mic/vop/vop_main.c 	iowrite8(1, &dc->guest_ack);
dc                577 drivers/misc/mic/vop/vop_main.c 	struct mic_device_ctrl __iomem *dc
dc                579 drivers/misc/mic/vop/vop_main.c 	struct _vop_vdev *vdev = vop_dc_to_vdev(dc);
dc                583 drivers/misc/mic/vop/vop_main.c 	if (ioread8(&dc->config_change) == MIC_VIRTIO_PARAM_DEV_REMOVE) {
dc                589 drivers/misc/mic/vop/vop_main.c 			ioread8(&dc->config_change), ioread8(&d->type), vdev);
dc                594 drivers/misc/mic/vop/vop_main.c 		iowrite8(-1, &dc->h2c_vdev_db);
dc                598 drivers/misc/mic/vop/vop_main.c 		iowrite8(1, &dc->guest_ack);
dc                600 drivers/misc/mic/vop/vop_main.c 			__func__, __LINE__, ioread8(&dc->guest_ack));
dc                615 drivers/misc/mic/vop/vop_main.c 	struct mic_device_ctrl __iomem *dc;
dc                622 drivers/misc/mic/vop/vop_main.c 		dc = (void __iomem *)d + _vop_aligned_desc_size(d);
dc                644 drivers/misc/mic/vop/vop_main.c 					 &dc->config_change);
dc                649 drivers/misc/mic/vop/vop_main.c 				iowrite8(0, &dc->config_change);
dc                650 drivers/misc/mic/vop/vop_main.c 				iowrite8(0, &dc->guest_ack);
dc                138 drivers/misc/mic/vop/vop_main.h 	struct mic_device_ctrl *dc;
dc                 50 drivers/misc/mic/vop/vop_vringh.c 	s8 db = vdev->dc->h2c_vdev_db;
dc                 77 drivers/misc/mic/vop/vop_vringh.c 	vdev->dc->used_address_updated = 0;
dc                 99 drivers/misc/mic/vop/vop_vringh.c 	vdev->dc->vdev_reset = 0;
dc                100 drivers/misc/mic/vop/vop_vringh.c 	vdev->dc->host_ack = 1;
dc                133 drivers/misc/mic/vop/vop_vringh.c 	if (vdev->dc->used_address_updated)
dc                136 drivers/misc/mic/vop/vop_vringh.c 	if (vdev->dc->vdev_reset)
dc                172 drivers/misc/mic/vop/vop_vringh.c 	vdev->dc->config_change = MIC_VIRTIO_PARAM_CONFIG_CHANGED;
dc                176 drivers/misc/mic/vop/vop_vringh.c 		ret = wait_event_timeout(wake, vdev->dc->guest_ack,
dc                184 drivers/misc/mic/vop/vop_vringh.c 	vdev->dc->config_change = 0;
dc                185 drivers/misc/mic/vop/vop_vringh.c 	vdev->dc->guest_ack = 0;
dc                245 drivers/misc/mic/vop/vop_vringh.c 	struct mic_device_ctrl *dc;
dc                247 drivers/misc/mic/vop/vop_vringh.c 	dc = (void *)devpage + mic_aligned_desc_size(devpage);
dc                249 drivers/misc/mic/vop/vop_vringh.c 	dc->config_change = 0;
dc                250 drivers/misc/mic/vop/vop_vringh.c 	dc->guest_ack = 0;
dc                251 drivers/misc/mic/vop/vop_vringh.c 	dc->vdev_reset = 0;
dc                252 drivers/misc/mic/vop/vop_vringh.c 	dc->host_ack = 0;
dc                253 drivers/misc/mic/vop/vop_vringh.c 	dc->used_address_updated = 0;
dc                254 drivers/misc/mic/vop/vop_vringh.c 	dc->c2h_vdev_db = -1;
dc                255 drivers/misc/mic/vop/vop_vringh.c 	dc->h2c_vdev_db = -1;
dc                256 drivers/misc/mic/vop/vop_vringh.c 	vdev->dc = dc;
dc                361 drivers/misc/mic/vop/vop_vringh.c 	vdev->dc->c2h_vdev_db = vdev->virtio_db;
dc                428 drivers/misc/mic/vop/vop_vringh.c 	vop_dev_remove(vi, vdev->dc, vpdev);
dc                267 drivers/mtd/nand/raw/marvell_nand.c #define MARVELL_LAYOUT(ws, dc, ds, nc, fcc, db, sb, eb, ldb, lsb, leb)	\
dc                270 drivers/mtd/nand/raw/marvell_nand.c 		.chunk = dc,						\
dc                 52 drivers/net/ethernet/intel/e1000/e1000_ethtool.c 	{ "tx_deferred_ok", E1000_STAT(stats.dc) },
dc               1264 drivers/net/ethernet/intel/e1000/e1000_hw.h 	u64 dc;
dc               3632 drivers/net/ethernet/intel/e1000/e1000_main.c 	adapter->stats.dc += er32(DC);
dc                 63 drivers/net/ethernet/intel/e1000e/ethtool.c 	E1000_STAT("tx_deferred_ok", stats.dc),
dc                347 drivers/net/ethernet/intel/e1000e/hw.h 	u64 dc;
dc               4896 drivers/net/ethernet/intel/e1000e/netdev.c 		adapter->stats.dc += phy_data;
dc               4945 drivers/net/ethernet/intel/e1000e/netdev.c 			adapter->stats.dc += er32(DC);
dc                178 drivers/net/ethernet/intel/igb/e1000_hw.h 	u64 dc;
dc                 50 drivers/net/ethernet/intel/igb/igb_ethtool.c 	IGB_STAT("tx_deferred_ok", stats.dc),
dc                554 drivers/net/ethernet/intel/igb/igb_ethtool.c 	regs_buff[64] = adapter->stats.dc;
dc               6349 drivers/net/ethernet/intel/igb/igb_main.c 	adapter->stats.dc += rd32(E1000_DC);
dc                 41 drivers/net/ethernet/intel/igc/igc_ethtool.c 	IGC_STAT("tx_deferred_ok", stats.dc),
dc                221 drivers/net/ethernet/intel/igc/igc_ethtool.c 	regs_buff[40] = adapter->stats.dc;
dc                230 drivers/net/ethernet/intel/igc/igc_hw.h 	u64 dc;
dc               1991 drivers/net/ethernet/intel/igc/igc_main.c 	adapter->stats.dc += rd32(IGC_DC);
dc                 52 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c 	{"tx_deferred_ok", IXGB_STAT(stats.dc)},
dc                321 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c 	*reg++ = IXGB_GET_STAT(adapter, dc);	/* 120 */
dc                718 drivers/net/ethernet/intel/ixgb/ixgb_hw.h 	u64 dc;
dc               1664 drivers/net/ethernet/intel/ixgb/ixgb_main.c 	adapter->stats.dc += IXGB_READ_REG(&adapter->hw, DC);
dc                256 drivers/net/wireless/ath/ath9k/ar9003_wow.c 		u32 dc = REG_READ(ah, AR_DIRECT_CONNECT);
dc                258 drivers/net/wireless/ath/ath9k/ar9003_wow.c 		if (!(dc & AR_DC_TSF2_ENABLE))
dc                 81 drivers/net/wireless/marvell/libertas/if_spi.h #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dc) ((dc & 0xffff0000)>>16)
dc                 82 drivers/net/wireless/marvell/libertas/if_spi.h #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dc) (dc & 0x000000ff)
dc               1255 drivers/net/xen-netback/netback.c 	pending_ring_idx_t dc, dp;
dc               1259 drivers/net/xen-netback/netback.c 	dc = queue->dealloc_cons;
dc               1271 drivers/net/xen-netback/netback.c 		while (dc != dp) {
dc               1274 drivers/net/xen-netback/netback.c 				queue->dealloc_ring[pending_index(dc++)];
dc               1290 drivers/net/xen-netback/netback.c 	queue->dealloc_cons = dc;
dc                230 drivers/power/supply/da9052-battery.c 	bool dc;
dc                244 drivers/power/supply/da9052-battery.c 	dc = dcinsel && dcindet;
dc                248 drivers/power/supply/da9052-battery.c 	if (dc || vbus) {
dc                232 drivers/power/supply/smb347-charger.c 	bool dc = false;
dc                245 drivers/power/supply/smb347-charger.c 		dc = !(val & IRQSTAT_E_DCIN_UV_STAT);
dc                250 drivers/power/supply/smb347-charger.c 	ret = smb->mains_online != dc || smb->usb_online != usb;
dc                251 drivers/power/supply/smb347-charger.c 	smb->mains_online = dc;
dc                116 drivers/pwm/pwm-bcm-kona.c 	unsigned long prescale = PRESCALE_MIN, pc, dc;
dc                138 drivers/pwm/pwm-bcm-kona.c 		dc = div64_u64(val, div);
dc                141 drivers/pwm/pwm-bcm-kona.c 		if (pc < PERIOD_COUNT_MIN || dc < DUTY_CYCLE_HIGH_MIN)
dc                145 drivers/pwm/pwm-bcm-kona.c 		if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX)
dc                168 drivers/pwm/pwm-bcm-kona.c 		writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
dc                101 drivers/pwm/pwm-brcmstb.c 	unsigned long pc, dc, cword = CONST_VAR_F_MAX;
dc                111 drivers/pwm/pwm-brcmstb.c 		dc = PWM_ON_PERIOD_MAX;
dc                132 drivers/pwm/pwm-brcmstb.c 		dc = tmp;
dc                138 drivers/pwm/pwm-brcmstb.c 		if (pc == PWM_PERIOD_MIN || (dc < PWM_ON_MIN && duty_ns))
dc                142 drivers/pwm/pwm-brcmstb.c 		if (pc <= PWM_ON_PERIOD_MAX && dc <= PWM_ON_PERIOD_MAX)
dc                178 drivers/pwm/pwm-brcmstb.c 	brcmstb_pwm_writel(p, dc, PWM_ON(channel));
dc                 41 drivers/pwm/pwm-puv3.c 	unsigned long period_cycles, prescale, pv, dc;
dc                 60 drivers/pwm/pwm-puv3.c 		dc = OST_PWMDCCR_FDCYCLE;
dc                 62 drivers/pwm/pwm-puv3.c 		dc = (pv + 1) * duty_ns / period_ns;
dc                 71 drivers/pwm/pwm-puv3.c 	writel(pv - dc, puv3->base + OST_PWM_DCCR);
dc                 65 drivers/pwm/pwm-pxa.c 	unsigned long period_cycles, prescale, pv, dc;
dc                 85 drivers/pwm/pwm-pxa.c 		dc = PWMDCR_FD;
dc                 87 drivers/pwm/pwm-pxa.c 		dc = (pv + 1) * duty_ns / period_ns;
dc                 97 drivers/pwm/pwm-pxa.c 	writel(dc, pc->mmio_base + offset + PWMDCR);
dc                 82 drivers/pwm/pwm-spear.c 	unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
dc                102 drivers/pwm/pwm-spear.c 		dc = div64_u64(val, div);
dc                105 drivers/pwm/pwm-spear.c 		if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
dc                112 drivers/pwm/pwm-spear.c 		if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
dc                130 drivers/pwm/pwm-spear.c 	spear_pwm_writel(pc, pwm->hwpwm, PWMDCR, dc);
dc                 77 drivers/pwm/pwm-vt8500.c 	unsigned long period_cycles, prescale, pv, dc;
dc                106 drivers/pwm/pwm-vt8500.c 	dc = c;
dc                114 drivers/pwm/pwm-vt8500.c 	writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
dc               1112 drivers/scsi/esas2r/esas2r.h 					      struct esas2r_disc_context *dc);
dc               1114 drivers/scsi/esas2r/esas2r.h 					       struct esas2r_disc_context *dc,
dc                291 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc = &a->disc_ctx;
dc                298 drivers/scsi/esas2r/esas2r_disc.c 	dc->disc_evt |= disc_evt;
dc                314 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc = &a->disc_ctx;
dc                326 drivers/scsi/esas2r/esas2r_disc.c 	if (dc->disc_evt) {
dc                352 drivers/scsi/esas2r/esas2r_disc.c 	esas2r_trace("disc_evt: %d", dc->disc_evt);
dc                354 drivers/scsi/esas2r/esas2r_disc.c 	dc->flags = 0;
dc                357 drivers/scsi/esas2r/esas2r_disc.c 		dc->flags |= DCF_POLLED;
dc                359 drivers/scsi/esas2r/esas2r_disc.c 	rq->interrupt_cx = dc;
dc                363 drivers/scsi/esas2r/esas2r_disc.c 	if (dc->disc_evt & DCDE_DEV_SCAN) {
dc                364 drivers/scsi/esas2r/esas2r_disc.c 		dc->disc_evt &= ~DCDE_DEV_SCAN;
dc                366 drivers/scsi/esas2r/esas2r_disc.c 		dc->flags |= DCF_DEV_SCAN;
dc                367 drivers/scsi/esas2r/esas2r_disc.c 		dc->state = DCS_BLOCK_DEV_SCAN;
dc                368 drivers/scsi/esas2r/esas2r_disc.c 	} else if (dc->disc_evt & DCDE_DEV_CHANGE) {
dc                369 drivers/scsi/esas2r/esas2r_disc.c 		dc->disc_evt &= ~DCDE_DEV_CHANGE;
dc                371 drivers/scsi/esas2r/esas2r_disc.c 		dc->flags |= DCF_DEV_CHANGE;
dc                372 drivers/scsi/esas2r/esas2r_disc.c 		dc->state = DCS_DEV_RMV;
dc                389 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc                394 drivers/scsi/esas2r/esas2r_disc.c 	while (dc->flags & (DCF_DEV_CHANGE | DCF_DEV_SCAN)) {
dc                397 drivers/scsi/esas2r/esas2r_disc.c 		switch (dc->state) {
dc                433 drivers/scsi/esas2r/esas2r_disc.c 			dc->flags &= ~(DCF_DEV_CHANGE | DCF_DEV_SCAN);
dc                439 drivers/scsi/esas2r/esas2r_disc.c 			dc->state = DCS_DISC_DONE;
dc                505 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc                512 drivers/scsi/esas2r/esas2r_disc.c 	dc->state = DCS_DISC_DONE;
dc                520 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc                539 drivers/scsi/esas2r/esas2r_disc.c 	rq->interrupt_cx = dc;
dc                551 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc                560 drivers/scsi/esas2r/esas2r_disc.c 		dc->scan_gen = rq->func_rsp.mgt_rsp.scan_generation;
dc                562 drivers/scsi/esas2r/esas2r_disc.c 	dc->state = DCS_RAID_GRP_INFO;
dc                563 drivers/scsi/esas2r/esas2r_disc.c 	dc->raid_grp_ix = 0;
dc                569 drivers/scsi/esas2r/esas2r_disc.c 	if (!(dc->flags & DCF_POLLED))
dc                580 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc                587 drivers/scsi/esas2r/esas2r_disc.c 	esas2r_trace("raid_group_idx: %d", dc->raid_grp_ix);
dc                589 drivers/scsi/esas2r/esas2r_disc.c 	if (dc->raid_grp_ix >= VDA_MAX_RAID_GROUPS) {
dc                590 drivers/scsi/esas2r/esas2r_disc.c 		dc->state = DCS_DISC_DONE;
dc                606 drivers/scsi/esas2r/esas2r_disc.c 			     dc->scan_gen,
dc                611 drivers/scsi/esas2r/esas2r_disc.c 	grpinfo->grp_index = dc->raid_grp_ix;
dc                615 drivers/scsi/esas2r/esas2r_disc.c 	rq->interrupt_cx = dc;
dc                627 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc                637 drivers/scsi/esas2r/esas2r_disc.c 		dc->scan_gen = rq->func_rsp.mgt_rsp.scan_generation;
dc                638 drivers/scsi/esas2r/esas2r_disc.c 		dc->raid_grp_ix = 0;
dc                649 drivers/scsi/esas2r/esas2r_disc.c 			dc->raid_grp_ix++;
dc                651 drivers/scsi/esas2r/esas2r_disc.c 			memcpy(&dc->raid_grp_name[0],
dc                655 drivers/scsi/esas2r/esas2r_disc.c 			dc->interleave = le32_to_cpu(grpinfo->interleave);
dc                656 drivers/scsi/esas2r/esas2r_disc.c 			dc->block_size = le32_to_cpu(grpinfo->block_size);
dc                658 drivers/scsi/esas2r/esas2r_disc.c 			dc->state = DCS_PART_INFO;
dc                659 drivers/scsi/esas2r/esas2r_disc.c 			dc->part_num = 0;
dc                669 drivers/scsi/esas2r/esas2r_disc.c 		dc->dev_ix = 0;
dc                670 drivers/scsi/esas2r/esas2r_disc.c 		dc->state = DCS_PT_DEV_INFO;
dc                679 drivers/scsi/esas2r/esas2r_disc.c 	if (!(dc->flags & DCF_POLLED))
dc                690 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc                697 drivers/scsi/esas2r/esas2r_disc.c 	esas2r_trace("part_num: %d", dc->part_num);
dc                699 drivers/scsi/esas2r/esas2r_disc.c 	if (dc->part_num >= VDA_MAX_PARTITIONS) {
dc                700 drivers/scsi/esas2r/esas2r_disc.c 		dc->state = DCS_RAID_GRP_INFO;
dc                701 drivers/scsi/esas2r/esas2r_disc.c 		dc->raid_grp_ix++;
dc                717 drivers/scsi/esas2r/esas2r_disc.c 			     dc->scan_gen,
dc                722 drivers/scsi/esas2r/esas2r_disc.c 	partinfo->part_no = dc->part_num;
dc                725 drivers/scsi/esas2r/esas2r_disc.c 	       &dc->raid_grp_name[0],
dc                730 drivers/scsi/esas2r/esas2r_disc.c 	rq->interrupt_cx = dc;
dc                742 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc                752 drivers/scsi/esas2r/esas2r_disc.c 		dc->scan_gen = rq->func_rsp.mgt_rsp.scan_generation;
dc                753 drivers/scsi/esas2r/esas2r_disc.c 		dc->raid_grp_ix = 0;
dc                754 drivers/scsi/esas2r/esas2r_disc.c 		dc->state = DCS_RAID_GRP_INFO;
dc                758 drivers/scsi/esas2r/esas2r_disc.c 		dc->part_num = partinfo->part_no;
dc                760 drivers/scsi/esas2r/esas2r_disc.c 		dc->curr_virt_id = le16_to_cpu(partinfo->target_id);
dc                762 drivers/scsi/esas2r/esas2r_disc.c 		esas2r_targ_db_add_raid(a, dc);
dc                764 drivers/scsi/esas2r/esas2r_disc.c 		dc->part_num++;
dc                772 drivers/scsi/esas2r/esas2r_disc.c 		dc->state = DCS_RAID_GRP_INFO;
dc                773 drivers/scsi/esas2r/esas2r_disc.c 		dc->raid_grp_ix++;
dc                780 drivers/scsi/esas2r/esas2r_disc.c 	if (!(dc->flags & DCF_POLLED))
dc                791 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc                798 drivers/scsi/esas2r/esas2r_disc.c 	esas2r_trace("dev_ix: %d", dc->dev_ix);
dc                809 drivers/scsi/esas2r/esas2r_disc.c 			     dc->scan_gen,
dc                810 drivers/scsi/esas2r/esas2r_disc.c 			     dc->dev_ix,
dc                816 drivers/scsi/esas2r/esas2r_disc.c 	rq->interrupt_cx = dc;
dc                828 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc                838 drivers/scsi/esas2r/esas2r_disc.c 		dc->scan_gen = rq->func_rsp.mgt_rsp.scan_generation;
dc                839 drivers/scsi/esas2r/esas2r_disc.c 		dc->dev_ix = 0;
dc                840 drivers/scsi/esas2r/esas2r_disc.c 		dc->state = DCS_PT_DEV_INFO;
dc                844 drivers/scsi/esas2r/esas2r_disc.c 		dc->dev_ix = le16_to_cpu(rq->func_rsp.mgt_rsp.dev_index);
dc                846 drivers/scsi/esas2r/esas2r_disc.c 		dc->curr_virt_id = le16_to_cpu(devinfo->target_id);
dc                849 drivers/scsi/esas2r/esas2r_disc.c 			dc->curr_phys_id =
dc                851 drivers/scsi/esas2r/esas2r_disc.c 			dc->dev_addr_type = ATTO_GDA_AT_PORT;
dc                852 drivers/scsi/esas2r/esas2r_disc.c 			dc->state = DCS_PT_DEV_ADDR;
dc                854 drivers/scsi/esas2r/esas2r_disc.c 			esas2r_trace("curr_virt_id: %d", dc->curr_virt_id);
dc                855 drivers/scsi/esas2r/esas2r_disc.c 			esas2r_trace("curr_phys_id: %d", dc->curr_phys_id);
dc                857 drivers/scsi/esas2r/esas2r_disc.c 			dc->dev_ix++;
dc                866 drivers/scsi/esas2r/esas2r_disc.c 		dc->state = DCS_DISC_DONE;
dc                873 drivers/scsi/esas2r/esas2r_disc.c 	if (!(dc->flags & DCF_POLLED))
dc                884 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc                915 drivers/scsi/esas2r/esas2r_disc.c 	rq->interrupt_cx = dc;
dc                927 drivers/scsi/esas2r/esas2r_disc.c 	hi->data.get_dev_addr.target_id = le32_to_cpu(dc->curr_phys_id);
dc                928 drivers/scsi/esas2r/esas2r_disc.c 	hi->data.get_dev_addr.addr_type = dc->dev_addr_type;
dc                942 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc                959 drivers/scsi/esas2r/esas2r_disc.c 		if (dc->dev_addr_type == ATTO_GDA_AT_PORT) {
dc                961 drivers/scsi/esas2r/esas2r_disc.c 				memcpy(&dc->sas_addr,
dc                965 drivers/scsi/esas2r/esas2r_disc.c 				memset(&dc->sas_addr, 0, sizeof(dc->sas_addr));
dc                968 drivers/scsi/esas2r/esas2r_disc.c 			dc->dev_addr_type = ATTO_GDA_AT_UNIQUE;
dc                975 drivers/scsi/esas2r/esas2r_disc.c 							     dc,
dc                984 drivers/scsi/esas2r/esas2r_disc.c 					memcpy(&t->sas_addr, &dc->sas_addr,
dc               1007 drivers/scsi/esas2r/esas2r_disc.c 	if (dc->flags & DCF_DEV_SCAN) {
dc               1008 drivers/scsi/esas2r/esas2r_disc.c 		dc->dev_ix++;
dc               1009 drivers/scsi/esas2r/esas2r_disc.c 		dc->state = DCS_PT_DEV_INFO;
dc               1010 drivers/scsi/esas2r/esas2r_disc.c 	} else if (dc->flags & DCF_DEV_CHANGE) {
dc               1011 drivers/scsi/esas2r/esas2r_disc.c 		dc->curr_targ++;
dc               1012 drivers/scsi/esas2r/esas2r_disc.c 		dc->state = DCS_DEV_ADD;
dc               1022 drivers/scsi/esas2r/esas2r_disc.c 	if (!(dc->flags & DCF_POLLED))
dc               1046 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc               1074 drivers/scsi/esas2r/esas2r_disc.c 	dc->state = DCS_DEV_ADD;
dc               1075 drivers/scsi/esas2r/esas2r_disc.c 	dc->curr_targ = a->targetdb;
dc               1085 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_disc_context *dc =
dc               1087 drivers/scsi/esas2r/esas2r_disc.c 	struct esas2r_target *t = dc->curr_targ;
dc               1092 drivers/scsi/esas2r/esas2r_disc.c 		dc->state = DCS_DISC_DONE;
dc               1104 drivers/scsi/esas2r/esas2r_disc.c 		dc->curr_virt_id = esas2r_targ_get_id(t, a);
dc               1109 drivers/scsi/esas2r/esas2r_disc.c 			dc->block_size = luevt->id.tgtlun_raid.dwblock_size;
dc               1110 drivers/scsi/esas2r/esas2r_disc.c 			dc->interleave = luevt->id.tgtlun_raid.dwinterleave;
dc               1112 drivers/scsi/esas2r/esas2r_disc.c 			dc->block_size = 0;
dc               1113 drivers/scsi/esas2r/esas2r_disc.c 			dc->interleave = 0;
dc               1120 drivers/scsi/esas2r/esas2r_disc.c 				dc->state = DCS_PT_DEV_ADDR;
dc               1121 drivers/scsi/esas2r/esas2r_disc.c 				dc->dev_addr_type = ATTO_GDA_AT_PORT;
dc               1122 drivers/scsi/esas2r/esas2r_disc.c 				dc->curr_phys_id = luevt->wphys_target_id;
dc               1130 drivers/scsi/esas2r/esas2r_disc.c 			dc->raid_grp_name[0] = 0;
dc               1132 drivers/scsi/esas2r/esas2r_disc.c 			esas2r_targ_db_add_raid(a, dc);
dc               1135 drivers/scsi/esas2r/esas2r_disc.c 		esas2r_trace("curr_virt_id: %d", dc->curr_virt_id);
dc               1136 drivers/scsi/esas2r/esas2r_disc.c 		esas2r_trace("curr_phys_id: %d", dc->curr_phys_id);
dc               1142 drivers/scsi/esas2r/esas2r_disc.c 	if (dc->state == DCS_DEV_ADD) {
dc               1145 drivers/scsi/esas2r/esas2r_disc.c 		dc->curr_targ++;
dc                392 drivers/scsi/esas2r/esas2r_int.c 	struct esas2r_disc_context *dc;
dc                404 drivers/scsi/esas2r/esas2r_int.c 		dc = (struct esas2r_disc_context *)rq->interrupt_cx;
dc                406 drivers/scsi/esas2r/esas2r_int.c 		dc->disc_evt = 0;
dc                121 drivers/scsi/esas2r/esas2r_targdb.c 					      dc)
dc                127 drivers/scsi/esas2r/esas2r_targdb.c 	if (dc->curr_virt_id >= ESAS2R_MAX_TARGETS) {
dc                133 drivers/scsi/esas2r/esas2r_targdb.c 	t = a->targetdb + dc->curr_virt_id;
dc                140 drivers/scsi/esas2r/esas2r_targdb.c 	esas2r_hdebug("add RAID %s, T:%d", dc->raid_grp_name,
dc                145 drivers/scsi/esas2r/esas2r_targdb.c 	if (dc->interleave == 0
dc                146 drivers/scsi/esas2r/esas2r_targdb.c 	    || dc->block_size  == 0) {
dc                156 drivers/scsi/esas2r/esas2r_targdb.c 	t->block_size = dc->block_size;
dc                157 drivers/scsi/esas2r/esas2r_targdb.c 	t->inter_byte = dc->interleave;
dc                158 drivers/scsi/esas2r/esas2r_targdb.c 	t->inter_block = dc->interleave / dc->block_size;
dc                159 drivers/scsi/esas2r/esas2r_targdb.c 	t->virt_targ_id = dc->curr_virt_id;
dc                173 drivers/scsi/esas2r/esas2r_targdb.c 					       struct esas2r_disc_context *dc,
dc                181 drivers/scsi/esas2r/esas2r_targdb.c 	if (dc->curr_virt_id >= ESAS2R_MAX_TARGETS) {
dc                192 drivers/scsi/esas2r/esas2r_targdb.c 		t = a->targetdb + dc->curr_virt_id;
dc                202 drivers/scsi/esas2r/esas2r_targdb.c 		      dc->curr_virt_id,
dc                203 drivers/scsi/esas2r/esas2r_targdb.c 		      dc->curr_phys_id);
dc                208 drivers/scsi/esas2r/esas2r_targdb.c 	t->virt_targ_id = dc->curr_virt_id;
dc                209 drivers/scsi/esas2r/esas2r_targdb.c 	t->phys_targ_id = dc->curr_phys_id;
dc               3355 drivers/scsi/qla2xxx/qla_init.c 	uint16_t dc;
dc               3368 drivers/scsi/qla2xxx/qla_init.c 	pci_read_config_word(vha->hw->pdev, 0x54, &dc);
dc               3375 drivers/scsi/qla2xxx/qla_init.c 	dc &= MPS_MASK;
dc               3376 drivers/scsi/qla2xxx/qla_init.c 	if (dc == (dw & MPS_MASK))
dc               3380 drivers/scsi/qla2xxx/qla_init.c 	dw |= dc;
dc                 62 drivers/spi/spi-ti-qspi.c 	u32 dc;
dc                265 drivers/spi/spi-ti-qspi.c 					cmd, qspi->dc, *txbuf);
dc                292 drivers/spi/spi-ti-qspi.c 					cmd, qspi->dc, *txbuf);
dc                297 drivers/spi/spi-ti-qspi.c 					cmd, qspi->dc, *txbuf);
dc                337 drivers/spi/spi-ti-qspi.c 		dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
dc                593 drivers/spi/spi-ti-qspi.c 	qspi->dc = 0;
dc                596 drivers/spi/spi-ti-qspi.c 		qspi->dc |= QSPI_CKPHA(spi->chip_select);
dc                598 drivers/spi/spi-ti-qspi.c 		qspi->dc |= QSPI_CKPOL(spi->chip_select);
dc                600 drivers/spi/spi-ti-qspi.c 		qspi->dc |= QSPI_CSPOL(spi->chip_select);
dc                612 drivers/spi/spi-ti-qspi.c 	ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
dc                 30 drivers/staging/fbtft/fb_agm1264k-fl.c #define RS			gpio.dc
dc                122 drivers/staging/fbtft/fb_pcd8544.c 	gpiod_set_value(par->gpio.dc, 1);
dc                 42 drivers/staging/fbtft/fb_ra8875.c 	gpiod_set_value(par->gpio.dc, 1);
dc                171 drivers/staging/fbtft/fb_ssd1305.c 	gpiod_set_value(par->gpio.dc, 1);
dc                194 drivers/staging/fbtft/fb_ssd1306.c 	gpiod_set_value(par->gpio.dc, 1);
dc                158 drivers/staging/fbtft/fb_ssd1325.c 	gpiod_set_value(par->gpio.dc, 1);
dc                 84 drivers/staging/fbtft/fb_ssd1331.c 	if (par->gpio.dc)
dc                 85 drivers/staging/fbtft/fb_ssd1331.c 		gpiod_set_value(par->gpio.dc, 0);
dc                107 drivers/staging/fbtft/fb_ssd1331.c 	if (par->gpio.dc)
dc                108 drivers/staging/fbtft/fb_ssd1331.c 		gpiod_set_value(par->gpio.dc, 1);
dc                 97 drivers/staging/fbtft/fb_tls8204.c 		gpiod_set_value(par->gpio.dc, 0);
dc                112 drivers/staging/fbtft/fb_tls8204.c 		gpiod_set_value(par->gpio.dc, 1);
dc                254 drivers/staging/fbtft/fb_uc1611.c 		gpiod_set_value(par->gpio.dc, 1);
dc                139 drivers/staging/fbtft/fb_uc1701.c 		gpiod_set_value(par->gpio.dc, 1);
dc                141 drivers/staging/fbtft/fb_uc1701.c 		gpiod_set_value(par->gpio.dc, 0);
dc                138 drivers/staging/fbtft/fbtft-bus.c 	if (par->gpio.dc)
dc                139 drivers/staging/fbtft/fbtft-bus.c 		gpiod_set_value(par->gpio.dc, 1);
dc                 36 drivers/staging/fbtft/fbtft-core.c int fbtft_write_buf_dc(struct fbtft_par *par, void *buf, size_t len, int dc)
dc                 40 drivers/staging/fbtft/fbtft-core.c 	if (par->gpio.dc)
dc                 41 drivers/staging/fbtft/fbtft-core.c 		gpiod_set_value(par->gpio.dc, dc);
dc                106 drivers/staging/fbtft/fbtft-core.c 	ret = fbtft_request_one_gpio(par, "dc", 0, &par->gpio.dc);
dc               1116 drivers/staging/fbtft/fbtft-core.c 	    !par->gpio.dc) {
dc                 47 drivers/staging/fbtft/fbtft-io.c 	u64 val, dc, tmp;
dc                 67 drivers/staging/fbtft/fbtft-io.c 			dc = (*src & 0x0100) ? 1 : 0;
dc                 69 drivers/staging/fbtft/fbtft-io.c 			tmp |= dc << bits;
dc                210 drivers/staging/fbtft/fbtft.h 		struct gpio_desc *dc;
dc                240 drivers/staging/fbtft/fbtft.h int fbtft_write_buf_dc(struct fbtft_par *par, void *buf, size_t len, int dc);
dc                288 drivers/target/target_core_xcopy.c 	int dc = (desc[1] & 0x02);
dc                309 drivers/target/target_core_xcopy.c 		desc_len, xop->stdi, xop->dtdi, dc);
dc                318 drivers/target/target_core_xcopy.c 	if (dc != 0) {
dc                335 drivers/tty/nozomi.c 	struct nozomi *dc;
dc                492 drivers/tty/nozomi.c static void nozomi_setup_memory(struct nozomi *dc)
dc                494 drivers/tty/nozomi.c 	void __iomem *offset = dc->base_addr + dc->config_table.dl_start;
dc                501 drivers/tty/nozomi.c 	dc->port[PORT_MDM].dl_addr[CH_A] = offset;
dc                502 drivers/tty/nozomi.c 	dc->port[PORT_MDM].dl_addr[CH_B] =
dc                503 drivers/tty/nozomi.c 				(offset += dc->config_table.dl_mdm_len1);
dc                504 drivers/tty/nozomi.c 	dc->port[PORT_MDM].dl_size[CH_A] =
dc                505 drivers/tty/nozomi.c 				dc->config_table.dl_mdm_len1 - buff_offset;
dc                506 drivers/tty/nozomi.c 	dc->port[PORT_MDM].dl_size[CH_B] =
dc                507 drivers/tty/nozomi.c 				dc->config_table.dl_mdm_len2 - buff_offset;
dc                510 drivers/tty/nozomi.c 	dc->port[PORT_DIAG].dl_addr[CH_A] =
dc                511 drivers/tty/nozomi.c 				(offset += dc->config_table.dl_mdm_len2);
dc                512 drivers/tty/nozomi.c 	dc->port[PORT_DIAG].dl_size[CH_A] =
dc                513 drivers/tty/nozomi.c 				dc->config_table.dl_diag_len1 - buff_offset;
dc                514 drivers/tty/nozomi.c 	dc->port[PORT_DIAG].dl_addr[CH_B] =
dc                515 drivers/tty/nozomi.c 				(offset += dc->config_table.dl_diag_len1);
dc                516 drivers/tty/nozomi.c 	dc->port[PORT_DIAG].dl_size[CH_B] =
dc                517 drivers/tty/nozomi.c 				dc->config_table.dl_diag_len2 - buff_offset;
dc                520 drivers/tty/nozomi.c 	dc->port[PORT_APP1].dl_addr[CH_A] =
dc                521 drivers/tty/nozomi.c 				(offset += dc->config_table.dl_diag_len2);
dc                522 drivers/tty/nozomi.c 	dc->port[PORT_APP1].dl_size[CH_A] =
dc                523 drivers/tty/nozomi.c 				dc->config_table.dl_app1_len - buff_offset;
dc                526 drivers/tty/nozomi.c 	dc->port[PORT_APP2].dl_addr[CH_A] =
dc                527 drivers/tty/nozomi.c 				(offset += dc->config_table.dl_app1_len);
dc                528 drivers/tty/nozomi.c 	dc->port[PORT_APP2].dl_size[CH_A] =
dc                529 drivers/tty/nozomi.c 				dc->config_table.dl_app2_len - buff_offset;
dc                532 drivers/tty/nozomi.c 	dc->port[PORT_CTRL].dl_addr[CH_A] =
dc                533 drivers/tty/nozomi.c 				(offset += dc->config_table.dl_app2_len);
dc                534 drivers/tty/nozomi.c 	dc->port[PORT_CTRL].dl_size[CH_A] =
dc                535 drivers/tty/nozomi.c 				dc->config_table.dl_ctrl_len - buff_offset;
dc                537 drivers/tty/nozomi.c 	offset = dc->base_addr + dc->config_table.ul_start;
dc                540 drivers/tty/nozomi.c 	dc->port[PORT_MDM].ul_addr[CH_A] = offset;
dc                541 drivers/tty/nozomi.c 	dc->port[PORT_MDM].ul_size[CH_A] =
dc                542 drivers/tty/nozomi.c 				dc->config_table.ul_mdm_len1 - buff_offset;
dc                543 drivers/tty/nozomi.c 	dc->port[PORT_MDM].ul_addr[CH_B] =
dc                544 drivers/tty/nozomi.c 				(offset += dc->config_table.ul_mdm_len1);
dc                545 drivers/tty/nozomi.c 	dc->port[PORT_MDM].ul_size[CH_B] =
dc                546 drivers/tty/nozomi.c 				dc->config_table.ul_mdm_len2 - buff_offset;
dc                549 drivers/tty/nozomi.c 	dc->port[PORT_DIAG].ul_addr[CH_A] =
dc                550 drivers/tty/nozomi.c 				(offset += dc->config_table.ul_mdm_len2);
dc                551 drivers/tty/nozomi.c 	dc->port[PORT_DIAG].ul_size[CH_A] =
dc                552 drivers/tty/nozomi.c 				dc->config_table.ul_diag_len - buff_offset;
dc                555 drivers/tty/nozomi.c 	dc->port[PORT_APP1].ul_addr[CH_A] =
dc                556 drivers/tty/nozomi.c 				(offset += dc->config_table.ul_diag_len);
dc                557 drivers/tty/nozomi.c 	dc->port[PORT_APP1].ul_size[CH_A] =
dc                558 drivers/tty/nozomi.c 				dc->config_table.ul_app1_len - buff_offset;
dc                561 drivers/tty/nozomi.c 	dc->port[PORT_APP2].ul_addr[CH_A] =
dc                562 drivers/tty/nozomi.c 				(offset += dc->config_table.ul_app1_len);
dc                563 drivers/tty/nozomi.c 	dc->port[PORT_APP2].ul_size[CH_A] =
dc                564 drivers/tty/nozomi.c 				dc->config_table.ul_app2_len - buff_offset;
dc                567 drivers/tty/nozomi.c 	dc->port[PORT_CTRL].ul_addr[CH_A] =
dc                568 drivers/tty/nozomi.c 				(offset += dc->config_table.ul_app2_len);
dc                569 drivers/tty/nozomi.c 	dc->port[PORT_CTRL].ul_size[CH_A] =
dc                570 drivers/tty/nozomi.c 				dc->config_table.ul_ctrl_len - buff_offset;
dc                575 drivers/tty/nozomi.c static void dump_table(const struct nozomi *dc)
dc                577 drivers/tty/nozomi.c 	DBG3("signature: 0x%08X", dc->config_table.signature);
dc                578 drivers/tty/nozomi.c 	DBG3("version: 0x%04X", dc->config_table.version);
dc                580 drivers/tty/nozomi.c 				dc->config_table.product_information);
dc                581 drivers/tty/nozomi.c 	DBG3("toggle enabled: %d", dc->config_table.toggle.enabled);
dc                582 drivers/tty/nozomi.c 	DBG3("toggle up_mdm: %d", dc->config_table.toggle.mdm_ul);
dc                583 drivers/tty/nozomi.c 	DBG3("toggle dl_mdm: %d", dc->config_table.toggle.mdm_dl);
dc                584 drivers/tty/nozomi.c 	DBG3("toggle dl_dbg: %d", dc->config_table.toggle.diag_dl);
dc                586 drivers/tty/nozomi.c 	DBG3("dl_start: 0x%04X", dc->config_table.dl_start);
dc                587 drivers/tty/nozomi.c 	DBG3("dl_mdm_len0: 0x%04X, %d", dc->config_table.dl_mdm_len1,
dc                588 drivers/tty/nozomi.c 	   dc->config_table.dl_mdm_len1);
dc                589 drivers/tty/nozomi.c 	DBG3("dl_mdm_len1: 0x%04X, %d", dc->config_table.dl_mdm_len2,
dc                590 drivers/tty/nozomi.c 	   dc->config_table.dl_mdm_len2);
dc                591 drivers/tty/nozomi.c 	DBG3("dl_diag_len0: 0x%04X, %d", dc->config_table.dl_diag_len1,
dc                592 drivers/tty/nozomi.c 	   dc->config_table.dl_diag_len1);
dc                593 drivers/tty/nozomi.c 	DBG3("dl_diag_len1: 0x%04X, %d", dc->config_table.dl_diag_len2,
dc                594 drivers/tty/nozomi.c 	   dc->config_table.dl_diag_len2);
dc                595 drivers/tty/nozomi.c 	DBG3("dl_app1_len: 0x%04X, %d", dc->config_table.dl_app1_len,
dc                596 drivers/tty/nozomi.c 	   dc->config_table.dl_app1_len);
dc                597 drivers/tty/nozomi.c 	DBG3("dl_app2_len: 0x%04X, %d", dc->config_table.dl_app2_len,
dc                598 drivers/tty/nozomi.c 	   dc->config_table.dl_app2_len);
dc                599 drivers/tty/nozomi.c 	DBG3("dl_ctrl_len: 0x%04X, %d", dc->config_table.dl_ctrl_len,
dc                600 drivers/tty/nozomi.c 	   dc->config_table.dl_ctrl_len);
dc                601 drivers/tty/nozomi.c 	DBG3("ul_start: 0x%04X, %d", dc->config_table.ul_start,
dc                602 drivers/tty/nozomi.c 	   dc->config_table.ul_start);
dc                603 drivers/tty/nozomi.c 	DBG3("ul_mdm_len[0]: 0x%04X, %d", dc->config_table.ul_mdm_len1,
dc                604 drivers/tty/nozomi.c 	   dc->config_table.ul_mdm_len1);
dc                605 drivers/tty/nozomi.c 	DBG3("ul_mdm_len[1]: 0x%04X, %d", dc->config_table.ul_mdm_len2,
dc                606 drivers/tty/nozomi.c 	   dc->config_table.ul_mdm_len2);
dc                607 drivers/tty/nozomi.c 	DBG3("ul_diag_len: 0x%04X, %d", dc->config_table.ul_diag_len,
dc                608 drivers/tty/nozomi.c 	   dc->config_table.ul_diag_len);
dc                609 drivers/tty/nozomi.c 	DBG3("ul_app1_len: 0x%04X, %d", dc->config_table.ul_app1_len,
dc                610 drivers/tty/nozomi.c 	   dc->config_table.ul_app1_len);
dc                611 drivers/tty/nozomi.c 	DBG3("ul_app2_len: 0x%04X, %d", dc->config_table.ul_app2_len,
dc                612 drivers/tty/nozomi.c 	   dc->config_table.ul_app2_len);
dc                613 drivers/tty/nozomi.c 	DBG3("ul_ctrl_len: 0x%04X, %d", dc->config_table.ul_ctrl_len,
dc                614 drivers/tty/nozomi.c 	   dc->config_table.ul_ctrl_len);
dc                617 drivers/tty/nozomi.c static inline void dump_table(const struct nozomi *dc) { }
dc                624 drivers/tty/nozomi.c static int nozomi_read_config_table(struct nozomi *dc)
dc                626 drivers/tty/nozomi.c 	read_mem32((u32 *) &dc->config_table, dc->base_addr + 0,
dc                629 drivers/tty/nozomi.c 	if (dc->config_table.signature != NOZOMI_CONFIG_MAGIC) {
dc                630 drivers/tty/nozomi.c 		dev_err(&dc->pdev->dev, "ConfigTable Bad! 0x%08X != 0x%08X\n",
dc                631 drivers/tty/nozomi.c 			dc->config_table.signature, NOZOMI_CONFIG_MAGIC);
dc                635 drivers/tty/nozomi.c 	if ((dc->config_table.version == 0)
dc                636 drivers/tty/nozomi.c 	    || (dc->config_table.toggle.enabled == TOGGLE_VALID)) {
dc                640 drivers/tty/nozomi.c 		nozomi_setup_memory(dc);
dc                642 drivers/tty/nozomi.c 		dc->port[PORT_MDM].toggle_ul = dc->config_table.toggle.mdm_ul;
dc                643 drivers/tty/nozomi.c 		dc->port[PORT_MDM].toggle_dl = dc->config_table.toggle.mdm_dl;
dc                644 drivers/tty/nozomi.c 		dc->port[PORT_DIAG].toggle_dl = dc->config_table.toggle.diag_dl;
dc                646 drivers/tty/nozomi.c 		   dc->port[PORT_MDM].toggle_ul,
dc                647 drivers/tty/nozomi.c 		   dc->port[PORT_MDM].toggle_dl, dc->port[PORT_DIAG].toggle_dl);
dc                649 drivers/tty/nozomi.c 		dump_table(dc);
dc                652 drivers/tty/nozomi.c 			memset(&dc->port[i].ctrl_dl, 0, sizeof(struct ctrl_dl));
dc                653 drivers/tty/nozomi.c 			memset(&dc->port[i].ctrl_ul, 0, sizeof(struct ctrl_ul));
dc                657 drivers/tty/nozomi.c 		dc->last_ier = dc->last_ier | CTRL_DL;
dc                658 drivers/tty/nozomi.c 		writew(dc->last_ier, dc->reg_ier);
dc                660 drivers/tty/nozomi.c 		dc->state = NOZOMI_STATE_ALLOCATED;
dc                661 drivers/tty/nozomi.c 		dev_info(&dc->pdev->dev, "Initialization OK!\n");
dc                665 drivers/tty/nozomi.c 	if ((dc->config_table.version > 0)
dc                666 drivers/tty/nozomi.c 	    && (dc->config_table.toggle.enabled != TOGGLE_VALID)) {
dc                670 drivers/tty/nozomi.c 		dev_info(&dc->pdev->dev, "Version of card: %d\n",
dc                671 drivers/tty/nozomi.c 			 dc->config_table.version);
dc                674 drivers/tty/nozomi.c 		nozomi_setup_memory(dc);
dc                682 drivers/tty/nozomi.c 		write_mem32(dc->port[PORT_MDM].ul_addr[CH_A],
dc                684 drivers/tty/nozomi.c 		write_mem32(dc->port[PORT_MDM].ul_addr[CH_B],
dc                687 drivers/tty/nozomi.c 		writew(MDM_UL | DIAG_DL | MDM_DL, dc->reg_fcr);
dc                696 drivers/tty/nozomi.c static void enable_transmit_ul(enum port_type port, struct nozomi *dc)
dc                701 drivers/tty/nozomi.c 		dc->last_ier |= mask[port];
dc                702 drivers/tty/nozomi.c 		writew(dc->last_ier, dc->reg_ier);
dc                704 drivers/tty/nozomi.c 		dev_err(&dc->pdev->dev, "Called with wrong port?\n");
dc                709 drivers/tty/nozomi.c static void disable_transmit_ul(enum port_type port, struct nozomi *dc)
dc                715 drivers/tty/nozomi.c 		dc->last_ier &= mask[port];
dc                716 drivers/tty/nozomi.c 		writew(dc->last_ier, dc->reg_ier);
dc                718 drivers/tty/nozomi.c 		dev_err(&dc->pdev->dev, "Called with wrong port?\n");
dc                723 drivers/tty/nozomi.c static void enable_transmit_dl(enum port_type port, struct nozomi *dc)
dc                728 drivers/tty/nozomi.c 		dc->last_ier |= mask[port];
dc                729 drivers/tty/nozomi.c 		writew(dc->last_ier, dc->reg_ier);
dc                731 drivers/tty/nozomi.c 		dev_err(&dc->pdev->dev, "Called with wrong port?\n");
dc                736 drivers/tty/nozomi.c static void disable_transmit_dl(enum port_type port, struct nozomi *dc)
dc                742 drivers/tty/nozomi.c 		dc->last_ier &= mask[port];
dc                743 drivers/tty/nozomi.c 		writew(dc->last_ier, dc->reg_ier);
dc                745 drivers/tty/nozomi.c 		dev_err(&dc->pdev->dev, "Called with wrong port?\n");
dc                753 drivers/tty/nozomi.c static int send_data(enum port_type index, struct nozomi *dc)
dc                756 drivers/tty/nozomi.c 	struct port *port = &dc->port[index];
dc                762 drivers/tty/nozomi.c 	size = kfifo_out(&port->fifo_ul, dc->send_buf,
dc                774 drivers/tty/nozomi.c 	write_mem32(addr + 4, (u32 *) dc->send_buf, size);
dc                782 drivers/tty/nozomi.c static int receive_data(enum port_type index, struct nozomi *dc)
dc                787 drivers/tty/nozomi.c 	struct port *port = &dc->port[index];
dc                800 drivers/tty/nozomi.c 		disable_transmit_dl(index, dc);
dc                806 drivers/tty/nozomi.c 		dev_err(&dc->pdev->dev, "size == 0?\n");
dc                828 drivers/tty/nozomi.c 	set_bit(index, &dc->flip);
dc                885 drivers/tty/nozomi.c static int receive_flow_control(struct nozomi *dc)
dc                892 drivers/tty/nozomi.c 	read_mem32((u32 *) &ctrl_dl, dc->port[PORT_CTRL].dl_addr[CH_A], 2);
dc                915 drivers/tty/nozomi.c 		if (dc->state == NOZOMI_STATE_ALLOCATED) {
dc                920 drivers/tty/nozomi.c 			dc->state = NOZOMI_STATE_READY;
dc                921 drivers/tty/nozomi.c 			dev_info(&dc->pdev->dev, "Device READY!\n");
dc                925 drivers/tty/nozomi.c 		dev_err(&dc->pdev->dev,
dc                930 drivers/tty/nozomi.c 	DBG1("0x%04X->0x%04X", *((u16 *)&dc->port[port].ctrl_dl),
dc                933 drivers/tty/nozomi.c 	old_ctrl = dc->port[port].ctrl_dl;
dc                934 drivers/tty/nozomi.c 	dc->port[port].ctrl_dl = ctrl_dl;
dc                939 drivers/tty/nozomi.c 		disable_transmit_ul(port, dc);
dc                943 drivers/tty/nozomi.c 		if (kfifo_len(&dc->port[port].fifo_ul)) {
dc                947 drivers/tty/nozomi.c 				kfifo_len(&dc->port[port].fifo_ul));
dc                948 drivers/tty/nozomi.c 			enable_transmit_ul(port, dc);
dc                960 drivers/tty/nozomi.c 		dc->port[port].tty_icount.cts++;
dc                962 drivers/tty/nozomi.c 		dc->port[port].tty_icount.dsr++;
dc                964 drivers/tty/nozomi.c 		dc->port[port].tty_icount.rng++;
dc                966 drivers/tty/nozomi.c 		dc->port[port].tty_icount.dcd++;
dc                968 drivers/tty/nozomi.c 	wake_up_interruptible(&dc->port[port].tty_wait);
dc                972 drivers/tty/nozomi.c 	   dc->port[port].tty_icount.dcd, dc->port[port].tty_icount.cts,
dc                973 drivers/tty/nozomi.c 	   dc->port[port].tty_icount.rng, dc->port[port].tty_icount.dsr);
dc                979 drivers/tty/nozomi.c 					const struct nozomi *dc)
dc                991 drivers/tty/nozomi.c 		dev_err(&dc->pdev->dev,
dc               1003 drivers/tty/nozomi.c static int send_flow_control(struct nozomi *dc)
dc               1009 drivers/tty/nozomi.c 		if (dc->port[i].update_flow_control) {
dc               1014 drivers/tty/nozomi.c 			dc->port[i].ctrl_ul.port = port2ctrl(i, dc);
dc               1015 drivers/tty/nozomi.c 			ctrl = (u16 *)&dc->port[i].ctrl_ul;
dc               1016 drivers/tty/nozomi.c 			write_mem32(dc->port[PORT_CTRL].ul_addr[0], \
dc               1018 drivers/tty/nozomi.c 			dc->port[i].update_flow_control = 0;
dc               1030 drivers/tty/nozomi.c static int handle_data_dl(struct nozomi *dc, enum port_type port, u8 *toggle,
dc               1034 drivers/tty/nozomi.c 		if (receive_data(port, dc)) {
dc               1035 drivers/tty/nozomi.c 			writew(mask1, dc->reg_fcr);
dc               1040 drivers/tty/nozomi.c 			if (receive_data(port, dc)) {
dc               1041 drivers/tty/nozomi.c 				writew(mask2, dc->reg_fcr);
dc               1046 drivers/tty/nozomi.c 		if (receive_data(port, dc)) {
dc               1047 drivers/tty/nozomi.c 			writew(mask2, dc->reg_fcr);
dc               1052 drivers/tty/nozomi.c 			if (receive_data(port, dc)) {
dc               1053 drivers/tty/nozomi.c 				writew(mask1, dc->reg_fcr);
dc               1058 drivers/tty/nozomi.c 		dev_err(&dc->pdev->dev, "port out of sync!, toggle:%d\n",
dc               1070 drivers/tty/nozomi.c static int handle_data_ul(struct nozomi *dc, enum port_type port, u16 read_iir)
dc               1072 drivers/tty/nozomi.c 	u8 *toggle = &(dc->port[port].toggle_ul);
dc               1075 drivers/tty/nozomi.c 		dc->last_ier &= ~MDM_UL;
dc               1076 drivers/tty/nozomi.c 		writew(dc->last_ier, dc->reg_ier);
dc               1077 drivers/tty/nozomi.c 		if (send_data(port, dc)) {
dc               1078 drivers/tty/nozomi.c 			writew(MDM_UL1, dc->reg_fcr);
dc               1079 drivers/tty/nozomi.c 			dc->last_ier = dc->last_ier | MDM_UL;
dc               1080 drivers/tty/nozomi.c 			writew(dc->last_ier, dc->reg_ier);
dc               1085 drivers/tty/nozomi.c 			dc->last_ier &= ~MDM_UL;
dc               1086 drivers/tty/nozomi.c 			writew(dc->last_ier, dc->reg_ier);
dc               1087 drivers/tty/nozomi.c 			if (send_data(port, dc)) {
dc               1088 drivers/tty/nozomi.c 				writew(MDM_UL2, dc->reg_fcr);
dc               1089 drivers/tty/nozomi.c 				dc->last_ier = dc->last_ier | MDM_UL;
dc               1090 drivers/tty/nozomi.c 				writew(dc->last_ier, dc->reg_ier);
dc               1096 drivers/tty/nozomi.c 		dc->last_ier &= ~MDM_UL;
dc               1097 drivers/tty/nozomi.c 		writew(dc->last_ier, dc->reg_ier);
dc               1098 drivers/tty/nozomi.c 		if (send_data(port, dc)) {
dc               1099 drivers/tty/nozomi.c 			writew(MDM_UL2, dc->reg_fcr);
dc               1100 drivers/tty/nozomi.c 			dc->last_ier = dc->last_ier | MDM_UL;
dc               1101 drivers/tty/nozomi.c 			writew(dc->last_ier, dc->reg_ier);
dc               1106 drivers/tty/nozomi.c 			dc->last_ier &= ~MDM_UL;
dc               1107 drivers/tty/nozomi.c 			writew(dc->last_ier, dc->reg_ier);
dc               1108 drivers/tty/nozomi.c 			if (send_data(port, dc)) {
dc               1109 drivers/tty/nozomi.c 				writew(MDM_UL1, dc->reg_fcr);
dc               1110 drivers/tty/nozomi.c 				dc->last_ier = dc->last_ier | MDM_UL;
dc               1111 drivers/tty/nozomi.c 				writew(dc->last_ier, dc->reg_ier);
dc               1116 drivers/tty/nozomi.c 		writew(read_iir & MDM_UL, dc->reg_fcr);
dc               1117 drivers/tty/nozomi.c 		dev_err(&dc->pdev->dev, "port out of sync!\n");
dc               1125 drivers/tty/nozomi.c 	struct nozomi *dc = dev_id;
dc               1129 drivers/tty/nozomi.c 	if (!dc)
dc               1132 drivers/tty/nozomi.c 	spin_lock(&dc->spin_mutex);
dc               1133 drivers/tty/nozomi.c 	read_iir = readw(dc->reg_iir);
dc               1142 drivers/tty/nozomi.c 	read_iir &= dc->last_ier;
dc               1149 drivers/tty/nozomi.c 		dc->last_ier);
dc               1152 drivers/tty/nozomi.c 		if (unlikely(!nozomi_read_config_table(dc))) {
dc               1153 drivers/tty/nozomi.c 			dc->last_ier = 0x0;
dc               1154 drivers/tty/nozomi.c 			writew(dc->last_ier, dc->reg_ier);
dc               1155 drivers/tty/nozomi.c 			dev_err(&dc->pdev->dev, "Could not read status from "
dc               1158 drivers/tty/nozomi.c 			writew(RESET, dc->reg_fcr);
dc               1165 drivers/tty/nozomi.c 		dc->last_ier &= ~CTRL_UL;
dc               1166 drivers/tty/nozomi.c 		writew(dc->last_ier, dc->reg_ier);
dc               1167 drivers/tty/nozomi.c 		if (send_flow_control(dc)) {
dc               1168 drivers/tty/nozomi.c 			writew(CTRL_UL, dc->reg_fcr);
dc               1169 drivers/tty/nozomi.c 			dc->last_ier = dc->last_ier | CTRL_UL;
dc               1170 drivers/tty/nozomi.c 			writew(dc->last_ier, dc->reg_ier);
dc               1174 drivers/tty/nozomi.c 		receive_flow_control(dc);
dc               1175 drivers/tty/nozomi.c 		writew(CTRL_DL, dc->reg_fcr);
dc               1178 drivers/tty/nozomi.c 		if (!handle_data_dl(dc, PORT_MDM,
dc               1179 drivers/tty/nozomi.c 				&(dc->port[PORT_MDM].toggle_dl), read_iir,
dc               1181 drivers/tty/nozomi.c 			dev_err(&dc->pdev->dev, "MDM_DL out of sync!\n");
dc               1186 drivers/tty/nozomi.c 		if (!handle_data_ul(dc, PORT_MDM, read_iir)) {
dc               1187 drivers/tty/nozomi.c 			dev_err(&dc->pdev->dev, "MDM_UL out of sync!\n");
dc               1192 drivers/tty/nozomi.c 		if (!handle_data_dl(dc, PORT_DIAG,
dc               1193 drivers/tty/nozomi.c 				&(dc->port[PORT_DIAG].toggle_dl), read_iir,
dc               1195 drivers/tty/nozomi.c 			dev_err(&dc->pdev->dev, "DIAG_DL out of sync!\n");
dc               1200 drivers/tty/nozomi.c 		dc->last_ier &= ~DIAG_UL;
dc               1201 drivers/tty/nozomi.c 		writew(dc->last_ier, dc->reg_ier);
dc               1202 drivers/tty/nozomi.c 		if (send_data(PORT_DIAG, dc)) {
dc               1203 drivers/tty/nozomi.c 			writew(DIAG_UL, dc->reg_fcr);
dc               1204 drivers/tty/nozomi.c 			dc->last_ier = dc->last_ier | DIAG_UL;
dc               1205 drivers/tty/nozomi.c 			writew(dc->last_ier, dc->reg_ier);
dc               1209 drivers/tty/nozomi.c 		if (receive_data(PORT_APP1, dc))
dc               1210 drivers/tty/nozomi.c 			writew(APP1_DL, dc->reg_fcr);
dc               1213 drivers/tty/nozomi.c 		dc->last_ier &= ~APP1_UL;
dc               1214 drivers/tty/nozomi.c 		writew(dc->last_ier, dc->reg_ier);
dc               1215 drivers/tty/nozomi.c 		if (send_data(PORT_APP1, dc)) {
dc               1216 drivers/tty/nozomi.c 			writew(APP1_UL, dc->reg_fcr);
dc               1217 drivers/tty/nozomi.c 			dc->last_ier = dc->last_ier | APP1_UL;
dc               1218 drivers/tty/nozomi.c 			writew(dc->last_ier, dc->reg_ier);
dc               1222 drivers/tty/nozomi.c 		if (receive_data(PORT_APP2, dc))
dc               1223 drivers/tty/nozomi.c 			writew(APP2_DL, dc->reg_fcr);
dc               1226 drivers/tty/nozomi.c 		dc->last_ier &= ~APP2_UL;
dc               1227 drivers/tty/nozomi.c 		writew(dc->last_ier, dc->reg_ier);
dc               1228 drivers/tty/nozomi.c 		if (send_data(PORT_APP2, dc)) {
dc               1229 drivers/tty/nozomi.c 			writew(APP2_UL, dc->reg_fcr);
dc               1230 drivers/tty/nozomi.c 			dc->last_ier = dc->last_ier | APP2_UL;
dc               1231 drivers/tty/nozomi.c 			writew(dc->last_ier, dc->reg_ier);
dc               1236 drivers/tty/nozomi.c 	spin_unlock(&dc->spin_mutex);
dc               1239 drivers/tty/nozomi.c 		if (test_and_clear_bit(a, &dc->flip))
dc               1240 drivers/tty/nozomi.c 			tty_flip_buffer_push(&dc->port[a].port);
dc               1244 drivers/tty/nozomi.c 	spin_unlock(&dc->spin_mutex);
dc               1248 drivers/tty/nozomi.c static void nozomi_get_card_type(struct nozomi *dc)
dc               1254 drivers/tty/nozomi.c 		size += pci_resource_len(dc->pdev, i);
dc               1257 drivers/tty/nozomi.c 	dc->card_type = size == 2048 ? F32_2 : F32_8;
dc               1259 drivers/tty/nozomi.c 	dev_info(&dc->pdev->dev, "Card type is: %d\n", dc->card_type);
dc               1262 drivers/tty/nozomi.c static void nozomi_setup_private_data(struct nozomi *dc)
dc               1264 drivers/tty/nozomi.c 	void __iomem *offset = dc->base_addr + dc->card_type / 2;
dc               1267 drivers/tty/nozomi.c 	dc->reg_fcr = (void __iomem *)(offset + R_FCR);
dc               1268 drivers/tty/nozomi.c 	dc->reg_iir = (void __iomem *)(offset + R_IIR);
dc               1269 drivers/tty/nozomi.c 	dc->reg_ier = (void __iomem *)(offset + R_IER);
dc               1270 drivers/tty/nozomi.c 	dc->last_ier = 0;
dc               1271 drivers/tty/nozomi.c 	dc->flip = 0;
dc               1273 drivers/tty/nozomi.c 	dc->port[PORT_MDM].token_dl = MDM_DL;
dc               1274 drivers/tty/nozomi.c 	dc->port[PORT_DIAG].token_dl = DIAG_DL;
dc               1275 drivers/tty/nozomi.c 	dc->port[PORT_APP1].token_dl = APP1_DL;
dc               1276 drivers/tty/nozomi.c 	dc->port[PORT_APP2].token_dl = APP2_DL;
dc               1279 drivers/tty/nozomi.c 		init_waitqueue_head(&dc->port[i].tty_wait);
dc               1285 drivers/tty/nozomi.c 	const struct nozomi *dc = dev_get_drvdata(dev);
dc               1287 drivers/tty/nozomi.c 	return sprintf(buf, "%d\n", dc->card_type);
dc               1294 drivers/tty/nozomi.c 	const struct nozomi *dc = dev_get_drvdata(dev);
dc               1296 drivers/tty/nozomi.c 	return sprintf(buf, "%u\n", dc->open_ttys);
dc               1300 drivers/tty/nozomi.c static void make_sysfs_files(struct nozomi *dc)
dc               1302 drivers/tty/nozomi.c 	if (device_create_file(&dc->pdev->dev, &dev_attr_card_type))
dc               1303 drivers/tty/nozomi.c 		dev_err(&dc->pdev->dev,
dc               1305 drivers/tty/nozomi.c 	if (device_create_file(&dc->pdev->dev, &dev_attr_open_ttys))
dc               1306 drivers/tty/nozomi.c 		dev_err(&dc->pdev->dev,
dc               1310 drivers/tty/nozomi.c static void remove_sysfs_files(struct nozomi *dc)
dc               1312 drivers/tty/nozomi.c 	device_remove_file(&dc->pdev->dev, &dev_attr_card_type);
dc               1313 drivers/tty/nozomi.c 	device_remove_file(&dc->pdev->dev, &dev_attr_open_ttys);
dc               1321 drivers/tty/nozomi.c 	struct nozomi *dc = NULL;
dc               1337 drivers/tty/nozomi.c 	dc = kzalloc(sizeof(struct nozomi), GFP_KERNEL);
dc               1338 drivers/tty/nozomi.c 	if (unlikely(!dc)) {
dc               1344 drivers/tty/nozomi.c 	dc->pdev = pdev;
dc               1346 drivers/tty/nozomi.c 	ret = pci_enable_device(dc->pdev);
dc               1352 drivers/tty/nozomi.c 	ret = pci_request_regions(dc->pdev, NOZOMI_NAME);
dc               1360 drivers/tty/nozomi.c 	nozomi_get_card_type(dc);
dc               1362 drivers/tty/nozomi.c 	dc->base_addr = pci_iomap(dc->pdev, 0, dc->card_type);
dc               1363 drivers/tty/nozomi.c 	if (!dc->base_addr) {
dc               1369 drivers/tty/nozomi.c 	dc->send_buf = kmalloc(SEND_BUF_MAX, GFP_KERNEL);
dc               1370 drivers/tty/nozomi.c 	if (!dc->send_buf) {
dc               1377 drivers/tty/nozomi.c 		if (kfifo_alloc(&dc->port[i].fifo_ul, FIFO_BUFFER_SIZE_UL,
dc               1386 drivers/tty/nozomi.c 	spin_lock_init(&dc->spin_mutex);
dc               1388 drivers/tty/nozomi.c 	nozomi_setup_private_data(dc);
dc               1391 drivers/tty/nozomi.c 	dc->last_ier = 0;
dc               1392 drivers/tty/nozomi.c 	writew(dc->last_ier, dc->reg_ier);
dc               1395 drivers/tty/nozomi.c 			NOZOMI_NAME, dc);
dc               1401 drivers/tty/nozomi.c 	DBG1("base_addr: %p", dc->base_addr);
dc               1403 drivers/tty/nozomi.c 	make_sysfs_files(dc);
dc               1405 drivers/tty/nozomi.c 	dc->index_start = ndev_idx * MAX_PORT;
dc               1406 drivers/tty/nozomi.c 	ndevs[ndev_idx] = dc;
dc               1408 drivers/tty/nozomi.c 	pci_set_drvdata(pdev, dc);
dc               1411 drivers/tty/nozomi.c 	dc->last_ier = RESET;
dc               1412 drivers/tty/nozomi.c 	iowrite16(dc->last_ier, dc->reg_ier);
dc               1414 drivers/tty/nozomi.c 	dc->state = NOZOMI_STATE_ENABLED;
dc               1418 drivers/tty/nozomi.c 		struct port *port = &dc->port[i];
dc               1419 drivers/tty/nozomi.c 		port->dc = dc;
dc               1423 drivers/tty/nozomi.c 				dc->index_start + i, &pdev->dev);
dc               1437 drivers/tty/nozomi.c 		tty_unregister_device(ntty_driver, dc->index_start + i);
dc               1438 drivers/tty/nozomi.c 		tty_port_destroy(&dc->port[i].port);
dc               1442 drivers/tty/nozomi.c 		kfifo_free(&dc->port[i].fifo_ul);
dc               1444 drivers/tty/nozomi.c 	kfree(dc->send_buf);
dc               1445 drivers/tty/nozomi.c 	iounmap(dc->base_addr);
dc               1451 drivers/tty/nozomi.c 	kfree(dc);
dc               1456 drivers/tty/nozomi.c static void tty_exit(struct nozomi *dc)
dc               1463 drivers/tty/nozomi.c 		tty_port_tty_hangup(&dc->port[i].port, false);
dc               1467 drivers/tty/nozomi.c 	while (dc->open_ttys)
dc               1470 drivers/tty/nozomi.c 		tty_unregister_device(ntty_driver, dc->index_start + i);
dc               1471 drivers/tty/nozomi.c 		tty_port_destroy(&dc->port[i].port);
dc               1480 drivers/tty/nozomi.c 	struct nozomi *dc = pci_get_drvdata(pdev);
dc               1483 drivers/tty/nozomi.c 	dc->last_ier = 0;
dc               1484 drivers/tty/nozomi.c 	writew(dc->last_ier, dc->reg_ier);
dc               1486 drivers/tty/nozomi.c 	tty_exit(dc);
dc               1497 drivers/tty/nozomi.c 	write_mem32(dc->port[PORT_CTRL].ul_addr[0], (u32 *)&ctrl, 2);
dc               1498 drivers/tty/nozomi.c 	writew(CTRL_UL, dc->reg_fcr);	/* push the token to the card. */
dc               1500 drivers/tty/nozomi.c 	remove_sysfs_files(dc);
dc               1502 drivers/tty/nozomi.c 	free_irq(pdev->irq, dc);
dc               1505 drivers/tty/nozomi.c 		kfifo_free(&dc->port[i].fifo_ul);
dc               1507 drivers/tty/nozomi.c 	kfree(dc->send_buf);
dc               1509 drivers/tty/nozomi.c 	iounmap(dc->base_addr);
dc               1515 drivers/tty/nozomi.c 	ndevs[dc->index_start / MAX_PORT] = NULL;
dc               1517 drivers/tty/nozomi.c 	kfree(dc);
dc               1549 drivers/tty/nozomi.c 	struct nozomi *dc = get_dc_by_tty(tty);
dc               1551 drivers/tty/nozomi.c 	if (!port || !dc || dc->state != NOZOMI_STATE_READY)
dc               1567 drivers/tty/nozomi.c 	struct nozomi *dc = port->dc;
dc               1571 drivers/tty/nozomi.c 	spin_lock_irqsave(&dc->spin_mutex, flags);
dc               1572 drivers/tty/nozomi.c 	dc->last_ier = dc->last_ier | port->token_dl;
dc               1573 drivers/tty/nozomi.c 	writew(dc->last_ier, dc->reg_ier);
dc               1574 drivers/tty/nozomi.c 	dc->open_ttys++;
dc               1575 drivers/tty/nozomi.c 	spin_unlock_irqrestore(&dc->spin_mutex, flags);
dc               1589 drivers/tty/nozomi.c 	struct nozomi *dc = port->dc;
dc               1593 drivers/tty/nozomi.c 	spin_lock_irqsave(&dc->spin_mutex, flags);
dc               1594 drivers/tty/nozomi.c 	dc->last_ier &= ~(port->token_dl);
dc               1595 drivers/tty/nozomi.c 	writew(dc->last_ier, dc->reg_ier);
dc               1596 drivers/tty/nozomi.c 	dc->open_ttys--;
dc               1597 drivers/tty/nozomi.c 	spin_unlock_irqrestore(&dc->spin_mutex, flags);
dc               1622 drivers/tty/nozomi.c 	struct nozomi *dc = get_dc_by_tty(tty);
dc               1628 drivers/tty/nozomi.c 	if (!dc || !port)
dc               1633 drivers/tty/nozomi.c 	spin_lock_irqsave(&dc->spin_mutex, flags);
dc               1635 drivers/tty/nozomi.c 	if (port == &(dc->port[PORT_MDM])) {
dc               1638 drivers/tty/nozomi.c 			enable_transmit_ul(tty->index % MAX_PORT, dc);
dc               1640 drivers/tty/nozomi.c 			dev_err(&dc->pdev->dev,
dc               1644 drivers/tty/nozomi.c 		enable_transmit_ul(tty->index % MAX_PORT, dc);
dc               1646 drivers/tty/nozomi.c 	spin_unlock_irqrestore(&dc->spin_mutex, flags);
dc               1664 drivers/tty/nozomi.c 	const struct nozomi *dc = get_dc_by_tty(tty);
dc               1666 drivers/tty/nozomi.c 	if (dc)
dc               1693 drivers/tty/nozomi.c 	struct nozomi *dc = get_dc_by_tty(tty);
dc               1696 drivers/tty/nozomi.c 	spin_lock_irqsave(&dc->spin_mutex, flags);
dc               1706 drivers/tty/nozomi.c 	spin_unlock_irqrestore(&dc->spin_mutex, flags);
dc               1777 drivers/tty/nozomi.c 	struct nozomi *dc = get_dc_by_tty(tty);
dc               1781 drivers/tty/nozomi.c 	spin_lock_irqsave(&dc->spin_mutex, flags);
dc               1782 drivers/tty/nozomi.c 	enable_transmit_dl(tty->index % MAX_PORT, dc);
dc               1785 drivers/tty/nozomi.c 	spin_unlock_irqrestore(&dc->spin_mutex, flags);
dc               1794 drivers/tty/nozomi.c 	struct nozomi *dc = get_dc_by_tty(tty);
dc               1798 drivers/tty/nozomi.c 	spin_lock_irqsave(&dc->spin_mutex, flags);
dc               1800 drivers/tty/nozomi.c 	spin_unlock_irqrestore(&dc->spin_mutex, flags);
dc               1807 drivers/tty/nozomi.c 	struct nozomi *dc = get_dc_by_tty(tty);
dc               1810 drivers/tty/nozomi.c 	if (unlikely(!dc || !port)) {
dc               2351 drivers/usb/core/devio.c 	struct usbdevfs_disconnect_claim dc;
dc               2354 drivers/usb/core/devio.c 	if (copy_from_user(&dc, arg, sizeof(dc)))
dc               2357 drivers/usb/core/devio.c 	intf = usb_ifnum_to_if(ps->dev, dc.interface);
dc               2367 drivers/usb/core/devio.c 		if ((dc.flags & USBDEVFS_DISCONNECT_CLAIM_IF_DRIVER) &&
dc               2368 drivers/usb/core/devio.c 				strncmp(dc.driver, intf->dev.driver->name,
dc               2369 drivers/usb/core/devio.c 					sizeof(dc.driver)) != 0)
dc               2372 drivers/usb/core/devio.c 		if ((dc.flags & USBDEVFS_DISCONNECT_CLAIM_EXCEPT_DRIVER) &&
dc               2373 drivers/usb/core/devio.c 				strncmp(dc.driver, intf->dev.driver->name,
dc               2374 drivers/usb/core/devio.c 					sizeof(dc.driver)) == 0)
dc               2381 drivers/usb/core/devio.c 	return claimintf(ps, dc.interface);
dc                131 drivers/usb/musb/cppi_dma.h 	struct dma_chan *dc;
dc                148 drivers/usb/musb/musb_cppi41.c 		struct dma_chan *dc = cppi41_channel->dc;
dc                162 drivers/usb/musb/musb_cppi41.c 		dma_desc = dmaengine_prep_slave_single(dc,
dc                174 drivers/usb/musb/musb_cppi41.c 		dma_async_issue_pending(dc);
dc                243 drivers/usb/musb/musb_cppi41.c 	dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
dc                417 drivers/usb/musb/musb_cppi41.c 	struct dma_chan *dc = cppi41_channel->dc;
dc                465 drivers/usb/musb/musb_cppi41.c 	dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
dc                478 drivers/usb/musb/musb_cppi41.c 	dma_async_issue_pending(dc);
dc                498 drivers/usb/musb/musb_cppi41.c 	if (!cppi41_channel->dc)
dc                628 drivers/usb/musb/musb_cppi41.c 		ret = dmaengine_terminate_all(cppi41_channel->dc);
dc                647 drivers/usb/musb/musb_cppi41.c 	struct dma_chan *dc;
dc                651 drivers/usb/musb/musb_cppi41.c 		dc = ctrl->tx_channel[i].dc;
dc                652 drivers/usb/musb/musb_cppi41.c 		if (dc)
dc                653 drivers/usb/musb/musb_cppi41.c 			dma_release_channel(dc);
dc                654 drivers/usb/musb/musb_cppi41.c 		dc = ctrl->rx_channel[i].dc;
dc                655 drivers/usb/musb/musb_cppi41.c 		if (dc)
dc                656 drivers/usb/musb/musb_cppi41.c 			dma_release_channel(dc);
dc                680 drivers/usb/musb/musb_cppi41.c 		struct dma_chan *dc;
dc                719 drivers/usb/musb/musb_cppi41.c 		dc = dma_request_chan(dev->parent, str);
dc                720 drivers/usb/musb/musb_cppi41.c 		if (IS_ERR(dc)) {
dc                721 drivers/usb/musb/musb_cppi41.c 			ret = PTR_ERR(dc);
dc                728 drivers/usb/musb/musb_cppi41.c 		cppi41_channel->dc = dc;
dc                107 drivers/usb/serial/safe_serial.c #define MY_USB_DEVICE(vend, prod, dc, ic, isc) \
dc                114 drivers/usb/serial/safe_serial.c 	.bDeviceClass = (dc),\
dc                 34 drivers/video/fbdev/geode/gxfb.h 	uint32_t dc[DC_REG_COUNT];
dc                 44 drivers/video/fbdev/geode/lxfb.h 	uint32_t dc[DC_REG_COUNT];
dc                605 drivers/video/fbdev/geode/lxfb_ops.c 	memcpy(par->dc, par->dc_regs, sizeof(par->dc));
dc                620 drivers/video/fbdev/geode/lxfb_ops.c 	filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
dc                671 drivers/video/fbdev/geode/lxfb_ops.c 	for (i = 0; i < ARRAY_SIZE(par->dc); i++) {
dc                686 drivers/video/fbdev/geode/lxfb_ops.c 			write_dc(par, i, par->dc[i] | DC_DV_CTL_CLEAR_DV_RAM);
dc                704 drivers/video/fbdev/geode/lxfb_ops.c 			write_dc(par, i, par->dc[i]);
dc                714 drivers/video/fbdev/geode/lxfb_ops.c 	filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
dc                806 drivers/video/fbdev/geode/lxfb_ops.c 	write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
dc                808 drivers/video/fbdev/geode/lxfb_ops.c 	write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
dc                 33 drivers/video/fbdev/geode/suspend_gx.c 	memcpy(par->dc, par->dc_regs, sizeof(par->dc));
dc                 88 drivers/video/fbdev/geode/suspend_gx.c 	for (i = 0; i < ARRAY_SIZE(par->dc); i++) {
dc                 97 drivers/video/fbdev/geode/suspend_gx.c 			write_dc(par, i, par->dc[i] & ~(DC_GENERAL_CFG_VIDE |
dc                105 drivers/video/fbdev/geode/suspend_gx.c 			write_dc(par, i, par->dc[i] & ~(DC_DISPLAY_CFG_VDEN |
dc                124 drivers/video/fbdev/geode/suspend_gx.c 			write_dc(par, i, par->dc[i]);
dc                200 drivers/video/fbdev/geode/suspend_gx.c 	write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG] &
dc                203 drivers/video/fbdev/geode/suspend_gx.c 	write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG] &
dc                227 drivers/video/fbdev/geode/suspend_gx.c 	write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
dc                229 drivers/video/fbdev/geode/suspend_gx.c 	write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
dc               1376 fs/cifs/dfs_cache.c static void do_refresh_tcon(struct dfs_cache *dc, struct dfs_cache_vol_info *vi,
dc               1424 fs/cifs/dfs_cache.c 						     &numrefs, dc->dc_nlsc,
dc               1451 fs/cifs/dfs_cache.c 	struct dfs_cache *dc = container_of(work, struct dfs_cache,
dc               1458 fs/cifs/dfs_cache.c 	mutex_lock(&dc->dc_lock);
dc               1460 fs/cifs/dfs_cache.c 	list_for_each_entry(vi, &dc->dc_vol_list, vi_list) {
dc               1468 fs/cifs/dfs_cache.c 			do_refresh_tcon(dc, vi, tcon);
dc               1475 fs/cifs/dfs_cache.c 	queue_delayed_work(cifsiod_wq, &dc->dc_refresh, dc->dc_ttl * HZ);
dc               1476 fs/cifs/dfs_cache.c 	mutex_unlock(&dc->dc_lock);
dc                940 fs/f2fs/segment.c 	struct discard_cmd *dc;
dc                946 fs/f2fs/segment.c 	dc = f2fs_kmem_cache_alloc(discard_cmd_slab, GFP_NOFS);
dc                947 fs/f2fs/segment.c 	INIT_LIST_HEAD(&dc->list);
dc                948 fs/f2fs/segment.c 	dc->bdev = bdev;
dc                949 fs/f2fs/segment.c 	dc->lstart = lstart;
dc                950 fs/f2fs/segment.c 	dc->start = start;
dc                951 fs/f2fs/segment.c 	dc->len = len;
dc                952 fs/f2fs/segment.c 	dc->ref = 0;
dc                953 fs/f2fs/segment.c 	dc->state = D_PREP;
dc                954 fs/f2fs/segment.c 	dc->queued = 0;
dc                955 fs/f2fs/segment.c 	dc->error = 0;
dc                956 fs/f2fs/segment.c 	init_completion(&dc->wait);
dc                957 fs/f2fs/segment.c 	list_add_tail(&dc->list, pend_list);
dc                958 fs/f2fs/segment.c 	spin_lock_init(&dc->lock);
dc                959 fs/f2fs/segment.c 	dc->bio_ref = 0;
dc                963 fs/f2fs/segment.c 	return dc;
dc                973 fs/f2fs/segment.c 	struct discard_cmd *dc;
dc                975 fs/f2fs/segment.c 	dc = __create_discard_cmd(sbi, bdev, lstart, start, len);
dc                977 fs/f2fs/segment.c 	rb_link_node(&dc->rb_node, parent, p);
dc                978 fs/f2fs/segment.c 	rb_insert_color_cached(&dc->rb_node, &dcc->root, leftmost);
dc                980 fs/f2fs/segment.c 	return dc;
dc                984 fs/f2fs/segment.c 							struct discard_cmd *dc)
dc                986 fs/f2fs/segment.c 	if (dc->state == D_DONE)
dc                987 fs/f2fs/segment.c 		atomic_sub(dc->queued, &dcc->queued_discard);
dc                989 fs/f2fs/segment.c 	list_del(&dc->list);
dc                990 fs/f2fs/segment.c 	rb_erase_cached(&dc->rb_node, &dcc->root);
dc                991 fs/f2fs/segment.c 	dcc->undiscard_blks -= dc->len;
dc                993 fs/f2fs/segment.c 	kmem_cache_free(discard_cmd_slab, dc);
dc                999 fs/f2fs/segment.c 							struct discard_cmd *dc)
dc               1004 fs/f2fs/segment.c 	trace_f2fs_remove_discard(dc->bdev, dc->start, dc->len);
dc               1006 fs/f2fs/segment.c 	spin_lock_irqsave(&dc->lock, flags);
dc               1007 fs/f2fs/segment.c 	if (dc->bio_ref) {
dc               1008 fs/f2fs/segment.c 		spin_unlock_irqrestore(&dc->lock, flags);
dc               1011 fs/f2fs/segment.c 	spin_unlock_irqrestore(&dc->lock, flags);
dc               1013 fs/f2fs/segment.c 	f2fs_bug_on(sbi, dc->ref);
dc               1015 fs/f2fs/segment.c 	if (dc->error == -EOPNOTSUPP)
dc               1016 fs/f2fs/segment.c 		dc->error = 0;
dc               1018 fs/f2fs/segment.c 	if (dc->error)
dc               1021 fs/f2fs/segment.c 			KERN_INFO, dc->lstart, dc->start, dc->len, dc->error);
dc               1022 fs/f2fs/segment.c 	__detach_discard_cmd(dcc, dc);
dc               1027 fs/f2fs/segment.c 	struct discard_cmd *dc = (struct discard_cmd *)bio->bi_private;
dc               1030 fs/f2fs/segment.c 	dc->error = blk_status_to_errno(bio->bi_status);
dc               1032 fs/f2fs/segment.c 	spin_lock_irqsave(&dc->lock, flags);
dc               1033 fs/f2fs/segment.c 	dc->bio_ref--;
dc               1034 fs/f2fs/segment.c 	if (!dc->bio_ref && dc->state == D_SUBMIT) {
dc               1035 fs/f2fs/segment.c 		dc->state = D_DONE;
dc               1036 fs/f2fs/segment.c 		complete_all(&dc->wait);
dc               1038 fs/f2fs/segment.c 	spin_unlock_irqrestore(&dc->lock, flags);
dc               1115 fs/f2fs/segment.c 						struct discard_cmd *dc,
dc               1118 fs/f2fs/segment.c 	struct block_device *bdev = dc->bdev;
dc               1129 fs/f2fs/segment.c 	if (dc->state != D_PREP)
dc               1135 fs/f2fs/segment.c 	trace_f2fs_issue_discard(bdev, dc->start, dc->len);
dc               1137 fs/f2fs/segment.c 	lstart = dc->lstart;
dc               1138 fs/f2fs/segment.c 	start = dc->start;
dc               1139 fs/f2fs/segment.c 	len = dc->len;
dc               1142 fs/f2fs/segment.c 	dc->len = 0;
dc               1158 fs/f2fs/segment.c 		dc->len += len;
dc               1171 fs/f2fs/segment.c 			spin_lock_irqsave(&dc->lock, flags);
dc               1172 fs/f2fs/segment.c 			if (dc->state == D_PARTIAL)
dc               1173 fs/f2fs/segment.c 				dc->state = D_SUBMIT;
dc               1174 fs/f2fs/segment.c 			spin_unlock_irqrestore(&dc->lock, flags);
dc               1185 fs/f2fs/segment.c 		spin_lock_irqsave(&dc->lock, flags);
dc               1187 fs/f2fs/segment.c 			dc->state = D_SUBMIT;
dc               1189 fs/f2fs/segment.c 			dc->state = D_PARTIAL;
dc               1190 fs/f2fs/segment.c 		dc->bio_ref++;
dc               1191 fs/f2fs/segment.c 		spin_unlock_irqrestore(&dc->lock, flags);
dc               1194 fs/f2fs/segment.c 		dc->queued++;
dc               1195 fs/f2fs/segment.c 		list_move_tail(&dc->list, wait_list);
dc               1200 fs/f2fs/segment.c 		bio->bi_private = dc;
dc               1229 fs/f2fs/segment.c 	struct discard_cmd *dc = NULL;
dc               1241 fs/f2fs/segment.c 	dc = __attach_discard_cmd(sbi, bdev, lstart, start, len, parent,
dc               1243 fs/f2fs/segment.c 	if (!dc)
dc               1246 fs/f2fs/segment.c 	return dc;
dc               1250 fs/f2fs/segment.c 						struct discard_cmd *dc)
dc               1252 fs/f2fs/segment.c 	list_move_tail(&dc->list, &dcc->pend_list[plist_idx(dc->len)]);
dc               1256 fs/f2fs/segment.c 				struct discard_cmd *dc, block_t blkaddr)
dc               1259 fs/f2fs/segment.c 	struct discard_info di = dc->di;
dc               1262 fs/f2fs/segment.c 	if (dc->state == D_DONE || dc->len == 1) {
dc               1263 fs/f2fs/segment.c 		__remove_discard_cmd(sbi, dc);
dc               1270 fs/f2fs/segment.c 		dc->len = blkaddr - dc->lstart;
dc               1271 fs/f2fs/segment.c 		dcc->undiscard_blks += dc->len;
dc               1272 fs/f2fs/segment.c 		__relocate_discard_cmd(dcc, dc);
dc               1278 fs/f2fs/segment.c 			__insert_discard_tree(sbi, dc->bdev, blkaddr + 1,
dc               1283 fs/f2fs/segment.c 			dc->lstart++;
dc               1284 fs/f2fs/segment.c 			dc->len--;
dc               1285 fs/f2fs/segment.c 			dc->start++;
dc               1286 fs/f2fs/segment.c 			dcc->undiscard_blks += dc->len;
dc               1287 fs/f2fs/segment.c 			__relocate_discard_cmd(dcc, dc);
dc               1298 fs/f2fs/segment.c 	struct discard_cmd *dc;
dc               1306 fs/f2fs/segment.c 	dc = (struct discard_cmd *)f2fs_lookup_rb_tree_ret(&dcc->root,
dc               1311 fs/f2fs/segment.c 	if (dc)
dc               1312 fs/f2fs/segment.c 		prev_dc = dc;
dc               1410 fs/f2fs/segment.c 	struct discard_cmd *dc;
dc               1417 fs/f2fs/segment.c 	dc = (struct discard_cmd *)f2fs_lookup_rb_tree_ret(&dcc->root,
dc               1422 fs/f2fs/segment.c 	if (!dc)
dc               1423 fs/f2fs/segment.c 		dc = next_dc;
dc               1427 fs/f2fs/segment.c 	while (dc) {
dc               1431 fs/f2fs/segment.c 		if (dc->state != D_PREP)
dc               1439 fs/f2fs/segment.c 		dcc->next_pos = dc->lstart + dc->len;
dc               1440 fs/f2fs/segment.c 		err = __submit_discard_cmd(sbi, dpolicy, dc, &issued);
dc               1445 fs/f2fs/segment.c 		node = rb_next(&dc->rb_node);
dc               1447 fs/f2fs/segment.c 			__remove_discard_cmd(sbi, dc);
dc               1448 fs/f2fs/segment.c 		dc = rb_entry_safe(node, struct discard_cmd, rb_node);
dc               1453 fs/f2fs/segment.c 	if (!dc)
dc               1469 fs/f2fs/segment.c 	struct discard_cmd *dc, *tmp;
dc               1497 fs/f2fs/segment.c 		list_for_each_entry_safe(dc, tmp, pend_list, list) {
dc               1498 fs/f2fs/segment.c 			f2fs_bug_on(sbi, dc->state != D_PREP);
dc               1510 fs/f2fs/segment.c 			__submit_discard_cmd(sbi, dpolicy, dc, &issued);
dc               1533 fs/f2fs/segment.c 	struct discard_cmd *dc, *tmp;
dc               1540 fs/f2fs/segment.c 		list_for_each_entry_safe(dc, tmp, pend_list, list) {
dc               1541 fs/f2fs/segment.c 			f2fs_bug_on(sbi, dc->state != D_PREP);
dc               1542 fs/f2fs/segment.c 			__remove_discard_cmd(sbi, dc);
dc               1557 fs/f2fs/segment.c 							struct discard_cmd *dc)
dc               1562 fs/f2fs/segment.c 	wait_for_completion_io(&dc->wait);
dc               1564 fs/f2fs/segment.c 	f2fs_bug_on(sbi, dc->state != D_DONE);
dc               1565 fs/f2fs/segment.c 	dc->ref--;
dc               1566 fs/f2fs/segment.c 	if (!dc->ref) {
dc               1567 fs/f2fs/segment.c 		if (!dc->error)
dc               1568 fs/f2fs/segment.c 			len = dc->len;
dc               1569 fs/f2fs/segment.c 		__remove_discard_cmd(sbi, dc);
dc               1583 fs/f2fs/segment.c 	struct discard_cmd *dc, *tmp;
dc               1591 fs/f2fs/segment.c 	list_for_each_entry_safe(dc, tmp, wait_list, list) {
dc               1592 fs/f2fs/segment.c 		if (dc->lstart + dc->len <= start || end <= dc->lstart)
dc               1594 fs/f2fs/segment.c 		if (dc->len < dpolicy->granularity)
dc               1596 fs/f2fs/segment.c 		if (dc->state == D_DONE && !dc->ref) {
dc               1597 fs/f2fs/segment.c 			wait_for_completion_io(&dc->wait);
dc               1598 fs/f2fs/segment.c 			if (!dc->error)
dc               1599 fs/f2fs/segment.c 				trimmed += dc->len;
dc               1600 fs/f2fs/segment.c 			__remove_discard_cmd(sbi, dc);
dc               1602 fs/f2fs/segment.c 			dc->ref++;
dc               1610 fs/f2fs/segment.c 		trimmed += __wait_one_discard_bio(sbi, dc);
dc               1639 fs/f2fs/segment.c 	struct discard_cmd *dc;
dc               1643 fs/f2fs/segment.c 	dc = (struct discard_cmd *)f2fs_lookup_rb_tree(&dcc->root,
dc               1645 fs/f2fs/segment.c 	if (dc) {
dc               1646 fs/f2fs/segment.c 		if (dc->state == D_PREP) {
dc               1647 fs/f2fs/segment.c 			__punch_discard_cmd(sbi, dc, blkaddr);
dc               1649 fs/f2fs/segment.c 			dc->ref++;
dc               1656 fs/f2fs/segment.c 		__wait_one_discard_bio(sbi, dc);
dc               2750 fs/f2fs/segment.c 	struct discard_cmd *dc;
dc               2763 fs/f2fs/segment.c 	dc = (struct discard_cmd *)f2fs_lookup_rb_tree_ret(&dcc->root,
dc               2768 fs/f2fs/segment.c 	if (!dc)
dc               2769 fs/f2fs/segment.c 		dc = next_dc;
dc               2773 fs/f2fs/segment.c 	while (dc && dc->lstart <= end) {
dc               2777 fs/f2fs/segment.c 		if (dc->len < dpolicy->granularity)
dc               2780 fs/f2fs/segment.c 		if (dc->state != D_PREP) {
dc               2781 fs/f2fs/segment.c 			list_move_tail(&dc->list, &dcc->fstrim_list);
dc               2785 fs/f2fs/segment.c 		err = __submit_discard_cmd(sbi, dpolicy, dc, &issued);
dc               2788 fs/f2fs/segment.c 			start = dc->lstart + dc->len;
dc               2791 fs/f2fs/segment.c 				__remove_discard_cmd(sbi, dc);
dc               2800 fs/f2fs/segment.c 		node = rb_next(&dc->rb_node);
dc               2802 fs/f2fs/segment.c 			__remove_discard_cmd(sbi, dc);
dc               2803 fs/f2fs/segment.c 		dc = rb_entry_safe(node, struct discard_cmd, rb_node);
dc               3722 fs/nfsd/nfs4state.c 	struct nfsd4_destroy_clientid *dc = &u->destroy_clientid;
dc               3729 fs/nfsd/nfs4state.c 	unconf = find_unconfirmed_client(&dc->clientid, true, nn);
dc               3730 fs/nfsd/nfs4state.c 	conf = find_confirmed_client(&dc->clientid, true, nn);
dc               1556 fs/nfsd/nfs4xdr.c static __be32 nfsd4_decode_destroy_clientid(struct nfsd4_compoundargs *argp, struct nfsd4_destroy_clientid *dc)
dc               1561 fs/nfsd/nfs4xdr.c 	COPYMEM(&dc->clientid, 8);
dc               1613 fs/reiserfs/do_balan.c 	struct disk_child *dc;
dc               1624 fs/reiserfs/do_balan.c 	dc = B_N_CHILD(bh, 0);
dc               1626 fs/reiserfs/do_balan.c 	for (i = 0; i <= B_NR_ITEMS(bh); i++, dc++) {
dc               1627 fs/reiserfs/do_balan.c 		if (!is_reusable(s, dc_block_number(dc), 1)) {
dc               1631 fs/reiserfs/do_balan.c 				       dc, bh);
dc                136 fs/reiserfs/ibalance.c 	struct disk_child *dc;
dc                151 fs/reiserfs/ibalance.c 	dc = B_N_CHILD(cur, to + 1);
dc                153 fs/reiserfs/ibalance.c 	memmove(dc + count, dc, (nr + 1 - (to + 1)) * DC_SIZE);
dc                161 fs/reiserfs/ibalance.c 	memcpy(dc, new_dc, DC_SIZE * count);
dc                213 fs/reiserfs/ibalance.c 	struct disk_child *dc;
dc                243 fs/reiserfs/ibalance.c 	dc = B_N_CHILD(cur, first_p);
dc                245 fs/reiserfs/ibalance.c 	memmove(dc, dc + del_num, (nr + 1 - first_p - del_num) * DC_SIZE);
dc                312 fs/reiserfs/ibalance.c 	struct disk_child *dc;
dc                343 fs/reiserfs/ibalance.c 	dc = B_N_CHILD(dest, dest_order);
dc                345 fs/reiserfs/ibalance.c 	memmove(dc + cpy_num, dc, (nr_dest - dest_order) * DC_SIZE);
dc                348 fs/reiserfs/ibalance.c 	memcpy(dc, B_N_CHILD(src, src_order), DC_SIZE * cpy_num);
dc                883 fs/reiserfs/ibalance.c 			struct disk_child *dc;
dc                907 fs/reiserfs/ibalance.c 			dc = B_N_CHILD(tbSh, 0);
dc                908 fs/reiserfs/ibalance.c 			put_dc_size(dc,
dc                911 fs/reiserfs/ibalance.c 			put_dc_block_number(dc, insert_ptr[k]->b_blocknr);
dc                952 fs/reiserfs/ibalance.c 			struct disk_child *dc;
dc                973 fs/reiserfs/ibalance.c 			dc = B_N_CHILD(tb->R[h], 0);
dc                974 fs/reiserfs/ibalance.c 			put_dc_size(dc,
dc                979 fs/reiserfs/ibalance.c 			put_dc_block_number(dc,
dc               1003 fs/reiserfs/ibalance.c 		struct disk_child *dc;
dc               1017 fs/reiserfs/ibalance.c 		dc = B_N_CHILD(tbSh, 0);
dc               1018 fs/reiserfs/ibalance.c 		put_dc_block_number(dc, tbSh_1->b_blocknr);
dc               1019 fs/reiserfs/ibalance.c 		put_dc_size(dc,
dc               1098 fs/reiserfs/ibalance.c 			struct disk_child *dc;
dc               1119 fs/reiserfs/ibalance.c 			dc = B_N_CHILD(S_new, 0);
dc               1120 fs/reiserfs/ibalance.c 			put_dc_size(dc,
dc               1125 fs/reiserfs/ibalance.c 			put_dc_block_number(dc,
dc                168 fs/reiserfs/prints.c static int scnprintf_disk_child(char *buf, size_t size, struct disk_child *dc)
dc                171 fs/reiserfs/prints.c 			 dc_block_number(dc), dc_size(dc));
dc                445 fs/reiserfs/prints.c 	struct disk_child *dc;
dc                464 fs/reiserfs/prints.c 	dc = B_N_CHILD(bh, from);
dc                465 fs/reiserfs/prints.c 	reiserfs_printk("PTR %d: %y ", from, dc);
dc                467 fs/reiserfs/prints.c 	for (i = from, key = internal_key(bh, from), dc++; i < to;
dc                468 fs/reiserfs/prints.c 	     i++, key++, dc++) {
dc                469 fs/reiserfs/prints.c 		reiserfs_printk("KEY %d: %k PTR %d: %y ", i, key, i + 1, dc);
dc               2494 fs/unicode/mkutf8data.c 	unsigned int *dc;
dc               2512 fs/unicode/mkutf8data.c 				dc = unicode_data[*um].utf32nfdi;
dc               2513 fs/unicode/mkutf8data.c 				if (dc) {
dc               2514 fs/unicode/mkutf8data.c 					for (j = 0; dc[j]; j++)
dc               2515 fs/unicode/mkutf8data.c 						mapping[i++] = dc[j];
dc               2549 fs/unicode/mkutf8data.c 	unsigned int *dc;
dc               2566 fs/unicode/mkutf8data.c 				dc = unicode_data[*um].utf32nfdicf;
dc               2567 fs/unicode/mkutf8data.c 				if (dc) {
dc               2568 fs/unicode/mkutf8data.c 					for (j = 0; dc[j]; j++)
dc               2569 fs/unicode/mkutf8data.c 						mapping[i++] = dc[j];
dc                 34 fs/xfs/scrub/parent.c 	struct dir_context	dc;
dc                 42 fs/xfs/scrub/parent.c 	struct dir_context	*dc,
dc                 51 fs/xfs/scrub/parent.c 	spc = container_of(dc, struct xchk_parent_ctx, dc);
dc                 65 fs/xfs/scrub/parent.c 		.dc.actor = xchk_parent_actor,
dc                 66 fs/xfs/scrub/parent.c 		.dc.pos = 0,
dc                 97 fs/xfs/scrub/parent.c 		error = xfs_readdir(sc->tp, parent, &spc.dc, bufsize);
dc                100 fs/xfs/scrub/parent.c 		if (oldpos == spc.dc.pos)
dc                102 fs/xfs/scrub/parent.c 		oldpos = spc.dc.pos;
dc                 60 include/drm/drm_mipi_dbi.h 	struct gpio_desc *dc;
dc                134 include/drm/drm_mipi_dbi.h 		      struct gpio_desc *dc);
dc                 72 include/linux/mlx5/mlx5_ifc_fpga.h 	u8         dc[0x1];
dc                674 include/media/v4l2-mem2mem.h 				   struct v4l2_decoder_cmd *dc);
dc                 11 include/trace/events/tegra_apb_dma.h 	TP_PROTO(struct dma_chan *dc, dma_cookie_t cookie, struct dma_tx_state *state),
dc                 12 include/trace/events/tegra_apb_dma.h 	TP_ARGS(dc, cookie, state),
dc                 14 include/trace/events/tegra_apb_dma.h 		__string(chan,	dev_name(&dc->dev->device))
dc                 19 include/trace/events/tegra_apb_dma.h 		__assign_str(chan, dev_name(&dc->dev->device));
dc                 28 include/trace/events/tegra_apb_dma.h 	TP_PROTO(struct dma_chan *dc, int count, void *ptr),
dc                 29 include/trace/events/tegra_apb_dma.h 	TP_ARGS(dc, count, ptr),
dc                 31 include/trace/events/tegra_apb_dma.h 		__string(chan,	dev_name(&dc->dev->device))
dc                 36 include/trace/events/tegra_apb_dma.h 		__assign_str(chan, dev_name(&dc->dev->device));
dc                 45 include/trace/events/tegra_apb_dma.h 	TP_PROTO(struct dma_chan *dc, int irq),
dc                 46 include/trace/events/tegra_apb_dma.h 	TP_ARGS(dc, irq),
dc                 48 include/trace/events/tegra_apb_dma.h 		__string(chan,	dev_name(&dc->dev->device))
dc                 52 include/trace/events/tegra_apb_dma.h 		__assign_str(chan, dev_name(&dc->dev->device));
dc                287 include/video/imx-ipu-v3.h void ipu_dc_put(struct ipu_dc *dc);
dc                288 include/video/imx-ipu-v3.h int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
dc                291 include/video/imx-ipu-v3.h void ipu_dc_enable_channel(struct ipu_dc *dc);
dc                292 include/video/imx-ipu-v3.h void ipu_dc_disable_channel(struct ipu_dc *dc);
dc                498 include/video/imx-ipu-v3.h 	int dc;
dc               2217 net/bluetooth/hci_request.c 			struct hci_cp_disconnect dc;
dc               2219 net/bluetooth/hci_request.c 			dc.handle = cpu_to_le16(conn->handle);
dc               2220 net/bluetooth/hci_request.c 			dc.reason = reason;
dc               2221 net/bluetooth/hci_request.c 			hci_req_add(req, HCI_OP_DISCONNECT, sizeof(dc), &dc);
dc                189 net/core/utils.c 	u8 *d, *dc = NULL;
dc                227 net/core/utils.c 				dc = d;
dc                229 net/core/utils.c 				if (dc - dbuf >= sizeof(dbuf))
dc                262 net/core/utils.c 		if (!dc && d + 2 < dbuf + sizeof(dbuf)) {
dc                270 net/core/utils.c 		if ((dc && d + 4 < dbuf + sizeof(dbuf)) ||
dc                283 net/core/utils.c 	if (dc) {
dc                284 net/core/utils.c 		while (d >= dc)
dc                286 net/core/utils.c 		while (i >= dc - dbuf)
dc                261 net/wireless/core.h 		} dc;
dc               1144 net/wireless/sme.c 	ev->dc.ie = ((u8 *)ev) + sizeof(*ev);
dc               1145 net/wireless/sme.c 	ev->dc.ie_len = ie_len;
dc               1146 net/wireless/sme.c 	memcpy((void *)ev->dc.ie, ie, ie_len);
dc               1147 net/wireless/sme.c 	ev->dc.reason = reason;
dc               1148 net/wireless/sme.c 	ev->dc.locally_generated = locally_generated;
dc                880 net/wireless/util.c 						ev->dc.ie, ev->dc.ie_len,
dc                881 net/wireless/util.c 						ev->dc.reason,
dc                882 net/wireless/util.c 						!ev->dc.locally_generated);