davinci_nand_readl  131 drivers/mtd/nand/raw/davinci_nand.c 	return davinci_nand_readl(info, NANDF1ECC_OFFSET
davinci_nand_readl  149 drivers/mtd/nand/raw/davinci_nand.c 	nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
davinci_nand_readl  226 drivers/mtd/nand/raw/davinci_nand.c 	davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
davinci_nand_readl  231 drivers/mtd/nand/raw/davinci_nand.c 	val = davinci_nand_readl(info, NANDFCR_OFFSET);
davinci_nand_readl  247 drivers/mtd/nand/raw/davinci_nand.c 	code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
davinci_nand_readl  248 drivers/mtd/nand/raw/davinci_nand.c 	code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
davinci_nand_readl  249 drivers/mtd/nand/raw/davinci_nand.c 	code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
davinci_nand_readl  250 drivers/mtd/nand/raw/davinci_nand.c 	code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
davinci_nand_readl  267 drivers/mtd/nand/raw/davinci_nand.c 		davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
davinci_nand_readl  326 drivers/mtd/nand/raw/davinci_nand.c 	davinci_nand_readl(info, NANDFSR_OFFSET);
davinci_nand_readl  335 drivers/mtd/nand/raw/davinci_nand.c 	davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
davinci_nand_readl  342 drivers/mtd/nand/raw/davinci_nand.c 			davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
davinci_nand_readl  355 drivers/mtd/nand/raw/davinci_nand.c 		ecc_state = (davinci_nand_readl(info,
davinci_nand_readl  361 drivers/mtd/nand/raw/davinci_nand.c 		u32	fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
davinci_nand_readl  365 drivers/mtd/nand/raw/davinci_nand.c 			davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
davinci_nand_readl  368 drivers/mtd/nand/raw/davinci_nand.c 			davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
davinci_nand_readl  386 drivers/mtd/nand/raw/davinci_nand.c 			error_address = davinci_nand_readl(info,
davinci_nand_readl  388 drivers/mtd/nand/raw/davinci_nand.c 			error_value = davinci_nand_readl(info,
davinci_nand_readl  391 drivers/mtd/nand/raw/davinci_nand.c 			error_address = davinci_nand_readl(info,
davinci_nand_readl  393 drivers/mtd/nand/raw/davinci_nand.c 			error_value = davinci_nand_readl(info,
davinci_nand_readl  454 drivers/mtd/nand/raw/davinci_nand.c 	return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
davinci_nand_readl  784 drivers/mtd/nand/raw/davinci_nand.c 	val = davinci_nand_readl(info, NANDFCR_OFFSET);
davinci_nand_readl  805 drivers/mtd/nand/raw/davinci_nand.c 	val = davinci_nand_readl(info, NRCSR_OFFSET);