d_offset           83 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c 	u32 ctrl1, d_offset, t_count, bpp;
d_offset          129 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c 	d_offset = m->hdisplay * bpp / 8;
d_offset          131 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c 	writel(CRT_DISP_OFFSET(d_offset) | CRT_TERM_COUNT(t_count),
d_offset          132 fs/readdir.c   	unsigned long	d_offset;
d_offset          165 fs/readdir.c   		__put_user(offset, &dirent->d_offset) ||
d_offset          398 fs/readdir.c   	compat_ulong_t	d_offset;
d_offset          432 fs/readdir.c   		__put_user(offset, &dirent->d_offset) ||
d_offset          175 include/net/6lowpan.h 	u8 d_offset;
d_offset          100 net/ieee802154/6lowpan/reassembly.c 	offset = lowpan_802154_cb(skb)->d_offset << 3;
d_offset          260 net/ieee802154/6lowpan/reassembly.c 		fail |= lowpan_fetch_skb(skb, &cb->d_offset, 1);
d_offset          263 net/ieee802154/6lowpan/reassembly.c 		cb->d_offset = 0;