cvmx_write_csr 147 arch/mips/cavium-octeon/executive/cvmx-boot-vector.c cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8); cvmx_write_csr 148 arch/mips/cavium-octeon/executive/cvmx-boot-vector.c cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, v); cvmx_write_csr 150 arch/mips/cavium-octeon/executive/cvmx-boot-vector.c cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, 15 * 8); cvmx_write_csr 151 arch/mips/cavium-octeon/executive/cvmx-boot-vector.c cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, kseg0_mem); cvmx_write_csr 152 arch/mips/cavium-octeon/executive/cvmx-boot-vector.c cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000); cvmx_write_csr 261 arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue_id & 0xffff); cvmx_write_csr 69 arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); cvmx_write_csr 96 arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); cvmx_write_csr 140 arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); cvmx_write_csr 62 arch/mips/cavium-octeon/executive/cvmx-helper-loop.c cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64); cvmx_write_csr 68 arch/mips/cavium-octeon/executive/cvmx-helper-loop.c cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); cvmx_write_csr 106 arch/mips/cavium-octeon/executive/cvmx-helper-npi.c cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), cvmx_write_csr 109 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); cvmx_write_csr 110 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); cvmx_write_csr 111 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); cvmx_write_csr 112 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); cvmx_write_csr 114 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp); cvmx_write_csr 116 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp); cvmx_write_csr 118 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp); cvmx_write_csr 120 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); cvmx_write_csr 138 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12); cvmx_write_csr 140 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11); cvmx_write_csr 142 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10); cvmx_write_csr 144 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9); cvmx_write_csr 180 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64); cvmx_write_csr 184 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64); cvmx_write_csr 207 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface), cvmx_write_csr 218 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface), cvmx_write_csr 220 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL cvmx_write_csr 224 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), cvmx_write_csr 226 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), cvmx_write_csr 229 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), cvmx_write_csr 231 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), cvmx_write_csr 245 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface), cvmx_write_csr 318 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), cvmx_write_csr 326 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); cvmx_write_csr 332 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos.u64); cvmx_write_csr 340 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64); cvmx_write_csr 350 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_NPI_DBG_SELECT, cvmx_write_csr 359 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); cvmx_write_csr 386 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 50); cvmx_write_csr 387 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40); cvmx_write_csr 388 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); cvmx_write_csr 390 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5); cvmx_write_csr 391 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40); cvmx_write_csr 392 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); cvmx_write_csr 394 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); cvmx_write_csr 395 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); cvmx_write_csr 396 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); cvmx_write_csr 418 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TXX_CLK cvmx_write_csr 428 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); cvmx_write_csr 431 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), cvmx_write_csr 438 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); cvmx_write_csr 439 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, cvmx_write_csr 444 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp_save.u64); cvmx_write_csr 448 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); cvmx_write_csr 62 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); cvmx_write_csr 82 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface), cvmx_write_csr 103 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), cvmx_write_csr 118 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG cvmx_write_csr 153 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), cvmx_write_csr 172 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), cvmx_write_csr 214 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); cvmx_write_csr 257 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); cvmx_write_csr 258 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); cvmx_write_csr 265 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); cvmx_write_csr 266 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); cvmx_write_csr 273 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512); cvmx_write_csr 274 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192); cvmx_write_csr 281 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), cvmx_write_csr 285 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); cvmx_write_csr 292 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); cvmx_write_csr 353 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); cvmx_write_csr 378 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), cvmx_write_csr 89 arch/mips/cavium-octeon/executive/cvmx-helper-spi.c cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64); cvmx_write_csr 118 arch/mips/cavium-octeon/executive/cvmx-helper-spi.c cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64); cvmx_write_csr 107 arch/mips/cavium-octeon/executive/cvmx-helper-util.c cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64); cvmx_write_csr 116 arch/mips/cavium-octeon/executive/cvmx-helper-util.c cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64); cvmx_write_csr 147 arch/mips/cavium-octeon/executive/cvmx-helper-util.c cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), cvmx_write_csr 158 arch/mips/cavium-octeon/executive/cvmx-helper-util.c cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64); cvmx_write_csr 164 arch/mips/cavium-octeon/executive/cvmx-helper-util.c cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64); cvmx_write_csr 191 arch/mips/cavium-octeon/executive/cvmx-helper-util.c cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64); cvmx_write_csr 211 arch/mips/cavium-octeon/executive/cvmx-helper-util.c cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64); cvmx_write_csr 242 arch/mips/cavium-octeon/executive/cvmx-helper-util.c cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64); cvmx_write_csr 273 arch/mips/cavium-octeon/executive/cvmx-helper-util.c cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface), cvmx_write_csr 78 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); cvmx_write_csr 100 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64); cvmx_write_csr 128 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); cvmx_write_csr 136 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); cvmx_write_csr 140 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); cvmx_write_csr 142 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); cvmx_write_csr 144 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); cvmx_write_csr 153 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64); cvmx_write_csr 164 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64); cvmx_write_csr 185 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); cvmx_write_csr 203 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1); cvmx_write_csr 204 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512); cvmx_write_csr 205 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192); cvmx_write_csr 206 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); cvmx_write_csr 209 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface), cvmx_write_csr 211 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), cvmx_write_csr 213 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_PCSXX_INT_REG(interface), cvmx_write_csr 230 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64); cvmx_write_csr 231 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64); cvmx_write_csr 232 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64); cvmx_write_csr 236 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); cvmx_write_csr 240 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); cvmx_write_csr 284 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); cvmx_write_csr 285 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); cvmx_write_csr 286 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); cvmx_write_csr 653 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64); cvmx_write_csr 666 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_PKO_REG_MIN_PKT, min_pkt.u64); cvmx_write_csr 816 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0); cvmx_write_csr 838 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), cvmx_write_csr 896 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG cvmx_write_csr 899 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), cvmx_write_csr 901 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), cvmx_write_csr 904 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_GMXX_RXX_JABBER cvmx_write_csr 907 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX cvmx_write_csr 939 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG cvmx_write_csr 942 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), cvmx_write_csr 944 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), cvmx_write_csr 946 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_GMXX_RXX_JABBER cvmx_write_csr 949 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX cvmx_write_csr 952 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0); cvmx_write_csr 1029 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64); cvmx_write_csr 54 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), cvmx_write_csr 227 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64); cvmx_write_csr 235 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), cvmx_write_csr 268 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64); cvmx_write_csr 276 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_write_csr(CVMX_PCSXX_INT_REG(index), cvmx_write_csr 297 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64); cvmx_write_csr 306 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_write_csr(CVMX_SPXX_INT_REG(index), cvmx_write_csr 337 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64); cvmx_write_csr 345 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_write_csr(CVMX_STXX_INT_REG(index), cvmx_write_csr 370 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64); cvmx_write_csr 69 arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64); cvmx_write_csr 137 arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64); cvmx_write_csr 102 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask); cvmx_write_csr 119 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_SPAR0, cvmx_write_csr 124 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_SPAR1, cvmx_write_csr 129 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_SPAR2, cvmx_write_csr 134 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_SPAR3, cvmx_write_csr 154 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask); cvmx_write_csr 156 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_SPAR4, cvmx_write_csr 201 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64); cvmx_write_csr 228 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_TADX_PRF(tad), cvmx_write_csr 365 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64); cvmx_write_csr 372 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64); cvmx_write_csr 376 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64); cvmx_write_csr 390 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64); cvmx_write_csr 397 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64); cvmx_write_csr 402 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_DBG, 0); cvmx_write_csr 908 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64); cvmx_write_csr 916 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_DBG, 0); cvmx_write_csr 107 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_MEM_IQUEUE_PTRS, config.u64); cvmx_write_csr 133 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64); cvmx_write_csr 154 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64); cvmx_write_csr 198 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64); cvmx_write_csr 220 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); cvmx_write_csr 222 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); cvmx_write_csr 225 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); cvmx_write_csr 227 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); cvmx_write_csr 266 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64); cvmx_write_csr 277 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); cvmx_write_csr 289 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); cvmx_write_csr 314 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); cvmx_write_csr 316 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64); cvmx_write_csr 543 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); cvmx_write_csr 544 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64); cvmx_write_csr 604 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64); cvmx_write_csr 605 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64); cvmx_write_csr 643 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64); cvmx_write_csr 644 arch/mips/cavium-octeon/executive/cvmx-pko.c cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64); cvmx_write_csr 208 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); cvmx_write_csr 210 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); cvmx_write_csr 213 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0); cvmx_write_csr 214 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0); cvmx_write_csr 217 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); cvmx_write_csr 238 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), cvmx_write_csr 243 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), cvmx_write_csr 248 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SPXX_INT_REG(interface), cvmx_write_csr 250 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); cvmx_write_csr 251 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_STXX_INT_REG(interface), cvmx_write_csr 253 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64); cvmx_write_csr 267 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); cvmx_write_csr 272 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); cvmx_write_csr 288 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64); cvmx_write_csr 291 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SPXX_DBG_DESKEW_CTL(interface), cvmx_write_csr 325 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); cvmx_write_csr 339 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), cvmx_write_csr 346 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SRXX_SPI4_STAT(interface), cvmx_write_csr 362 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_STXX_ARB_CTL(interface), stxx_arb_ctl.u64); cvmx_write_csr 368 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_GMXX_TX_SPI_MAX(interface), cvmx_write_csr 373 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_GMXX_TX_SPI_THRESH(interface), cvmx_write_csr 379 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_GMXX_TX_SPI_CTL(interface), cvmx_write_csr 387 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface), cvmx_write_csr 402 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), cvmx_write_csr 409 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_STXX_SPI4_STAT(interface), cvmx_write_csr 456 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); cvmx_write_csr 481 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); cvmx_write_csr 529 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); cvmx_write_csr 535 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64); cvmx_write_csr 551 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); cvmx_write_csr 589 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); cvmx_write_csr 601 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64); cvmx_write_csr 643 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); cvmx_write_csr 651 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64); cvmx_write_csr 657 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_GMXX_RXX_FRM_MIN(0, interface), cvmx_write_csr 661 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(0, interface), cvmx_write_csr 665 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_write_csr(CVMX_GMXX_RXX_JABBER(0, interface), gmxx_rxx_jabber.u64); cvmx_write_csr 46 arch/mips/cavium-octeon/executive/octeon-model.c cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64); cvmx_write_csr 107 arch/mips/cavium-octeon/oct_ilm.c cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64); cvmx_write_csr 143 arch/mips/cavium-octeon/oct_ilm.c cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64); cvmx_write_csr 313 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); cvmx_write_csr 322 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); cvmx_write_csr 345 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); cvmx_write_csr 354 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); cvmx_write_csr 377 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); cvmx_write_csr 386 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); cvmx_write_csr 417 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); cvmx_write_csr 419 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); cvmx_write_csr 450 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); cvmx_write_csr 452 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); cvmx_write_csr 477 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); cvmx_write_csr 481 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); cvmx_write_csr 498 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask); cvmx_write_csr 514 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask); cvmx_write_csr 527 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_SUM2_PPX_IP4(index), mask); cvmx_write_csr 542 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(coreid), mask); cvmx_write_csr 561 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); cvmx_write_csr 565 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); cvmx_write_csr 580 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); cvmx_write_csr 584 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); cvmx_write_csr 601 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); cvmx_write_csr 603 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INT_SUM1, mask); cvmx_write_csr 625 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); cvmx_write_csr 632 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); cvmx_write_csr 655 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); cvmx_write_csr 662 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); cvmx_write_csr 696 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), cfg.u64); cvmx_write_csr 729 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); cvmx_write_csr 739 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); cvmx_write_csr 752 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_GPIO_INT_CLR, mask); cvmx_write_csr 829 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); cvmx_write_csr 831 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); cvmx_write_csr 864 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); cvmx_write_csr 867 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); cvmx_write_csr 877 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); cvmx_write_csr 880 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); cvmx_write_csr 907 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask); cvmx_write_csr 909 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask); cvmx_write_csr 1082 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); cvmx_write_csr 1096 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid); cvmx_write_csr 1389 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); cvmx_write_csr 1390 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); cvmx_write_csr 1391 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); cvmx_write_csr 1392 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); cvmx_write_csr 1412 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(base + regx + ipx, 0); cvmx_write_csr 1646 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); cvmx_write_csr 1663 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); cvmx_write_csr 1678 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); cvmx_write_csr 1694 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); cvmx_write_csr 1709 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); cvmx_write_csr 1725 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); cvmx_write_csr 1739 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); cvmx_write_csr 1753 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); cvmx_write_csr 1765 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); cvmx_write_csr 1776 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); cvmx_write_csr 1806 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); cvmx_write_csr 1825 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); cvmx_write_csr 2127 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(host_data->en_reg, en); cvmx_write_csr 2141 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(host_data->en_reg, en); cvmx_write_csr 2248 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(host_data->en_reg, en); cvmx_write_csr 2249 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(host_data->raw_reg, 1ull << i); cvmx_write_csr 2257 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(host_data->raw_reg, 1ull << i); cvmx_write_csr 2319 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(host_data->en_reg, 0); /* disable all IRQs */ cvmx_write_csr 2320 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(host_data->raw_reg, ~0); /* ack any outstanding */ cvmx_write_csr 2396 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64); cvmx_write_csr 2402 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(isc_ctl_addr, isc_ctl.u64); cvmx_write_csr 2419 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64); cvmx_write_csr 2420 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(isc_ctl_addr, 0); cvmx_write_csr 2444 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(isc_w1c_addr, isc_w1c.u64); cvmx_write_csr 2460 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(isc_w1c_addr, isc_w1c.u64); cvmx_write_csr 2484 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(isc_w1c_addr, isc_w1c.u64); cvmx_write_csr 2513 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64); cvmx_write_csr 2519 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(isc_ctl_addr, isc_ctl.u64); cvmx_write_csr 2604 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(isc_w1c_addr, isc_w1c.u64); cvmx_write_csr 2659 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(isc_w1c_addr, isc_w1c.u64); cvmx_write_csr 2685 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(isc_w1s_addr, isc_w1s.u64); cvmx_write_csr 2705 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(isc_w1c_addr, isc_ctl.u64); cvmx_write_csr 2706 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(isc_ctl_addr, 0); cvmx_write_csr 2713 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(isc_ctl_addr, isc_ctl.u64); cvmx_write_csr 2755 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(isc_w1c_addr, isc_w1c.u64); cvmx_write_csr 2791 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip2), 0); cvmx_write_csr 2792 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_IDT_PP(idt_ip2, 0), 1ull << core); cvmx_write_csr 2793 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_IDT_IO(idt_ip2), 0); cvmx_write_csr 2796 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip3), 1); cvmx_write_csr 2797 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_IDT_PP(idt_ip3, 0), 1ull << core); cvmx_write_csr 2798 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_IDT_IO(idt_ip3), 0); cvmx_write_csr 2801 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip4), 2); cvmx_write_csr 2802 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_IDT_PP(idt_ip4, 0), 0); cvmx_write_csr 2803 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_IDT_IO(idt_ip4), 0); cvmx_write_csr 2805 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_IDT_CTL(unused_idt2), 0); cvmx_write_csr 2806 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_IDT_PP(unused_idt2, 0), 0); cvmx_write_csr 2807 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_IDT_IO(unused_idt2), 0); cvmx_write_csr 2812 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_ISC_W1C(intsn), 2); cvmx_write_csr 2813 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(b + CIU3_ISC_CTL(intsn), 0); cvmx_write_csr 106 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64); cvmx_write_csr 115 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0), cvmx_write_csr 136 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); cvmx_write_csr 155 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); cvmx_write_csr 187 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); cvmx_write_csr 191 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); cvmx_write_csr 194 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); cvmx_write_csr 204 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); cvmx_write_csr 214 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); cvmx_write_csr 218 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); cvmx_write_csr 228 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); cvmx_write_csr 235 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); cvmx_write_csr 242 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); cvmx_write_csr 249 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); cvmx_write_csr 253 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull); cvmx_write_csr 309 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64); cvmx_write_csr 372 arch/mips/cavium-octeon/octeon-platform.c cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64); cvmx_write_csr 257 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); cvmx_write_csr 262 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); cvmx_write_csr 267 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64); cvmx_write_csr 274 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); cvmx_write_csr 280 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); cvmx_write_csr 363 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); cvmx_write_csr 368 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); cvmx_write_csr 380 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); cvmx_write_csr 390 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); cvmx_write_csr 427 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); cvmx_write_csr 435 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); cvmx_write_csr 449 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); cvmx_write_csr 457 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); cvmx_write_csr 462 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); cvmx_write_csr 480 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64); cvmx_write_csr 493 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64); cvmx_write_csr 210 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); cvmx_write_csr 212 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); cvmx_write_csr 280 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); cvmx_write_csr 436 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); cvmx_write_csr 438 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); cvmx_write_csr 444 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_RST_SOFT_RST, 1); cvmx_write_csr 446 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); cvmx_write_csr 463 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); cvmx_write_csr 480 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); cvmx_write_csr 481 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); cvmx_write_csr 638 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); cvmx_write_csr 649 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); cvmx_write_csr 774 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_LED_EN, 0); cvmx_write_csr 775 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_LED_PRT, 0); cvmx_write_csr 776 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_LED_DBG, 0); cvmx_write_csr 777 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_LED_PRT_FMT, 0); cvmx_write_csr 778 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); cvmx_write_csr 779 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); cvmx_write_csr 780 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); cvmx_write_csr 781 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); cvmx_write_csr 782 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_LED_EN, 1); cvmx_write_csr 851 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); cvmx_write_csr 853 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); cvmx_write_csr 1123 arch/mips/cavium-octeon/setup.c cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); cvmx_write_csr 79 arch/mips/cavium-octeon/smp.c cvmx_write_csr(mbox_clrx, action); cvmx_write_csr 106 arch/mips/cavium-octeon/smp.c cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); cvmx_write_csr 263 arch/mips/cavium-octeon/smp.c cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff); cvmx_write_csr 343 arch/mips/cavium-octeon/smp.c cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); cvmx_write_csr 344 arch/mips/cavium-octeon/smp.c cvmx_write_csr(CVMX_CIU_PP_RST, 0); cvmx_write_csr 391 arch/mips/cavium-octeon/smp.c cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); cvmx_write_csr 392 arch/mips/cavium-octeon/smp.c cvmx_write_csr(CVMX_CIU_PP_RST, 0); cvmx_write_csr 401 arch/mips/cavium-octeon/smp.c cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); cvmx_write_csr 165 arch/mips/include/asm/octeon/cvmx-fpa.h cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull, cvmx_write_csr 176 arch/mips/include/asm/octeon/cvmx-fpa.h cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64); cvmx_write_csr 95 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64); cvmx_write_csr 99 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64); cvmx_write_csr 103 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64); cvmx_write_csr 107 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64); cvmx_write_csr 111 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64); cvmx_write_csr 115 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64); cvmx_write_csr 120 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64); cvmx_write_csr 142 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); cvmx_write_csr 153 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); cvmx_write_csr 204 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, cvmx_write_csr 222 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, cvmx_write_csr 249 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, cvmx_write_csr 261 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, cvmx_write_csr 279 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, cvmx_write_csr 291 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, cvmx_write_csr 307 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, cvmx_write_csr 317 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, cvmx_write_csr 326 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64); cvmx_write_csr 334 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64); cvmx_write_csr 296 arch/mips/include/asm/octeon/cvmx-pip.h cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64); cvmx_write_csr 297 arch/mips/include/asm/octeon/cvmx-pip.h cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64); cvmx_write_csr 327 arch/mips/include/asm/octeon/cvmx-pip.h cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64); cvmx_write_csr 343 arch/mips/include/asm/octeon/cvmx-pip.h cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64); cvmx_write_csr 357 arch/mips/include/asm/octeon/cvmx-pip.h cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64); cvmx_write_csr 387 arch/mips/include/asm/octeon/cvmx-pip.h cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64); cvmx_write_csr 470 arch/mips/include/asm/octeon/cvmx-pip.h cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64); cvmx_write_csr 474 arch/mips/include/asm/octeon/cvmx-pip.h cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64); cvmx_write_csr 493 arch/mips/include/asm/octeon/cvmx-pip.h cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); cvmx_write_csr 519 arch/mips/include/asm/octeon/cvmx-pip.h cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); cvmx_write_csr 587 arch/mips/include/asm/octeon/cvmx-pko.h cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); cvmx_write_csr 593 arch/mips/include/asm/octeon/cvmx-pko.h cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64); cvmx_write_csr 600 arch/mips/include/asm/octeon/cvmx-pko.h cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64); cvmx_write_csr 606 arch/mips/include/asm/octeon/cvmx-pko.h cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); cvmx_write_csr 612 arch/mips/include/asm/octeon/cvmx-pko.h cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); cvmx_write_csr 1857 arch/mips/include/asm/octeon/cvmx-pow.h cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64); cvmx_write_csr 1907 arch/mips/include/asm/octeon/cvmx-pow.h cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64); cvmx_write_csr 282 arch/mips/include/asm/octeon/cvmx.h cvmx_write_csr((__force uint64_t)csr_addr, val); cvmx_write_csr 278 arch/mips/pci/msi-octeon.c cvmx_write_csr(mis_ena_reg[irq_index], en); cvmx_write_csr 294 arch/mips/pci/msi-octeon.c cvmx_write_csr(mis_ena_reg[irq_index], en); cvmx_write_csr 340 arch/mips/pci/msi-octeon.c cvmx_write_csr(msi_rcv_reg[index], 1ull << bit); cvmx_write_csr 369 arch/mips/pci/pci-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1); cvmx_write_csr 377 arch/mips/pci/pci-octeon.c cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64); cvmx_write_csr 381 arch/mips/pci/pci-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4); cvmx_write_csr 498 arch/mips/pci/pci-octeon.c cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64); cvmx_write_csr 606 arch/mips/pci/pci-octeon.c cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64); cvmx_write_csr 700 arch/mips/pci/pci-octeon.c cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1); cvmx_write_csr 178 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64); cvmx_write_csr 185 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64); cvmx_write_csr 207 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64); cvmx_write_csr 213 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64); cvmx_write_csr 446 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64); cvmx_write_csr 461 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64); cvmx_write_csr 465 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64); cvmx_write_csr 618 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64); cvmx_write_csr 624 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64); cvmx_write_csr 645 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM)); cvmx_write_csr 745 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64); cvmx_write_csr 767 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); cvmx_write_csr 770 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); cvmx_write_csr 776 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); cvmx_write_csr 779 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); cvmx_write_csr 800 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); cvmx_write_csr 802 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); cvmx_write_csr 809 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); cvmx_write_csr 813 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); cvmx_write_csr 832 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64); cvmx_write_csr 886 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64); cvmx_write_csr 905 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64); cvmx_write_csr 915 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1); cvmx_write_csr 916 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1); cvmx_write_csr 920 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0); cvmx_write_csr 923 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE); cvmx_write_csr 953 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0); cvmx_write_csr 974 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64); cvmx_write_csr 985 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64); cvmx_write_csr 1029 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc); cvmx_write_csr 1044 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f); cvmx_write_csr 1099 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64); cvmx_write_csr 1245 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64); cvmx_write_csr 1252 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64); cvmx_write_csr 1269 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); cvmx_write_csr 1271 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); cvmx_write_csr 1278 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); cvmx_write_csr 1282 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); cvmx_write_csr 1338 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64); cvmx_write_csr 1359 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64); cvmx_write_csr 1370 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1); cvmx_write_csr 1371 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1); cvmx_write_csr 1375 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0); cvmx_write_csr 1383 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0); cvmx_write_csr 1397 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64); cvmx_write_csr 1403 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64); cvmx_write_csr 1406 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE); cvmx_write_csr 1415 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64); cvmx_write_csr 1426 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64); cvmx_write_csr 1508 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64); cvmx_write_csr 1520 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64); cvmx_write_csr 2073 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(port), sli_ctl_portx.u64); cvmx_write_csr 2080 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(!port), sli_ctl_portx.u64); cvmx_write_csr 118 drivers/ata/pata_octeon_cf.c cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64); cvmx_write_csr 207 drivers/ata/pata_octeon_cf.c cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64); cvmx_write_csr 210 drivers/ata/pata_octeon_cf.c cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1), cvmx_write_csr 282 drivers/ata/pata_octeon_cf.c cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64); cvmx_write_csr 577 drivers/ata/pata_octeon_cf.c cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64); cvmx_write_csr 580 drivers/ata/pata_octeon_cf.c cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64); cvmx_write_csr 612 drivers/ata/pata_octeon_cf.c cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64); cvmx_write_csr 647 drivers/ata/pata_octeon_cf.c cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64); cvmx_write_csr 651 drivers/ata/pata_octeon_cf.c cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64); cvmx_write_csr 655 drivers/ata/pata_octeon_cf.c cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64); cvmx_write_csr 723 drivers/ata/pata_octeon_cf.c cvmx_write_csr(cf_port->dma_base + DMA_INT, cvmx_write_csr 1020 drivers/ata/pata_octeon_cf.c cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64); cvmx_write_csr 1024 drivers/ata/pata_octeon_cf.c cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64); cvmx_write_csr 1028 drivers/ata/pata_octeon_cf.c cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64); cvmx_write_csr 36 drivers/char/hw_random/octeon-rng.c cvmx_write_csr((u64)p->control_status, ctl.u64); cvmx_write_csr 47 drivers/char/hw_random/octeon-rng.c cvmx_write_csr((u64)p->control_status, ctl.u64); cvmx_write_csr 41 drivers/edac/octeon_edac-l2c.c cvmx_write_csr(CVMX_L2T_ERR, l2t_err_reset.u64); cvmx_write_csr 56 drivers/edac/octeon_edac-l2c.c cvmx_write_csr(CVMX_L2D_ERR, l2d_err_reset.u64); cvmx_write_csr 100 drivers/edac/octeon_edac-l2c.c cvmx_write_csr(CVMX_L2C_ERR_TDTX(tad), err_tdtx_reset.u64); cvmx_write_csr 123 drivers/edac/octeon_edac-l2c.c cvmx_write_csr(CVMX_L2C_ERR_TTGX(tad), err_ttgx_reset.u64); cvmx_write_csr 160 drivers/edac/octeon_edac-l2c.c cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64); cvmx_write_csr 165 drivers/edac/octeon_edac-l2c.c cvmx_write_csr(CVMX_L2T_ERR, l2d_err.u64); cvmx_write_csr 68 drivers/edac/octeon_edac-lmc.c cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx), cfg0.u64); cvmx_write_csr 121 drivers/edac/octeon_edac-lmc.c cvmx_write_csr(CVMX_LMCX_INT(mci->mc_idx), int_reg.u64); cvmx_write_csr 266 drivers/edac/octeon_edac-lmc.c cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), cfg0.u64); cvmx_write_csr 298 drivers/edac/octeon_edac-lmc.c cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), en.u64); cvmx_write_csr 46 drivers/gpio/gpio-octeon.c cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0); cvmx_write_csr 55 drivers/gpio/gpio-octeon.c cvmx_write_csr(reg, mask); cvmx_write_csr 69 drivers/gpio/gpio-octeon.c cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64); cvmx_write_csr 166 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); cvmx_write_csr 178 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); cvmx_write_csr 245 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_IRING2, 1); cvmx_write_csr 281 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64); cvmx_write_csr 298 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(CVMX_MIXX_TSCTL(p->port), 0); cvmx_write_csr 468 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64); cvmx_write_csr 520 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); cvmx_write_csr 525 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); cvmx_write_csr 607 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); cvmx_write_csr 614 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64); cvmx_write_csr 616 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM0, cam_state.cam[0]); cvmx_write_csr 617 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM1, cam_state.cam[1]); cvmx_write_csr 618 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM2, cam_state.cam[2]); cvmx_write_csr 619 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM3, cam_state.cam[3]); cvmx_write_csr 620 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM4, cam_state.cam[4]); cvmx_write_csr 621 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM5, cam_state.cam[5]); cvmx_write_csr 622 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM_EN, cam_state.cam_mask); cvmx_write_csr 626 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); cvmx_write_csr 653 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_MAX, max_packet); cvmx_write_csr 659 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_JABBER, cvmx_write_csr 674 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64); cvmx_write_csr 715 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, clock_comp); cvmx_write_csr 730 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(CVMX_MIO_PTP_CLOCK_CFG, ptp.u64); cvmx_write_csr 751 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); cvmx_write_csr 773 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); cvmx_write_csr 808 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); cvmx_write_csr 831 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); cvmx_write_csr 882 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); cvmx_write_csr 901 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_TX_CLK, agl_clk.u64); cvmx_write_csr 1014 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); cvmx_write_csr 1023 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); cvmx_write_csr 1042 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64); cvmx_write_csr 1048 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64); cvmx_write_csr 1053 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64); cvmx_write_csr 1072 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); cvmx_write_csr 1091 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); cvmx_write_csr 1106 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); cvmx_write_csr 1117 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); cvmx_write_csr 1125 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64); cvmx_write_csr 1138 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0xae); cvmx_write_csr 1145 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_CTL, 1); cvmx_write_csr 1146 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP, 0); cvmx_write_csr 1147 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD, 0); cvmx_write_csr 1149 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_TX_STATS_CTL, 1); cvmx_write_csr 1150 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_TX_STAT0, 0); cvmx_write_csr 1151 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_TX_STAT1, 0); cvmx_write_csr 1154 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR)); cvmx_write_csr 1165 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64); cvmx_write_csr 1170 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64); cvmx_write_csr 1176 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); cvmx_write_csr 1205 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); cvmx_write_csr 1322 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_ORING2, 1); cvmx_write_csr 103 drivers/net/phy/mdio-cavium.h cvmx_write_csr(addr, val); cvmx_write_csr 3628 drivers/staging/octeon-usb/octeon-hcd.c cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT, pri_cnt.u64); cvmx_write_csr 115 drivers/staging/octeon/ethernet-mdio.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); cvmx_write_csr 34 drivers/staging/octeon/ethernet-rgmii.c cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface), cvmx_write_csr 44 drivers/staging/octeon/ethernet-rgmii.c cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); cvmx_write_csr 49 drivers/staging/octeon/ethernet-rgmii.c cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), cvmx_write_csr 199 drivers/staging/octeon/ethernet-rx.c cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(coreid), cvmx_write_csr 204 drivers/staging/octeon/ethernet-rx.c cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), cvmx_write_csr 230 drivers/staging/octeon/ethernet-rx.c cvmx_write_csr(CVMX_SSO_WQ_IQ_DIS, cvmx_write_csr 232 drivers/staging/octeon/ethernet-rx.c cvmx_write_csr(CVMX_SSO_WQ_INT, cvmx_write_csr 240 drivers/staging/octeon/ethernet-rx.c cvmx_write_csr(CVMX_POW_WQ_INT, wq_int.u64); cvmx_write_csr 386 drivers/staging/octeon/ethernet-rx.c cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(coreid), old_group_mask); cvmx_write_csr 389 drivers/staging/octeon/ethernet-rx.c cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask); cvmx_write_csr 492 drivers/staging/octeon/ethernet-rx.c cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(i), int_thr.u64); cvmx_write_csr 496 drivers/staging/octeon/ethernet-rx.c cvmx_write_csr(CVMX_SSO_WQ_INT_PC, int_pc.u64); cvmx_write_csr 504 drivers/staging/octeon/ethernet-rx.c cvmx_write_csr(CVMX_POW_WQ_INT_THRX(i), int_thr.u64); cvmx_write_csr 508 drivers/staging/octeon/ethernet-rx.c cvmx_write_csr(CVMX_POW_WQ_INT_PC, int_pc.u64); cvmx_write_csr 529 drivers/staging/octeon/ethernet-rx.c cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(i), 0); cvmx_write_csr 531 drivers/staging/octeon/ethernet-rx.c cvmx_write_csr(CVMX_POW_WQ_INT_THRX(i), 0); cvmx_write_csr 86 drivers/staging/octeon/ethernet-spi.c cvmx_write_csr(CVMX_SPXX_INT_REG(index), spx_int_reg.u64); cvmx_write_csr 93 drivers/staging/octeon/ethernet-spi.c cvmx_write_csr(CVMX_STXX_INT_REG(index), stx_int_reg.u64); cvmx_write_csr 99 drivers/staging/octeon/ethernet-spi.c cvmx_write_csr(CVMX_SPXX_INT_MSK(index), 0); cvmx_write_csr 100 drivers/staging/octeon/ethernet-spi.c cvmx_write_csr(CVMX_STXX_INT_MSK(index), 0); cvmx_write_csr 138 drivers/staging/octeon/ethernet-spi.c cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); cvmx_write_csr 149 drivers/staging/octeon/ethernet-spi.c cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64); cvmx_write_csr 221 drivers/staging/octeon/ethernet-spi.c cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); cvmx_write_csr 222 drivers/staging/octeon/ethernet-spi.c cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); cvmx_write_csr 69 drivers/staging/octeon/ethernet-tx.c cvmx_write_csr(CVMX_CIU_TIMX(1), ciu_timx.u64); cvmx_write_csr 692 drivers/staging/octeon/ethernet-tx.c cvmx_write_csr(CVMX_CIU_TIMX(1), 0); cvmx_write_csr 703 drivers/staging/octeon/ethernet-tx.c cvmx_write_csr(CVMX_CIU_TIMX(1), 0); cvmx_write_csr 159 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64); cvmx_write_csr 260 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(index, interface), cvmx_write_csr 272 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_PIP_FRM_LEN_CHKX(interface), cvmx_write_csr 280 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_RXX_JABBER(index, interface), cvmx_write_csr 325 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), cvmx_write_csr 328 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_RXX_ADR_CTL(index, interface), cvmx_write_csr 331 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN cvmx_write_csr 334 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN cvmx_write_csr 337 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), cvmx_write_csr 361 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), cvmx_write_csr 364 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac); cvmx_write_csr 365 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface), cvmx_write_csr 367 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface), cvmx_write_csr 369 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface), cvmx_write_csr 371 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface), cvmx_write_csr 373 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface), cvmx_write_csr 375 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface), cvmx_write_csr 378 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), cvmx_write_csr 474 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); cvmx_write_csr 661 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, iface), delay_value); cvmx_write_csr 665 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, iface), delay_value); cvmx_write_csr 756 drivers/staging/octeon/ethernet.c cvmx_write_csr(CVMX_PIP_PRT_TAGX(port), cvmx_write_csr 582 drivers/watchdog/octeon-wdt-main.c cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); cvmx_write_csr 603 drivers/watchdog/octeon-wdt-main.c cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);