cvmx_read_csr 45 arch/mips/cavium-octeon/csrc-octeon.c rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); cvmx_read_csr 52 arch/mips/cavium-octeon/csrc-octeon.c rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT); cvmx_read_csr 86 arch/mips/cavium-octeon/csrc-octeon.c u64 clk_count = cvmx_read_csr(clk_reg); cvmx_read_csr 169 arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); cvmx_read_csr 264 arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); cvmx_read_csr 268 arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); cvmx_read_csr 280 arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS cvmx_read_csr 242 arch/mips/cavium-octeon/executive/cvmx-helper-board.c cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface)); cvmx_read_csr 70 arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c cvmx_read_csr(CVMX_CIU_QLM_JTGC); cvmx_read_csr 98 arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); cvmx_read_csr 142 arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); cvmx_read_csr 59 arch/mips/cavium-octeon/executive/cvmx-helper-loop.c port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); cvmx_read_csr 66 arch/mips/cavium-octeon/executive/cvmx-helper-loop.c ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); cvmx_read_csr 103 arch/mips/cavium-octeon/executive/cvmx-helper-npi.c cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); cvmx_read_csr 56 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); cvmx_read_csr 113 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); cvmx_read_csr 115 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface)); cvmx_read_csr 117 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)); cvmx_read_csr 168 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); cvmx_read_csr 203 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL cvmx_read_csr 243 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface)); cvmx_read_csr 270 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); cvmx_read_csr 314 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); cvmx_read_csr 319 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) & cvmx_read_csr 327 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c pko_mem_queue_qos.u64 = cvmx_read_csr(CVMX_PKO_MEM_QUEUE_QOS); cvmx_read_csr 336 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); cvmx_read_csr 341 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); cvmx_read_csr 360 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); cvmx_read_csr 402 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); cvmx_read_csr 425 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); cvmx_read_csr 432 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) | (1 << cvmx_read_csr 60 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); cvmx_read_csr 70 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); cvmx_read_csr 72 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface)); cvmx_read_csr 98 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface)); cvmx_read_csr 108 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); cvmx_read_csr 113 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG cvmx_read_csr 150 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); cvmx_read_csr 211 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); cvmx_read_csr 230 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); cvmx_read_csr 237 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); cvmx_read_csr 288 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); cvmx_read_csr 351 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); cvmx_read_csr 376 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); cvmx_read_csr 416 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); cvmx_read_csr 426 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); cvmx_read_csr 433 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); cvmx_read_csr 444 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG cvmx_read_csr 454 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG cvmx_read_csr 87 arch/mips/cavium-octeon/executive/cvmx-helper-spi.c enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE); cvmx_read_csr 116 arch/mips/cavium-octeon/executive/cvmx-helper-spi.c port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); cvmx_read_csr 189 arch/mips/cavium-octeon/executive/cvmx-helper-util.c gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface)); cvmx_read_csr 209 arch/mips/cavium-octeon/executive/cvmx-helper-util.c gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface)); cvmx_read_csr 218 arch/mips/cavium-octeon/executive/cvmx-helper-util.c pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE); cvmx_read_csr 252 arch/mips/cavium-octeon/executive/cvmx-helper-util.c gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface)); cvmx_read_csr 50 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); cvmx_read_csr 76 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); cvmx_read_csr 126 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); cvmx_read_csr 134 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface)); cvmx_read_csr 139 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface)); cvmx_read_csr 141 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface)); cvmx_read_csr 143 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface)); cvmx_read_csr 149 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); cvmx_read_csr 156 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); cvmx_read_csr 183 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); cvmx_read_csr 199 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); cvmx_read_csr 210 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface))); cvmx_read_csr 212 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface))); cvmx_read_csr 214 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_read_csr(CVMX_PCSXX_INT_REG(interface))); cvmx_read_csr 238 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); cvmx_read_csr 270 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); cvmx_read_csr 271 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface)); cvmx_read_csr 273 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface)); cvmx_read_csr 308 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); cvmx_read_csr 309 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface)); cvmx_read_csr 97 arch/mips/cavium-octeon/executive/cvmx-helper.c qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); cvmx_read_csr 111 arch/mips/cavium-octeon/executive/cvmx-helper.c qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(interface)); cvmx_read_csr 123 arch/mips/cavium-octeon/executive/cvmx-helper.c qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(3)); cvmx_read_csr 128 arch/mips/cavium-octeon/executive/cvmx-helper.c qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1)); cvmx_read_csr 170 arch/mips/cavium-octeon/executive/cvmx-helper.c mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2)); cvmx_read_csr 172 arch/mips/cavium-octeon/executive/cvmx-helper.c mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1)); cvmx_read_csr 189 arch/mips/cavium-octeon/executive/cvmx-helper.c qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2)); cvmx_read_csr 197 arch/mips/cavium-octeon/executive/cvmx-helper.c qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); cvmx_read_csr 208 arch/mips/cavium-octeon/executive/cvmx-helper.c qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); cvmx_read_csr 218 arch/mips/cavium-octeon/executive/cvmx-helper.c mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); cvmx_read_csr 248 arch/mips/cavium-octeon/executive/cvmx-helper.c mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); cvmx_read_csr 327 arch/mips/cavium-octeon/executive/cvmx-helper.c mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); cvmx_read_csr 374 arch/mips/cavium-octeon/executive/cvmx-helper.c port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); cvmx_read_csr 375 arch/mips/cavium-octeon/executive/cvmx-helper.c tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port)); cvmx_read_csr 796 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_read_csr(CVMX_GMXX_PRTX_CFG cvmx_read_csr 799 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT))); cvmx_read_csr 801 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT))); cvmx_read_csr 803 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_read_csr(CVMX_GMXX_RXX_JABBER cvmx_read_csr 806 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX cvmx_read_csr 822 arch/mips/cavium-octeon/executive/cvmx-helper.c wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT); cvmx_read_csr 892 arch/mips/cavium-octeon/executive/cvmx-helper.c cvmx_read_csr(CVMX_GMXX_PRTX_CFG cvmx_read_csr 1026 arch/mips/cavium-octeon/executive/cvmx-helper.c l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG); cvmx_read_csr 55 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block))); cvmx_read_csr 236 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block))); cvmx_read_csr 277 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_read_csr(CVMX_PCSXX_INT_REG(index))); cvmx_read_csr 307 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_read_csr(CVMX_SPXX_INT_REG(index))); cvmx_read_csr 346 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c cvmx_read_csr(CVMX_STXX_INT_REG(index))); cvmx_read_csr 65 arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block)); cvmx_read_csr 83 arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); cvmx_read_csr 58 arch/mips/cavium-octeon/executive/cvmx-l2c.c return cvmx_read_csr(CVMX_L2C_WPAR_PPX(core)) & 0xffff; cvmx_read_csr 73 arch/mips/cavium-octeon/executive/cvmx-l2c.c return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> field; cvmx_read_csr 75 arch/mips/cavium-octeon/executive/cvmx-l2c.c return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> field; cvmx_read_csr 77 arch/mips/cavium-octeon/executive/cvmx-l2c.c return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> field; cvmx_read_csr 79 arch/mips/cavium-octeon/executive/cvmx-l2c.c return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> field; cvmx_read_csr 120 arch/mips/cavium-octeon/executive/cvmx-l2c.c (cvmx_read_csr(CVMX_L2C_SPAR0) & ~(0xFF << field)) | cvmx_read_csr 125 arch/mips/cavium-octeon/executive/cvmx-l2c.c (cvmx_read_csr(CVMX_L2C_SPAR1) & ~(0xFF << field)) | cvmx_read_csr 130 arch/mips/cavium-octeon/executive/cvmx-l2c.c (cvmx_read_csr(CVMX_L2C_SPAR2) & ~(0xFF << field)) | cvmx_read_csr 135 arch/mips/cavium-octeon/executive/cvmx-l2c.c (cvmx_read_csr(CVMX_L2C_SPAR3) & ~(0xFF << field)) | cvmx_read_csr 157 arch/mips/cavium-octeon/executive/cvmx-l2c.c (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask); cvmx_read_csr 164 arch/mips/cavium-octeon/executive/cvmx-l2c.c return cvmx_read_csr(CVMX_L2C_WPAR_IOBX(0)) & 0xffff; cvmx_read_csr 166 arch/mips/cavium-octeon/executive/cvmx-l2c.c return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF); cvmx_read_csr 175 arch/mips/cavium-octeon/executive/cvmx-l2c.c pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL); cvmx_read_csr 210 arch/mips/cavium-octeon/executive/cvmx-l2c.c l2c_tadx_prf.u64 = cvmx_read_csr(CVMX_L2C_TADX_PRF(0)); cvmx_read_csr 238 arch/mips/cavium-octeon/executive/cvmx-l2c.c return cvmx_read_csr(CVMX_L2C_PFC0); cvmx_read_csr 244 arch/mips/cavium-octeon/executive/cvmx-l2c.c counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad)); cvmx_read_csr 249 arch/mips/cavium-octeon/executive/cvmx-l2c.c return cvmx_read_csr(CVMX_L2C_PFC1); cvmx_read_csr 255 arch/mips/cavium-octeon/executive/cvmx-l2c.c counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad)); cvmx_read_csr 260 arch/mips/cavium-octeon/executive/cvmx-l2c.c return cvmx_read_csr(CVMX_L2C_PFC2); cvmx_read_csr 266 arch/mips/cavium-octeon/executive/cvmx-l2c.c counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad)); cvmx_read_csr 272 arch/mips/cavium-octeon/executive/cvmx-l2c.c return cvmx_read_csr(CVMX_L2C_PFC3); cvmx_read_csr 278 arch/mips/cavium-octeon/executive/cvmx-l2c.c counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad)); cvmx_read_csr 331 arch/mips/cavium-octeon/executive/cvmx-l2c.c l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0)); cvmx_read_csr 362 arch/mips/cavium-octeon/executive/cvmx-l2c.c l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR); cvmx_read_csr 373 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_read_csr(CVMX_L2C_DBG); cvmx_read_csr 377 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_read_csr(CVMX_L2C_LCKOFF); cvmx_read_csr 379 arch/mips/cavium-octeon/executive/cvmx-l2c.c if (((union cvmx_l2c_cfg)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) { cvmx_read_csr 392 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_read_csr(CVMX_L2C_LCKBASE); cvmx_read_csr 399 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_read_csr(CVMX_L2C_LCKBASE); cvmx_read_csr 403 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_read_csr(CVMX_L2C_DBG); cvmx_read_csr 405 arch/mips/cavium-octeon/executive/cvmx-l2c.c l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR); cvmx_read_csr 677 arch/mips/cavium-octeon/executive/cvmx-l2c.c l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0)); cvmx_read_csr 738 arch/mips/cavium-octeon/executive/cvmx-l2c.c l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL); cvmx_read_csr 743 arch/mips/cavium-octeon/executive/cvmx-l2c.c l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG); cvmx_read_csr 823 arch/mips/cavium-octeon/executive/cvmx-l2c.c mio_fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); cvmx_read_csr 846 arch/mips/cavium-octeon/executive/cvmx-l2c.c l2d_fus3 = cvmx_read_csr(CVMX_L2D_FUS3); cvmx_read_csr 909 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_read_csr(CVMX_L2C_DBG); cvmx_read_csr 917 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_read_csr(CVMX_L2C_DBG); cvmx_read_csr 254 arch/mips/cavium-octeon/executive/cvmx-pko.c flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); cvmx_read_csr 275 arch/mips/cavium-octeon/executive/cvmx-pko.c pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); cvmx_read_csr 287 arch/mips/cavium-octeon/executive/cvmx-pko.c pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); cvmx_read_csr 207 arch/mips/cavium-octeon/executive/cvmx-spi.c spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface)); cvmx_read_csr 209 arch/mips/cavium-octeon/executive/cvmx-spi.c stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface)); cvmx_read_csr 219 arch/mips/cavium-octeon/executive/cvmx-spi.c spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface)); cvmx_read_csr 249 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_read_csr(CVMX_SPXX_INT_REG(interface))); cvmx_read_csr 252 arch/mips/cavium-octeon/executive/cvmx-spi.c cvmx_read_csr(CVMX_STXX_INT_REG(interface))); cvmx_read_csr 449 arch/mips/cavium-octeon/executive/cvmx-spi.c stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); cvmx_read_csr 474 arch/mips/cavium-octeon/executive/cvmx-spi.c stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); cvmx_read_csr 533 arch/mips/cavium-octeon/executive/cvmx-spi.c spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface)); cvmx_read_csr 548 arch/mips/cavium-octeon/executive/cvmx-spi.c stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); cvmx_read_csr 586 arch/mips/cavium-octeon/executive/cvmx-spi.c srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface)); cvmx_read_csr 609 arch/mips/cavium-octeon/executive/cvmx-spi.c stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); cvmx_read_csr 641 arch/mips/cavium-octeon/executive/cvmx-spi.c srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface)); cvmx_read_csr 649 arch/mips/cavium-octeon/executive/cvmx-spi.c stxx_com_ctl.u64 = cvmx_read_csr(CVMX_STXX_COM_CTL(interface)); cvmx_read_csr 47 arch/mips/cavium-octeon/executive/octeon-model.c while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD)) cvmx_read_csr 74 arch/mips/cavium-octeon/executive/octeon-model.c l2d_fus3 = (cvmx_read_csr(CVMX_L2D_FUS3) >> 34) & 0x3; cvmx_read_csr 75 arch/mips/cavium-octeon/executive/octeon-model.c fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); cvmx_read_csr 76 arch/mips/cavium-octeon/executive/octeon-model.c fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); cvmx_read_csr 413 arch/mips/cavium-octeon/executive/octeon-model.c if (cvmx_read_csr(CVMX_MIO_FUS_PDF) & (0x1ULL << 32)) cvmx_read_csr 85 arch/mips/cavium-octeon/flash_setup.c region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); cvmx_read_csr 109 arch/mips/cavium-octeon/oct_ilm.c timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer)); cvmx_read_csr 145 arch/mips/cavium-octeon/oct_ilm.c timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer)); cvmx_read_csr 1292 arch/mips/cavium-octeon/octeon-irq.c u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2)); cvmx_read_csr 1309 arch/mips/cavium-octeon/octeon-irq.c u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1); cvmx_read_csr 1327 arch/mips/cavium-octeon/octeon-irq.c u64 ciu_sum = cvmx_read_csr(CVMX_CIU_SUM2_PPX_IP4(coreid)); cvmx_read_csr 1328 arch/mips/cavium-octeon/octeon-irq.c u64 ciu_en = cvmx_read_csr(CVMX_CIU_EN2_PPX_IP4(coreid)); cvmx_read_csr 1393 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); cvmx_read_csr 1415 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)); cvmx_read_csr 1976 arch/mips/cavium-octeon/octeon-irq.c sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(core_id)) & 0xfful; cvmx_read_csr 1983 arch/mips/cavium-octeon/octeon-irq.c src = cvmx_read_csr(src_reg); cvmx_read_csr 2002 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY); cvmx_read_csr 2004 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP2(core_id)); cvmx_read_csr 2013 arch/mips/cavium-octeon/octeon-irq.c u64 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP3(core_id)) >> 60; cvmx_read_csr 2029 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY); cvmx_read_csr 2031 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP3(core_id)); cvmx_read_csr 2125 arch/mips/cavium-octeon/octeon-irq.c en = cvmx_read_csr(host_data->en_reg); cvmx_read_csr 2139 arch/mips/cavium-octeon/octeon-irq.c en = cvmx_read_csr(host_data->en_reg); cvmx_read_csr 2231 arch/mips/cavium-octeon/octeon-irq.c en = cvmx_read_csr(host_data->en_reg); cvmx_read_csr 2232 arch/mips/cavium-octeon/octeon-irq.c raw = cvmx_read_csr(host_data->raw_reg); cvmx_read_csr 2246 arch/mips/cavium-octeon/octeon-irq.c en = cvmx_read_csr(host_data->en_reg); cvmx_read_csr 2360 arch/mips/cavium-octeon/octeon-irq.c isc.u64 = cvmx_read_csr(ciu3_info->ciu3_addr + CIU3_ISC_CTL(hwirq)); cvmx_read_csr 2403 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(isc_ctl_addr); cvmx_read_csr 2421 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(isc_ctl_addr); cvmx_read_csr 2445 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(isc_w1c_addr); cvmx_read_csr 2461 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(isc_w1c_addr); cvmx_read_csr 2485 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(isc_w1c_addr); cvmx_read_csr 2520 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(isc_ctl_addr); cvmx_read_csr 2581 arch/mips/cavium-octeon/octeon-irq.c dest_pp_int.u64 = cvmx_read_csr(ciu3_addr + CIU3_DEST_PP_INT(3 * cvmx_get_local_core_num())); cvmx_read_csr 2605 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(isc_w1c_addr); cvmx_read_csr 2645 arch/mips/cavium-octeon/octeon-irq.c dest_pp_int.u64 = cvmx_read_csr(ciu3_addr + CIU3_DEST_PP_INT(1 + 3 * core)); cvmx_read_csr 2660 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(isc_w1c_addr); cvmx_read_csr 2686 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(isc_w1s_addr); cvmx_read_csr 2715 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(isc_ctl_addr); cvmx_read_csr 2756 arch/mips/cavium-octeon/octeon-irq.c cvmx_read_csr(isc_w1c_addr); cvmx_read_csr 2873 arch/mips/cavium-octeon/octeon-irq.c consts.u64 = cvmx_read_csr(base_addr + CIU3_CONST); cvmx_read_csr 39 arch/mips/cavium-octeon/octeon-platform.c clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); cvmx_read_csr 110 arch/mips/cavium-octeon/octeon-platform.c cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0)); cvmx_read_csr 120 arch/mips/cavium-octeon/octeon-platform.c clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); cvmx_read_csr 189 arch/mips/cavium-octeon/octeon-platform.c clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); cvmx_read_csr 297 arch/mips/cavium-octeon/octeon-platform.c ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0)); cvmx_read_csr 362 arch/mips/cavium-octeon/octeon-platform.c ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0)); cvmx_read_csr 951 arch/mips/cavium-octeon/octeon-platform.c mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); cvmx_read_csr 974 arch/mips/cavium-octeon/octeon-platform.c cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); cvmx_read_csr 1041 arch/mips/cavium-octeon/octeon-platform.c mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); cvmx_read_csr 254 arch/mips/cavium-octeon/octeon-usb.c gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); cvmx_read_csr 259 arch/mips/cavium-octeon/octeon-usb.c gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); cvmx_read_csr 264 arch/mips/cavium-octeon/octeon-usb.c gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio)); cvmx_read_csr 271 arch/mips/cavium-octeon/octeon-usb.c uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); cvmx_read_csr 277 arch/mips/cavium-octeon/octeon-usb.c uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); cvmx_read_csr 359 arch/mips/cavium-octeon/octeon-usb.c uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); cvmx_read_csr 366 arch/mips/cavium-octeon/octeon-usb.c uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); cvmx_read_csr 377 arch/mips/cavium-octeon/octeon-usb.c uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); cvmx_read_csr 381 arch/mips/cavium-octeon/octeon-usb.c uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); cvmx_read_csr 388 arch/mips/cavium-octeon/octeon-usb.c uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); cvmx_read_csr 393 arch/mips/cavium-octeon/octeon-usb.c uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); cvmx_read_csr 433 arch/mips/cavium-octeon/octeon-usb.c uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); cvmx_read_csr 447 arch/mips/cavium-octeon/octeon-usb.c uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); cvmx_read_csr 455 arch/mips/cavium-octeon/octeon-usb.c uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); cvmx_read_csr 460 arch/mips/cavium-octeon/octeon-usb.c uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); cvmx_read_csr 472 arch/mips/cavium-octeon/octeon-usb.c shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG); cvmx_read_csr 491 arch/mips/cavium-octeon/octeon-usb.c uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index)); cvmx_read_csr 721 arch/mips/cavium-octeon/setup.c rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); cvmx_read_csr 726 arch/mips/cavium-octeon/setup.c rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT); cvmx_read_csr 805 arch/mips/cavium-octeon/setup.c if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { cvmx_read_csr 1119 arch/mips/cavium-octeon/setup.c lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); cvmx_read_csr 71 arch/mips/cavium-octeon/smp.c action = cvmx_read_csr(mbox_clrx); cvmx_read_csr 148 arch/mips/include/asm/octeon/cvmx-fpa.h status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); cvmx_read_csr 163 arch/mips/include/asm/octeon/cvmx-fpa.h cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull); cvmx_read_csr 188 arch/mips/include/asm/octeon/cvmx-fpa.h cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool))); cvmx_read_csr 117 arch/mips/include/asm/octeon/cvmx-ipd.h ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); cvmx_read_csr 132 arch/mips/include/asm/octeon/cvmx-ipd.h ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); cvmx_read_csr 151 arch/mips/include/asm/octeon/cvmx-ipd.h ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); cvmx_read_csr 166 arch/mips/include/asm/octeon/cvmx-ipd.h ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT); cvmx_read_csr 171 arch/mips/include/asm/octeon/cvmx-ipd.h ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); cvmx_read_csr 180 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID); cvmx_read_csr 197 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); cvmx_read_csr 207 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); cvmx_read_csr 230 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID); cvmx_read_csr 242 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL); cvmx_read_csr 252 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_read_csr cvmx_read_csr 272 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL); cvmx_read_csr 282 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_read_csr cvmx_read_csr 300 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); cvmx_read_csr 310 arch/mips/include/asm/octeon/cvmx-ipd.h cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); cvmx_read_csr 324 arch/mips/include/asm/octeon/cvmx-ipd.h ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); cvmx_read_csr 332 arch/mips/include/asm/octeon/cvmx-ipd.h pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST); cvmx_read_csr 389 arch/mips/include/asm/octeon/cvmx-pip.h stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num)); cvmx_read_csr 390 arch/mips/include/asm/octeon/cvmx-pip.h stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num)); cvmx_read_csr 391 arch/mips/include/asm/octeon/cvmx-pip.h stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num)); cvmx_read_csr 392 arch/mips/include/asm/octeon/cvmx-pip.h stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num)); cvmx_read_csr 393 arch/mips/include/asm/octeon/cvmx-pip.h stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num)); cvmx_read_csr 394 arch/mips/include/asm/octeon/cvmx-pip.h stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num)); cvmx_read_csr 395 arch/mips/include/asm/octeon/cvmx-pip.h stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num)); cvmx_read_csr 396 arch/mips/include/asm/octeon/cvmx-pip.h stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num)); cvmx_read_csr 397 arch/mips/include/asm/octeon/cvmx-pip.h stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num)); cvmx_read_csr 398 arch/mips/include/asm/octeon/cvmx-pip.h stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num)); cvmx_read_csr 400 arch/mips/include/asm/octeon/cvmx-pip.h cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num)); cvmx_read_csr 402 arch/mips/include/asm/octeon/cvmx-pip.h cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num)); cvmx_read_csr 404 arch/mips/include/asm/octeon/cvmx-pip.h cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num)); cvmx_read_csr 517 arch/mips/include/asm/octeon/cvmx-pip.h pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index)); cvmx_read_csr 589 arch/mips/include/asm/octeon/cvmx-pko.h pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0); cvmx_read_csr 596 arch/mips/include/asm/octeon/cvmx-pko.h pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1); cvmx_read_csr 607 arch/mips/include/asm/octeon/cvmx-pko.h debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); cvmx_read_csr 613 arch/mips/include/asm/octeon/cvmx-pko.h debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); cvmx_read_csr 1271 arch/mips/include/asm/octeon/cvmx-pow.h load_resp.u64 = cvmx_read_csr(load_addr.u64); cvmx_read_csr 1298 arch/mips/include/asm/octeon/cvmx-pow.h load_resp.u64 = cvmx_read_csr(load_addr.u64); cvmx_read_csr 1366 arch/mips/include/asm/octeon/cvmx-pow.h result.u64 = cvmx_read_csr(ptr.u64); cvmx_read_csr 1419 arch/mips/include/asm/octeon/cvmx-pow.h result.u64 = cvmx_read_csr(ptr.u64); cvmx_read_csr 1855 arch/mips/include/asm/octeon/cvmx-pow.h grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num)); cvmx_read_csr 1880 arch/mips/include/asm/octeon/cvmx-pow.h grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num)); cvmx_read_csr 79 arch/mips/include/asm/octeon/cvmx-spi.h uint64_t gmxState = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); cvmx_read_csr 299 arch/mips/include/asm/octeon/cvmx.h return cvmx_read_csr((__force uint64_t) csr_addr); cvmx_read_csr 386 arch/mips/include/asm/octeon/cvmx.h return cvmx_read_csr(node_addr); cvmx_read_csr 465 arch/mips/include/asm/octeon/cvmx.h c.u64 = cvmx_read_csr(address); \ cvmx_read_csr 491 arch/mips/include/asm/octeon/cvmx.h ciu_fuse = cvmx_read_csr(ciu_fuse_reg); cvmx_read_csr 126 arch/mips/include/asm/octeon/octeon-feature.h fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); cvmx_read_csr 314 arch/mips/include/asm/octeon/octeon-model.h static inline uint64_t cvmx_read_csr(uint64_t csr_addr); cvmx_read_csr 276 arch/mips/pci/msi-octeon.c en = cvmx_read_csr(mis_ena_reg[irq_index]); cvmx_read_csr 279 arch/mips/pci/msi-octeon.c cvmx_read_csr(mis_ena_reg[irq_index]); cvmx_read_csr 292 arch/mips/pci/msi-octeon.c en = cvmx_read_csr(mis_ena_reg[irq_index]); cvmx_read_csr 295 arch/mips/pci/msi-octeon.c cvmx_read_csr(mis_ena_reg[irq_index]); cvmx_read_csr 352 arch/mips/pci/msi-octeon.c u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \ cvmx_read_csr 370 arch/mips/pci/pci-octeon.c cvmx_read_csr(CVMX_CIU_SOFT_PRST); cvmx_read_csr 382 arch/mips/pci/pci-octeon.c cvmx_read_csr(CVMX_CIU_SOFT_PRST); cvmx_read_csr 417 arch/mips/pci/pci-octeon.c cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); cvmx_read_csr 420 arch/mips/pci/pci-octeon.c cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); cvmx_read_csr 179 arch/mips/pci/pcie-octeon.c pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port)); cvmx_read_csr 186 arch/mips/pci/pcie-octeon.c pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port)); cvmx_read_csr 436 arch/mips/pci/pcie-octeon.c npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2); cvmx_read_csr 456 arch/mips/pci/pcie-octeon.c prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port)); cvmx_read_csr 463 arch/mips/pci/pcie-octeon.c sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port)); cvmx_read_csr 594 arch/mips/pci/pcie-octeon.c pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port)); cvmx_read_csr 622 arch/mips/pci/pcie-octeon.c pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port)); cvmx_read_csr 645 arch/mips/pci/pcie-octeon.c cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM)); cvmx_read_csr 712 arch/mips/pci/pcie-octeon.c npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS); cvmx_read_csr 723 arch/mips/pci/pcie-octeon.c npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); cvmx_read_csr 757 arch/mips/pci/pcie-octeon.c ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); cvmx_read_csr 768 arch/mips/pci/pcie-octeon.c ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); cvmx_read_csr 774 arch/mips/pci/pcie-octeon.c ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); cvmx_read_csr 777 arch/mips/pci/pcie-octeon.c ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); cvmx_read_csr 788 arch/mips/pci/pcie-octeon.c ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); cvmx_read_csr 790 arch/mips/pci/pcie-octeon.c ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); cvmx_read_csr 807 arch/mips/pci/pcie-octeon.c ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); cvmx_read_csr 811 arch/mips/pci/pcie-octeon.c ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); cvmx_read_csr 830 arch/mips/pci/pcie-octeon.c pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port)); cvmx_read_csr 848 arch/mips/pci/pcie-octeon.c pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port)); cvmx_read_csr 859 arch/mips/pci/pcie-octeon.c pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port)); cvmx_read_csr 867 arch/mips/pci/pcie-octeon.c pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port)); cvmx_read_csr 883 arch/mips/pci/pcie-octeon.c npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL); cvmx_read_csr 966 arch/mips/pci/pcie-octeon.c npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1); cvmx_read_csr 977 arch/mips/pci/pcie-octeon.c npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0); cvmx_read_csr 1030 arch/mips/pci/pcie-octeon.c cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT); cvmx_read_csr 1032 arch/mips/pci/pcie-octeon.c dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); cvmx_read_csr 1036 arch/mips/pci/pcie-octeon.c dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); cvmx_read_csr 1045 arch/mips/pci/pcie-octeon.c cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT); cvmx_read_csr 1046 arch/mips/pci/pcie-octeon.c dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); cvmx_read_csr 1097 arch/mips/pci/pcie-octeon.c pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port)); cvmx_read_csr 1173 arch/mips/pci/pcie-octeon.c qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port)); cvmx_read_csr 1203 arch/mips/pci/pcie-octeon.c sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port)); cvmx_read_csr 1231 arch/mips/pci/pcie-octeon.c mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port)); cvmx_read_csr 1241 arch/mips/pci/pcie-octeon.c ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1); cvmx_read_csr 1248 arch/mips/pci/pcie-octeon.c ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0); cvmx_read_csr 1257 arch/mips/pci/pcie-octeon.c ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); cvmx_read_csr 1259 arch/mips/pci/pcie-octeon.c ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); cvmx_read_csr 1276 arch/mips/pci/pcie-octeon.c ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); cvmx_read_csr 1280 arch/mips/pci/pcie-octeon.c ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); cvmx_read_csr 1299 arch/mips/pci/pcie-octeon.c pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port)); cvmx_read_csr 1302 arch/mips/pci/pcie-octeon.c pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port)); cvmx_read_csr 1335 arch/mips/pci/pcie-octeon.c sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL); cvmx_read_csr 1392 arch/mips/pci/pcie-octeon.c pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port)); cvmx_read_csr 1398 arch/mips/pci/pcie-octeon.c sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port)); cvmx_read_csr 1424 arch/mips/pci/pcie-octeon.c pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port)); cvmx_read_csr 1506 arch/mips/pci/pcie-octeon.c pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1)); cvmx_read_csr 1517 arch/mips/pci/pcie-octeon.c pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1)); cvmx_read_csr 1527 arch/mips/pci/pcie-octeon.c pemx_int_sum.u64 = cvmx_read_csr(CVMX_PEMX_INT_SUM(1)); cvmx_read_csr 1906 arch/mips/pci/pcie-octeon.c npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS); cvmx_read_csr 1911 arch/mips/pci/pcie-octeon.c mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(0)); cvmx_read_csr 1921 arch/mips/pci/pcie-octeon.c sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0)); cvmx_read_csr 1979 arch/mips/pci/pcie-octeon.c dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); cvmx_read_csr 1985 arch/mips/pci/pcie-octeon.c mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(1)); cvmx_read_csr 1994 arch/mips/pci/pcie-octeon.c sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1)); cvmx_read_csr 2068 arch/mips/pci/pcie-octeon.c sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(port)); cvmx_read_csr 2075 arch/mips/pci/pcie-octeon.c sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(!port)); cvmx_read_csr 108 drivers/ata/pata_octeon_cf.c reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); cvmx_read_csr 178 drivers/ata/pata_octeon_cf.c reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0)); cvmx_read_csr 249 drivers/ata/pata_octeon_cf.c pin_defs.u64 = cvmx_read_csr(CVMX_MIO_BOOT_PIN_DEFS); cvmx_read_csr 637 drivers/ata/pata_octeon_cf.c dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG); cvmx_read_csr 692 drivers/ata/pata_octeon_cf.c dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT); cvmx_read_csr 693 drivers/ata/pata_octeon_cf.c dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG); cvmx_read_csr 29 drivers/edac/octeon_edac-l2c.c l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR); cvmx_read_csr 44 drivers/edac/octeon_edac-l2c.c l2d_err.u64 = cvmx_read_csr(CVMX_L2D_ERR); cvmx_read_csr 68 drivers/edac/octeon_edac-l2c.c err_tdtx.u64 = cvmx_read_csr(CVMX_L2C_ERR_TDTX(tad)); cvmx_read_csr 103 drivers/edac/octeon_edac-l2c.c err_ttgx.u64 = cvmx_read_csr(CVMX_L2C_ERR_TTGX(tad)); cvmx_read_csr 157 drivers/edac/octeon_edac-l2c.c l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR); cvmx_read_csr 162 drivers/edac/octeon_edac-l2c.c l2d_err.u64 = cvmx_read_csr(CVMX_L2D_ERR); cvmx_read_csr 44 drivers/edac/octeon_edac-lmc.c cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx)); cvmx_read_csr 47 drivers/edac/octeon_edac-lmc.c fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx)); cvmx_read_csr 79 drivers/edac/octeon_edac-lmc.c int_reg.u64 = cvmx_read_csr(CVMX_LMCX_INT(mci->mc_idx)); cvmx_read_csr 91 drivers/edac/octeon_edac-lmc.c fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx)); cvmx_read_csr 240 drivers/edac/octeon_edac-lmc.c cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(0)); cvmx_read_csr 263 drivers/edac/octeon_edac-lmc.c cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc)); cvmx_read_csr 272 drivers/edac/octeon_edac-lmc.c config.u64 = cvmx_read_csr(CVMX_LMCX_CONFIG(0)); cvmx_read_csr 295 drivers/edac/octeon_edac-lmc.c en.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc)); cvmx_read_csr 76 drivers/gpio/gpio-octeon.c u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT); cvmx_read_csr 164 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); cvmx_read_csr 176 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); cvmx_read_csr 257 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); cvmx_read_csr 261 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); cvmx_read_csr 296 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c ns = cvmx_read_csr(CVMX_MIXX_TSTAMP(p->port)); cvmx_read_csr 307 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); cvmx_read_csr 328 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c drop = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP); cvmx_read_csr 329 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c bad = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD); cvmx_read_csr 349 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0); cvmx_read_csr 350 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c s1.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT1); cvmx_read_csr 478 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); cvmx_read_csr 486 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); cvmx_read_csr 522 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); cvmx_read_csr 526 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_read_csr(p->mix + MIX_CTL); cvmx_read_csr 529 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST); cvmx_read_csr 534 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST); cvmx_read_csr 604 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c agl_gmx_prtx.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); cvmx_read_csr 671 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mixx_isr.u64 = cvmx_read_csr(p->mix + MIX_ISR); cvmx_read_csr 675 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_read_csr(p->mix + MIX_ISR); cvmx_read_csr 707 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c ptp.u64 = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_CFG); cvmx_read_csr 721 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP); cvmx_read_csr 749 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL); cvmx_read_csr 771 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL); cvmx_read_csr 804 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); cvmx_read_csr 813 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); cvmx_read_csr 827 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); cvmx_read_csr 840 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); cvmx_read_csr 885 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); cvmx_read_csr 891 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); cvmx_read_csr 892 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c agl_clk.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_CLK); cvmx_read_csr 1009 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); cvmx_read_csr 1016 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); cvmx_read_csr 1032 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL); cvmx_read_csr 1089 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); cvmx_read_csr 1100 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); cvmx_read_csr 1107 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_read_csr(p->agl_prt_ctl); /* Force write out before wait */ cvmx_read_csr 1115 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); cvmx_read_csr 1120 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl); cvmx_read_csr 1127 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_read_csr(p->agl_prt_ctl); cvmx_read_csr 1154 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR)); cvmx_read_csr 108 drivers/net/phy/mdio-cavium.h return cvmx_read_csr(addr); cvmx_read_csr 113 drivers/staging/octeon/ethernet-mdio.c gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); cvmx_read_csr 31 drivers/staging/octeon/ethernet-rgmii.c gmxx_rxx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, cvmx_read_csr 38 drivers/staging/octeon/ethernet-rgmii.c ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); cvmx_read_csr 47 drivers/staging/octeon/ethernet-rgmii.c gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, cvmx_read_csr 76 drivers/staging/octeon/ethernet-rgmii.c gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG cvmx_read_csr 94 drivers/staging/octeon/ethernet-rx.c cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface)); cvmx_read_csr 198 drivers/staging/octeon/ethernet-rx.c old_group_mask = cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid)); cvmx_read_csr 201 drivers/staging/octeon/ethernet-rx.c cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid)); /* Flush */ cvmx_read_csr 203 drivers/staging/octeon/ethernet-rx.c old_group_mask = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(coreid)); cvmx_read_csr 387 drivers/staging/octeon/ethernet-rx.c cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid)); /* Flush */ cvmx_read_csr 85 drivers/staging/octeon/ethernet-spi.c spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(index)); cvmx_read_csr 88 drivers/staging/octeon/ethernet-spi.c spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(index)); cvmx_read_csr 92 drivers/staging/octeon/ethernet-spi.c stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(index)); cvmx_read_csr 95 drivers/staging/octeon/ethernet-spi.c stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(index)); cvmx_read_csr 112 drivers/staging/octeon/ethernet-spi.c rsl_int_blocks.u64 = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS); cvmx_read_csr 127 drivers/staging/octeon/ethernet-spi.c spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface)); cvmx_read_csr 140 drivers/staging/octeon/ethernet-spi.c stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface)); cvmx_read_csr 237 drivers/staging/octeon/ethernet-tx.c cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); cvmx_read_csr 156 drivers/staging/octeon/ethernet.c ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); cvmx_read_csr 324 drivers/staging/octeon/ethernet.c cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); cvmx_read_csr 360 drivers/staging/octeon/ethernet.c cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); cvmx_read_csr 470 drivers/staging/octeon/ethernet.c gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); cvmx_read_csr 724 drivers/staging/octeon/ethernet.c cvmx_read_csr(CVMX_PIP_PRT_TAGX(port)); cvmx_read_csr 251 drivers/watchdog/octeon-wdt-main.c octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16); cvmx_read_csr 253 drivers/watchdog/octeon-wdt-main.c octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16); cvmx_read_csr 256 drivers/watchdog/octeon-wdt-main.c octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16); cvmx_read_csr 258 drivers/watchdog/octeon-wdt-main.c octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16); cvmx_read_csr 261 drivers/watchdog/octeon-wdt-main.c octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16); cvmx_read_csr 265 drivers/watchdog/octeon-wdt-main.c octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16); cvmx_read_csr 267 drivers/watchdog/octeon-wdt-main.c octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);